Memory management method and electronic device
By setting and dynamically adjusting the memory waterline for each CPU core, the problem that the traditional PCP caching mechanism cannot meet the memory requirements of different threads is solved, achieving efficient utilization and precise management of memory resources.
CN122450643APending Publication Date: 2026-07-24HONOR DEVICE CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HONOR DEVICE CO LTD
- Filing Date
- 2025-01-24
- Publication Date
- 2026-07-24
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Figure CN122450643A_ABST
Abstract
The application discloses a memory management method and an electronic device, and relates to the technical field of memory management. Each CPU core of the electronic device has a corresponding local cache module, and the local cache module has a corresponding memory water line used for determining the total memory quantity of the local cache module. The electronic device can acquire target information corresponding to the local cache module, and the target information includes the number of idle memory pages of the local cache module detected at a preset detection time. When the target information represents that the total memory quantity of the PCP is insufficient or excessively large, the electronic device adjusts the memory water line of the corresponding PCP, so that the adjusted PCPs can timely meet the individualized demand of the memory resources of the threads on the corresponding CPU core.
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