A gate driving circuit, method and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit, a method and a display panel. The gate driving circuit comprises N cascaded gate driving units. The nth gate driving unit comprises: a pull-up module configured to charge a driving control node in response to an output signal of the nth-i gate driving unit; a stage transmission output module configured to output a stage transmission signal under the action of a voltage on the driving control node and a clock signal of the current stage; a driving output module configured to output a gate driving signal under the action of the voltage on the driving control node and the clock signal of the current stage; and a local brushing control module configured to, in a local refresh mode, control the driving output module to output the gate driving signal if the current stage is a refresh row, and control the driving output module to stop outputting the gate driving signal if the current stage is a non-refresh row. The application can reduce the aging speed of the display panel.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit, method, and display panel. Background Technology

[0002] Among related technologies, Gate Driver Less (GDL) is a technical solution based on amorphous silicon (a-SiTFT) fabrication that directly integrates the shift register circuit of an external gate driver integrated circuit onto the display panel array substrate. This solution can completely replace a separate gate driver IC, simplifying the display driver architecture through process integration, thereby significantly reducing device procurement and module assembly costs. However, the frequent pixel refresh control by the gate driver IC will accelerate the aging of the display panel and reduce its lifespan.

[0003] Therefore, how to reduce the aging rate of display panels is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit, method, and display panel, which solves the problem of how to reduce the aging rate of the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, comprising N cascaded gate driving units. The nth gate driving unit includes: a pull-up module connected to a driving control node, configured to charge the driving control node in response to the output signal of the nth gate driving unit; a stage transmission output module connected to the driving control node and the clock signal line of the current stage, configured to output a stage transmission signal under the action of the voltage on the driving control node and the clock signal of the current stage; a driving output module connected to the driving control node and the clock signal line of the current stage, configured to output a gate driving signal under the action of the voltage on the driving control node and the clock signal of the current stage; and a partial refresh control module connected to the output terminal of the driving output module, configured to: in partial refresh mode, if the current stage is a refresh row, control the driving output module to output the gate driving signal; if the current stage is a non-refresh row, control the driving output module to stop outputting the gate driving signal.

[0006] Optionally, the partial refresh control module includes: a first control submodule, which has a first partial refresh control node and a second partial refresh control node, configured to: generate a first control signal at the first partial refresh control node and generate a second control signal at the second partial refresh control node in partial refresh mode; wherein the voltage polarities of the first control signal and the second control signal are opposite; and a second control submodule, which is connected to the output terminals of the first partial refresh control node, the second partial refresh control node, and the drive output module, respectively, configured to: if the current level is a refresh row, control the drive output module to output the gate drive signal under the action of the first control signal and the second control signal; if the current level is a non-refresh row, control the drive output module to stop outputting the gate drive signal under the action of the first control signal and the second control signal.

[0007] Optionally, the first control submodule includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; the control terminal of the first transistor is connected to a first brush control terminal, the first terminal of the first transistor and the first terminal of the second transistor are connected to a high-level terminal, the second terminal of the first transistor, the first terminal of the third transistor, and the control terminal of the fourth transistor are connected to a second brush control node; the control terminal of the second transistor is connected to the second brush control terminal, the second terminal of the second transistor, the control terminal of the third transistor, and the first terminal of the fourth transistor are connected to the first brush control node; the second terminal of the third transistor and the second terminal of the fourth transistor are connected to a low-level terminal.

[0008] Optionally, the second control submodule includes a fifth transistor and a sixth transistor; the control terminal of the fifth transistor is connected to the second local brush control node, the first terminal of the fifth transistor is connected to the output terminal of the drive output module, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor; the control terminal of the sixth transistor is connected to the output terminal of the stage transmission output module, and the second terminal of the sixth transistor is connected to the first local brush control node.

[0009] Optionally, the second control submodule includes: a fifth transistor, a sixth transistor, and a seventh transistor; the control terminal of the fifth transistor is connected to the second local brush control node, the first terminal of the fifth transistor is connected to the output terminal of the drive output module, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor; the control terminal of the sixth transistor is connected to the second terminal of the seventh transistor, and the second terminal of the sixth transistor is connected to the first local brush control node; the control terminal of the seventh transistor is connected to the drive control node, and the first terminal of the seventh transistor is connected to the output terminal of the stage transmission output module.

[0010] Optionally, the stage output module includes: an eighth transistor and a first capacitor; the control terminal of the eighth transistor is connected to the drive control node and the first terminal of the first capacitor respectively, the first terminal of the eighth transistor is connected to the clock signal line of the current stage, and the second terminal of the eighth transistor is connected to the second terminal of the first capacitor.

[0011] Optionally, the drive output module includes: a ninth transistor and a second capacitor; the control terminal of the ninth transistor is connected to the drive control node and the first terminal of the second capacitor respectively, the first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor is connected to the second terminal of the second capacitor.

[0012] Secondly, this application provides a gate driving method applied to the gate driving circuit described in any one of the first aspects. The method includes: a pull-up module charging the drive control node in response to the output signal of the ni-th stage gate driving unit; a stage transmission output module outputting a stage transmission signal under the action of the voltage on the drive control node and the clock signal of the current stage; a drive output module outputting a gate driving signal under the action of the voltage on the drive control node and the clock signal of the current stage; and a partial refresh control module controlling the drive output module to output the gate driving signal in partial refresh mode if the current stage is a refresh row, and controlling the drive output module to stop outputting the gate driving signal if the current stage is a non-refresh row.

[0013] Optionally, the stage transmission output module includes an eighth transistor and a first capacitor. When the drive output module stops outputting the gate drive signal, the stage transmission output module outputs a stage transmission signal under the action of the voltage on the drive control node and the clock signal of the current stage, including: the eighth transistor outputs a stage transmission signal under the action of the voltage on the first capacitor and the clock signal of the current stage; wherein, the voltage on the drive control node is stored in the first capacitor.

[0014] Thirdly, this application provides a display panel including a display area and a non-display area, wherein the display area includes multiple scan lines, and the non-display area includes a gate driving circuit as described in any one of the first aspects, and the drive output module of the gate driving circuit is connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, by connecting the output terminal of the local refresh control module to the output terminal of the drive output module, in the local refresh mode, if the current level is a refresh row, the drive output module is controlled to output the gate drive signal; if the current level is a non-refresh row, the drive output module is controlled to stop outputting the gate drive signal, thereby enabling selective local refresh of the display panel without refreshing every row of pixels for every frame signal, which can reduce the aging speed of the display panel. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate driving circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 3 A timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0021] Figure 4 Another timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0023] Figure 6 A schematic flowchart of a gate driving method provided in an embodiment of this application is shown.

[0024] Explanation of reference numerals in the attached figures: 100 Gate drive unit; 110 Pull-up module; 120 Stage output module; 130 Drive output module; 140 Local brush control module; 141 First control submodule; 142 Second control submodule; 150 Pull-down module; 160 Noise reduction module.

[0025] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; C1, first capacitor; C2, second capacitor; VGH, high-level terminal; VSS, low-level terminal; SW1, first brush control terminal; SW2, second brush control terminal. Detailed Implementation

[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0027] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0028] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0029] Figure 1 A schematic diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth gate driving unit 100 includes: a pull-up module 110, a stage output module 120, a drive output module 130, and a local brush control module 140. The pull-up module 110 is connected to the drive control node Qn. The stage output module 120 is connected to the drive control node Qn and the clock signal line CKm of the current stage. The drive output module 130 is connected to the drive control node Qn and the clock signal line CKm of the current stage. The local brush control module 140 is connected to the output terminal Fn of the drive output module 130.

[0030] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, Fn-i represents the output terminal of the ni-th stage transmission output module 120, Qn represents the current stage drive control node Qn, Fn represents the output terminal of the current stage transmission output module 120, and Gn represents the output terminal of the current stage drive output module 130.

[0031] In some embodiments, the pull-up module 110 is configured to charge the drive control node Qn in response to the output signal of the nth gate drive unit 100.

[0032] For example, when the pull-up module 110 receives the output signal of the ni-th gate drive unit 100, the pull-up module 110 will be turned on to charge the drive control node Qn, so as to generate a voltage on the drive control node Qn.

[0033] In some embodiments, the stage transmission module 120 is configured to output a stage transmission signal under the influence of the voltage on the drive control node Qn and the clock signal of the current stage.

[0034] For example, when the clock signal of the current stage arrives, the voltage on the drive control node Qn and the clock signal of the current stage will control the stage transmission module 120 to turn on. The stage transmission module 120 outputs the stage transmission signal of the current stage for stage transmission, which acts on the adjacent gate drive unit 100 to precharge the drive control node Qn, or pull down the output terminal Fn of the stage transmission module 120 and the output terminal Gn of the drive output module 130 after outputting the gate drive signal of the current stage.

[0035] In some embodiments, the drive output module 130 is configured to output a gate drive signal under the action of the voltage on the drive control node Qn and the clock signal of the current stage.

[0036] For example, when the clock signal of the current stage arrives, under the action of the voltage on the drive control node Qn and the clock signal of the current stage, the drive output module 130 will also be turned on, and output the gate drive signal of the current stage to refresh the pixel of the current stage.

[0037] In some embodiments, the local refresh control module 140 is configured to: in local refresh mode, if the current level is a refresh row, control the drive output module 130 to output a gate drive signal; if the current level is a non-refresh row, control the drive output module 130 to stop outputting the gate drive signal.

[0038] For example, if the current level is a refresh row, it means that the current level needs to output a gate drive signal. The local refresh control module 140 then controls the drive output module 130 to output a gate drive signal to refresh the pixels of the current level. If the current level is a non-refresh signal, the local refresh control module 140 controls the drive output module 130 to stop outputting the gate drive signal and will not refresh the pixels of the current level. This enables selective local refresh of the display panel without refreshing every row of pixels in every frame, thus reducing the aging speed of the display panel.

[0039] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the local brush control module 140 includes: a first control submodule 141 and a second control submodule 142. The first control submodule 141 has a first local brush control node An and a second local brush control node Bn. The second control submodule 142 is connected to the first local brush control node An, the second local brush control node Bn and the output terminal of the drive output module 130, respectively.

[0040] In some embodiments, the first control submodule 141 is configured to: generate a first control signal at the first refresh control node An and generate a second control signal at the second refresh control node Bn in a local refresh mode; wherein the voltage polarities of the first control signal and the second control signal are opposite.

[0041] For example, by generating a first control signal at the first brush control node An and a second control signal at the second brush control node Bn in the first control submodule 141, the output of the gate drive signal can be controlled. By setting the voltage polarities of the first control signal and the second control signal to be opposite, the process of outputting the gate drive signal and the process of stopping the output of the gate drive signal can be interlocked to ensure the reliability of the brush control.

[0042] In some embodiments, the second control submodule 142 is configured to: if the current level is a refresh row, control the drive output module 130 to output a gate drive signal under the action of the first control signal and the second control signal; if the current level is a non-refresh row, control the drive output module 130 to stop outputting the gate drive signal under the action of the first control signal and the second control signal.

[0043] For example, when the first control signal is a high-level signal and the second control signal is a low-level signal, the drive output module 130 can be controlled to output a gate drive signal to refresh the pixel of the current level; when the first control signal is a low-level signal and the second control signal is a high-level signal, the drive output module 130 can be controlled to stop outputting the gate drive signal and not refresh the pixel of the current level.

[0044] In some embodiments, please refer to Figure 2 As shown, the first control submodule 141 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4; the control terminal of the first transistor T1 is connected to the first brush control terminal SW1, the first terminal of the first transistor T1 and the first terminal of the second transistor T2 are connected to the high-level terminal VGH, the second terminal of the first transistor T1, the first terminal of the third transistor T3, and the control terminal of the fourth transistor T4 are connected to the second brush control node; the control terminal of the second transistor T2 is connected to the second brush control terminal SW2, the second terminal of the second transistor T2, the control terminal of the third transistor T3, and the first terminal of the fourth transistor T4 are connected to the first brush control node; the second terminal of the third transistor T3 and the second terminal of the fourth transistor T4 are connected to the low-level terminal VSS.

[0045] In some embodiments, the second control submodule 142 includes: a fifth transistor T5 and a sixth transistor T6; the control terminal of the fifth transistor T5 is connected to the second brush control node Bn, the first terminal of the fifth transistor T5 is connected to the output terminal of the drive output module 130, and the second terminal of the fifth transistor T5 is connected to the first terminal of the sixth transistor T6; the control terminal of the sixth transistor T6 is connected to the output terminal of the stage transmission output module 120, and the second terminal of the sixth transistor T6 is connected to the first brush control node An.

[0046] For example, Figure 3 A timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 and Figure 3 As shown, from Figure 3It can be seen that level n-1 is a non-refreshing row, and the current level is a refreshing row. When the non-refreshing row switches to the refreshing row, for level n-1, during the working period (t2~t3), the first refresh control terminal SW1 outputs a high-level signal, and the second refresh control terminal SW2 outputs a low-level signal. The first transistor T1 will be turned on, the second transistor T2 will be turned off, the third transistor T3 will be turned off, and the fourth transistor T4 will be turned on. The first transistor T1 pulls the second refresh control node to the high-level terminal VGH, making the second control signal generated by the second refresh control node Bn-1 a high-level signal. The first refresh control node An-1 will be... The fourth transistor T4 is pulled down to the low-level terminal VSS, making the first control signal generated by the first brush control node An-1 a low-level signal. The control terminal of the fifth transistor T5 will receive the high-level signal from the second brush control node Bn-1 and turn on. The sixth transistor T6 will also receive the stage transmission signal from the (n-1)th stage and turn on. The output terminal of the drive output module 130 will be connected to the first brush control node An-1 through the fifth transistor T5 and the sixth transistor T6, thereby pulling down the output terminal of the drive output module 130 to a low potential. The (n-1)th stage will not output a gate drive signal, thus not refreshing the pixels of the (n-1)th stage. For the current stage, during the current stage's operating period (t3~t4), the first brush control terminal SW1 outputs a high-level signal, the second brush control terminal SW2 outputs a low-level signal, the first transistor T1 will be turned off, the second transistor T2 will be turned on, the third transistor T3 will be turned on, the fourth transistor T4 will be turned off, the first brush control node will be pulled up to a high potential through the second transistor T2, the first control signal generated by the first brush control node An is a high-level signal, the control terminal of the sixth transistor T6 receives the stage transmission signal of the current stage and is turned on, but the third transistor T3 pulls down the second brush control node Bn to a low potential, the voltage generated by the second brush control node Bn is a low-level signal, the fifth transistor T5 will be turned off, the output terminal of the drive output module 130 will be disconnected from the first brush control node An, and the output terminal of the drive output module 130 will output a gate drive signal to refresh the pixels of the current stage.

[0047] For example, Figure 4 Another timing diagram of a gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 and Figure 4 As shown, from Figure 4It can be seen that level n-1 is a refresh row, and the current level is a non-refresh row. When the refresh row switches to a non-refresh row, for level n-1, during the working period (t2~t3) of level n-1, the first refresh control terminal SW1 outputs a low-level signal, and the second refresh control terminal SW2 outputs a high-level signal. The first transistor T1 will be turned off, the second transistor T2 will be turned on, the third transistor T3 will be turned on, and the fourth transistor T4 will be turned off. The first refresh control node An-1 will be pulled up to a high potential through the second transistor T2. The first control signal generated by n-1 is a high-level signal. The control terminal of the sixth transistor T6 receives the transmission signal of the n-1th stage and turns on. However, the third transistor T3 pulls down the second local refresh control node Bn-1 to a low potential. The second control signal generated by the second local refresh control node Bn-1 is a low-level signal. The fifth transistor T5 will be turned off. The output terminal of the drive output module 130 will be disconnected from the first local refresh control node An-1. The output terminal of the drive output module 130 will output a gate drive signal to refresh the pixel of the n-1th stage. For the current stage, the first brush control terminal SW1 outputs a high-level signal, and the second brush control terminal SW2 outputs a low-level signal. The first transistor T1 will turn on, the second transistor T2 will turn off, the third transistor T3 will turn off, and the fourth transistor T4 will turn on. The first transistor T1 pulls the second brush control node Bn up to the high-level terminal VGH. The second control signal generated by the second brush control node Bn is a high-level signal, which pulls the first brush control node An down to the low-level terminal VSS by the fourth transistor T4. The second control signal generated by the first brush control node An... The first control signal is a low-level signal, and the second brush control node Bn generates a high-level signal. The control terminal of the fifth transistor T5 will receive the high-level signal from the second brush control node Bn and turn on. The sixth transistor T6 will also receive the current stage's transmission signal and turn on. The output terminal of the drive output module 130 will be connected to the first brush control node An through the fifth transistor T5 and the sixth transistor T6, thereby pulling down the output terminal of the drive output module 130 to a low potential. The current stage will not output a gate drive signal, thus not refreshing the pixels of the current stage.

[0048] In some embodiments, the pull-up module 110 includes a tenth transistor T10, the control terminal of the tenth transistor T10 and the first terminal of the tenth transistor T10 are respectively connected to the output terminal of the stage transmission module 120 of the nith stage, and the second terminal of the tenth transistor T10 is connected to the drive control node Qn.

[0049] For example, i can be 1, and the output signal of the ni-th stage can be the stage transmission signal of the ni-th stage. When the stage transmission signal of the ni-th stage is received at the control terminal of the tenth transistor T10, the tenth transistor T10 will be turned on to precharge the drive control node Qn so as to generate a voltage on the drive control node Qn.

[0050] In some embodiments, please refer to Figure 2 As shown, the stage transmission module 120 includes: an eighth transistor T8 and a first capacitor C1; the control terminal of the eighth transistor T8 is connected to the drive control node Qn and the first terminal of the first capacitor C1 respectively, the first terminal of the eighth transistor T8 is connected to the clock signal line CKm of the current stage, and the second terminal of the eighth transistor T8 is connected to the second terminal of the first capacitor C1.

[0051] For example, the pull-up module 110 pre-charges the drive control node, that is, pre-charges the first capacitor C1. When the clock signal of the current stage arrives, the voltage on the first capacitor C1 will bootstrap, raising the voltage of the drive control node Qn, ensuring the conduction of the eighth transistor T8, and outputting the stage transmission signal of the current stage. By setting the first capacitor C1, when the output terminal of the drive output module 130 is pulled down to a low potential, the voltage of the drive control node Qn can bootstrap through the first capacitor C1, ensuring the conduction of the eighth transistor T8, thereby ensuring the output of the stage transmission signal.

[0052] In some embodiments, the drive output module 130 includes: a ninth transistor T9 and a second capacitor C2; the control terminal of the ninth transistor T9 is connected to the first terminal of the drive control node Qn and the second capacitor C2 respectively, the first terminal of the ninth transistor T9 is connected to the clock signal line CKm of the current stage, and the second terminal of the ninth transistor T9 is connected to the second terminal of the second capacitor C2.

[0053] For example, when the pull-up module 110 precharges the drive control node Qn, it will also precharge the second capacitor C2. When the clock signal of the current stage arrives, the voltage of the second capacitor C2 will bootstrap the drive control node Qn to ensure that the ninth transistor T9 is turned on and the output gate drive signal refreshes the pixel of the current stage.

[0054] In some embodiments, the gate driving unit 100 further includes a pull-down module 150, which includes an eleventh transistor T11 and a twelfth transistor T12. The control terminal of the eleventh transistor T11 is connected to the first terminal of the eleventh transistor T11 and the output terminal of the stage output module 120 of the nth stage, respectively. The second terminal of the eleventh transistor T11 is connected to the driving control node Qn.

[0055] In some embodiments, the nth-stage gate driving unit 100 further includes a noise reduction module 160, which is connected to the driving control node Qn, the output terminal Fn of the stage transmission output module 120, the output terminal Qn of the driving output module 130, and the low-level terminal VSS, respectively. It is configured to: when the voltage on the driving control node Qn is a low-level signal, pull down the driving control node Qn, the output terminal Fn of the stage transmission output module 120, the output terminal Qn of the driving output module 130, and the low-level terminal VSS to the low-level terminal VSS according to the noise reduction signal, so as to reduce the noise of the driving control node Qn, the output terminal Fn of the stage transmission output module 120, and the output terminal Qn of the driving output module 130.

[0056] For example, when the stage transmission output module 120 of the nith stage outputs the nith stage transmission signal, the eleventh transistor T11 will be turned on to precharge the drive control node Qn so as to generate a voltage at the drive control node Qn. When the clock signal of the current stage arrives, the control stage transmission output module 120 outputs the stage transmission signal and controls the drive output module 130 to output the gate drive signal.

[0057] In some embodiments, Figure 5 A circuit diagram of another gate driving unit 100 provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 5 As shown, the second control submodule 142 includes: a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7; the control terminal of the fifth transistor T5 is connected to the first brush control node, the first terminal of the fifth transistor T5 is connected to the output terminal of the drive output module 130, and the second terminal of the fifth transistor T5 is connected to the first terminal of the sixth transistor T6; the control terminal of the sixth transistor T6 is connected to the second terminal of the seventh transistor T7, and the second terminal of the sixth transistor T6 is connected to the second brush control node; the control terminal of the seventh transistor T7 is connected to the drive control node Qn, and the first terminal of the seventh transistor T7 is connected to the output terminal of the stage transmission output module 120.

[0058] For example, please refer to Figure 3 and Figure 5 As shown, by connecting the seventh transistor T7 to the output terminal of the current stage's output module 120 and the current stage's drive control node Qn, the seventh transistor T7 will only conduct when the current stage outputs a signal and the current stage's drive control node Qn generates a voltage. This ensures that the output terminal of the drive output module 130 is controlled to output a gate drive signal during the current stage's scan period. Figure 3It can be seen that the (n-1)th level is a non-refreshing row, and the current level is a refreshing row. When the non-refreshing row switches to the refreshing row, for the nith level, during the working period (t2~t3) of the (n-1)th level, the first refresh control terminal SW1 outputs a high-level signal, and the second refresh control terminal SW2 outputs a low-level signal. The first transistor T1 will be turned on, the second transistor T2 will be turned off, the third transistor T3 will be turned off, and the fourth transistor T4 will be turned on. The first transistor T1 pulls the second refresh control node Bn-1 up to the high-level terminal VGH, so the second control signal generated by the second refresh control node Bn-1 will be a high-level signal. The first refresh control node An-1 will be pulled down to the low-level terminal VGH by the fourth transistor T4. SS will receive a low-level signal from the first control signal generated by the first brush control node An-1. The control terminal of the fifth transistor T5 will receive a high-level signal from the second brush control node Bn-1 and be turned on. The seventh transistor T7 will also receive the stage transmission signal of the (n-1)th stage and the voltage on the drive control node Qn-1 of the (n-1)th stage and be turned on. This will turn on the sixth transistor T6. The output terminal of the drive output module 130 will be connected to the first brush control node An-1 through the fifth transistor T5 and the sixth transistor T6, thereby pulling down the output terminal of the drive output module 130 to a low potential. The (n-1)th stage will not output a gate drive signal, thus not refreshing the pixels of the (n-1)th stage. For the current stage, during the current stage's operating period (t3~t4), the first brush control terminal SW1 outputs a high-level signal, the second brush control terminal SW2 outputs a low-level signal, the first transistor T1 will be turned off, the second transistor T2 will be turned on, the third transistor T3 will be turned on, and the fourth transistor T4 will be turned off. The first brush control node will be pulled up to a high potential through the second transistor T2. The first control signal generated by the first brush control node An is a high-level signal. The control terminal of the seventh transistor T7 receives the stage transmission signal of the current stage and the voltage on the current stage's drive control node Qn and is turned on, thereby turning on the sixth transistor T6. However, the third transistor T3 pulls the second brush control node Bn down to a low potential. The second control signal generated by the second brush control node Bn is a low-level signal. The fifth transistor T5 will be turned off, the output terminal of the drive output module 130 will be disconnected from the first brush control node An, and the output terminal of the drive output module 130 will output a gate drive signal to refresh the pixels of the current stage.

[0059] For example, please refer to Figure 4 and Figure 5 As shown, from Figure 4It can be seen that level n-1 is a refresh row, and the current level is a non-refresh row. When the refresh row switches to a non-refresh row, for level n-1, during the working period (t2~t3), the first refresh control terminal SW1 outputs a low-level signal, and the second refresh control terminal SW2 outputs a high-level signal. The first transistor T1 will be turned off, the second transistor T2 will be turned on, the third transistor T3 will be turned on, and the fourth transistor T4 will be turned off. The first refresh control node An-1 will be pulled up to a high potential through the second transistor T2. The first control signal generated is a high-level signal. The control terminal of the seventh transistor T7 receives the transmission signal of the (n-1)th stage and the voltage on the drive control node Qn-1 of the (n-1)th stage and turns on, thereby controlling the sixth transistor T6 to turn on. However, the third transistor T3 pulls down the second local refresh control node Bn-1 to a low potential, the fifth transistor T5 will turn off, the output terminal of the drive output module 130 will disconnect from the first local refresh control node An-1, and the output terminal of the drive output module 130 will output a gate drive signal to refresh the pixel of the (n-1)th stage. For the current stage, the first brush control terminal SW1 outputs a high-level signal, and the second brush control terminal SW2 outputs a low-level signal. The first transistor T1 will be turned on, the second transistor T2 will be turned off, the third transistor T3 will be turned off, and the fourth transistor T4 will be turned on. The first transistor T1 pulls the second brush control node Bn up to the high-level terminal VGH, resulting in a high-level second control signal generated by the second brush control node Bn. The first brush control node An will be pulled down to the low-level terminal VSS by the fourth transistor T4, resulting in a low-level first control signal generated by the first brush control node An. The second control signal generated by Bn is a high-level signal. The control terminal of the fifth transistor T5 will receive the high-level signal from the second local refresh control node Bn and turn on. The control terminal of the seventh transistor T7 will receive the current stage transmission signal and the voltage on the current stage drive control node Qn and turn on, thereby controlling the sixth transistor T6 to turn on. The output terminal of the drive output module 130 will be connected to the first local refresh control node An through the fifth transistor T5 and the sixth transistor T6, thereby pulling down the output terminal of the drive output module 130 to a low potential. The current stage will not output a gate drive signal, thus not refreshing the pixels of the current stage.

[0060] Figure 6 The diagram shows a schematic flow chart of a gate driving method provided in an embodiment of this application. The gate driving circuit and method include the following steps S110 to S140.

[0061] S110, the pull-up module responds to the output signal of the ni-th gate drive unit and charges the drive control node.

[0062] S120, the stage transmission module outputs the stage transmission signal under the action of the voltage on the drive control node and the clock signal of the current stage.

[0063] S130, the drive output module outputs a gate drive signal under the action of the voltage on the drive control node and the clock signal of the current stage.

[0064] S140, in partial refresh mode, if the current level is a refresh row, the control module controls the drive output module to output the gate drive signal; if the current level is a non-refresh row, the control module controls the drive output module to stop outputting the gate drive signal.

[0065] In some embodiments, the stage transmission module includes an eighth transistor and a first capacitor. When the drive output module stops outputting the gate drive signal, the stage transmission module outputs a stage transmission signal under the action of the voltage on the drive control node and the clock signal of the current stage, including: the eighth transistor outputs a stage transmission signal under the action of the voltage on the first capacitor and the clock signal of the current stage; wherein the voltage on the drive control node is stored in the first capacitor.

[0066] In the method embodiments of this application, the working principle of the gate driving method is the same as that of the gate driving circuit, and will not be described again here.

[0067] In some embodiments, this application also provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive output module of the gate driving circuit is connected to at least one scan line.

[0068] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0069] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0070] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the drive control node, is configured to charge the drive control node in response to the output signal of the nith gate drive unit. The stage transmission module is connected to the drive control node and the clock signal line of the current stage, respectively, and is configured to output the stage transmission signal under the action of the voltage on the drive control node and the clock signal of the current stage. The drive output module is connected to the drive control node and the clock signal line of the current stage, respectively, and is configured to output a gate drive signal under the action of the voltage on the drive control node and the clock signal of the current stage. The local control module includes a first control submodule and a second control submodule; The first control submodule, having a first local refresh control node and a second local refresh control node, is configured to: generate a first control signal at the first local refresh control node and generate a second control signal at the second local refresh control node in local refresh mode; wherein the voltage polarities of the first control signal and the second control signal are opposite. The second control submodule is connected to the output terminals of the first local refresh control node, the second local refresh control node, and the drive output module, respectively, and is configured to: if the current level is a refresh row, control the drive output module to output the gate drive signal under the action of the first control signal and the second control signal; if the current level is a non-refresh row, control the drive output module to stop outputting the gate drive signal under the action of the first control signal and the second control signal.

2. The gate driving circuit according to claim 1, characterized in that, The first control submodule includes: a first transistor, a second transistor, a third transistor, and a fourth transistor; The control terminal of the first transistor is connected to the first brush control terminal, the first terminal of the first transistor and the first terminal of the second transistor are connected to the high-level terminal, and the second terminal of the first transistor, the first terminal of the third transistor, and the control terminal of the fourth transistor are connected to the second brush control node. The control terminal of the second transistor is connected to the control terminal of the second brush, and the second terminal of the second transistor is connected to the control terminal of the third transistor and the first terminal of the fourth transistor at the first brush control node. The second terminal of the third transistor and the second terminal of the fourth transistor are connected to the low-level terminal.

3. The gate driving circuit according to claim 1, characterized in that, The second control submodule includes: a fifth transistor and a sixth transistor; The control terminal of the fifth transistor is connected to the second local brush control node, the first terminal of the fifth transistor is connected to the output terminal of the drive output module, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor. The control terminal of the sixth transistor is connected to the output terminal of the stage transmission module, and the second terminal of the sixth transistor is connected to the first local brush control node.

4. The gate driving circuit according to claim 1, characterized in that, The second control submodule includes: a fifth transistor, a sixth transistor, and a seventh transistor; The control terminal of the fifth transistor is connected to the second local brush control node, the first terminal of the fifth transistor is connected to the output terminal of the drive output module, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor. The control terminal of the sixth transistor is connected to the second terminal of the seventh transistor, and the second terminal of the sixth transistor is connected to the first local brush control node; The control terminal of the seventh transistor is connected to the drive control node, and the first terminal of the seventh transistor is connected to the output terminal of the stage transmission module.

5. The gate driving circuit according to claim 1, characterized in that, The stage transmission module includes: an eighth transistor and a first capacitor; The control terminal of the eighth transistor is connected to the drive control node and the first terminal of the first capacitor, the first terminal of the eighth transistor is connected to the clock signal line of the current stage, and the second terminal of the eighth transistor is connected to the second terminal of the first capacitor.

6. The gate driving circuit according to claim 1, characterized in that, The drive output module includes: a ninth transistor and a second capacitor; The control terminal of the ninth transistor is connected to the drive control node and the first terminal of the second capacitor, the first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor is connected to the second terminal of the second capacitor.

7. A gate driving method, characterized in that, Applied to the gate drive circuit according to any one of claims 1-6, the method comprises: The pull-up module responds to the output signal of the nith gate drive unit and charges the drive control node. Under the influence of the voltage on the drive control node and the clock signal of the current stage, the stage transmission module outputs the stage transmission signal; The drive output module outputs a gate drive signal under the influence of the voltage at the drive control node and the clock signal of the current stage; In partial refresh mode, if the current level is a refresh row, the local refresh control module controls the drive output module to output the gate drive signal; if the current level is a non-refresh row, the drive output module controls the drive output module to stop outputting the gate drive signal.

8. The gate driving method according to claim 7, characterized in that, The stage transmission output module includes an eighth transistor and a first capacitor. When the drive output module stops outputting the gate drive signal, the stage transmission output module outputs a stage transmission signal under the action of the voltage on the drive control node and the clock signal of the current stage, including: The eighth transistor outputs a transmission signal under the action of the voltage on the first capacitor and the clock signal of the current stage; wherein, the voltage on the drive control node is stored in the first capacitor.

9. A display panel, comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-6, wherein the driving output module of the gate driving circuit is connected to at least one of the scan lines.

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