A gate driving circuit and a display panel

Abstract

Embodiments of the present application provide a gate drive circuit and a display panel. A cascade output unit outputs a cascade signal with a low level through a cascade signal output end. A display output unit outputs a high level scanning signal through a scanning signal output end. In this way, the output of the scanning signal of the current stage can be controlled on the basis of ensuring stable downward transmission of the cascade signal. The possibility of unstable or failure of the GOA drive cascade signal caused by the excessive driving load of the AA part of the display panel in the gate drive circuit is reduced, and the driving performance of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a gate driving circuit and a display panel. Background Technology

[0002] With the increasing application of Organic Light-Emitting Diode (OLED) technology to medium and large-sized display panels for notebook computers and information technology (IT) applications, it has become crucial to design a system that can reduce the effective display (AA) driving load and power consumption of the array substrate gate driver (GOA). Summary of the Invention

[0003] The purpose of this application is to provide a gate driving circuit and a display panel. The specific technical solution is as follows:

[0004] On one hand, embodiments of this application provide a gate driving circuit, including multiple cascaded gate driving sub-circuits, wherein the gate driving sub-circuits include:

[0005] It includes multiple cascaded gate drive sub-circuits, wherein the gate drive sub-circuit includes:

[0006] Input control unit, cascaded output unit, display output unit;

[0007] The first terminal of the input control unit is connected to the cascade signal output terminal of the previous stage gate drive sub-circuit, and the control terminal of the input control unit is connected to the first clock signal; the first input terminal of the cascaded output unit is connected to the first high voltage signal; the second input terminal of the cascaded output unit is connected to the low voltage signal; the first input terminal of the display output unit is connected to the second high voltage signal, and the second input terminal of the display output unit is connected to the low voltage signal.

[0008] When the first clock signal is valid and the cascade signal received from the previous stage gate drive sub-circuit is low, the cascade output unit outputs the low voltage signal through the cascade signal output terminal, and the display output unit outputs the second high voltage signal through the scan signal output terminal.

[0009] When the first clock signal is invalid and / or the received cascade signal of the previous stage gate driver sub-circuit is high, the cascade output unit outputs the first high voltage signal through the cascade signal output terminal, and the display output unit outputs the low voltage signal through the scan signal output terminal.

[0010] In one possible embodiment, the circuit further includes:

[0011] Input control unit, first output node unit, second output control unit, second output node unit, voltage regulation and isolation control unit, first energy storage unit, second energy storage unit, output pull-down enhancement unit; first node, second node, third node, fourth node;

[0012] The first terminal of the input control unit is connected to the cascade signal output terminal of the previous stage gate drive sub-circuit, and the control terminal of the input control unit is connected to the first clock signal.

[0013] The second end of the input control unit, the first end of the first output node unit, and the control end of the second output control unit are all connected to the first node.

[0014] The second end of the first output node unit, the control end of the second output node unit, the second control end of the cascaded output unit, and the first end of the second energy storage unit are all connected to the second node.

[0015] The second terminal of the second output control unit, the second terminal of the second output node unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, and the first control terminal of the display output unit are all connected to the third node;

[0016] The second terminal of the voltage regulation and isolation control unit, the control terminal of the output pull-down enhancement unit, and the second control terminal of the display output unit are all connected to the fourth node;

[0017] The control terminal of the first output node unit is connected to the first valid signal;

[0018] The control terminal of the voltage stabilizing and isolating control unit is connected to a second valid signal;

[0019] The first terminal of the second output control unit, the second input terminal of the cascaded output unit, and the second input terminal of the display output unit are all connected to a low voltage signal;

[0020] The first terminal of the second output node unit and the first input terminal of the cascaded output unit are both connected to the first high voltage signal;

[0021] The first terminal of the first energy storage unit and the first input terminal of the display output unit are both connected to the second high voltage signal;

[0022] The first terminal of the output pull-down enhancement unit is connected to the second clock signal;

[0023] The output terminal of the cascaded output unit and the second terminal of the second energy storage unit are connected to the cascade signal output terminal of the gate drive sub-circuit of this stage;

[0024] The output terminal of the display output unit is connected to the scan signal output terminal of the gate drive sub-circuit of this stage;

[0025] The second high voltage is not greater than the first high voltage;

[0026] When the first clock signal is valid and the received cascade signal from the previous stage gate driver sub-circuit is low, the second high voltage signal forms a path with the first input terminal of the display output unit, and the low voltage signal forms a path with the second input terminal of the cascaded output unit; when the low voltage signal does not form a path with the second input terminal of the display output unit, and the first high voltage signal does not form a path with the first input terminal of the cascaded output unit; the cascaded output unit outputs the low voltage signal through the cascade signal output terminal, and the display output unit outputs the second high voltage signal through the scan signal output terminal;

[0027] When the first clock signal is invalid and / or the received cascade signal from the previous stage gate driver sub-circuit is high, the second high voltage does not form a path with the first input terminal of the display output unit, and the low voltage signal does not form a path with the second input terminal of the cascade output unit; the low voltage signal forms a path with the second input terminal of the display output unit, and the first high voltage signal forms a path with the first input terminal of the cascade output unit; the cascade output unit outputs the first high voltage signal through the cascade signal output terminal, and the display output unit outputs the low voltage signal through the scan signal output terminal.

[0028] In one possible embodiment, both the first valid signal and the second valid signal are low-level signals; the control terminal of the first output node unit and the control terminal of the voltage regulation and isolation control unit are both connected to the low-voltage signals;

[0029] or,

[0030] Both the first valid signal and the second valid signal are high-level signals;

[0031] The control terminal of the first output node unit and the control terminal of the voltage regulation and isolation control unit are both connected to the first high voltage signal or the second high voltage signal.

[0032] In one possible embodiment, the second output control unit includes a third transistor;

[0033] The control terminal of the third transistor is connected to the second terminal of the input control unit, the first terminal of the first output node unit, and the first node.

[0034] The first terminal of the third transistor is connected to the second input terminal of the cascaded output unit, the second input terminal of the display output unit, and the low voltage signal.

[0035] The second terminal of the third transistor is connected to the second terminal of the second output node unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, the first control terminal of the display output unit, and the third node.

[0036] The third transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

[0037] In one possible embodiment, the third transistor is an N-type transistor.

[0038] In one possible embodiment, the second output node unit includes a fourth transistor;

[0039] The control terminal of the fourth transistor is connected to the second terminal of the first output node unit, the second control terminal of the cascaded output unit, the first terminal of the second energy storage unit, and the second node.

[0040] The first terminal of the fourth transistor is connected to the first input terminal and the first high-voltage signal of the cascaded output unit.

[0041] The second terminal of the fourth transistor is connected to the second terminal of the second output control unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, the first control terminal of the display output unit, and the third node;

[0042] The fourth transistor is configured to turn on when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and not turn on when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

[0043] In one possible embodiment, the cascaded output unit includes a fifth transistor and a sixth transistor;

[0044] The first terminal of the fifth transistor is connected to the first terminal of the second output control unit, the second input terminal of the display output unit, and the low voltage signal.

[0045] The control terminal of the fifth transistor is connected to the second terminal of the first output node unit, the control terminal of the second output node unit, the first terminal of the second energy storage unit, and the second node.

[0046] The control terminal of the sixth transistor is connected to the second terminal of the second output control unit, the second terminal of the second output node unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, the first control terminal of the display output unit, and the third node;

[0047] The second terminal of the sixth transistor is connected to the first terminal of the second output node unit and the first high-voltage signal.

[0048] The first terminal of the sixth transistor, the second terminal of the fifth transistor, and the second terminal of the second energy storage unit are connected to the stage transmission signal output terminal of the gate drive sub-circuit of this stage;

[0049] The fifth transistor is configured to turn on when the first clock signal is valid and the received stage transmission signal of the previous stage gate driving sub-circuit is low; and not turn on when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driving sub-circuit is high.

[0050] The sixth transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

[0051] In one possible embodiment, the output pull-down enhancement unit includes an eighth transistor and a third capacitor;

[0052] The control terminal of the eighth transistor, the first terminal of the third capacitor, the second terminal of the voltage regulation and isolation control unit, the second control terminal of the display output unit, and the fourth node are connected;

[0053] The first terminal of the eighth transistor is connected to the second terminal of the third capacitor;

[0054] The second terminal of the eighth transistor is connected to the second clock signal;

[0055] The eighth transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

[0056] In one possible embodiment, the display output unit includes a ninth transistor and a tenth transistor;

[0057] The control terminal of the ninth transistor is connected to the second terminal of the voltage regulation and isolation control unit, the control terminal of the output pull-down enhancement unit, and the fourth node;

[0058] The first terminal of the ninth transistor is connected to the first terminal of the second output control unit, the second input terminal of the cascaded output unit, and the low voltage signal.

[0059] The control terminal of the tenth transistor is connected to the second terminal of the second output control unit, the second terminal of the second output node unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, and the third node.

[0060] The second terminal of the tenth transistor is connected to the first terminal of the first energy storage unit and the second high-voltage signal.

[0061] The second terminal of the ninth transistor and the first terminal of the tenth transistor are connected to the scan signal output terminal of the gate drive sub-circuit of this stage;

[0062] The tenth transistor is configured to be turned on when the first clock signal is an active signal and the received stage transmission signal of the previous stage gate driving sub-circuit is low; and not to be turned on when the first clock signal is an inactive signal and / or the received stage transmission signal of the previous stage gate driving sub-circuit is high.

[0063] The ninth transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

[0064] On the other hand, this application also provides a display panel including the gate driving circuit described in any of the above claims.

[0065] Beneficial effects of the embodiments in this application:

[0066] This application provides a gate driving circuit and a display panel. When the first clock signal is valid, the input control unit is turned on. The cascade signal of the previous stage gate driving sub-circuit can be connected to the gate driving circuit through the input control unit. When the input control unit is turned on and the cascade signal of the previous stage gate driving sub-circuit is low, the second high voltage forms a path with the first input terminal of the display output unit, and the low voltage forms a path with the second input terminal of the cascaded output unit. When the low voltage does not form a path with the second input terminal of the display output unit, the first high voltage does not form a path with the first input terminal of the cascaded output unit. The cascaded output unit outputs a low-level cascade signal through the cascade signal output terminal, and the display output unit outputs a high-level scan signal through the scan signal output terminal. In this way, the output of the scan signal of this stage can be controlled while ensuring the stable transmission of the cascade signal. This reduces the possibility of unstable or failed GOA driving cascade signal due to excessive driving load of the AA part of the display panel in the gate driving circuit, which is beneficial to improving the driving performance of the display panel.

[0067] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0068] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0069] Figure 1 A schematic diagram of a gate driving circuit provided in an embodiment of this application;

[0070] Figure 2 A schematic diagram of the structure of the nth-stage gate driving sub-circuit of the gate driving circuit provided in an embodiment of this application;

[0071] Figure 3 This is another schematic diagram of the structure of the nth-stage gate driving sub-circuit of the gate driving circuit provided in the embodiments of this application;

[0072] Figure 4 Provided for the embodiments of this application Figure 3 A waveform diagram of each node in the gate driver sub-circuit;

[0073] Figure 5 Provided for the embodiments of this application Figure 3 The base output waveform of the gate driver circuit. Detailed Implementation

[0074] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0075] like Figure 1 As shown, Figure 1 This is a schematic diagram of the gate driving circuit provided in an embodiment of this application. The gate driving circuit provided in this application includes multiple cascaded gate driving sub-circuits. Figure 1 In this diagram, CK1 is the first clock signal, CK2 is the second clock signal, CR is the cascade signal, and OUT_AA is the scan signal. Taking the cascaded gate driver sub-circuits from the first to the (n+2)th stage as an example, GOA1 is the first stage gate driver sub-circuit, GOA2 is the second stage gate driver sub-circuit, GOAn is the nth stage gate driver sub-circuit, and GOAn+2 is the (n+2)th stage gate driver sub-circuit. While the first to (n+2)th stage gate driver sub-circuits sequentially output their respective cascade signals, they can also output their respective scan signals OUT_AA through the display output unit. For example, while the first stage gate driver sub-circuit outputs its cascade signal CR(1), the display output unit outputs its respective scan signal OUT_AA(1). Similarly, while the nth stage gate driver sub-circuit outputs its cascade signal CR(n), the display output unit outputs its respective scan signal OUT_AA(n). AA(n) represents the corresponding display area. OUT_AA(n) is used to drive AA(n).

[0076] In this application, the gate control signal output by the current stage gate driver sub-circuit serves as the gate control signal for the next stage gate driver sub-circuit, and the gate control signal of the first stage gate driver sub-circuit is the input start signal STV. The gate control signal output by the current stage gate driver sub-circuit is transmitted to the next stage gate driver sub-circuit.

[0077] This application provides a gate driving circuit, including multiple cascaded gate driving sub-circuits, wherein the gate driving sub-circuits include:

[0078] Input control unit, cascaded output unit, display output unit;

[0079] The first terminal of the input control unit is connected to the cascade signal output terminal of the previous stage gate drive sub-circuit, and the control terminal of the input control unit is connected to the first clock signal; the first input terminal of the cascade output unit is connected to the first high voltage signal; the second input terminal of the cascade output unit is connected to the low voltage signal; the first input terminal of the display output unit is connected to the second high voltage signal, and the second input terminal of the display output unit is connected to the low voltage signal.

[0080] When the first clock signal is valid and the cascade signal received from the previous stage gate driver sub-circuit is low, the cascade output unit outputs a low voltage signal through the cascade signal output terminal, and the display output unit outputs a second high voltage signal through the scan signal output terminal.

[0081] When the first clock signal is invalid and / or the received cascade signal from the previous stage gate driver circuit is high, the cascade output unit outputs a first high voltage signal through the cascade signal output terminal, and the display output unit outputs a low voltage through the scan signal output terminal.

[0082] When the first clock signal is valid, the input control unit is turned on. The transmission signal of the previous stage gate drive sub-circuit can be connected to the gate drive circuit through the input control unit. When the input control unit is turned on and the transmission signal of the previous stage gate drive sub-circuit is low, the second high voltage forms a path with the first input terminal of the display output unit, and the low voltage forms a path with the second input terminal of the cascaded output unit. When the low voltage does not form a path with the second input terminal of the display output unit, the first high voltage does not form a path with the first input terminal of the cascaded output unit. The cascaded output unit outputs a low-level transmission signal through the transmission signal output terminal, and the display output unit outputs a high-level scan signal through the scan signal output terminal. In this way, the output of the scan signal of this stage can be controlled while ensuring the stable transmission of the transmission signal. This reduces the possibility of unstable or failed GOA drive transmission signals caused by excessive drive load on the AA part of the display panel in the gate drive circuit, which is beneficial to improving the driving performance of the display panel.

[0083] like Figure 2 As shown, this application embodiment provides a gate driving circuit, including multiple cascaded gate driving sub-circuits, wherein the gate driving sub-circuit includes:

[0084] Input control unit 01, first output node unit 02, second output control unit 03, second output node unit 04, cascaded output unit 06, voltage regulation and isolation control unit 09, first energy storage unit 08, second energy storage unit 05, output pull-down enhancement unit 10, display output unit 07; first node N1, second node N2, third node N3, fourth node N4;

[0085] The first terminal of the input control unit 01 is connected to the stage transmission signal output terminal of the previous stage gate drive sub-circuit, and the control terminal of the input control unit 01 is connected to the first clock signal CK1.

[0086] The second terminal of the input control unit 01, the first terminal of the first output node unit 02, and the control terminal of the second output control unit 03 are all connected to the first node.

[0087] The second end of the first output node unit 02, the control end of the second output node unit 04, the second control end of the cascaded output unit 06, and the first end of the second energy storage unit 05 are all connected to the second node.

[0088] The second terminal of the second output control unit 03, the second terminal of the second output node unit 04, the first control terminal of the cascaded output unit 06, the first terminal of the voltage regulation and isolation control unit 09, the second terminal of the first energy storage unit 08, and the first control terminal of the display output unit 07 are all connected to the third node.

[0089] The second terminal of the voltage regulation and isolation control unit 09, the control terminal of the output pull-down enhancement unit 10, and the second control terminal of the display output unit 07 are all connected to the fourth node;

[0090] The control terminal of the first output node unit 02 is connected to the first valid signal;

[0091] The control terminal of the voltage stabilizing and isolating control unit 09 is connected to the second valid signal;

[0092] The first terminal of the second output control unit 03, the second input terminal of the cascaded output unit 06, and the second input terminal of the display output unit 07 are all connected to the low voltage signal VGL.

[0093] The first terminal of the second output node unit 04 and the first input terminal of the cascaded output unit 06 are both connected to the first high voltage signal VGH1.

[0094] The first terminal of the first energy storage unit 08 and the first input terminal of the display output unit 07 are both connected to the second high voltage signal VGH2.

[0095] The first terminal of the output pull-down enhancement unit 10 is connected to the second clock signal CK2;

[0096] The output terminal of the cascaded output unit 06 and the second terminal of the second energy storage unit 05 are connected to the cascade signal output terminal of the gate drive sub-circuit of this stage;

[0097] The output terminal of the display output unit 07 is at least connected to the scan signal output terminal of the gate drive sub-circuit of this stage;

[0098] The second highest voltage is no greater than the first highest voltage.

[0099] Figure 2 yes Figure 1 The diagram shows the structure of the nth stage gate driver sub-circuit (GOAn), where CR(n-1) is the stage transmission signal output by the previous stage gate driver sub-circuit, i.e., the stage transmission signal output by the (n-1)th stage gate driver sub-circuit.

[0100] Optionally, this application may include at least two clock signals, two high-voltage signals, and one low-voltage signal. The first clock signal CK1 and the second clock signal CK2 are clock signals with the same frequency, equal duty cycle, and a phase difference. In one example, the phase difference between CK1 and CK2 can be 180°.

[0101] The first output node unit is connected to the first valid signal, and the voltage regulation and isolation control unit is connected to the second valid signal. In the gate control circuit, the first output node unit and the voltage regulation and isolation control unit are always in a conducting state. The first valid signal can be a high-level signal or a low-level signal, and the second valid signal can be a high-level signal or a low-level signal.

[0102] The first valid signal and the second valid signal can be signals from the same signal source, or signals from different signal sources, depending on the specific circumstances. When the first valid signal and the second valid signal are signals from the same signal source, the number of signal sources can be reduced, thus reducing wiring.

[0103] In one possible embodiment, both the first valid signal and the second valid signal are low-level signals; the control terminal of the first output node unit and the control terminal of the voltage regulation and isolation control unit are both connected to low-voltage signals.

[0104] In one possible embodiment, both the first valid signal and the second valid signal are high-level signals; the control terminal of the first output node unit and the control terminal of the voltage regulation and isolation control unit are both connected to the first high-voltage signal.

[0105] In one possible embodiment, both the first valid signal and the second valid signal are high-level signals; the control terminal of the first output node unit and the control terminal of the voltage regulation and isolation control unit are both connected to the second high-voltage signal.

[0106] When CK1 is a valid signal, and the received cascade signal from the previous stage gate driver sub-circuit is low, the input control unit, the first output node unit, the second output node unit, and the voltage regulation and isolation control unit are turned on, while the second output control unit and the output pull-down enhancement unit are not turned on. The second high voltage forms a path with the first input terminal of the display output unit, and the low voltage signal forms a path with the second input terminal of the cascaded output unit. The low voltage signal does not form a path with the second input terminal of the display output unit, and the first high voltage signal does not form a path with the first input terminal of the cascaded output unit. The cascaded output unit outputs VGL through the cascade signal output terminal, and the display output unit outputs VGH2 through the scan signal output terminal.

[0107] When the first clock signal is invalid and / or the received cascade signal from the previous stage gate driver sub-circuit is of type two, the second high voltage does not form a path with the first input terminal of the display output unit, and the low voltage signal does not form a path with the second input terminal of the cascade output unit; when the low voltage signal forms a path with the second input terminal of the display output unit, and the first high voltage signal forms a path with the first input terminal of the cascade output unit; the cascade output unit outputs VGH1 through the cascade signal output terminal, and the display output unit outputs VGL through the scan signal output terminal.

[0108] In one example, when the cascade signal is low and CK1 is active, the input control unit is turned on, node N1 writes a low-level signal, the first output node unit turns on in response to the control of the first active signal, node N2 writes a low-level signal, the second output control unit does not turn on in response to the low-level signal of node N1, and the second output node unit turns on in response to the low-level signal of node N2. This, in turn, the first high-voltage signal VGH1 controls the potential of node N3. In response to the high-level signal written to node N3, the first input terminal of the display output unit forms a path with VGH2. Because the second output control unit is not turned on, and in response to the high-level signal written to node N3, the first input terminal of the cascade output unit does not form a path with VGH1. Because node N2 writes a low-level signal, in response to the low-level signal written to node N2, the second input terminal of the cascade output unit forms a path with VGL, and the output terminal of the cascade output unit outputs the VGL signal. In response to the voltage regulation isolation control unit being turned on and the N3 node being written with a high-level signal, the output pull-down enhancement unit is not turned on, the second input terminal of the display output unit does not form a path with VGL, and the output terminal of the display output unit outputs VGH2.

[0109] When the cascade signal is high and / or CK1 is invalid, node N1 is high. The first output node unit turns on in response to the control of the first valid signal, node N2 writes a high-level signal, the second output control unit turns on in response to the high-level signal of node N1, and the second output node unit does not turn on in response to the high-level signal of node N2. Consequently, the low-voltage signal VGL controls the potential of node N3. In response to the low-level signal written to node N3, the first input terminal of the display output unit does not form a path with VGH2 because the second output control unit turns on. Also, in response to the low-level signal written to node N3, the first input terminal of the cascade output unit forms a path with VGH1. Because node N2 writes a high-level signal, the second input terminal of the cascade output unit does not form a path with VGL, and the output terminal of the cascade output unit outputs the VGH1 signal. In response to the voltage regulation isolation control unit turning on and the low-level signal written to node N3, the output pull-down enhancement unit turns on, the second input terminal of the display output unit forms a path with VGL, and the output terminal of the display output unit outputs VGL. This allows for control of the output of the scanning signal at this stage while ensuring stable transmission of the stage transmission signal. It also reduces the possibility of unstable or failed GOA drive stage transmission signals caused by excessive drive load on the AA section of the display panel, thus improving the driving performance of the display panel.

[0110] In one possible embodiment, the input control unit 01 includes a first transistor T1;

[0111] The first terminal of the first transistor T1 is connected to the stage transmission signal output terminal of the previous stage gate drive sub-circuit, and the control terminal of the first transistor T1 is connected to the first clock signal CK1; the second terminal of the first transistor T1 is connected to the first terminal of the first output node unit 02, the control terminal of the second output control unit 03, and the first node.

[0112] When the first clock signal CK1 is valid, the first transistor T1 responds to the control of the valid signal and is responsible for transmitting the stage transmission signal output from the stage transmission signal output terminal of the previous stage gate driver sub-circuit to the node, thereby realizing the start-up of the current stage gate driver sub-circuit.

[0113] For the first transistor T1 of the first-stage gate drive sub-circuit, the first terminal of the first transistor T1 is connected to the start signal.

[0114] The first transistor T1 can be either a P-type transistor or an N-type transistor. In one example, if the first transistor T1 is a P-type transistor, then when CK1 is a low-level signal, the first transistor T1 is turned on, and when CK1 is a high-level signal, the first transistor T1 is not turned on.

[0115] In one possible embodiment, the first output node unit 02 includes a second transistor T2, and the first terminal of the second transistor T2 is connected to the second terminal of the input control unit 01, the control terminal of the second output control unit 03, and the first node.

[0116] The second terminal of the second transistor T2 is connected to the control terminal of the second output node unit 04, the second control terminal of the cascaded output unit 06, the first terminal of the second energy storage unit 05, and the second node.

[0117] The control terminal of the second transistor T2 is connected to the first valid signal.

[0118] The second transistor T2 can be either a P-type transistor or an N-type transistor. Transistor T2 needs to control the potential of the N2 node, maintain its on state, and continuously receive a valid signal at its control terminal. When transistor T2 is a P-type transistor, its control terminal is connected to a low-level signal; when transistor T2 is an N-type transistor, its control terminal is connected to a high-level signal.

[0119] In one example, the second transistor T2 is a P-type transistor; the first active signal is VGL. In another example, the second transistor T2 is an N-type transistor; the first active signal is either VGH1 or VGH2.

[0120] In one possible embodiment, the second output control unit 03 includes a third transistor T3;

[0121] The control terminal of the third transistor T3 is connected to the second terminal of the input control unit 01, the first terminal of the first output node unit 02, and the first node.

[0122] The first terminal of the third transistor T3 is connected to the second input terminal of the cascaded output unit 06, the second input terminal of the display output unit 07, and the low voltage signal VGL.

[0123] The second terminal of the third transistor T3 is connected to the second terminal of the second output node unit 04, the first control terminal of the cascaded output unit 06, the first terminal of the voltage regulation and isolation control unit 09, the second terminal of the first energy storage unit 08, the first control terminal of the display output unit 07, and the third node.

[0124] The third transistor is an N-type transistor, configured to not conduct when the first clock signal is valid and the received cascade signal from the previous stage gate driver circuit is low; and to conduct when the first clock signal is invalid and / or the received cascade signal from the previous stage gate driver circuit is high. The third transistor T3 is used to control node N3 to write a low level when the first clock signal is invalid and / or the received cascade signal from the previous stage gate driver circuit is high, thereby controlling the cascaded output unit to output a first high-voltage signal through the cascade signal output terminal, and the display output unit to output a low-voltage signal through the scan signal output terminal.

[0125] In one possible embodiment, the second output node unit 04 includes a fourth transistor T4;

[0126] The control terminal of the fourth transistor T4 is connected to the second terminal of the first output node unit 02, the second control terminal of the cascaded output unit 06, the first terminal of the second energy storage unit 05, and the second node.

[0127] The first terminal of the fourth transistor T4 is connected to the first input terminal of the cascaded output unit 06 and the first high voltage signal VGH1.

[0128] The second terminal of the fourth transistor T4 is connected to the second terminal of the second output control unit 03, the first control terminal of the cascaded output unit 06, the first terminal of the voltage regulation and isolation control unit 09, the second terminal of the first energy storage unit 08, the first control terminal of the display output unit 07, and the third node.

[0129] The fourth transistor T4 is configured to turn on when the first clock signal is valid and the cascade signal received from the previous stage gate drive sub-circuit is low, control the N3 node to write a high level, control the cascade output unit to output a low voltage signal through the cascade signal output terminal, and control the display output unit to output a second high voltage signal through the scan signal output terminal.

[0130] It does not conduct when the first clock signal is invalid and / or the received stage transmission signal from the previous stage gate driver circuit is high.

[0131] Transistor T4 is used to control the potential of node N2. Transistor T4 can be a P-type transistor.

[0132] In one possible embodiment, the cascaded output unit 06 includes a fifth transistor T5 and a sixth transistor T6;

[0133] The first terminal of the fifth transistor T5 is connected to the first terminal of the second output control unit 03, the second input terminal of the display output unit 07, and the low voltage signal VGL.

[0134] The control terminal of the fifth transistor T5 is connected to the second terminal of the first output node unit 02, the control terminal of the second output node unit 04, the first terminal of the second energy storage unit 05, and the second node.

[0135] The control terminal of the sixth transistor T6 is connected to the second terminal of the second output control unit 03, the second terminal of the second output node unit 04, the first terminal of the voltage regulation and isolation control unit 09, the second terminal of the first energy storage unit 08, the first control terminal of the display output unit 07, and the third node.

[0136] The second terminal of the sixth transistor T6 is connected to the first terminal of the second output node unit 04 and the first high voltage signal VGH1.

[0137] The first terminal of the sixth transistor T6, the second terminal of the fifth transistor T5, and the second terminal of the second energy storage unit 05 are connected to the stage transmission signal output terminal of the gate drive sub-circuit of this stage;

[0138] The fifth transistor is configured to turn on when the first clock signal is valid and the stage transmission signal received from the previous stage gate drive sub-circuit is low; and not turn on when the first clock signal is invalid and / or the stage transmission signal received from the previous stage gate drive sub-circuit is high.

[0139] The sixth transistor is configured to not conduct when the first clock signal is valid and the stage transmission signal received from the previous stage gate drive sub-circuit is low; and to conduct when the first clock signal is invalid and / or the stage transmission signal received from the previous stage gate drive sub-circuit is high.

[0140] Both the fifth transistor T5 and the sixth transistor T6 are P-type transistors. The fifth transistor T5 and the sixth transistor T6 do not conduct simultaneously. When CK1 is a valid signal and the received stage transmission signal from the previous stage gate drive sub-circuit is low, the sixth transistor T6 is not conducting, and the fifth transistor T5 is conducting. When CK1 is an invalid signal, and / or the received stage transmission signal from the previous stage gate drive sub-circuit is high, the sixth transistor T6 is conducting, and the fifth transistor T5 is not conducting.

[0141] In one possible embodiment, the voltage regulation isolation control unit 09 includes a seventh transistor T7;

[0142] The control terminal of the seventh transistor T7 is connected to the second valid signal;

[0143] The first terminal of the seventh transistor T7 is connected to the second terminal of the second output control unit 03, the second terminal of the second output node unit 04, the first control terminal of the cascaded output unit 06, the second terminal of the first energy storage unit 08, the first control terminal of the display output unit 07, and the third node.

[0144] The second terminal of the seventh transistor T7, the control terminal of the output pull-down enhancement unit 10, and the second control terminal of the display output unit 07 are all connected to the fourth node.

[0145] The seventh transistor, T7, can be either a P-type or an N-type transistor. Transistor T7 needs to control the potential of node N4, maintain its on state, and continuously receive a valid signal at its control terminal. When transistor T7 is a P-type transistor, its control terminal is connected to a low-level signal; when transistor T7 is an N-type transistor, its control terminal is connected to a high-level signal.

[0146] In one example, the seventh transistor T7 is a P-type transistor; the second valid signal is VGL. In another example, the seventh transistor T7 is an N-type transistor; the second valid signal is either VGH1 or VGH2.

[0147] In one possible embodiment, the output pull-down enhancement unit 10 includes an eighth transistor T8 and a third capacitor;

[0148] The control terminal of the eighth transistor T8, the first terminal of the third capacitor, the second terminal of the voltage regulation and isolation control unit 09, the second control terminal of the display output unit 07, and the fourth node are connected;

[0149] The first terminal of the eighth transistor T8 is connected to the second terminal of the third capacitor;

[0150] The second terminal of the eighth transistor T8 is connected to the second clock signal CK2.

[0151] The eighth transistor T8 is configured to not conduct when the first clock signal is an active signal and the stage transmission signal received from the previous stage gate drive sub-circuit is low; and to conduct when the first clock signal is an inactive signal and / or the stage transmission signal received from the previous stage gate drive sub-circuit is high.

[0152] The eighth transistor T8 is a P-type transistor. When node N3 is at a low potential, node N4 is at a low potential. At this time, transistor T8 is turned on. When the second clock signal CK2 is a low-level signal, it can enhance the low potential of node N4, so that transistor T9 is turned on stably, thereby enabling the display output unit to stably output a low voltage signal.

[0153] In one possible embodiment, the display output unit 07 includes a ninth transistor T9 and a tenth transistor T10;

[0154] The control terminal of the ninth transistor T9 is connected to the second terminal of the voltage regulation and isolation control unit 09, the control terminal of the output pull-down enhancement unit 10, and the fourth node;

[0155] The first terminal of the ninth transistor T9 is connected to the first terminal of the second output control unit 03, the second input terminal of the cascaded output unit 06, and the low voltage signal VGL.

[0156] The control terminal of the tenth transistor T10 is connected to the second terminal of the second output control unit 03, the second terminal of the second output node unit 04, the first control terminal of the cascaded output unit 06, the first terminal of the voltage regulation and isolation control unit 09, the second terminal of the first energy storage unit 08, and the third node.

[0157] The second terminal of the tenth transistor T10 is connected to the first terminal of the first energy storage unit 08 and the second high voltage signal VGH2.

[0158] The second terminal of the ninth transistor T9 and the first terminal of the tenth transistor T10 are connected to the scan signal output terminal of the gate drive sub-circuit of this stage;

[0159] The tenth transistor is configured to turn on when the first clock signal is valid and the stage transmission signal received from the previous stage gate drive sub-circuit is low; and not turn on when the first clock signal is invalid and / or the stage transmission signal received from the previous stage gate drive sub-circuit is high.

[0160] The ninth transistor is configured to not conduct when the first clock signal is valid and the stage transmission signal received from the previous stage gate drive sub-circuit is low; and to conduct when the first clock signal is invalid and / or the stage transmission signal received from the previous stage gate drive sub-circuit is high.

[0161] The ninth transistor T9 is a P-type transistor, and the tenth transistor T10 is an N-type transistor. The ninth and tenth transistors do not conduct simultaneously.

[0162] In one possible embodiment, the first energy storage unit includes a capacitor CQ connected between a first control terminal of the display output unit and a first input terminal of the display output unit.

[0163] Capacitor CQ can increase the voltage difference between the control terminal and the first input terminal of the display output unit, ensuring that the first input terminal of the display output unit is smoothly connected to VGH2.

[0164] In one possible embodiment, the second energy storage unit includes a capacitor CP, which is connected between the second control terminal of the cascaded output unit and the cascaded signal output terminal of the cascaded output unit.

[0165] Capacitor CQ can increase the voltage difference between the second control terminal of the cascaded output unit and the output of the cascaded output unit, ensuring that the second input terminal of the cascaded output unit is smoothly connected to VGL.

[0166] Based on the above embodiments, taking the gate driving circuit from the first-stage gate driving sub-circuit to the (n + 3)-stage gate driving sub-circuit in cascade as an example, refer to Figure 3 , the gate driving sub-circuit includes 10 transistors. Among them, both transistor T3 and transistor T10 are N-type transistors, and the rest of the transistors are P-type transistors. CK1 is the first clock signal, and CK2 is the second clock signal. The first clock signal CK1 and the second clock signal CK2 are clock signals with the same frequency, equal duty cycle, and a phase difference. Figure 4 Provided by an embodiment of the present application Figure 3 A waveform diagram of each node of the gate driving sub-circuit, Figure 5 Provided by an embodiment of the present application Figure 3 The basic transmission waveform diagram of the gate driving sub-circuit.

[0167] As Figure 4 shown:

[0168] In the t1 stage:

[0169] When the output CR<n - 1> in the previous cycle is high level and CK1 is low level, transistor T1 conducts, and the N1 node inputs CR <n-1>When the voltage level is high, transistor T2 is normally on, and the input CR at node N2 is... <n-1>When it is at a high level, the transistor T5 is not turned on, that is, the transistor T5 is in a non-conducting state, and VGL cannot be transmitted to the stage transmission signal output terminal through the transistor T5.

[0170] Moreover, since the transistor T3 is an N-type transistor and the N1 node is at a high level, at this time the N3 node is in a low level state, the transistor T6 is turned on, VGH1 is transmitted to the stage transmission signal output terminal through the transistor T6, and the CR(n) output by the stage transmission signal output terminal is at a high level. Because the N4 node is also at a low level, the transistor T9 is turned on. When CK2 is coupled and pulled down, VGL is transmitted to the output terminal of the display output unit through the transistor T9, and OUT_AAn with a low level is output from the output terminal;

[0171] At the t2 stage:

[0172] When the CR<n-1> output in the previous cycle is at a low level and CK1 is at a low level, the transistor T1 is turned on, and the CR is input to the N1 node <n-1>When the voltage level is low, transistor T2 is normally on, and the input CR at node N2 is low. <n-1>When it is at a low level, the transistor T5 is turned on, and VGL is transmitted to the stage transmission signal output terminal through the transistor T5.

[0173] Moreover, since the transistor T3 is an N-type transistor and the N1 node is at a low level, the transistor T4 is turned on at this time. VGH1 controls the N3 node to be in a high-level state, the transistor T6 is not turned on, the transistor T10 is turned on, and VGH2 is transmitted to the output terminal of the display output unit through T10. Because the N4 node is at a high level, the transistor T9 is not turned on, and VGL cannot be transmitted to the output terminal of the display output unit through the transistor T9. OUT_AAn with a high level is output from the output terminal.

[0174] In the t3 stage:

[0175] When the CR<n - 1> output in the previous cycle is at a high level and CK1 is at a low level, the transistor T1 is turned on, and the CR is input to the N1 node <n-1>When the voltage level is high, transistor T2 is normally on, and the input CR at node N2 is... <n-1>When the signal level is high, transistor T5 is not conducting, meaning transistor T5 is in a non-conducting state, and VGL cannot be transmitted to the stage signal output terminal through transistor T5.

[0176] Furthermore, since transistor T3 is an N-type transistor and node N1 is at a high level, node N3 is at a low level, transistor T6 is turned on, and VGH1 is transmitted to the stage signal output terminal through transistor T6. The CR(n) output by the stage signal output terminal is at a high level. Since node N4 is also at a low level, transistor T9 is turned on. At this time, since the low level is not enough to fully turn on transistor T9, the output OUT_AAn is approximately half the low level output when transistor T9 is fully turned on. When CK2 is pulled down by a low level coupling, the output is at a low level, which is the low level output when transistor T9 is fully turned on.

[0177] Furthermore, the Emission (EM) GOA, or gate drive circuit for the light-emitting control array substrate, is a light-emitting timing drive unit integrated on the array substrate of the display panel. It works in conjunction with the scanning GOA to output light-emitting control signals and precisely regulate the timing and duration of pixel light emission. This application uses an EM-type GOA circuit with a hybrid structure of P-type and N-type transistors. Without affecting the performance of the GOA, the GOA circuit outputs a low-level state for a long time. Transistors T3 and T10 use N-type transistors, which have low leakage current. This can reduce the possible leakage behavior of the GOA circuit and improve the driving stability of the GOA.

[0178] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0179] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the display panel embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0180] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A gate driving circuit, characterized in that, It includes multiple cascaded gate drive sub-circuits, wherein the gate drive sub-circuit includes: Input control unit, cascaded output unit, display output unit; The first terminal of the input control unit is connected to the cascade signal output terminal of the previous stage gate drive sub-circuit, and the control terminal of the input control unit is connected to the first clock signal; the first input terminal of the cascaded output unit is connected to the first high voltage signal; the second input terminal of the cascaded output unit is connected to the low voltage signal; the first input terminal of the display output unit is connected to the second high voltage signal, and the second input terminal of the display output unit is connected to the low voltage signal. When the first clock signal is valid and the cascade signal received from the previous stage gate driver sub-circuit is low, the cascade output unit outputs the low voltage signal through the cascade signal output terminal, and the display output unit outputs the second high voltage signal through the scan signal output terminal. When the first clock signal is invalid and / or the received cascade signal of the previous stage gate driver sub-circuit is high, the cascade output unit outputs the first high voltage signal through the cascade signal output terminal, and the display output unit outputs the low voltage signal through the scan signal output terminal.

2. The circuit according to claim 1, characterized in that, The circuit also includes: Input control unit, first output node unit, second output control unit, second output node unit, voltage regulation and isolation control unit, first energy storage unit, second energy storage unit, output pull-down enhancement unit; first node, second node, third node, fourth node; The first terminal of the input control unit is connected to the cascade signal output terminal of the previous stage gate drive sub-circuit, and the control terminal of the input control unit is connected to the first clock signal. The second end of the input control unit, the first end of the first output node unit, and the control end of the second output control unit are all connected to the first node. The second end of the first output node unit, the control end of the second output node unit, the second control end of the cascaded output unit, and the first end of the second energy storage unit are all connected to the second node. The second terminal of the second output control unit, the second terminal of the second output node unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, and the first control terminal of the display output unit are all connected to the third node; The second terminal of the voltage regulation and isolation control unit, the control terminal of the output pull-down enhancement unit, and the second control terminal of the display output unit are all connected to the fourth node; The control terminal of the first output node unit is connected to the first valid signal; The control terminal of the voltage stabilizing and isolating control unit is connected to a second valid signal; The first terminal of the second output control unit, the second input terminal of the cascaded output unit, and the second input terminal of the display output unit are all connected to a low voltage signal; The first terminal of the second output node unit and the first input terminal of the cascaded output unit are both connected to the first high voltage signal; The first terminal of the first energy storage unit and the first input terminal of the display output unit are both connected to the second high voltage signal; The first terminal of the output pull-down enhancement unit is connected to the second clock signal; The output terminal of the cascaded output unit and the second terminal of the second energy storage unit are connected to the cascade signal output terminal of the gate drive sub-circuit of this stage; The output terminal of the display output unit is connected to the scan signal output terminal of the gate drive sub-circuit of this stage; The second high voltage is not greater than the first high voltage; When the first clock signal is valid and the received cascade signal from the previous stage gate driver sub-circuit is low, the second high voltage signal forms a path with the first input terminal of the display output unit, and the low voltage signal forms a path with the second input terminal of the cascaded output unit; when the low voltage signal does not form a path with the second input terminal of the display output unit, and the first high voltage signal does not form a path with the first input terminal of the cascaded output unit; the cascaded output unit outputs the low voltage signal through the cascade signal output terminal, and the display output unit outputs the second high voltage signal through the scan signal output terminal; When the first clock signal is invalid and / or the received cascade signal from the previous stage gate driver sub-circuit is high, the second high voltage does not form a path with the first input terminal of the display output unit, and the low voltage signal does not form a path with the second input terminal of the cascade output unit; the low voltage signal forms a path with the second input terminal of the display output unit, and the first high voltage signal forms a path with the first input terminal of the cascade output unit; the cascade output unit outputs the first high voltage signal through the cascade signal output terminal, and the display output unit outputs the low voltage signal through the scan signal output terminal.

3. The circuit according to claim 2, characterized in that, Both the first valid signal and the second valid signal are low-level signals; the control terminal of the first output node unit and the control terminal of the voltage regulation and isolation control unit are both connected to the low-voltage signal; or, Both the first valid signal and the second valid signal are high-level signals; The control terminal of the first output node unit and the control terminal of the voltage regulation and isolation control unit are both connected to the first high voltage signal or the second high voltage signal.

4. The circuit according to claim 2, characterized in that, The second output control unit includes a third transistor; The control terminal of the third transistor is connected to the second terminal of the input control unit, the first terminal of the first output node unit, and the first node. The first terminal of the third transistor is connected to the second input terminal of the cascaded output unit, the second input terminal of the display output unit, and the low voltage signal. The second terminal of the third transistor is connected to the second terminal of the second output node unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, the first control terminal of the display output unit, and the third node. The third transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

5. The circuit according to claim 4, characterized in that, The third transistor is an N-type transistor.

6. The circuit according to claim 2, characterized in that, The second output node unit includes a fourth transistor; The control terminal of the fourth transistor is connected to the second terminal of the first output node unit, the second control terminal of the cascaded output unit, the first terminal of the second energy storage unit, and the second node. The first terminal of the fourth transistor is connected to the first input terminal and the first high-voltage signal of the cascaded output unit. The second terminal of the fourth transistor is connected to the second terminal of the second output control unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, the first control terminal of the display output unit, and the third node; The fourth transistor is configured to turn on when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and not turn on when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

7. The circuit according to claim 2, characterized in that, The cascaded output unit includes a fifth transistor and a sixth transistor; The first terminal of the fifth transistor is connected to the first terminal of the second output control unit, the second input terminal of the display output unit, and the low voltage signal. The control terminal of the fifth transistor is connected to the second terminal of the first output node unit, the control terminal of the second output node unit, the first terminal of the second energy storage unit, and the second node. The control terminal of the sixth transistor is connected to the second terminal of the second output control unit, the second terminal of the second output node unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, the first control terminal of the display output unit, and the third node; The second terminal of the sixth transistor is connected to the first terminal of the second output node unit and the first high-voltage signal. The first terminal of the sixth transistor, the second terminal of the fifth transistor, and the second terminal of the second energy storage unit are connected to the stage transmission signal output terminal of the gate drive sub-circuit of this stage; The fifth transistor is configured to turn on when the first clock signal is valid and the received stage transmission signal of the previous stage gate driving sub-circuit is low; and not turn on when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driving sub-circuit is high. The sixth transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

8. The circuit according to claim 2, characterized in that, The output pull-down enhancement unit includes an eighth transistor and a third capacitor; The control terminal of the eighth transistor, the first terminal of the third capacitor, the second terminal of the voltage regulation and isolation control unit, the second control terminal of the display output unit, and the fourth node are connected; The first terminal of the eighth transistor is connected to the second terminal of the third capacitor; The second terminal of the eighth transistor is connected to the second clock signal; The eighth transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

9. The circuit according to claim 2, characterized in that, The display output unit includes a ninth transistor and a tenth transistor; The control terminal of the ninth transistor is connected to the second terminal of the voltage regulation and isolation control unit, the control terminal of the output pull-down enhancement unit, and the fourth node; The first terminal of the ninth transistor is connected to the first terminal of the second output control unit, the second input terminal of the cascaded output unit, and the low voltage signal. The control terminal of the tenth transistor is connected to the second terminal of the second output control unit, the second terminal of the second output node unit, the first control terminal of the cascaded output unit, the first terminal of the voltage regulation and isolation control unit, the second terminal of the first energy storage unit, and the third node. The second terminal of the tenth transistor is connected to the first terminal of the first energy storage unit and the second high-voltage signal. The second terminal of the ninth transistor and the first terminal of the tenth transistor are connected to the scan signal output terminal of the gate drive sub-circuit of this stage; The tenth transistor is configured to be turned on when the first clock signal is an active signal and the received stage transmission signal of the previous stage gate driving sub-circuit is low; and not to be turned on when the first clock signal is an inactive signal and / or the received stage transmission signal of the previous stage gate driving sub-circuit is high. The ninth transistor is configured to not conduct when the first clock signal is valid and the received stage transmission signal of the previous stage gate driver sub-circuit is low; and to conduct when the first clock signal is invalid and / or the received stage transmission signal of the previous stage gate driver sub-circuit is high.

10. A display panel, characterized in that, Includes the circuit described in any one of claims 1 to 9.

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