Semiconductor device and operating method thereof, memory device and operating method thereof

Abstract

Embodiments of the present disclosure provide a semiconductor device and an operating method thereof, a memory device and an operating method thereof. The semiconductor device includes: a memory array; the memory array includes a plurality of memory cells; the memory cells are configured to store weight data; a control circuit coupled with the memory array; the control circuit is configured to: perform N write operations to write N same target weight data in the memory array; the selected word lines corresponding to each target weight data are different; N is an integer greater than 1; and perform an operation based on the N target weight data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its operation method, and a storage device and its operation method. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of the above, embodiments of this disclosure provide a semiconductor device and a method for operating the same, as well as a storage device and a method for operating the same.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising: a memory array; the memory array comprising a plurality of memory cells; the memory cells being configured to store weight data; a control circuit coupled to the memory array; the control circuit being configured to: perform N write operations to write N identical target weight data into the memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1; and perform calculations based on the N target weight data.

[0005] In a second aspect, embodiments of this disclosure provide a storage device, including: a memory array; the memory array including a plurality of memory cells; the memory cells being configured to store weight data; and peripheral circuitry coupled to the memory array; the peripheral circuitry being configured to: perform N write operations to write N identical target weight data into the memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1; and output a calculation result based on the N target weight data.

[0006] Thirdly, embodiments of this disclosure provide an operation method for a semiconductor device, including: performing N write operations to write N identical target weight data into a memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1; and performing calculations based on the N target weight data.

[0007] Fourthly, embodiments of this disclosure provide an operation method for a storage device, including: performing N write operations to write N identical target weight data into a memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1; and outputting a calculation result based on the N target weight data.

[0008] In the technical solution provided in this disclosure, the control circuit is configured to: perform N write operations to write N identical target weight data into the memory array; each target weight data corresponds to a different selected word line; and perform calculations based on the N target weight data, so that the N target weight data correspond to multiple input voltages corresponding to the input data, thereby enabling synchronous calculations of multiple elements in the input data with the weight matrix, thereby improving the efficiency of calculation while enhancing the flexibility of calculation. Attached Figure Description

[0009] Figure 1 A schematic diagram of a semiconductor device provided in an embodiment of this application;

[0010] Figure 2 This is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of this application;

[0011] Figure 3A This is a schematic cross-sectional view of a memory array including NAND-type memory strings according to an embodiment of this application;

[0012] Figure 3B This is a perspective view of a memory array including NAND-type memory strings according to an embodiment of this application;

[0013] Figure 4A This is a schematic diagram illustrating an exemplary signal twisting method including peripheral circuitry according to an embodiment of this application;

[0014] Figure 4B This is a schematic diagram of an exemplary memory device including a memory array and peripheral circuitry according to an embodiment of this application;

[0015] Figure 5 This is a schematic diagram of a semiconductor device including a memory array, as described in an embodiment of this application.

[0016] Figure 6A A schematic diagram showing the mapping of an input feature map (IFM) and convolutional kernels to a memory array, provided in an embodiment of this application;

[0017] Figure 6B A schematic diagram of the computation process in a semiconductor device provided in an embodiment of this application;

[0018] Figure 7 A schematic flowchart illustrating an operation method of a semiconductor device provided in an embodiment of this disclosure;

[0019] Figure 8 This is a flowchart illustrating an operation method of a storage device provided in an embodiment of the present disclosure. Detailed Implementation

[0020] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0022] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0024] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0027] As the parameters of large AIGC (Artificial Intelligence Generated Content) models continue to grow, the traditional von Neumann architecture faces the "memory wall" and "power wall" problems. The bandwidth between the central processing unit (CPU) and memory has become a bottleneck restricting the performance of AI chips. Inspired by the working mode of the human brain, in-memory computing architecture has flourished in recent years. By embedding computing functions in memory, it avoids data transfer back and forth, reducing the impact of the memory wall and power wall, and thus has the potential to build high-performance, high-bandwidth, and high-energy-efficiency computing systems. At the same time, the data era places higher demands on storage density, and more bits, such as 4.5 bits, is an effective way to increase storage density. Based on this, semiconductor devices that can simultaneously realize more bits of storage and in-memory computing will be of great significance.

[0028] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their conductivity, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to: Static Random-Access Memory (SRAM), NAND flash memory, NOR flash memory, and Dynamic Random-Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied and important component in IMC chips.

[0029] In this embodiment of the disclosure, the semiconductor device includes a memory array 100 and a control circuit 200 coupled to the memory array 100. The control circuit 200 includes peripheral circuitry 210 and arithmetic circuitry 220, with the arithmetic circuitry 220 coupled to the peripheral circuitry 210. The peripheral circuitry 210 serves as the peripheral circuitry of the memory array 100.

[0030] In some embodiments, the memory array 100, peripheral circuitry 210, and computing circuitry 220 can be formed in parallel on different substrates. For example, the memory array 100 can be formed on a first substrate, the peripheral circuitry 210 on a second substrate, and the computing circuitry 220 on a third substrate. Then, they are stacked on top of each other using various bonding techniques such as hybrid bonding and transfer bonding.

[0031] In this embodiment of the present disclosure, by vertically integrating the memory array 100, peripheral circuit 210, and arithmetic circuit 220, and by vertically separating the memory array 100, peripheral circuit 210, and arithmetic circuit 220 into different planes, the chip size can be reduced and the storage density can be increased.

[0032] In this embodiment of the disclosure, the memory array 100 includes an AND type memory array, a NAND type memory array, or a NOR type memory array.

[0033] The following description uses a three-dimensional NAND flash memory as an example, and a memory array 100 as a three-dimensional NAND flash memory array, to illustrate the memory array 100 and the peripheral circuit 210. Here, the memory array 100 can be referred to as follows: Figures 2 to 4B The memory array 301 described herein can be understood; the peripheral circuit 210 can be referred to as follows. Figure 4A and Figure 4BTo understand the peripheral circuit described.

[0034] Figure 2 A schematic circuit diagram of an exemplary memory device 300 according to some aspects of this application is shown. The memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate. In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0035] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the programming state by writing one of the three possible nominal storage values ​​to the cell, and a fourth nominal storage value can be used for the erase state.

[0036] It should be noted that the storage state mentioned here is the same as the storage state of the storage cell in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has two storage states (i.e., two memory states), which include one programming state and one erase state. Another example is an MLC type storage cell with four storage states, including one erase state and three programming states. Yet another example is a TLC type storage cell with eight storage states, including one erase state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, including one erase state and fifteen programming states.

[0037] like Figure 2 As shown, each memory string 308 may include a lower selection transistor (BSG) 310 (also known as a source-side selection transistor) at its source end and an upper selection transistor (TSG) 312 (also known as a drain-side selection transistor) at its drain end. BSG 310 and TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled through the same source layer (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0038] like Figure 2As shown, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source layer 314 (e.g., coupled to ground). In some implementations, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source layer 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304 can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. Reference Figure 2 Each memory cell 306 in the multiple memory cells is coupled to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 through the corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0039] Figure 3A A schematic cross-sectional view of an exemplary memory array 301, including a memory string 308, exemplified by NAND, is shown according to some aspects of this application. Figure 3A As shown, the NAND memory array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure perpendicularly penetrating the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and adjacent gate layers 411 are separated by an insulating layer 412.

[0040] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer. In some embodiments, the stack 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0041] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0042] Figure 3B This is a perspective view of a memory array including NAND flash memory strings according to an embodiment of this application. Figure 3B As shown, the memory array 301 sequentially includes multiple bit lines BL (e.g., m lines), multiple up-select transistor TSG lines (e.g., p lines), multiple word lines (e.g., n lines), down-select transistor BSG lines, source layer CSL, and multiple memory cells coupled to the word lines.

[0043] Return to reference Figure 2The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source layer 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source layer 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0044] Figure 4A Some exemplary semiconductor devices are shown, with peripheral circuitry including control logic 512, a digital-to-analog converter 501 connected to the control logic 512, and an analog-to-digital converter 502 connected to the memory array 301. The analog-to-digital converter 502 is connected to the control logic 512.

[0045] During the computation phase using semiconductor devices, the digital-to-analog converter circuit 501 converts digital signals into voltage signals required by the memory array 301 in the in-memory computing chip. The analog-to-digital converter circuit 502 converts the current signals output by the memory array 301 into digital signals. The control logic 512 can be coupled to peripheral circuits and configured to control the operation of the peripheral circuits. The control logic 512 can also be used to receive input data sent by the memory controller and send the calculation results to the arithmetic circuit.

[0046] Figure 4B Some exemplary peripheral circuits are shown, except Figure 3A In addition to the structure of the peripheral circuitry shown, the peripheral circuitry includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that it may also include... Figure 3B Additional peripheral circuitry not shown.

[0047] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory array 301 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0048] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source layer voltages to be supplied to memory array 301.

[0049] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 706 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0050] Figure 5 This is a schematic diagram of a semiconductor device including a memory array, as described in an embodiment of this application. During the computation stage using the semiconductor device as a memory computing chip, it is necessary to perform multiplication or multiplication-accumulation operations between the input matrix and the weight matrix. The input matrix can be an input vector or input matrix composed of multiple input data, and the weight matrix consists of multiple weight data. Each input data in the input matrix needs to be multiplied and accumulated with the multiple weight data in the weight matrix to obtain the corresponding element in the output data.

[0051] To achieve the aforementioned computational functions, the memory array can be configured to store weight data. Specifically, the weight data in the weight matrix can be written into the memory array according to a certain mapping rule, and each storage cell in the memory array can be configured to store at least one bit of the weight data. During the computation phase, input data can be received from external devices. Each element in the input data can be converted into an input voltage by a digital-to-analog converter circuit and input to the memory array via word lines / bit lines.

[0052] In some embodiments, the control circuit is configured to: perform multiple write operations to write N identical target weight data into the memory array, where N is an integer greater than 1; and perform calculations based on the N target weight data.

[0053] In this embodiment of the disclosure, writing N target weight data into the memory array allows the N target weight data to correspond to multiple input voltages corresponding to the input data. Thus, the semiconductor device provided in this embodiment of the disclosure can realize the synchronous operation of multiple elements in the input data with the weight matrix. In other words, the input voltages corresponding to multiple elements in the input data can be input simultaneously without sequential input, thereby improving the efficiency of the operation while increasing the flexibility of the operation.

[0054] like Figure 5 As shown, taking two weight data points w1 and w2 in the weight matrix as an example, four write operations are performed on weight data w1 to write four target weight data points w into the memory array. 11 w 12 w 13 and w 14 Perform four write operations on the weight data w2 to write four target weight data w into the memory array. 21 w 22 w 23 and w 24 Four target weight data w 11 w 12 w 13 and w 14 Each target weight data point is identical to the weight data w1, and there are four target weight data points w1 and w2. 21 w 22 w 23 and w 24 Each target weight data in the data is the same as the weight data w2.

[0055] like Figure 5 As shown, the weight data is 4 bits. For an SLC storage unit, M can be 4. One SLC storage unit can store one bit of the 4-bit weight data, so one 4-bit weight data occupies 4 SLC storage units. That is, 4 target weight data w 11 w 12 w 13 and w 14 Each target weight data occupies 4 SLC storage units, and the 4 target weight data w 11 w 12 w 13 and w 14 A total of 16 SLC storage units are used. In other examples, for MLC storage units, M can be 2, and one MLC storage unit can store two bits of the 4-bit weight data, so one 4-bit weight data occupies 2 SLC storage units.

[0056] In some embodiments, the selected word line corresponding to each of the N target weight data is different. Here, the selected word line is the word line coupled to the storage unit where the target weight data is written. Figure 5 As shown, the target weight data w 11 The corresponding selected text line WL1, target weight data w 12 The corresponding selected text line WL2, target weight data w 13 The corresponding selected text line WL3, target weight data w14 The corresponding selected word line is WL4. Specifically: In the N write operations performed on the weight data w1, a word line shift is performed during each write operation. For example, the line address output by the line decoder is incremented by 1 before each write operation. During the first write operation of the weight data w1, the line address output by the line decoder is X00, corresponding to the selected word line WL1. Therefore, during the second write operation of the weight data w1, the line address output by the line decoder is X00 plus 1, meaning X01 corresponds to the selected word line WL2. This continues until the third write operation of the weight data w1, when the line decoder outputs the line address X02, corresponding to the selected word line WL3. Finally, during the fourth write operation of the weight data w1, the line address output by the line decoder is X03, corresponding to the selected word line WL4.

[0057] In some embodiments, the storage units corresponding to N target weight data share at least one selected bit line. Here, the selected bit line is the bit line coupled to the storage unit where the target weight data is written. Figure 5 As shown, the target weight data w 11 Corresponding to selected bit lines BL1-BL4, target weight data w 12 Corresponding to selected bit lines BL2-BL5, target weight data w 13 Corresponding to selected bit lines BL3-BL6, target weight data w 14 The corresponding selected bit lines are BL4-BL7. Specifically: In the N write operations performed on the weight data w1, bit line shifting is also performed during each write operation. For example, the column address output by the column decoder is incremented by 1 before each write operation. During the first write operation of the weight data w1, the column addresses Y00-Y03 output by the column decoder correspond to the selected bit lines BL1-BL4 respectively. Therefore, during the second write operation of the weight data w1, the column addresses output by the column decoder are Y00-Y03 incremented by 1, that is, Y01-Y04 correspond to the selected bit lines BL2-BL5 respectively, and so on. Therefore, during the third write operation of the weight data w1, the column addresses output by the column decoder are Y02-Y05 corresponding to the selected bit lines BL3-BL6, and during the fourth write operation of the weight data w1, the column addresses output by the column decoder are Y03-Y06 corresponding to the selected bit lines BL4-BL7.

[0058] In some embodiments, one weight data occupies M storage units, and the storage units corresponding to N target weight data share at most M-1 selected bit lines; M is an integer greater than 1, and N is less than or equal to M. For example... Figure 5 As shown, four write operations are performed on the weight data w1 to write four target weight data w into the memory array. 11 w 12 w 13 and w 14 ; 4 target weight data w 11 w12 w 13 and w 14 The corresponding storage units share a maximum of 3 selected bit lines, for example, the target weight data w 11 and target weight data w 12 Three selection lines are used in common, and the target weight data is w. 11 and target weight data w 13 Two selected mid-line lines are used together, and the target weight data is w. 11 and target weight data w 14 They share a single selected midline. Adjacent target weight data (e.g., w) 12 and w 13 w 13 and w 14 There are 3 selected mid-line lines in total.

[0059] In a specific example, a weight data occupies 4 storage units. Four write operations on the weight data can achieve synchronous operation between the 4 elements in the input data and the weight matrix; three write operations on the weight data can achieve synchronous operation between the 3 elements in the input data and the weight matrix; and two write operations on the weight data can achieve synchronous operation between the 2 elements in the input data and the weight matrix.

[0060] In some embodiments, one target weight data occupies M storage units, and the storage units corresponding to N target weight data are coupled to multiple M selected word lines; M is an integer greater than 1. For example... Figure 5 As shown, the four target weight data w 11 w 12 w 13 and w 14 The corresponding storage units are coupled to the selected word lines WL1-WL4.

[0061] In some embodiments, one target weight data occupies M storage units, and the storage units corresponding to N target weight data are coupled to at most 2M-1 selected bit lines; M is an integer greater than 1. Therefore, N target weight data occupies M*N storage units. Figure 5 As shown, the four target weight data w 11 w 12 w 13 and w 14 The corresponding memory cells are coupled to the selected bit lines BL1-BL7.

[0062] In some embodiments, M can be determined based on the data type of the weight data and the number of bits in the storage unit. For example, if the weight data is 4 bits, M can be 4 for an SLC storage unit; if the weight data is 6 bits, M can be 2 for a TLC storage unit; if the weight data is 9 bits, M can be 3 for a TLC storage unit; and if the weight data is 16 bits, M can be 4 for a QLC storage unit.

[0063] In some embodiments, the control circuit includes peripheral circuitry coupled to the memory array; the peripheral circuitry is configured to: write N target weight data into M*N memory cells; apply input voltages in parallel to N selected word lines; and obtain the calculation result based on the output current of the selected bit lines corresponding to the N target weight data. Here, the peripheral circuitry can refer to the aforementioned peripheral circuitry 210, peripheral circuitry 302, and... Figure 4A , Figure 4B The details are not elaborated here.

[0064] In some embodiments, the control circuit includes peripheral circuitry coupled to the memory array; the peripheral circuitry is configured to: perform N write operations on P weight data to write P*N target weight data into M*N*P memory cells; apply corresponding input voltages in parallel to N selected word lines coupled to the memory cells where the P*N target weight data is written; and obtain the calculation result based on the output current of the selected bit lines coupled to the memory cells where the P*N target weight data is written.

[0065] Here, P can be the number of weight data to be written, and P can be one or more. Each weight data is stored using M storage units. Based on this, the N target weight data corresponding to one weight data are stored using M*N storage units. That is, if the same weight data is stored N times in M*N storage units, then P weight data are written into M*N*P storage units.

[0066] As described above, in the embodiments of this disclosure, during the computation stage using a semiconductor device as a memory computing chip, before the operation begins, weight data is written into the corresponding memory cell of the memory array according to a certain mapping rule; then, according to the input data, the corresponding input voltage is applied to the selected bit line coupled to the memory cell where the target weight data is written; finally, the output current of the selected bit line coupled to the memory cell where the target weight data is written is received, and the result of multiplying or adding the input data and the data stored in the memory array (corresponding to the target weight data) is obtained according to the received current signal.

[0067] In some embodiments, the peripheral circuitry is configured to apply corresponding input voltages in parallel to the selected word lines coupled to the storage cells containing the N target weight data, based on the input data. That is, the input voltage applied to the selected word lines is related to the data value of the input data. The input data can be vector-type or matrix-type. In some embodiments, different input voltages can characterize different data values ​​of the input data; for example, if the input data includes 4 bits of data, then the 4 bits of input data correspond to 4 input voltages. (Continue to refer to...) Figure 5 The input voltage corresponding to input data 1 is V. in11 V in12 V in13 and V in14 It can simultaneously apply corresponding input voltages to the selected character lines WL1-WL4. Specifically, it applies input voltage V to the selected character line WL1. in11 Apply input voltage V to the selected character line WL2 in12 Apply input voltage V to the selected character line WL3 in13 And apply input voltage V to the selected word line WL4 in14 And apply a conduction voltage V to the unselected word line coupled to the same memory block. pass This ensures that all memory cells coupled to the unselected word lines are in a conducting state. In this case, whether each memory cell string generates a significant current depends only on whether the threshold voltage of the memory cell coupled to the selected word lines WL1-WL4 is greater than the input voltage. When the input voltage is greater than the threshold voltage of the memory cell, the memory cell string to which that memory cell belongs conducts and generates a significant current. When the input voltage V... in When the voltage is less than the threshold voltage of the memory cell, the entire memory cell string to which that cell belongs is turned off, and no significant current is generated. Similarly, the input voltage corresponding to input data 2 is V. in21 V in22 V in23 and V in24 It can simultaneously apply the corresponding input voltage to the selected character lines WL5-WL8.

[0068] In some embodiments, the peripheral circuitry is configured to perform parallel sensing operations on the selected bit lines coupled to the storage cells containing N target weight data, so as to obtain the calculation result based on the results of the parallel sensing operations. That is, the current on each selected bit line can be detected in parallel at the end coupled to the sensing circuit. Taking Figure 4 as an example, the current I1 on the selected bit line BL1 corresponds to the input voltage V. in11 Corresponding input data and weights w 11-1 Multiply by the input voltage V in21 The corresponding input data and w 21-1Multiply and sum the results; the current I2 of selected bit line BL2 corresponds to the input voltage V. in11 Corresponding input data and weights w 11-2 Multiply by the input voltage V in12 The corresponding input data and w 12-1 Multiply by the input voltage V in21 Corresponding input data and weights w 21-2 Multiply by the input voltage V in22 The corresponding input data and w 22-1 Multiply and sum the results; the current I3 on ​​the selected bit line BL3 corresponds to the input voltage V. in11 Corresponding input data and weights w 11-3 Multiply by the input voltage V in12 The corresponding input data and w 12-2 Multiply by the input voltage V in13 Corresponding input data and weights w 13-1 Multiplication, input voltage V in21 Corresponding input data and weights w 21-3 Multiply by the input voltage V in22 The corresponding input data and w 22-2 Multiply by the input voltage V in23 Corresponding input data and weights w 23-1 Multiply and sum the results; the current I4 on the selected bit line BL4 corresponds to the input voltage V. in11 Corresponding input data and weights w 11-4 Multiply by the input voltage V in12 The corresponding input data and w 12-3 Multiply by the input voltage V in13 Corresponding input data and weights w 13-2 Multiply by the input voltage V in14 Corresponding input data and weights w 14-1 Multiplication, input voltage V in21 Corresponding input data and weights w 21-4 Multiply by the input voltage V in22 The corresponding input data and w 22-3 Multiply by the input voltage V in23 Corresponding input data and weights w 23-2 Multiply by the input voltage V in24 Corresponding input data and weights w 24-1 Multiply and sum the results; select bit line BL5, the current I5 corresponds to the input voltage V. in12 The corresponding input data and w 12-4 Multiply by the input voltage V in13 Corresponding input data and weights w 13-3Multiply by the input voltage V in14 Corresponding input data and weights w 14-2 Multiply by the input voltage V in22 The corresponding input data and w 22-4 Multiply by the input voltage V in23 Corresponding input data and weights w 23-3 Multiply by the input voltage V in24 Corresponding input data and weights w 24-2 Multiply and sum the results; select bit line BL6, the current I6 corresponds to the input voltage V. in13 Corresponding input data and weights w 13-4 Multiply by the input voltage V in14 The corresponding input data and weights w are respectively 14-3 Multiply by the input voltage V in23 Corresponding input data and weights w 23-4 Multiply by the input voltage V in24 The corresponding input data and weights w are respectively 24-3 Multiply and sum the results; select the current I7 on bit line BL7, which corresponds to the input voltage V. in14 Corresponding input data and weights w 14-4 Multiply by the input voltage V in24 Corresponding input data and weights w 24-4 Multiply and then sum the results.

[0069] Based on the specific example above, the input voltage V in11 V in12 V in13 and V in14 The corresponding elements in the input data are α1, α2, α3, and α4, respectively, derived from the input voltage V. in21 V in22 V in23 and V in24 Given that the elements in the corresponding input data are α5, α6, α7, and α8, the result of the operation corresponding to I1 is α. 1* w 11-1 +α 5* w 21-1 The result of the operation corresponding to I2 is α. 1* w 11-2 +α 2* w 12-1 +α 5* w 21-2 +α 6* w 22-1 The result of the operation corresponding to I3 is α. 1* w 11-3 +α 2* w 12-2+α 3* w 13-1 +α 5* w 21-3 +α 6* w 22-2 +α 7* w 23-1 The result of the operation corresponding to I4 is α. 1* w 11-4 +α 2* w 12-3 +α 3* w 13-2 +α 4* w 14-1 +α 5* w 21-4 +α 6* w 22-3 +α 7* w 23-2 +α 8* w 24-1 The result of the operation corresponding to I5 is α. 2* w 12-4 +α 3* w 13-3 +α 4* w 14-2 +α 6* w 22-4 +α 7* w 23-3 +α 8* w 24-2 The result of the operation corresponding to I6 is α. 3* w 13-4 +α 4* w 14-3 +α 7* w 23-4 +α 8* w 24-3 The result of the operation corresponding to I7 is α. 4* w 14-4 +α 8* w 24-4 .

[0070] It should be noted that α1 and α5 are the least significant bits (LSB) in input data 1 and input data 2, respectively, and α4 and α8 are the most significant bits (MSB) in input data 1 and input data 2, respectively. 11-1 w 12-1 w 13-1 w 14-1 The target weight data w are respectively 11 w 12 w 13 w 14The lower position in the middle, w 21-1 w 22-1 w 23-1 w 24-1 The target weight data w are respectively 21 w 22 w 23 w 24 The lower position in the middle, w 11-4 w 12-4 w 13-4 w 14-4 The target weight data w are respectively 11 w 12 w 13 w 14 The high position in the middle, w 21-4 w 22-4 w 23-4 w 24-4 The target weight data w are respectively 21 w 22 w 23 w 24 It is at a high level.

[0071] Compared to the previous method which only allowed for the operation of one element of the input data with the weight matrix at a time, the semiconductor device provided in this disclosure can perform simultaneous operations on multiple elements of the input data with the weight matrix. In other words, the input voltages corresponding to multiple elements of the input data can be input simultaneously without having to be input sequentially, thereby improving the efficiency of the operation while increasing the flexibility of the operation.

[0072] Figure 6A This illustrates the process of mapping the input feature map (IFM) and convolutional kernels to the memory array. Figure 6B The computational process in a semiconductor device is illustrated. For example, such as... Figure 6AAs shown, the Input Feature Map (IFM) can be a 4×4 matrix, and the convolutional kernel can be a 2×2 matrix. Here, the Input Feature Map (IFM) is an input matrix composed of multiple input data, and the convolutional kernel is a weight matrix composed of multiple weight data. The example is given with 2-bit input and weight data. The first value "1" in the Input Feature Map (IFM) is converted to binary input data, which is "10" from least significant bit to most significant bit. The input voltage corresponding to the least significant bit ("1") of the input data "10" is applied to the selected word line WL1, and the input voltage corresponding to the most significant bit ("0") of the input data "10" is applied to the selected word line WL2. The second value "3" in the Input Feature Map (IFM) is converted to binary input data, which is "11" from least significant bit to most significant bit. The input voltage corresponding to the least significant bit ("1") of the input data "11" is applied to the selected word line WL3, and the input voltage corresponding to the most significant bit ("1") of the input data "11" is applied to the selected word line WL4. The first value "1" in the convolution kernel is converted into binary weight data, which is "10" from the least significant bit to the most significant bit. This weight data is written twice: first, it is written to the storage unit coupled to the selection word line WL1, and second, it is written to the storage unit coupled to the selection word line WL2. The second value "2" in the convolution kernel is converted into binary weight data, which is "01" from the least significant bit to the most significant bit. This weight data is written twice: first, it is written to the storage unit coupled to the selection word line WL3, and second, it is written to the storage unit coupled to the selection word line WL4.

[0073] It should be noted that the values ​​defined in the input feature map (IFM) and the convolution kernel are all example values ​​only, and the embodiments disclosed herein are not limited thereto.

[0074] In some embodiments, such as Figure 6B As shown, the peripheral circuit includes a sensing circuit 510, a shifting circuit 520, and a summing circuit 530. The sensing circuit 510 is coupled to the bit line and configured to acquire the output current of the selected bit line in parallel, and perform analog-to-digital conversion on the acquired output current. The shifting circuit 520 is coupled to the sensing circuit 510 and configured to shift multiple analog-to-digital conversion results. The summing circuit 530 is coupled to the shifting circuit 520 and configured to sum the shifted results corresponding to multiple analog-to-digital conversion results to obtain the calculation result.

[0075] In some embodiments, the peripheral circuitry may include multiple sensing circuits, one or more shift circuits, and one or more summing circuits. Different bit line outputs can be coupled to the inputs of different sensing circuits, each sensing circuit acquiring and performing analog-to-digital conversion on the input signal. The outputs of the sensing circuits can then be selectively coupled to the inputs of shift circuits, which perform shift processing on the input digital signals. The outputs of each shift circuit that has undergone shift processing are coupled to the input of a summing circuit, which performs summation on the input data and outputs the result.

[0076] In some embodiments, the sensing circuit 510 may include multiple single-channel analog-to-digital converters (ADCs) or one or more multi-channel ADCs. In some embodiments, the shift circuit 520 may include, but is not limited to, a shift register. In some embodiments, the summing circuit 530 may include an adder.

[0077] In some embodiments, such as Figure 6B As shown, the peripheral circuit may also include a multiplexer (MUX) 540, located between the analog-to-digital converter (ADC) circuit and the memory array. The ADC circuit converts the acquired output current into digital information, and the multiplexer 540 controls the connection and selection between the output channels of the memory array (such as selected bit lines) and the ADC circuit. The multiplexer 540 can control the connection and selection between the output channels of the memory array (such as selected bit lines) and the ADC circuit based on a strobe signal.

[0078] In some embodiments, such as Figure 6B As shown, the peripheral circuit may also include a register 550, which is used for temporary data storage. For example, register 550 may be used to store digital signals converted from analog-to-digital converters in sensing circuit 510, or to store intermediate calculation results.

[0079] In some embodiments, a weighted data occupies M storage units, and the shift amount for shifting the analog-to-digital conversion result is greater than or equal to 0 and less than or equal to 2M-2. Different output channels (e.g., different selected bit lines) correspond to different shift amounts, and the shift circuit 520 can determine the shift amount based on the strobe signal. For example... Figure 6A and Figure 6B As shown, a weight data occupies 2 storage units. The shift amount for shifting the analog-to-digital conversion result is greater than or equal to 0 and less than or equal to 2. The shift amount corresponding to the selected bit line BL1 is 0, the shift amount corresponding to the selected bit line BL2 is 1, and the shift amount corresponding to the selected bit line BL3 is 2.

[0080] In some embodiments, such as Figure 6A and Figure 6B As shown, the result corresponding to the current on selected bit line BL1 is Sum1 = 1×1 + 1×0, the result corresponding to the current on selected bit line BL2 is Sum2 = 1×0 + 0×1 + 1×1 + 1×0, and the result corresponding to the current on selected bit line BL3 is Sum3 = 0×0 + 1×1.

[0081] In a specific example, the current on the selected bit line is output to the sensing circuit 510 via multiplexer 540. The analog-to-digital converter (ADC) circuit in the sensing circuit 510 converts the current on the selected bit line into digital information. Specifically, the current on selected bit line BL1 is converted to Sum1 = 01, the current on selected bit line BL2 is converted to Sum2 = 01, and the current on selected bit line BL3 is converted to Sum3 = 01. The shift circuit 520 performs shift processing on the input digital signal. Specifically, Sum1 is shifted 0 bits to the left (similar to shifting 2 bits). 0 (Perform multiplication), shift Sum2 one bit to the left (similar to multiplication by 2). 1 (Perform multiplication), shift Sum3 to the left by 2 bits (similar to multiplication by 2). 2 (Multiplication is performed). The output of each shift circuit that has undergone shifting is coupled to the input of the summing circuit 530. The summing circuit 530 performs a summation operation on the input data, specifically, Sum = Sum1 × 2. 0 +Sum2×2 1 +Sum3×2 2 The calculation result Sum = 111 is output.

[0082] In other embodiments, Figure 6AIn the input feature map (IFM) and convolutional kernel shown, if the input data and weight data are 4-bit data, then the first value "1" in the input feature map (IFM) is converted into binary input data from low to high bits as "1000", and the corresponding input voltage is applied to the selected word lines WL1-WL4 in sequence. The second value "3" in the input feature map (IFM) is converted into binary input data from low to high bits as "1100", and the corresponding input voltage is applied to the selected word lines WL5-WL8 in sequence. The first value "1" in the convolutional kernel is converted into binary weight data from low to high bits as "1000", and this weight data is written 4 times. The 4 target weight data occupy the selected word lines WL1-WL4 and the selected bit lines BL1-BL7. The second value "2" in the convolutional kernel is converted into binary weight data from low to high bits as "0100", and the 4 target weight data occupy the selected word lines WL5-WL8 and the selected bit lines BL1-BL7. Each weight data point occupies 4 storage units. The shift amount for shifting the analog-to-digital conversion result is greater than or equal to 0 and less than or equal to 6. The shift amount corresponding to selected bit line BL1 is 0, the shift amount corresponding to selected bit line BL2 is 1, the shift amount corresponding to selected bit line BL3 is 2, the shift amount corresponding to selected bit line BL4 is 3, the shift amount corresponding to selected bit line BL5 is 4, the shift amount corresponding to selected bit line BL6 is 5, and the shift amount corresponding to selected bit line BL7 is 6. The current on selected bit line BL1 corresponds to Sum1 = 1×1 + 1×0, the current on selected bit line BL2 corresponds to Sum2 = 1×0 + 0×1 + 1×1 + 1×0, the current on selected bit line BL3 corresponds to Sum3 = 0×0 + 1×1, and the current on selected bit lines BL4 and BL7 both correspond to 0. After shifting and summing, Sum = Sum1×2 0 +Sum2×2 1 +Sum3×2 2 The calculation result Sum = 111 is output.

[0083] In this embodiment of the disclosure, after writing the weight data N times, input voltage can be applied to multiple selected word lines (word lines storing target weight data) simultaneously. As a result, the operation stages corresponding to multiple elements in the input data can overlap, which can greatly shorten the overall operation time and improve the operation efficiency of using semiconductor devices.

[0084] In some embodiments, the control circuit further includes an arithmetic circuit, which is coupled to peripheral circuits and configured to perform post-processing operations on the computation results. The arithmetic circuit may include a dedicated processor, including but not limited to a CPU, GPU, digital signal processor (DSP), tensor processing unit (TPU), visual processing unit (VPU), neural processing unit (NPU), collaborative processing unit (SPU), physical processing unit (PPU), and image signal processor (ISP). In a specific example, the arithmetic circuit is an NPU. The NPU can perform operations such as arithmetic / logic operations, rotation and shift operations, compensation operations, activation operations, and pooling operations.

[0085] In this embodiment of the disclosure, the post-processing operation includes multiple or one of compensation, activation, shift, or pooling operations. In a specific example, the memory array in the semiconductor device is configured to store N target weight data, the peripheral circuitry is configured to perform multiplication-accumulation operations in parallel based on the N target weight data, and output the operation result; the arithmetic circuitry is configured to perform an activation operation on the operation result to generate an output result. In some embodiments, the activation operation can be implemented by an activation function stored in the NPU, which may include, but is not limited to, a step function, a correction function, a sigmoid function, a hyperbolic tangent (tanh) function, and a softplus function (also known as a smoothing correction).

[0086] In some embodiments, the semiconductor device in the above embodiments includes a first semiconductor structure and a second semiconductor structure, the memory array is located in the first semiconductor structure, the control circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device.

[0087] In some embodiments, the semiconductor device includes a first semiconductor structure, a bonding layer, and a second semiconductor structure stacked along the thickness direction of the semiconductor device; a memory array is located in the first semiconductor structure, and a control circuit is located in the second semiconductor structure, with the control circuit and the memory array coupled through a bonding structure in the bonding layer.

[0088] In the embodiments of this disclosure, the first semiconductor structure and the second semiconductor structure of the semiconductor device can be formed by bonding two wafers. For example, the first semiconductor structure can be formed on one wafer, and the second semiconductor structure can be formed on another wafer, and then the two wafers can be bonded together. The first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. In other embodiments, the first semiconductor structure and the second semiconductor structure of the semiconductor device can also be formed on the same wafer, but the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. This stacked architecture of the first semiconductor structure and the second semiconductor structure along the thickness direction of the semiconductor device can save more area of ​​the semiconductor device.

[0089] In some embodiments, the semiconductor device in the above embodiments includes a first semiconductor structure, a second semiconductor structure, and a third semiconductor structure. The memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the computing circuit is located in the third semiconductor structure. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked along the thickness direction of the semiconductor device.

[0090] Based on a concept similar to the aforementioned semiconductor devices, this disclosure also provides a memory device, comprising: a memory array; the memory array including a plurality of memory cells; memory cells configured to store weight data; peripheral circuitry coupled to the memory array; the peripheral circuitry being configured to perform multiple write operations to write N identical target weight data into the memory array; each target weight data corresponding to a different selected word line; N being an integer greater than 1. Here, the peripheral circuitry can refer to the aforementioned peripheral circuitry 210, peripheral circuitry 302, and... Figure 4A , Figure 4B The details are not elaborated here.

[0091] In some embodiments, the peripheral circuit is configured to: apply input voltages in parallel to N selected word lines; obtain and output the calculation results based on the output current of the selected bit lines corresponding to the N target weight data.

[0092] In some embodiments, the peripheral circuit is configured to: apply input voltages in parallel to N selected word lines; perform parallel sensing operations on the selected bit lines corresponding to N target weight data, so as to obtain and output the calculation results based on the results of the parallel sensing operations.

[0093] In some embodiments, the storage units corresponding to the N target weight data share at least one selected bit line.

[0094] In some embodiments, one target weight data occupies M storage units, and the storage units corresponding to N target weight data share at most M-1 selected bit lines; M is an integer greater than 1, and N is less than or equal to M.

[0095] In some embodiments, one target weight data occupies M storage units, and the storage units corresponding to N target weight data are coupled to multiple M selected word lines; M is an integer greater than 1.

[0096] In some embodiments, one target weight data occupies M storage units, and the storage units corresponding to N target weight data are coupled to at most 2M-1 selected bit lines; M is an integer greater than 1.

[0097] In some embodiments, the peripheral circuit includes a sensing circuit, a shifting circuit, and a summing circuit; wherein, the sensing circuit is coupled to the selected bit line and configured to acquire the output current of the selected bit line in parallel, and perform analog-to-digital conversion on the acquired output current; the shifting circuit is coupled to the sensing circuit and configured to shift multiple analog-to-digital conversion results; the summing circuit is coupled to the shifting circuit and configured to sum the shifted results corresponding to the multiple analog-to-digital conversion results to obtain the calculation result.

[0098] In some embodiments, a weight data occupies M storage units, and the shift amount for shifting the analog-to-digital conversion result is greater than or equal to 0 and less than or equal to 2M-2; M is an integer greater than 1.

[0099] In some embodiments, the sensing circuit includes an analog-to-digital converter circuit; the analog-to-digital converter circuit is configured to convert the acquired output current into digital information to obtain an analog-to-digital conversion result.

[0100] In some embodiments, the storage device includes an AND type storage device, a NAND type storage device, or a NOR type storage device.

[0101] In some embodiments, the memory device in the above embodiments includes a first semiconductor structure and a second semiconductor structure, the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the memory device.

[0102] In the embodiments disclosed herein, the first and second semiconductor structures of the memory device can be formed by bonding two wafers. For example, the first semiconductor structure can be formed on one wafer, and the second semiconductor structure can be formed on another wafer, and then the two wafers can be bonded together. The first and second semiconductor structures are stacked along the thickness direction of the memory device. In other embodiments, the first and second semiconductor structures of the memory device can also be formed on the same wafer, but the first and second semiconductor structures are stacked along the thickness direction of the memory device. This stacked architecture saves more area of ​​the memory device.

[0103] Based on a concept similar to the aforementioned semiconductor device, this disclosure also provides a method for operating a semiconductor device. Figure 7 This is a schematic flowchart illustrating the operation method of the semiconductor device provided in the embodiments of this disclosure, such as... Figure 7 As shown, the operation method of a semiconductor device includes the following steps.

[0104] Step S610: Perform N write operations to write N identical target weight data into the memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1.

[0105] Step S620: Perform calculations based on N target weight data.

[0106] In some embodiments, the calculation based on N target weight data includes: applying input voltages in parallel to N selected word lines; and obtaining the calculation result based on the output current of the corresponding selected bit lines of the N target weight data.

[0107] In some embodiments, the calculation based on N target weight data includes: applying input voltages in parallel to N selected word lines; performing parallel sensing operations on the selected bit lines corresponding to the N target weight data, so as to obtain the calculation result based on the result of the parallel sensing operation.

[0108] In some embodiments, the calculation based on N target weight data includes: parallel acquisition of the output current of the selected bit line, and analog-to-digital conversion of the acquired output current; shifting of multiple analog-to-digital conversion results; and summing the shifted results corresponding to the multiple analog-to-digital conversion results to obtain the calculation result.

[0109] In some embodiments, the calculation based on N target weight data further includes: performing post-processing calculations on the calculation results; the post-processing calculations include multiple or one of compensation, activation, shifting or pooling operations.

[0110] In this embodiment of the disclosure, the operation method of the semiconductor device includes performing N write operations to write N identical target weight data into the memory array, and applying corresponding input voltages in parallel to N selected word lines coupled to the memory cells where the N target weight data are written. This allows the N target weight data to correspond to multiple input voltages corresponding to the input data. Thus, the semiconductor device provided in this embodiment of the disclosure can realize the synchronous operation of multiple elements in the input data with the weight matrix. In other words, the input voltages corresponding to multiple elements in the input data can be input simultaneously without sequential input, thereby improving the efficiency of the operation while increasing the flexibility of the operation.

[0111] Based on a concept similar to the aforementioned storage device, this disclosure also provides a method for operating the storage device. Figure 8 This is a flowchart illustrating the operation method of the storage device provided in the embodiments of this disclosure, as shown below. Figure 8 As shown, the operation method of the storage device includes the following steps.

[0112] Step S710: Perform N write operations to write N identical target weight data into the memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1.

[0113] Step S720: Output the calculation results based on the N target weight data.

[0114] In some embodiments, outputting the calculation result based on N target weight data includes: applying input voltages in parallel to N selected word lines; obtaining the calculation result and outputting the calculation result according to the output current of the selected bit lines corresponding to the N target weight data.

[0115] In some embodiments, outputting the calculation result based on N target weight data includes: applying input voltages in parallel to N selected word lines; performing parallel sensing operations on the selected bit lines corresponding to the N target weight data, so as to obtain the calculation result and output the calculation result based on the result of the parallel sensing operation.

[0116] In some embodiments, the calculation result is output based on N target weight data, including: parallel acquisition of the output current of the selected bit line, and analog-to-digital conversion of the acquired output current; shifting of multiple analog-to-digital conversion results; and summing the shifted results corresponding to multiple analog-to-digital conversion results to obtain the calculation result.

[0117] In this embodiment of the disclosure, the operation method of the storage device includes performing N write operations on the weight data to write N target weight data into the memory array, and applying input voltages in parallel to the N selected word lines coupled to the storage cells where the N target weight data are written. This allows the N target weight data to correspond to multiple input voltages corresponding to the input data. Thus, the storage device provided in this embodiment of the disclosure can realize the synchronous operation of multiple elements in the input data with the weight matrix. In other words, the input voltages corresponding to multiple elements in the input data can be input simultaneously without sequential input, thereby improving the efficiency of the operation while increasing the flexibility of the operation.

[0118] Based on the above-described semiconductor device, this disclosure also provides an electronic device, including: the semiconductor device described in any of the above embodiments or the memory device described in the above embodiments.

[0119] Here, the specific structure of the semiconductor device and memory device is referred to in the above embodiments. Since this electronic device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be repeated here.

[0120] In some embodiments, the electronic device may further include a host, wherein the host may be a processor of the electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), wherein the SoC may be, for example, an application processor (AP).

[0121] In some embodiments, the aforementioned electronic device may be any device capable of storing data, such as a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, or power bank.

[0122] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0123] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A memory array; the memory array includes multiple storage units; the storage units are configured to store weight data; A control circuit coupled to the memory array; the control circuit is configured to: Multiple write operations are performed to write N identical target weight data into the memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1; The calculation is performed based on the N target weight data.

2. The semiconductor device according to claim 1, characterized in that, The control circuit is configured to apply input voltages in parallel to the N selected word lines; The calculation result is obtained based on the output current of the selected bit line corresponding to the N target weight data.

3. The semiconductor device according to claim 2, characterized in that, The control circuit is configured to apply input voltages in parallel to the N selected word lines; Parallel sensing operations are performed on the selected bit lines corresponding to the N target weight data to obtain the calculation result based on the results of the parallel sensing operations.

4. The semiconductor device according to claim 1, characterized in that, The storage units corresponding to the N target weight data share at least one selected bit line.

5. The semiconductor device according to claim 1, characterized in that, One target weight data occupies M storage units, and the storage units corresponding to the N target weight data share at most M-1 selected bit lines; M is an integer greater than 1, and N is less than or equal to M.

6. The semiconductor device according to claim 1, characterized in that, One target weight data occupies M storage units, and the storage units corresponding to the N target weight data are coupled to multiple M selected word lines; M is an integer greater than 1.

7. The semiconductor device according to claim 1, characterized in that, One target weight data occupies M storage units, and the storage units corresponding to the N target weight data are coupled to at most 2M-1 selected bit lines; where M is an integer greater than 1.

8. The semiconductor device according to claim 3, characterized in that, The control circuit includes peripheral circuitry coupled to the memory array; the peripheral circuitry includes a sensing circuit, a shifting circuit, and an adding circuit; wherein, The sensing circuit is coupled to the selected bit line and configured to acquire the output current of the selected bit line in parallel, and perform analog-to-digital conversion on the acquired output current; The shift circuit is coupled to the sensing circuit and configured to perform shift processing on multiple analog-to-digital conversion results; The summing circuit is coupled to the shifting circuit and configured to sum the shifted results corresponding to the plurality of analog-to-digital conversion results to obtain the calculation result.

9. The semiconductor device according to claim 8, characterized in that, The control circuit further includes: an arithmetic circuit; the arithmetic circuit is coupled to the peripheral circuit and configured to perform post-processing operations on the arithmetic result; the post-processing operations include multiple or one of compensation, activation, shifting or pooling operations.

10. The semiconductor device according to claim 8, characterized in that, One target weight data occupies M storage units, and the shift amount for shifting the analog-to-digital conversion result is greater than or equal to 0 and less than or equal to 2M-2; where M is an integer greater than 1.

11. The semiconductor device according to claim 8, characterized in that, The sensing circuit includes an analog-to-digital converter circuit; the analog-to-digital converter circuit is configured to convert the acquired output current into digital information to obtain an analog-to-digital conversion result.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that, The memory array includes an AND type memory array, a NAND type memory array, or a NOR type memory array.

13. A storage device, characterized in that, include: Memory array; The memory array includes multiple storage units; the storage units are configured to store weight data. Peripheral circuitry coupled to the memory array; The peripheral circuit is configured as follows: Perform N write operations to write N identical target weight data into the memory array; each target weight data corresponds to a different selected word line; N is an integer greater than 1; The calculation results are output based on the N target weight data.

14. The storage device according to claim 13, characterized in that, The peripheral circuit is configured to apply input voltages in parallel to the N selected word lines; The calculation result is obtained and output based on the output current of the selected bit line corresponding to the N target weight data.

15. The storage device according to claim 13, characterized in that, The peripheral circuit is configured to apply input voltages in parallel to the N selected word lines; Parallel sensing operations are performed on the selected bit lines corresponding to the N target weight data, and the calculation results are obtained and output based on the results of the parallel sensing operations.

16. The storage device according to claim 13, characterized in that, The storage units corresponding to the N target weight data share at least one selected bit line.

17. The storage device according to claim 13, characterized in that, One target weight data occupies M storage units, and the storage units corresponding to the N target weight data share at most M-1 selected bit lines; M is an integer greater than 1, and N is less than or equal to M.

18. The storage device according to claim 13, characterized in that, One target weight data occupies M storage units, and the storage units corresponding to the N target weight data are coupled to multiple M selected word lines; M is an integer greater than 1.

19. The storage device according to claim 13, characterized in that, One target weight data occupies M storage units, and the storage units corresponding to the N target weight data are coupled to at most 2M-1 selected bit lines; where M is an integer greater than 1.

20. The storage device according to claim 15, characterized in that, The peripheral circuitry includes a sensing circuit, a shifting circuit, and an adding circuit; wherein... The sensing circuit is coupled to the selected bit line and configured to acquire the output current of the selected bit line in parallel, and perform analog-to-digital conversion on the acquired output current; The shift circuit is coupled to the sensing circuit and configured to perform shift processing on multiple analog-to-digital conversion results; The summing circuit is coupled to the shifting circuit and configured to sum the shifted results corresponding to the plurality of analog-to-digital conversion results to obtain the calculation result.

21. The storage device according to claim 20, characterized in that, One target weight data occupies M storage units, and the shift amount for shifting the analog-to-digital conversion result is greater than or equal to 0 and less than or equal to 2M-2; where M is an integer greater than 1.

22. The storage device according to claim 20, characterized in that, The sensing circuit includes an analog-to-digital converter circuit; the analog-to-digital converter circuit is configured to convert the acquired output current into digital information to obtain an analog-to-digital conversion result.

23. The storage device according to any one of claims 13 to 22, characterized in that, The storage device includes an AND type storage device, a NAND type storage device, or a NOR type storage device.

24. A method of operating a semiconductor device, characterized in that, include: Perform N write operations to write N identical target weight data into the memory array; The selected text line is different for each target weight data; N is an integer greater than 1; The calculation is performed based on the N target weight data.

25. The operating method according to claim 24, characterized in that, The calculation is performed based on the N target weight data, including: Input voltages are applied in parallel to the N selected word lines; The calculation result is obtained based on the output current of the selected bit line corresponding to the N target weight data.

26. The operating method according to claim 25, characterized in that, The calculation is performed based on the N target weight data, including: Input voltages are applied in parallel to the N selected word lines; Parallel sensing operations are performed on the selected bit lines corresponding to the N target weight data to obtain the calculation result based on the results of the parallel sensing operations.

27. The operating method according to claim 26, characterized in that, The calculation is performed based on the N target weight data, including: The output current of the selected bit line is acquired in parallel, and the acquired output current is processed by analog-to-digital conversion. Shift the results of multiple analog-to-digital conversions. The results of the shifted operations corresponding to the multiple analog-to-digital conversion results are summed to obtain the calculation result.

28. The operating method according to claim 27, characterized in that, The calculation based on the N target weight data also includes: The calculation result is subjected to post-processing operations; the post-processing operations include one or more of the following: compensation, activation, shifting, or pooling operations.

29. A method for operating a storage device, characterized in that, include: Perform N write operations to write N identical target weight data into the memory array; The selected text line is different for each target weight data; N is an integer greater than 1; The calculation results are output based on the N target weight data.

30. The operating method according to claim 29, characterized in that, The calculation results are output based on the N target weight data, including: Input voltages are applied in parallel to the N selected word lines; The calculation result is obtained and output based on the output current of the selected bit line corresponding to the N target weight data.

31. The operating method according to claim 30, characterized in that, The calculation results are output based on the N target weight data, including: Input voltages are applied in parallel to the N selected word lines; Parallel sensing operations are performed on the selected bit lines corresponding to the N target weight data, and the calculation results are obtained and output based on the results of the parallel sensing operations.

32. The operating method according to claim 31, characterized in that, The calculation results are output based on the N target weight data, including: The output current of the selected bit line is acquired in parallel, and the acquired output current is processed by analog-to-digital conversion. Shift the results of multiple analog-to-digital conversions. The results of the shifted operations corresponding to the multiple analog-to-digital conversion results are summed to obtain the calculation result.

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