Serdes

Abstract

A serializer and a deserializer are disclosed. The serializer includes a sequence module and a data up-conversion module. The data up-conversion module receives a data packet sequence from a media access control block based on an output operation frequency and outputs the data packet sequence based on a sequence operation frequency. The deserializer includes a de-sequence module and a plurality of data down-conversion modules. The deserializer generates a data operation frequency based on a de-sequence operation frequency and outputs a recovered data packet sequence based on the data operation frequency. Embodiments of the present application can transmit or receive data in coordination with an operation frequency of a media access control block and exchange data at a transmission frequency that meets the transmission specification requirements of a physical layer, thereby achieving the goal of improving the convenience of the serializer and the deserializer in applications.

Description

Technical Field

[0001] This application relates to a serializer and a deserializer, and more particularly to a serializer and deserializer operable at high frequencies. Background Technology

[0002] A serializer / deserializer (SerDes) is a physical (PHY) layer device that can convert data between parallel and serial communication modes and enable high-speed point-to-point transmission of large amounts of data using differential signals.

[0003] Generally, in applications, serializers / deserializers are directly connected to Media Access Control (MAC) layer components (e.g., Field Programmable Gate Array (FPGA) chips). Because FPGA chips operate at relatively low frequencies (e.g., several hundred MHz), the serializer / deserializer must operate at the lowest possible transmission frequency to match the FPGA chip's operating frequency.

[0004] However, as the requirements for physical layer transmission specifications increase, the transmission frequency requirements for serializers / deserializers also increase accordingly. Therefore, how to propose a serializer / deserializer suitable for MAC layer components and that meets the transmission specifications of the physical layer is one of the problems that this field aims to solve. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention proposes a serializer and deserializer that can transmit or receive data in conjunction with the operating frequency of an FPGA chip, and exchange data at a transmission frequency that meets the transmission specifications of the physical layer, thereby improving the convenience of serializer and deserializer applications.

[0006] To achieve one of the above objectives, the present invention proposes a serializer embodiment as a physical layer interface for an electronic device, comprising: a serialization module and a data upsampling processing module. The serialization module has a serial operation frequency for converting parallel data packets into a serially transmitted data stream. The data upsampling processing module includes a frequency divider unit and multiple asynchronous register units. The frequency divider unit is electrically connected to a media access control block and the serialization module, for receiving the serial operation frequency and generating a device operation frequency based on the serial operation frequency, which is provided to the media access control block. The device operation frequency is less than the serial operation frequency. The multiple asynchronous register units are electrically connected to the media access control block and the serialization module. The multiple asynchronous register units receive the serial operation frequency and an output operation frequency from the media access control block. The multiple asynchronous register units receive a sequence of data packets from the media access control block based on the output operation frequency and output the data packet sequence based on the serial operation frequency, where the output operation frequency is less than the serial operation frequency. The data packet sequence includes multiple non-repeating data packets, and the data stream includes repeated data packets.

[0007] To achieve one of the above objectives, the present invention proposes a deserializer embodiment for a physical layer interface of an electronic device, comprising a deserialization module and multiple data downsampling processing modules. The deserialization module has a deserialization operation frequency for receiving serially transmitted data streams and converting the data streams into a sequence of data packets for parallel transmission, the data packet sequence including repeating data packets. The data downsampling processing module includes a frequency division unit, an alignment unit, and a packet discarding unit. The frequency division unit is electrically connected to a media access control block and the deserialization module, for receiving the deserialization operation frequency and generating a data operation frequency based on the deserialization operation frequency, the data operation frequency being provided to the media access control block, the data operation frequency being less than the deserialization operation frequency. The alignment unit is electrically connected to the deserialization module, for receiving the deserialization operation frequency and the data packet sequence from the deserialization module, the alignment unit being used to determine the starting position of each data packet in the data packet sequence. The packet discarding unit is electrically connected to the alignment unit and the desequence module, and is used to receive the desequence operation frequency and the data packet sequence from the alignment unit, discard duplicate data packets in the data packet sequence, and output a restored data packet sequence, the restored data packet sequence including non-repeating data packets.

[0008] Based on the above, the serializer of this invention can upsample received low-frequency data to high-frequency data using a data upsampling module, and the deserializer of this invention downsamples received high-frequency data to low-frequency data. Therefore, the serializer / deserializer of this invention can transmit or receive low-frequency data in accordance with the operating frequency of MAC layer components, and exchange data at transmission frequencies that meet the physical layer's transmission specifications, thereby improving the convenience of serializer and deserializer applications. Attached Figure Description

[0009] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0010] Figure 1 This is a schematic diagram of a block embodiment of an electronic device;

[0011] Figure 2 This is a schematic diagram illustrating the application of electronic devices;

[0012] Figure 3 This is a schematic diagram of a serializer embodiment according to an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram of a data packet sequence embodiment according to an embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of a deserializer embodiment according to an embodiment of the present invention;

[0015] Figure 6 This is a schematic diagram of a data packet sequence embodiment according to an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] Figure 1This is a block diagram illustrating an embodiment of electronic device 100. Electronic device 100 is, for example, a host device such as a portable electronic device (e.g., a smartphone, tablet, etc.) or a non-portable electronic device (e.g., a desktop computer). Electronic device 100 is, for example, a data storage device or a flash memory device. For example, electronic device 100 is, for example, a solid-state disk (SSD) or flash memory. Generally, electronic device 100 includes a physical layer interface 110, an interface driver 120, and an application 130. Physical layer interface 110 is a physical circuit interface used to provide signals to external devices and receive signals from external devices. Physical layer interface 110 is, for example, MIPI M-PHY compliant. TM The physical layer interface 110 is, for example, a physical circuit conforming to the PCIe (Peripheral Component Interconnect Express) standard. The physical layer interface 110 is, for example, a physical circuit interface suitable for Universal Flash Storage (UFS). Interface driver 120 is electrically connected to physical layer interface 110. Interface driver 120 is used to generate or decode data packets to perform tasks requested from application 130. In memory system applications, tasks include, for example, read operations, write operations, etc. Data packets generated by interface driver 120 are provided to physical layer interface 110 for transmission through physical layer interface 110. Interface driver 120 is, for example, a UFS driver. Application 130 is executed by electronic device 100, for example, an application performing internal memory system read operations under user control. Thus, electronic device 100 can implement the data packet transmission required by application 130 based on physical layer interface 110 and interface driver 120 under user control.

[0018] Please refer to Figure 1 and Figure 2 , Figure 2 This is a schematic diagram illustrating the application of electronic device 100. Figure 2The invention includes electronic devices 100a and 100b. Electronic device 100a is, for example, a host device. Electronic device 100b is, for example, a flash memory storage device, and the invention is not limited thereto. Electronic device 100a includes a serializer 210a and a deserializer 220a that implement physical layer functions, and a media access control block 300a that implements media access control layer functions. Serializer 210a and deserializer 220a are, for example, the aforementioned physical layer interface 110, and media access control block 300a is, for example, the aforementioned interface driver 120. Electronic device 100b includes a serializer 210b and a deserializer 220b that implement physical layer functions, and a media access control block 300b that implements media access control layer functions. Serializer 210b and deserializer 220b are, for example, the aforementioned physical layer interface 110, and media access control block 300b is, for example, the aforementioned interface driver 120. Electronic devices 100a and 100b establish an electrical connection with each other through serializers 210a and 210b and deserializers 220a and 220b.

[0019] Media Access Control (MAC) block 300a is electrically connected to serializer 210a and deserializer 220a. MAC block 300a generates a sequence of data packets for parallel transmission and transmits this sequence to serializer 210a. MAC block 300a receives the data packet sequence from deserializer 220a. Serializer 210a receives the data packet sequence from MAC block 300a, converts the parallel data packet sequence into a serially transmitted data stream, and transmits the serially transmitted data stream to deserializer 220b of electronic device 100b. Deserializer 220a receives the data stream from serializer 210b of electronic device 100b, converts the serially transmitted data stream into a sequence of data packets for parallel transmission, and transmits the parallelly transmitted data packet sequence to MAC block 300a of electronic device 100a. The operation of media access control block 300b, serializer 210b and deserializer 220b is the same as that of media access control block 300a, serializer 210a and deserializer 220a, so it will not be described again here.

[0020] Please refer to Figure 3 , Figure 3 This is a schematic diagram of a serializer embodiment according to an embodiment of the present invention. Figure 3The serializer 210a is used as an example. The serializer 210a is electrically connected to the media access control block 300a. The serializer 210a provides the device operating frequency CK2 to the media access control block 300a. The device operating frequency CK2 is less than the sequence operating frequency CK1. The device operating frequency CK2 is the frequency at which the media access control block 300a can operate. The media access control block 300a generates a parallel data packet sequence DP based on the received device operating frequency CK2 and provides the device operating frequency CK2 as the output operating frequency CK3 to the serializer 210a. Thus, the media access control block 300a can generate a parallel data packet sequence DP based on the received device operating frequency CK2, at an output operating frequency CK3 corresponding to (same as) the device operating frequency CK2.

[0021] The serializer 210a includes a data upsampling processing module 211 and a sequence module 212. The sequence module 212 is electrically connected to the data upsampling processing module 211. The sequence module 212 has a sequence operation frequency CK1 and is used to receive a parallel data packet sequence DP from the data upsampling processing module 211. The sequence module 212 operates at the sequence operation frequency CK1 and converts the received data packet sequence DP into a serially transmitted data stream DS based on the sequence operation frequency CK1. The data upsampling processing module 211 includes a frequency divider unit 2111 and multiple asynchronous register units 2112. The frequency divider unit 2111 is electrically connected to the media access control block 300a and the sequence module 212. The frequency divider unit 2111 receives the sequence operation frequency CK1 from the sequence module 212 and generates a device operation frequency CK2 based on the sequence operation frequency CK1. Frequency divider 2111 reduces the sequence operation frequency CK1 to a lower device operation frequency CK2 based on a division factor (e.g., 2, 4, 6). Asynchronous register 2112 is electrically connected to the media access control block 300a and the sequence module 212. Asynchronous register 2112 receives the sequence operation frequency CK1 and the output operation frequency CK3 from the media access control block 300a. Asynchronous register 2112 receives the data packet sequence DP from the media access control block 300a based on the output operation frequency CK3 and outputs the data packet sequence DP based on the sequence operation frequency CK1. Asynchronous register 2112 is, for example, an asynchronous multiple-input multiple-output (FIFO) element. The number of asynchronous registers 2112 is related to the division factor of frequency divider 2111. For example, when the division factor of frequency divider 2111 is 2, the number of asynchronous registers 2112 is correspondingly 2. In this way, the data packet sequence DP transmitted at the output operating frequency CK3 is converted to be transmitted at the sequence operating frequency CK1, so that the sequence module 212 can operate at the higher sequence operating frequency CK1.

[0022] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a data packet sequence DP according to an embodiment of the present invention. The data packet sequence DP includes multiple data packets D1 and D2. Taking data packet D1 as an example, each data packet D1 includes complex synchronization bits S0 and complex data bits Data. Different data packets have different synchronization bits. For example, the complex synchronization bits S0 of data packet D1 are different from the complex synchronization bits S1 of data packet D2.

[0023] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a deserializer embodiment according to an embodiment of the present invention. Figure 5 The following explanation uses deserializer 220a as an example. Deserializer 220a is electrically connected to media access control block 300a. Deserializer 220a provides multiple data operation frequencies (e.g., data operation frequencies CK5 and CK7) and corresponding restored data packet sequences DP2 and DP3 to media access control block 300a. Data operation frequencies CK5 and CK7 are the frequencies at which media access control block 300a can operate. Media access control block 300a reads the parallel data packet sequence DP based on the received data operation frequency CK5.

[0024] The deserializer 220a includes a deserialization module 222 and multiple data down-frequency processing modules 221a and 221b. The number of data down-frequency processing modules 221a and 221b corresponds to the frequency division factor. The deserialization module 222 has a deserialization operation frequency. The deserialization module 222 is used to receive the data stream DS from the serializer 210b based on the deserialization operation frequency and convert the data stream DS into a parallel transmission data packet sequence DP1. The deserialization module 222 is also used to generate multiple data processing frequencies CK4 and CK6 based on the deserialization operation frequency. The data processing frequencies CK4 and CK6 have different frequencies. Please refer to [reference needed]. Figure 6 , Figure 6 This is a schematic diagram of a data packet sequence DP1 according to an embodiment of the present invention. The data packet sequence DP1 includes repeated data packets D1 and D2. For example, the data packet sequence DP1 includes two data packets D1 and two data packets D2. The number of repeated data packets D1 and D2 is related to the division factor of the division unit 2111 and / or the division unit 2211. For example, if the division factor is 2, then the data packet sequence DP1 includes two data packets D1 corresponding to the division factor.

[0025] Each data downsampling module 221a, 221b includes a frequency division unit 2211, an alignment unit 2212, and a packet discarding unit 2213. The following description uses data downsampling module 221a as an example. The frequency division unit 2211 is electrically connected to the media access control block 300a and the deserialization module 222. The frequency division unit 2211 receives the data processing frequency CK4 and generates a data operation frequency CK5 based on the data processing frequency CK4 and the frequency division factor. The data operation frequency CK5 is provided to the media access control block 300a, and the data operation frequency CK5 is less than the deserialization operation frequency and the data processing frequency CK4. The frequency division factor of the frequency division unit 2211 is the same as that of the frequency division unit 2211. The alignment unit 2212 is electrically connected to the deserialization module 222. The alignment unit 2212 receives the data processing frequency CK4 and the data packet sequence DP1 from the deserialization module 222. Alignment unit 2212 is used to determine the start position of each data packet in the data packet sequence DP1. Alignment unit 2212 is used to identify the synchronization bit of each data packet to determine the start position of each data packet in the data packet sequence based on the synchronization bit. For example, alignment unit 2212 identifies the synchronization bit S0 of data packet D1 in the data packet sequence DP1 based on the data processing frequency CK4 to determine the start position of data packet D1. Figure 6 The position of the 0th bit. Alignment unit 2212 can be implemented by logic circuitry. Packet discarding unit 2213 is electrically connected to alignment unit 2212, deserialization module 222, and media access control block 300a. Packet discarding unit 2213 receives data processing frequency CK4 and data packet sequence DP1 from alignment unit 2212, as well as the start position of data packet D1. Packet discarding unit 2213 reads data packet sequence DP1 based on data processing frequency CK4, determines the position of the first data packet D1 in data packet sequence DP1 based on the start position of data packet D1, discards duplicate data packets D1 in data packet sequence DP1, and outputs restored data packet sequence DP2 to media access control block 300a. Restored data packet sequence DP2 includes non-duplicate data packets D1. Please also refer to... Figure 6The packet discarding unit 2213 can read the data from bits 0 to 39 of the data packet sequence DP1 according to the known size and starting position of the data packet D1, and output the data from bits 0 to 39 of the data packet sequence DP1 as data packet D1. Simultaneously, the packet discarding unit 2213 does not read the data from bits 40 to 79 of the data packet sequence DP1, thereby discarding duplicate data packets D1. The data down-frequency processing module 221b receives the data processing frequency CK6, generates the data operation frequency CK7, and outputs the restored data packet sequence DP3 to the media access control block 300a. The restored data packet sequence DP3 includes the non-duplicate data packet D2. The operation of the data down-frequency processing module 221b is the same as that of the data down-frequency processing module 221a, and therefore will not be described further here.

[0026] In summary, the serializer of this invention can upsample received low-frequency data to high-frequency data using a data upsampling module, and the deserializer of this invention downsamples received high-frequency data to low-frequency data. Therefore, the serializer / deserializer of this invention can transmit or receive low-frequency data in accordance with the operating frequency of media access control layer elements, and exchange data at transmission frequencies that meet the physical layer's transmission specifications, thereby improving the convenience of serializer and deserializer applications.

[0027] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0028] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms fall within the scope of protection of this application.

Claims

1. A serializer, serving as a physical layer interface for an electronic device, characterized in that, include: The sequence module has a sequence operation frequency, which is used to convert parallel data packet sequences into serially transmitted data streams; as well as Data upsampling processing module, the data upsampling processing module includes: A frequency division unit, electrically connected to the media access control block and the sequence module, is used to receive the sequence operation frequency and generate a device operation frequency based on the sequence operation frequency. The device operation frequency is provided to the media access control block and is less than the sequence operation frequency. Multiple asynchronous register units are electrically connected to the media access control block and the sequence module. These asynchronous register units receive the sequence operation frequency and the output operation frequency from the media access control block. Based on the output operation frequency, each asynchronous register unit receives a data packet sequence from the media access control block and outputs the data packet sequence based on the sequence operation frequency. The output operation frequency is less than the sequence operation frequency. The data packet sequence includes multiple non-repeating data packets, and the data stream includes repeated data packets.

2. The serializer as claimed in claim 1, characterized in that, The number of the multiple asynchronous register units and the number of repeated data packets are related to the frequency division factor of the frequency division unit.

3. The serializer as described in claim 1, characterized in that, The data packet includes a complex number of synchronization bits and a complex number of data bits, and different data packets have different synchronization bits.

4. The serializer as claimed in claim 1, characterized in that, The multiple asynchronous register units are asynchronous multiple-input multiple-output elements.

5. The serializer as claimed in claim 1, characterized in that, The output operating frequency is the same as the device operating frequency.

6. A deserializer, serving as the physical layer interface of an electronic device, characterized in that, include: A desequence module has a desequence operation frequency for receiving serially transmitted data streams and converting the data streams into a sequence of data packets for parallel transmission, the data packet sequence including repeating data packets. as well as Multiple data down-frequency processing modules, the data down-frequency processing modules including: The frequency division unit is electrically connected to the media access control block and the deserialization module, and is used to receive the data processing frequency and generate a data operation frequency based on the data processing frequency. The data operation frequency is provided to the media access control block, and the data operation frequency is less than the deserialization operation frequency. An alignment unit, electrically connected to the deserialization module, is used to receive the data processing frequency and the data packet sequence from the deserialization module. The alignment unit is used to determine the start position of each data packet in the data packet sequence. A packet discarding unit, electrically connected to the alignment unit and the desequence module, is used to receive the data processing frequency and the data packet sequence from the alignment unit, discard duplicate data packets in the data packet sequence, and output a restored data packet sequence, the restored data packet sequence including non-duplicate data packets.

7. The deserializer as described in claim 6, characterized in that, The number of the multiple data down-processing modules and the number of repeated data packets are related to the frequency division factor of the frequency division unit.

8. The deserializer as described in claim 6, characterized in that, The data processing frequencies of the multiple data down-processing modules are different from each other.

9. The deserializer as described in claim 6, characterized in that, The data packet includes a complex number of synchronization bits and a complex number of data bits, and different data packets have different synchronization bits.

10. The deserializer as described in claim 9, characterized in that, The alignment unit is used to identify a plurality of the synchronization bits to determine the start position of each data packet in the data packet sequence based on the plurality of synchronization bits.

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