Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are disclosed. A display device includes a substrate, first and second gate lines extending in a first direction on the substrate and spaced apart from each other, a data line extending in a second direction crossing the first direction, first and second pixel circuits arranged in the first direction with the data line interposed therebetween, the first pixel circuit connected to the first gate line, the second pixel circuit connected to the second gate line, each of the first and second pixel circuits including a first transistor including a first semiconductor layer and a first gate electrode, a storage capacitor including a second storage electrode connected to the first gate electrode, and a sustain capacitor including a first sustain electrode connected to a first storage electrode of the storage capacitor, and a capacitance of the storage capacitor of the first pixel circuit is different from a capacitance of the storage capacitor of the second pixel circuit.

Description

Technical Field

[0001] Embodiments of the present invention provide a display device and an electronic device including the same. Background Technology

[0002] Recently, the applications of display devices have become more diversified. Furthermore, due to the thinning and lightening of display devices, their range of applications is expanding.

[0003] The display device includes a display panel, which includes display elements that realize pixels and pixel circuitry for controlling electrical signals applied to the display elements. The pixel circuitry includes thin-film transistors (TFTs), capacitors, and multiple wirings.

[0004] The uses of display devices are becoming more diverse, and there are various attempts to improve the quality of display devices through design. Summary of the Invention

[0005] Embodiments of the present invention provide a highly reliable display device and an electronic device including the same. However, these technical problems are exemplary and the scope of the present invention is not limited thereto.

[0006] One embodiment provides a display device, comprising: a substrate; a first gate line and a second gate line extending along a first direction and spaced apart from each other on the substrate; a data line extending along a second direction intersecting the first direction; a first pixel circuit and a second pixel circuit, wherein the data line is disposed between the first pixel circuit and the second pixel circuit and arranged along the first direction, wherein the first pixel circuit is connected to the first gate line, and the second pixel circuit is connected to the first gate line, wherein each of the first pixel circuit and the second pixel circuit includes: a first transistor including a first semiconductor layer and a first gate electrode; a storage capacitor including a second storage electrode connected to the first gate electrode, wherein the capacitance of the storage capacitor of the first pixel circuit is different from the capacitance of the storage capacitor of the second pixel circuit.

[0007] In one embodiment, the first pixel circuit and the second pixel circuit may share the data line.

[0008] In one embodiment, the display device may further include: a first light-emitting diode connected to the first pixel circuit; and a second light-emitting diode connected to the second pixel circuit, wherein the first light-emitting diode and the second light-emitting diode emit light of the same color.

[0009] In one embodiment, the storage capacitor may further include a third storage electrode disposed above the second storage electrode, wherein the third storage electrode may be connected to the first storage electrode of the storage capacitor via a contact hole.

[0010] In one embodiment, the area of ​​the first storage electrode of the first pixel circuit may be the same as the area of ​​the first storage electrode of the second pixel circuit, and the area of ​​the third storage electrode of the first pixel circuit may be the same as the area of ​​the third storage electrode of the second pixel circuit.

[0011] In one embodiment, the width of the second storage electrode of the first pixel circuit in the first direction may be configured to be different from the width of the second storage electrode of the second pixel circuit in the first direction.

[0012] In one embodiment, on a plane, the edge of the second storage electrode may be arranged inside the edge of the first storage electrode of the storage capacitor.

[0013] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a holding capacitor, including a first holding electrode connected to a first storage electrode of the storage capacitor, wherein the capacitance of the holding capacitor of the first pixel circuit may be configured to be different from the capacitance of the holding capacitor of the second pixel circuit.

[0014] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a holding capacitor, wherein the holding capacitor may include: a first holding electrode connected to a first storage electrode of the storage capacitor; and a second holding electrode disposed on the same layer as the first semiconductor layer, wherein the width of the second holding electrode of the first pixel circuit in the first direction may be configured to be different from the width of the second holding electrode of the second pixel circuit in the first direction.

[0015] In one embodiment, each of the first pixel circuit and the second pixel circuit further includes a holding capacitor, wherein the holding capacitor may include: a first holding electrode connected to a first storage electrode of the storage capacitor; a second holding electrode disposed on the same layer as the first semiconductor layer; a third holding electrode disposed above the first gate electrode; and a fourth holding electrode disposed above the third holding electrode, wherein the fourth holding electrode may be configured as part of a drive voltage line extending along the second direction.

[0016] In one embodiment, the fourth holding electrode is configured to branch into a first branch and a second branch in a region overlapping with the third holding electrode, wherein the first branch arranged in the first pixel circuit is arranged continuously, and wherein the first branch arranged in the second pixel circuit can be disconnected and equipped with a gap.

[0017] In one embodiment, the fourth holding electrode is configured to branch into a first branch and a second branch in the region overlapping with the third holding electrode, wherein the width of at least one of the first branch and the second branch arranged in the first pixel circuit may be configured to be different from the width of the first branch and the second branch arranged in the second pixel circuit.

[0018] In one embodiment, the display device may further include a third pixel circuit and a fourth pixel circuit, arranged in the next row of the first pixel circuit and the second pixel circuit, and arranged to place the data line between the third pixel circuit and the fourth pixel circuit, wherein the capacitance of the storage capacitor included in the third pixel circuit may be configured to be different from the capacitance of the storage capacitor included in the first pixel circuit.

[0019] In one embodiment, the display device may further include: a first light-emitting diode connected to the first pixel circuit; a second light-emitting diode connected to the second pixel circuit; a third light-emitting diode connected to the third pixel circuit; and a fourth light-emitting diode connected to the fourth pixel circuit, wherein the first light-emitting diode, the second light-emitting diode, the third light-emitting diode, and the fourth light-emitting diode can emit light of the same color.

[0020] One embodiment provides a display device, comprising: a substrate; first-1 gate lines and first-2 gate lines extending on the substrate along a first direction and spaced apart from each other; a data line extending along a second direction intersecting the first direction; a first pixel circuit and a second pixel circuit arranged along the first direction and sharing the data line, wherein the first pixel circuit is connected to the first-1 gate line, and the second pixel circuit is connected to the first-2 gate line, wherein each of the first pixel circuit and the second pixel circuit includes: a first transistor including a first semiconductor layer and a first gate electrode; a storage capacitor including a second storage electrode connected to the first gate electrode; and a holding capacitor including a first holding electrode connected to the first storage electrode of the storage capacitor, wherein the capacitance of the holding capacitor of the first pixel circuit is different from the capacitance of the holding capacitor of the second pixel circuit.

[0021] In one embodiment, the holding capacitor further includes a second holding electrode disposed on the same layer as the first semiconductor layer, wherein the width of the second holding electrode of the first pixel circuit in the first direction may be configured to be different from the width of the second holding electrode of the second pixel circuit in the first direction.

[0022] In one embodiment, the holding capacitor may include: a second holding electrode disposed on the same layer as the first semiconductor layer; a third holding electrode disposed above the first gate electrode; and a fourth holding electrode disposed above the third holding electrode, wherein the fourth holding electrode may be configured as part of a drive voltage line extending along the second direction.

[0023] In one embodiment, the area of ​​the fourth holding electrode of the first pixel circuit may be different from the area of ​​the fourth holding electrode of the second pixel circuit.

[0024] One embodiment provides an electronic device including a display device, the display device comprising: a substrate; a first-1 gate line and a first-2 gate line extending on the substrate along a first direction and spaced apart from each other; a data line extending along a second direction intersecting the first direction; a first pixel circuit and a second pixel circuit, the data line being disposed between the first pixel circuit and the second pixel circuit and arranged along the first direction, wherein the first pixel circuit is connected to the first-1 gate line, and the second pixel circuit is connected to the first-2 gate line, wherein each of the first pixel circuit and the second pixel circuit includes: a first transistor including a first semiconductor layer and a first gate electrode; a storage capacitor including a second storage electrode connected to the first gate electrode; and a holding capacitor including a first holding electrode connected to the first storage electrode of the storage capacitor, wherein the capacitance of the storage capacitor of the first pixel circuit is different from the capacitance of the storage capacitor of the second pixel circuit, and / or the capacitance of the holding capacitor of the first pixel circuit is different from the capacitance of the holding capacitor of the second pixel circuit.

[0025] In one embodiment, the electronic device may be one of a smartphone, tablet computer, laptop computer, television, desktop monitor, smart glasses, head-mounted display, smartwatch, vehicle dashboard, center console, center information display (CID), and room mirror display.

[0026] As described above, in the display device and electronic device according to the present invention, by applying different capacitances of storage capacitors and / or holding capacitors according to each pixel circuit, a highly reliable display device and electronic device can be provided.

[0027] The aforementioned effects are illustrative, and the effects of the present invention are not limited to those described above. Attached Figure Description

[0028] Figure 1 This is a schematic plan view of a display device according to one embodiment.

[0029] Figure 2 This is a schematic diagram illustrating an equivalent circuit diagram of a light-emitting diode (LED) as a light-emitting element corresponding to a pixel of a display device according to an embodiment, and a pixel circuit electrically connected to the LED.

[0030] Figure 3 This is a schematic cross-sectional view of a portion of a display device according to one embodiment.

[0031] Figure 4 This is a schematic plan view showing a portion of the pixel circuitry and wiring arranged in the display area of ​​a display device according to an embodiment.

[0032] Figure 5 This is a schematic diagram showing the arrangement of transistors, storage capacitors, and holding capacitors in the pixel circuit of a display device according to one embodiment.

[0033] Figures 6 to 10 It is shown schematically by layer. Figure 5 The diagram shows the arrangement of the components of the display device, including transistors, storage capacitors, and holding capacitors.

[0034] Figure 11 This is a plan view showing a portion of a display device according to an embodiment.

[0035] Figure 12 This is a plan view showing a portion of a display device according to an embodiment.

[0036] Figure 13 This is a plan view showing a portion of a display device according to an embodiment.

[0037] Figure 14 This is a plan view showing a portion of a display device according to an embodiment.

[0038] Figure 15 This is a plan view showing a portion of a display device according to an embodiment.

[0039] Figure 16 This is a plan view showing a portion of a display device according to an embodiment.

[0040] Figure 17 This is a block diagram of an electronic device according to one embodiment.

[0041] Figure 18 This is a schematic diagram of an electronic device according to various embodiments.

[0042] Explanation of reference numerals in the attached figures PC: Pixel circuit; T1~T6: Transistor Cst: Storage capacitor; Chold: Holding capacitor 1: Display device; 10: Electronic device Detailed Implementation

[0043] This invention can be modified in various ways and can have many embodiments. Specific embodiments are exemplarily shown in the accompanying drawings and will be described in detail in the accompanying description. References and Appendix Figure 1 The effects and features of the invention, as well as the methods for achieving these effects and features, will become clear from the detailed embodiments described below. However, the invention is not limited to the embodiments disclosed below, and can be implemented in various forms.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same or corresponding constituent elements will be given the same reference numerals, and repeated descriptions thereon will be omitted.

[0045] In the following embodiments, the terms "first," "second," etc., are not intended to be limiting, but are used to distinguish one constituent element from another.

[0046] In the following embodiments, unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0047] In the following embodiments, terms such as include or have refer to the presence of features or constituent elements described in the specification, rather than precluding the possibility of adding more than one other feature or constituent element.

[0048] In the following embodiments, when referring to a membrane, region, constituent element, or other part being located above or on another part, it includes not only the case where it is located immediately above the other part, but also the case where another membrane, region, constituent element, or other part is sandwiched between the two.

[0049] For ease of explanation, the dimensions of the constituent elements in the accompanying drawings may be exaggerated or reduced. For example, for ease of explanation, the dimensions and thicknesses of the various components shown in the drawings are arbitrarily shown, therefore the present invention is not necessarily limited to the dimensions and thicknesses shown in the drawings.

[0050] In cases where an embodiment can be implemented in different ways, the specific process sequence may also be performed differently from the described sequence. For example, two processes described consecutively may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0051] In the following embodiments, when referring to the connection of membranes, regions, constituent elements, etc., it includes not only the case where the membranes, regions, and constituent elements are directly connected, but also the case where the membranes, regions, and constituent elements are indirectly connected by intervening other membranes, regions, and constituent elements. For example, in this specification, when referring to the electrical connection of membranes, regions, constituent elements, etc., it includes not only the case where the membranes, regions, and constituent elements are directly electrically connected, but also the case where the membranes, regions, and constituent elements are indirectly electrically connected by intervening other membranes, regions, and constituent elements.

[0052] Figure 1 This is a schematic plan view of a display device according to one embodiment.

[0053] Reference Figure 1 The display device 1 may include a display area DA and a peripheral area PA outside the display area DA. The display area DA, as part of the displayed image, may have multiple pixels PX arranged thereon. The display area DA may have various shapes, such as circular, elliptical, polygonal, or specific graphic shapes. The multiple pixels PX may be implemented using various light-emitting elements, such as organic light-emitting elements, inorganic light-emitting elements, and quantum dot light-emitting elements, and the light-emitting elements may be connected to pixel circuits and driven.

[0054] The peripheral area PA of the display device 1 can be arranged outside the display area DA. A driver integrated circuit (IC) that provides electrical signals to be applied to the display area DA can be arranged in the peripheral area PA, and various wirings for transmitting electrical signals generated in the driver integrated circuit can be provided.

[0055] Figure 2 This is a schematic diagram illustrating an equivalent circuit of a light-emitting diode (LED) as a light-emitting element corresponding to a pixel of a display device 1 according to an embodiment, and a pixel circuit PC electrically connected to the LED.

[0056] The pixel circuit PC can be electrically connected to the first gate line GWL for transmitting the first gate signal GW, the second gate line GRL for transmitting the second gate signal GR, the third gate line EML for transmitting the third gate signal EM, the fourth gate line GBL for transmitting the fourth gate signal GB, the fifth gate line EMBL for transmitting the fifth gate signal EMB, and the data line DL for transmitting the data signal DATA. The light emission of the light-emitting diode (LED) is controlled by the third gate signal EM and the fifth gate signal EMB; therefore, the third gate signal EM and the fifth gate signal EMB can be light emission control signals, and the third gate line EML and the fifth gate line EMBL can represent light emission control lines. The pixel circuit PC can also be electrically connected to the drive voltage line PL for transmitting the drive voltage ELVDD, the reference voltage line VRL for transmitting the reference voltage Vref, and the first initialization voltage line VAL for transmitting the first initialization voltage Vaint.

[0057] The pixel circuit PC may include a first transistor T1 to a sixth transistor T6, a storage capacitor Cst, a holding capacitor Chold, and an auxiliary capacitor Ca.

[0058] The first transistor T1 can be a driving transistor that outputs a driving current corresponding to the data signal DATA, and the second transistor T2 to the sixth transistor T6 can be switching transistors that transmit signals.

[0059] In one embodiment, the first transistor T1 through the sixth transistor T6 may be an N-channel metal-oxide-semiconductor field-effect transistor (NMOS). These plurality of thin-film transistors T1 through T6 may comprise an oxide semiconductor material. However, this is not a limitation; at least one of the plurality of thin-film transistors T1 through T6 may be a p-channel metal-oxide-semiconductor field-effect transistor (PMOS). Various modifications are possible, such as configuring the fifth transistor T5 and / or the sixth transistor T6 as PMOS transistors, while the remaining thin-film transistors may be configured as NMOS transistors, etc.

[0060] The first terminal (or, first electrode) and the second terminal (or, second electrode) of each of the first transistors T1 to the sixth transistor T6 can be either a source (or, source electrode) or a drain (or drain electrode) depending on the voltage between the first terminal and the second terminal. For example, depending on the voltage between the first terminal and the second terminal, the first terminal can be the drain and the second terminal can be the source, or the first terminal can be the source and the second terminal can be the drain. Hereinafter, the node connected to the 1-1 gate electrode of the first transistor T1 can be defined as the first node N1, and the node connected to the second terminal of the first transistor T1 can be defined as the second node N2.

[0061] The first transistor T1 can be connected to the driving voltage line PL and the light-emitting diode (LED). The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a first gate (or, a first gate electrode), a first terminal, and a second terminal connected to the second node N2. The first transistor T1 may include a first-1 gate connected to the first node N1. The first transistor T1 may also include a first-2 gate connected to its own second terminal. The first-1 gate and the first-2 gate can be arranged facing each other on different layers. For example, the first-1 gate and the first-2 gate of the first transistor T1 can have a semiconductor layer placed between them and facing each other. In this specification, the first gate (or, the first gate electrode) of the first transistor T1 may refer to the first-1 gate (or, the first gate electrode) involved in the conduction and cutoff of the first transistor T1.

[0062] The first gate (or, gate 1-1) of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the storage capacitor Cst. Gate 1-2 of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the storage capacitor Cst, and the holding capacitor Chold. The first terminal of the first transistor T1 can be connected to the driving voltage line PL via the fifth transistor T5, and the second terminal can be connected to the pixel electrode of the light-emitting diode (LED) via the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the storage capacitor Cst, and the holding capacitor Chold. The first transistor T1 can receive the data signal DATA according to the switching operation of the second transistor T2 to control the amount of driving current flowing to the LED.

[0063] The second transistor T2 can be connected to the data line DL and the first transistor T1 at its first-to-first gate. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the first transistor T1 at its first-to-first gate, the first terminal of the third transistor T3, and the storage capacitor Cst. The second transistor T2 can be electrically connected to the data line DL and the first node N1 by being turned on by the first gate signal GW transmitted to the first gate line GWL, and can transmit the data signal DATA transmitted to the data line DL to the first node N1.

[0064] The third transistor T3 can be connected to the first transistor T1's gate (1-1) and the reference voltage line VRL. The third transistor T3 may include a gate connected to the second gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the first transistor T1's gate (1-1), the second terminal of the second transistor T2, and the storage capacitor Cst. The third transistor T3 can transmit the reference voltage Vref transmitted to the reference voltage line VRL to the first node N1 by turning on the second gate signal GR transmitted to the second gate line GRL.

[0065] A fourth transistor T4 can be connected to the sixth transistor T6 and the first initialization voltage line VAL. The fourth transistor T4 can be connected between the light-emitting diode (LED) and the first initialization voltage line VAL. The fourth transistor T4 may include a gate connected to the fourth gate line GBL, a first terminal connected to the third node N3, and a second terminal connected to the first initialization voltage line VAL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the LED. The fourth transistor T4 can transmit the first initialization voltage Vaint, transmitted to the first initialization voltage line VAL, to the third node N3 by turning on the fourth gate signal GB transmitted to the fourth gate line GBL, and can initialize the pixel electrode (e.g., the anode) of the LED.

[0066] The fifth transistor T5 can be connected to the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the third gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to the third gate signal EM transmitted to the third gate line EML.

[0067] The sixth transistor T6 can be connected to the first transistor T1 and the light-emitting diode (LED). The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, a storage capacitor Cst, and a holding capacitor Chold. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the LED. The sixth transistor T6 can be turned on or off according to the fifth gate signal EMB transmitted to the fifth gate line EMBL.

[0068] The storage capacitor Cst can be connected between the gate (1-1) of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the storage capacitor Cst can be connected to the first node N1, and the second electrode can be connected to the second node N2. The first electrode of the storage capacitor Cst can be connected to the gate (1-1) of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the storage capacitor Cst can be connected to the second terminal and the gate (1-2) of the first transistor T1, the second electrode of the holding capacitor Chold, and the first terminal of the sixth transistor T6. The storage capacitor Cst can store a data voltage that compensates for the threshold voltage of the first transistor T1.

[0069] If the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 can be turned on. If the voltage at the second terminal of the first transistor T1 drops to the difference (Vref-Vth1) between the reference voltage Vref and the threshold voltage (Vth1) of the first transistor T1, the first transistor T1 is turned off, and the storage capacitor Cst can store a voltage corresponding to the threshold voltage (Vth1) of the first transistor T1 to compensate for the threshold voltage (Vth1) of the first transistor T1.

[0070] The holding capacitor Chold can be connected between the drive voltage line PL and the second node N2. The first electrode of the holding capacitor Chold can be connected to the drive voltage line PL. The second electrode of the holding capacitor Chold can be connected to the second terminal of the first transistor T1 and the first-second gate, the second electrode of the storage capacitor Cst, and the first terminal of the sixth transistor T6. The holding capacitor Chold can store a compensation voltage used to compensate for the threshold voltage (Vth1) of the first transistor T1.

[0071] The capacitance of each of the storage capacitor Cst and the holding capacitor Chold can vary depending on the color of the light emitted from the light-emitting diode (LED).

[0072] The auxiliary capacitor Ca can be electrically connected to the sixth transistor T6, the holding voltage line VSSL, and the pixel electrode of the light-emitting diode (LED). The auxiliary capacitor Ca stores and maintains the voltage corresponding to the voltage difference between the pixel electrode of the LED and the holding voltage line VSSL, thereby preventing the problem of increased black brightness when the sixth transistor T6 is turned off.

[0073] The light-emitting diode (LED) can be connected to the first transistor T1 via a sixth transistor T6. The LED includes a pixel electrode (anode) connected to a third node N3 and a counter electrode (cathode) facing the pixel electrode, and the counter electrode can receive a common voltage ELVSS. As one embodiment, the counter electrode (cathode) can be electrically connected to a holding voltage line VSSL extending to the display area and providing the common voltage ELVSS. The drive current output by the first transistor T1 flows through the LED via the turned-on fifth transistor T5 and the turned-on sixth transistor T6, enabling the LED to emit light with a brightness corresponding to the magnitude of the drive current.

[0074] As previously mentioned, the multiple thin-film transistors T1 to T6 may comprise oxide semiconductor material. Oxide semiconductors have high carrier mobility and low leakage current, therefore, even with long driving times, the voltage drop is not large. That is, in the case of oxide semiconductors, even at low-frequency driving, the color change of the image based on the voltage drop is not significant, thus enabling low-frequency driving. Therefore, by comprising oxide semiconductor material in the multiple thin-film transistors T1 to T6, a display device that reduces power consumption while preventing leakage current generation can be realized.

[0075] Although Figure 2 The illustration shows a pixel circuit PC comprising six transistors, but the invention is not limited thereto. As another embodiment, the pixel circuit PC may have five or fewer transistors, or seven or more.

[0076] Figure 3 This is a schematic cross-sectional view of a portion of a display device 1 according to one embodiment.

[0077] Reference Figure 3 The display device 1 includes a light-emitting diode (LED) disposed in a display area DA. The LED is disposed on a substrate 100, and pixel circuitry may be disposed between the substrate 100 and the LED. As one embodiment, Figure 3 The diagram shows a first transistor T1, a storage capacitor Cst, and a holding capacitor Chold, which are components of the pixel circuit.

[0078] The first transistor T1 may include a first semiconductor layer A1 and a first gate electrode G1 overlapping the first semiconductor layer A1. The first transistor T1 may be a driving transistor.

[0079] The storage capacitor Cst may include a first storage electrode C11, a second storage electrode C12, and a third storage electrode C13 arranged in different layers and overlapping each other.

[0080] The first storage electrode C11 and the third storage electrode C13 can be connected through a contact hole. The second storage electrode C12 can be connected to the first gate electrode G1. The second storage electrode C12 can be integrated with the first gate electrode G1. The third storage electrode C13 can be connected to the first semiconductor layer A1 through a contact hole.

[0081] The holding capacitor Chold may include a first holding electrode C21, a second holding electrode C22, a third holding electrode C23, and a fourth holding electrode C24 arranged in different layers and overlapping each other.

[0082] The first holding electrode C21 and the third holding electrode C23 can be connected via a contact hole. The second holding electrode C22 and the fourth holding electrode C24 can receive the same constant voltage. The first holding electrode C21 can be connected to the first storage electrode C11. The first holding electrode C21 can be integrated with the first storage electrode C11. The second holding electrode C22 can be disposed on the same layer as the first semiconductor layer A1. The third holding electrode C23 can be integrated with the third storage electrode C13. The fourth holding electrode C24 can be integrated with the upper drive voltage line PLb.

[0083] The substrate 100 may comprise a glass material or a polymer resin. As one embodiment, the substrate 100 may have a structure in which a matrix layer comprising a polymer resin and a barrier layer comprising an inorganic insulating material such as silicon oxide or silicon nitride are alternately stacked. The polymer resin may include polymers such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, etc.

[0084] A lower metal layer BML and a lower driving voltage line PLA can be disposed on the substrate 100. The lower metal layer BML can perform the functions of the first storage electrode C11 of the storage capacitor Cst and the first holding electrode C21 of the holding capacitor Chold. That is, the lower metal layer BML may include the first storage electrode C11 and the first holding electrode C21. The first storage electrode C11 and the first holding electrode C21 can be disposed on the substrate 100.

[0085] The lower drive voltage line PLA can be the transmission drive voltage ELVDD (see reference). Figure 2 ) wiring.

[0086] The lower metal layer BML and the lower driving voltage line PLA may include one or more substances selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As a partial embodiment, the lower metal layer BML may be a single layer of molybdenum, a double-layer structure having a molybdenum layer and a titanium layer stacked, or a triple-layer structure having a titanium layer, an aluminum layer, and a titanium layer stacked.

[0087] The first insulating layer 111 can be disposed on the substrate 100 in such a way that it covers the lower metal layer BML and the lower driving voltage line PLA. That is, the first insulating layer 111 can cover the first storage electrode C11 of the storage capacitor Cst and the first holding electrode C21 of the holding capacitor Chold. The first insulating layer 111 can include inorganic insulators such as silicon oxide, silicon nitride, and silicon oxynitride, and can include a single-layer or multi-layer structure containing the aforementioned inorganic insulators. A semiconductor layer can be disposed on the first insulating layer 111.

[0088] A semiconductor layer may be disposed on the first insulating layer 111. Relatedly, Figure 3 This illustration shows the arrangement of the first semiconductor layer A1 of the first transistor T1 and the second holding electrode C22 of the holding capacitor Chold on the first insulating layer 111. The first semiconductor layer A1 may include a channel region CH1 and conductive regions disposed on both sides of the channel region CH1 and conductive. Figure 3 A first region B1 is shown as one of the conductive regions disposed on one side of the channel region CH1. The second holding electrode C22 of the holding capacitor Chold can be made of the same material as the first semiconductor layer A1 and can be configured to be conductive. The second holding electrode C22 can overlap with the first holding electrode C21, and a first insulating layer 111 is disposed between the second holding electrode C22 and the first holding electrode C21.

[0089] The first semiconductor layer A1 and the second holding electrode C22 of the holding capacitor Chold may comprise an oxide semiconductor material selected from at least one of the following: indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the first semiconductor layer A1 may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc. A conductor-enhancing (or conductivity-enhancing) process, such as plasma processing, may be performed on a portion of the first semiconductor layer A1 and the second holding electrode C22.

[0090] The second insulating layer 112 can be disposed on the first insulating layer 111 in such a way that it covers the first semiconductor layer A1 and the second holding electrode C22 of the holding capacitor Chold. The second insulating layer 112 can be disposed on the first semiconductor layer A1 and the second holding electrode C22 of the holding capacitor Chold. The second insulating layer 112 may include an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride, and may include a single-layer or multi-layer structure containing the aforementioned inorganic insulating material.

[0091] A first conductive layer CL1 may be disposed on a second insulating layer 112. The first conductive layer CL1 may function as a first gate electrode G1 and a second storage electrode C12 of a storage capacitor Cst. That is, the first conductive layer CL1 may include the first gate electrode G1 and the second storage electrode C12 of the storage capacitor Cst. The first gate electrode G1 may overlap with the channel region CH1 of the first semiconductor layer A1, and the second insulating layer 112 is disposed between the first gate electrode G1 and the channel region CH1 of the first semiconductor layer A1. The second storage electrode C12 may overlap with the first storage electrode C11, and the first insulating layer 111 and the second insulating layer 112 are disposed between the second storage electrode C12 and the first storage electrode C11.

[0092] The first conductive layer CL1 may include one or more substances selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As some embodiments, the first conductive layer CL1 may be a single layer of molybdenum, a double-layer structure having a molybdenum layer and a titanium layer stacked together, or a triple-layer structure having a titanium layer, an aluminum layer, and a titanium layer stacked together.

[0093] The third insulating layer 113 may be disposed on the second insulating layer 112 in a manner that covers the first conductive layer CL1. The third insulating layer 113 may be disposed on the first gate electrode G1 and the second storage electrode C12 of the storage capacitor Cst. The third insulating layer 113 may include inorganic insulators such as silicon oxide, silicon nitride, and silicon oxynitride, and may include a single-layer or multi-layer structure containing the aforementioned inorganic insulators.

[0094] A second conductive layer CL2, a data line DL, and a connection electrode CM can be disposed on the third insulating layer 113. The second conductive layer CL2 can function as the third storage electrode C13 of the storage capacitor Cst and the third holding electrode C23 of the holding capacitor Chold. The second conductive layer CL2 can be connected to the lower metal layer BML and the first region B1 of the first semiconductor layer A1 through contact holes. That is, the third storage electrode C13 can be connected to the first storage electrode C11 through contact holes. The third storage electrode C13 can overlap with the second storage electrode C12, and the third insulating layer 113 is placed between the third storage electrode C13 and the second storage electrode C12. The third holding electrode C23 can overlap with the second holding electrode C22, and the second insulating layer 112 and the third insulating layer 113 are placed between the third holding electrode C23 and the second holding electrode C22.

[0095] The data line DL can be arranged on the same layer as the second conductive layer CL2. The data line DL can also be arranged on the same layer as the third storage electrode C13 and the third holding electrode C23. The connecting electrode CM can be connected to the second holding electrode C22 and the lower drive voltage line PLA via a contact hole. That is, the second holding electrode C22 can be connected to the lower drive voltage line PLA via the connecting electrode CM and can receive a drive voltage as a constant voltage.

[0096] The second conductive layer CL2, the data line DL, and the connecting electrode CM may include one or more substances selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As part of the embodiments, the second conductive layer CL2, the data line DL, and the connecting electrode CM may be a single layer of molybdenum, or a double-layer structure with a molybdenum and titanium layer stacked, or a triple-layer structure with a titanium layer, an aluminum layer, and a titanium layer stacked.

[0097] The fourth insulating layer 114 can be arranged on the third insulating layer 113 in a manner that covers the second conductive layer CL2, the data line DL, and the connecting electrode CM. The fourth insulating layer 114 may include an organic insulating material. For example, the fourth insulating layer 114 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), polystyrene, polymer derivatives with phenolic groups, acrylic polymers, imide polymers, aromatic ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0098] An upper driving voltage line PLb may be arranged on the fourth insulating layer 114. A portion of the upper driving voltage line PLb may function as the fourth holding electrode C24 of the holding capacitor Chold. Alternatively, the fourth holding electrode C24 may be configured as a portion of the upper driving voltage line PLb. The fourth holding electrode C24 may be arranged on the fourth insulating layer 114 and may overlap with the third holding electrode C23, with the fourth insulating layer 114 positioned between the fourth holding electrode C24 and the third holding electrode C23.

[0099] The upper driving voltage line PLb and the fourth holding electrode C24 may include one or more substances selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). As part of the embodiments, the upper driving voltage line PLb and the fourth holding electrode C24 may be a single layer of molybdenum, a double-layer structure having a molybdenum layer and a titanium layer stacked, or a triple-layer structure having a titanium layer, an aluminum layer, and a titanium layer stacked.

[0100] The fifth insulating layer 115 can be arranged on the fourth insulating layer 114 in a manner that covers the upper driving voltage line PLb and the fourth holding electrode C24. The fifth insulating layer 115 may include an organic insulating material. For example, the fifth insulating layer 115 may include photoresist, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), polystyrene, polymer derivatives with phenolic groups, acrylic polymers, imide polymers, aromatic ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, vinyl alcohol polymers, or mixtures thereof.

[0101] A light-emitting diode (LED) may be disposed on the fifth insulating layer 115. The LED may include a pixel electrode 210, a light-emitting layer 222, and a counter electrode 230.

[0102] Pixel electrode 210 may be disposed on fifth insulating layer 115. Pixel electrode 210 may include a reflective film comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. As another embodiment, pixel electrode 210 may also include a conductive oxide layer above and / or below the aforementioned reflective film. The conductive oxide layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and / or aluminum zinc oxide (AZO). As one embodiment, pixel electrode 210 may have a three-layer structure of ITO layer / Ag layer / ITO layer.

[0103] A dam layer 123 may be disposed on the pixel electrode 210. The dam layer 123 includes an opening 123OP overlapping the pixel electrode 210 and may cover the edge of the pixel electrode 210. The dam layer 123 may include an organic insulator. As one embodiment, the dam layer 123 may include a light-transmitting organic insulator. As another embodiment, the dam layer 123 may include an organic insulator containing a light-shielding material. In one embodiment, the dam layer 123 may include a polyimide (PI) adhesive and a mixture of red, green, and blue pigments. Alternatively, the dam layer 123 may include a cardo-based adhesive resin and a mixture of lactam black pigment and blue pigment. Alternatively, the dam layer 123 may include carbon black. The dam layer 123 may improve the contrast of the display device.

[0104] Spacers 125 may be disposed on the dam layer 123. Spacers 125 may comprise a different material than the dam layer 123. For example, just as the dam layer 123 may comprise a negatively photosensitive material, the spacers 125 may comprise a positively photosensitive material, both comprising different materials and may be formed separately by a single masking process. As another embodiment, spacers 125 may comprise the same material as the dam layer 123 and may be formed together in the same masking process (e.g., a halftone mask process).

[0105] The light-emitting layer 222 may include a high-molecular-weight organic material or a low-molecular-weight organic material that emits light of a predetermined color. Depending on the light-emitting diode (LED), the light-emitting layer 222 may include a material that emits red, green, or blue light.

[0106] Functional layers may also be included below and / or above the light-emitting layer 222. For example, a first functional layer 221 may be further included between the pixel electrode 210 and the light-emitting layer 222, and a second functional layer 223 may be further included between the light-emitting layer 222 and the counter electrode 230, which will be described later. The first functional layer 221 may include a hole transport layer and / or a hole injection layer. The second functional layer 223 may include an electron transport layer and / or an electron injection layer.

[0107] The counter electrode 230 can be constructed using a conductive material with a low work function. For example, the counter electrode 230 may include a (semi-)transparent layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or alloys thereof. Alternatively, the counter electrode 230 may further include a layer such as ITO, IZO, ZnO, or In2O3 on top of the (semi-)transparent layer comprising the aforementioned materials.

[0108] Unlike the case where the pixel electrode 210 is formed separately in a manner corresponding to the light-emitting diode (LED), the counter electrode 230 may extend to correspond to the pixel electrode 210. For example, the pixel electrode 210 of one LED and the pixel electrode 210 of another LED may be separated from each other and spaced apart, but the counter electrode 230 overlapping with the pixel electrode 210 may extend to cover the aforementioned pixel electrode 210.

[0109] The encapsulation layer 300 can be disposed on the light-emitting diode (LED) and can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. As one embodiment, Figure 3 The illustration shows a case where the encapsulation layer 300 includes a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330.

[0110] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include one or more inorganic insulators selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be a single layer or multiple layers comprising the aforementioned substances. The organic encapsulation layer 320 may include polymer-based substances. Polymer-based materials may include acrylic resins, epoxy resins, polyimide resins, and polyethylene resins, etc. As one embodiment, the organic encapsulation layer 320 may include acrylate.

[0111] Figure 4 This is a schematic plan view showing a portion of the pixel circuitry and wiring arranged in the display area DA of a display device 1 according to an embodiment.

[0112] Reference Figure 4 The display device 1 includes a first gate line GWL1 and a first gate line GWL2 extending along a first direction (x direction), and a data line DL and a wiring WL extending along a second direction (y direction) intersecting the first direction. Furthermore, it includes a lower driving voltage line PLA extending along the first direction and an upper driving voltage line PLb extending along the second direction.

[0113] In the display area DA, the pixel circuits PC can be arranged along a first direction (e.g., the x-direction) and a second direction (e.g., the y-direction). Figure 4 Two pixel circuits PC, namely the first pixel circuit PC1 and the second pixel circuit PC2, are arranged adjacent to each other in the same row (e.g., the i-th row).

[0114] In this embodiment, the first pixel circuit PC1 and the second pixel circuit PC2 can share the data line DL. That is, the second transistor of the first pixel circuit PC1 and the second transistor of the second pixel circuit PC2 can be connected to the same data line DL. The first pixel circuit PC1 and the second pixel circuit PC2 can place the data line DL between them and arrange it along a first direction. The data line DL can be arranged extending along a second direction between the first pixel circuit PC1 and the second pixel circuit PC2.

[0115] In this embodiment, the first pixel circuit PC1 and the second pixel circuit PC2 share a data line DL, thereby reducing the number of data lines DL. Accordingly, the number of IC chips providing data signals can be reduced, thereby reducing power consumption and saving costs.

[0116] Furthermore, by sharing a data line DL, with the data line DL arranged on one side of each pixel circuit PC and other wiring WL arranged on the same layer as the data line DL on the other side, space can be used efficiently. For example, the wiring WL can be used as an initialization voltage line, a holding voltage line for transmitting a common voltage, etc.

[0117] A first pixel circuit PC1 can be connected to a first light-emitting diode (LED) to drive the first LED, and a second pixel circuit PC2 can be connected to a second LED to drive the second LED. In one embodiment, the first LED and the second LED can emit light of the same color. That is, the pixel circuit PC sharing the data line DL can be connected to LEDs that emit light of the same color. Accordingly, brightness differences based on color can be disregarded, thereby reducing power consumption.

[0118] The pixel circuits PCs of the shared data line DL can receive different gate signals from each other. The first pixel circuit PC1 can be connected to the first gate line GWL1, and the second pixel circuit PC2 can be connected to the first gate line GWL2. The pixel circuit PCs arranged on the left side of the shared data line DL can be connected to the first gate line GWL1, and the pixel circuit PCs arranged on the right side of the shared data line DL can be connected to the first gate line GWL2.

[0119] The driving voltage line PL may include a lower driving voltage line PLA and an upper driving voltage line PLb arranged on different layers. The lower driving voltage line PLA may be configured to extend along a first direction, and the upper driving voltage line PLb may extend along a second direction. The lower driving voltage line PLA and the upper driving voltage line PLb may be connected through contact holes CNT to form a mesh structure.

[0120] Figure 5This is a schematic diagram showing the arrangement of transistors T1 to T6, storage capacitor Cst, and holding capacitor Chold in the pixel circuit of a display device 1 according to an embodiment. Figures 6 to 10 It is shown schematically by layer. Figure 5 The diagram shows the arrangement of the components of the display device 1, including transistors T1 to T6, storage capacitor Cst, and holding capacitor Chold.

[0121] like Figures 5 to 10 As shown, the display device 1 includes a first pixel circuit PC1 and a second pixel circuit PC2 arranged side-by-side in a first direction, wherein a data line DL is positioned between the first pixel circuit PC1 and the second pixel circuit PC2. Figures 5 to 10 The structure shown can be repeated in the first direction (x direction) and / or the second direction (y direction).

[0122] Each of the first pixel circuit PC1 and the second pixel circuit PC2 may include transistors T1 to T6, a storage capacitor Cst, and a holding capacitor Chold. Most of the components included in the first pixel circuit PC1 may be arranged symmetrically with respect to the data line DL and the components included in the second pixel circuit PC2. In some embodiments, some components may be arranged asymmetrically. For example, the second transistor T2 and the third transistor T3 may be arranged asymmetrically with respect to the data line DL. Furthermore, the capacitances of the storage capacitor Cst and / or the holding capacitor Chold may be configured to be different from each other.

[0123] Reference Figure 3 and Figure 6 On substrate 100 (refer to) Figure 3 The lower gate line GWL1a, the lower gate line GWL2a, the reference voltage line VRL, the second gate line GRL, the lower metal layer BML, the lower drive voltage line PLA, the holding voltage line VSSL, the first initialization voltage line VAL1, and the second initialization voltage line VAL2 can be arranged on the upper gate line.

[0124] The lower gate line GWL1a (1-1), the lower gate line GWL2a (1-2), the reference voltage line VRL, the second gate line GRL, the lower drive voltage line PLA, the holding voltage line VSSL, the first initialization voltage line VAL1, and the second initialization voltage line VAL2 can extend along the first direction (x direction).

[0125] The lower gate line GWL1a of 1-1 can transmit the first gate signal GW to the first pixel circuit PC1 (see reference). Figure 2 The first gate signal GWL2a at the lower part of the first and second pixels can transmit the first gate signal GW to the second pixel circuit PC2 (see reference). Figure 2 The reference voltage line VRL can transmit the reference voltage Vref, and the second gate line GRL can transmit the second gate signal GR (refer to...). Figure 2 The VSSL voltage line can transmit the common voltage ELVSS.

[0126] The lower drive voltage line PLA can transmit the drive voltage ELVDD. The lower drive voltage line PLA may include a shield SHP protruding in the y-direction between the first pixel circuit PC1 and the second pixel circuit PC2. Since a constant voltage is applied to the shield SHP, interference caused by unwanted electrical signals that may be applied to the pixel circuits can be blocked.

[0127] The first initialization voltage line VAL1 can transmit a first initialization voltage (Vint1) to the pixel circuits driving the green and blue pixels. The second initialization voltage line VAL2 can transmit a second initialization voltage (Vint2) to the pixel circuits driving the red pixel. In some embodiments, the first initialization voltage (Vint1) and the second initialization voltage (Vint2) can have different values ​​from each other.

[0128] The lower metal layer BML can have an isolated shape, and one lower metal layer BML can be arranged in each pixel circuit. The lower metal layer BML can function as the first storage electrode C11 and the first holding electrode C21. Furthermore, the lower metal layer BML can overlap with the first gate electrode G1 and the first semiconductor layer A1 (described later), thereby preventing or minimizing light incident from the outside onto the first semiconductor layer A1. The lower metal layer BML can also function as the lower gate electrode of the first transistor T1.

[0129] A first insulating layer 111 may be disposed on the lower gate line GWL1a (1-1), the lower gate line GWL2a (1-2), the reference voltage line VRL, the lower metal layer BML, the lower drive voltage line PLA, the holding voltage line VSSL, the first initialization voltage line VAL1, and the second initialization voltage line VAL2. Figure 3 ).

[0130] Reference Figure 3 and Figure 7 The first semiconductor layer A1 to the sixth semiconductor layer A6 and the second holding electrode C22 can be disposed on the first insulating layer 111. The first semiconductor layer A1 to the sixth semiconductor layer A6 and the second holding electrode C22 can comprise the same material.

[0131] The first semiconductor layer A1 and the fifth semiconductor layer A5 can be connected as one unit. The second semiconductor layer A2 and the third semiconductor layer A3 can be connected as one unit. The fourth semiconductor layer A4 and the sixth semiconductor layer A6 can be connected as one unit. The first semiconductor layer A1 can be arranged adjacent to the second semiconductor layer A2 and the third semiconductor layer A3, but can be separated from each other. The fifth semiconductor layer A5 can be arranged adjacent to the sixth semiconductor layer A6, but can be separated from each other.

[0132] The second holding electrode C22 can be arranged to overlap with the lower metal layer BML. At least a portion of the lower metal layer BML that overlaps with the second holding electrode C22 can be the first holding electrode C21 of the holding capacitor Chold. The second holding electrode C22 can have an isolated shape, and one second holding electrode C22 can be arranged in each pixel circuit. A portion of the second holding electrode C22 can overlap with the lower driving voltage line PLA and can be electrically connected to the lower driving voltage line PLA to receive the driving voltage.

[0133] exist Figure 7 A second insulating layer 112 may be disposed on the structure shown (e.g., the first semiconductor layer A1 to the sixth semiconductor layer A6 and the second holding electrode C22). Figure 3 ).

[0134] Reference Figure 3 and Figure 8 The second insulating layer 112 may be provided with a first-1 upper gate line GWL1b, a first-2 upper gate line GWL2b, a third gate line EML, a fourth gate line GBL, a fifth gate line EMBL, a first gate electrode G1, a second gate electrode G2, and a third gate electrode G3.

[0135] The first-1 upper gate line GWL1b, the first-2 upper gate line GWL2b, the third gate line EML, the fourth gate line GBL, and the fifth gate line EMBL can extend along the first direction (x direction).

[0136] The upper gate line GWL1b of 1-1 can transmit the first gate signal GW to the first pixel circuit PC1 (see reference). Figure 2 The first gate signal GWL2b of the first-second upper gate line can transmit the first gate signal GW to the second pixel circuit PC2 (see reference). Figure 2The first-1 upper gate line GWL1b can overlap with the first-1 lower gate line GWL1a. The first-2 upper gate line GWL2b can overlap with the first-2 lower gate line GWL2a. The first-1 gate line GWL1 can include the first-1 upper gate line GWL1b and the first-1 lower gate line GWL1a. The first-2 gate line GWL2 can include the first-2 upper gate line GWL2b and the first-2 lower gate line GWL2a.

[0137] The third gate line EML can transmit the third gate signal EM, the fourth gate line GBL can transmit the fourth gate signal GB, and the fifth gate line EMBL can transmit the fifth gate signal EMB.

[0138] The first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 can be configured in an isolated shape. The first gate electrode G1 can overlap with the first semiconductor layer A1 to form a first transistor T1. The first gate electrode G1 can also function as the second storage electrode C12 of the storage capacitor Cst. The first gate electrode G1 can overlap with the lower metal layer BML.

[0139] The second gate electrode G2 can overlap with the second semiconductor layer A2 to form the second transistor T2. The third gate electrode G3 can overlap with the third semiconductor layer A3 to form the third transistor T3.

[0140] The third gate line EML can overlap with the fifth semiconductor layer A5, and the region of the third gate line EML that overlaps with the fifth semiconductor layer A5 can function as the fifth gate electrode. The fourth gate line GBL can overlap with the fourth semiconductor layer A4, and the region of the fourth gate line GBL that overlaps with the fourth semiconductor layer A4 can function as the fourth gate electrode. The fifth gate line EML can overlap with the sixth semiconductor layer A6, and the region of the fifth gate line EML that overlaps with the sixth semiconductor layer A6 can function as the sixth gate electrode.

[0141] exist Figure 8 A third insulating layer 113 can be arranged on the structure shown. Figure 3 ).

[0142] Reference Figure 3 and Figure 9 Data lines DL, a second conductive layer CL2, and connecting electrodes CM and CM' can be arranged on the third insulating layer 113. The data lines DL, the second conductive layer CL2, and the connecting electrodes CM and CM' can be made of the same material.

[0143] The data line DL can extend along a second direction (y-direction) between the first pixel circuit PC1 and the second pixel circuit PC2. The first pixel circuit PC1 and the second pixel circuit PC2 can share the data line DL.

[0144] The second conductive layer CL2 may include a third storage electrode C13 of the storage capacitor Cst and a third holding electrode C23 of the holding capacitor Chold. Connecting electrodes CM and CM' may be used to connect the components disposed beneath it to each other. The second conductive layer CL2 and the connecting electrodes CM and CM' may be configured in an isolated shape.

[0145] exist Figure 9 A fourth insulating layer 114 can be arranged on the structure shown. Figure 3 ).

[0146] Reference Figure 3 and Figure 10 An upper driving voltage line PLb and a second wiring WLb may be arranged on the fourth insulating layer 114. The upper driving voltage line PLb and the second wiring WLb may extend along a second direction.

[0147] The second wiring WLb can overlap with the data line DL. The second wiring WLb can be used to provide various signals or constant voltages. For example, the second wiring WLb can be used as a reference voltage line, a holding voltage line, etc., extending in a second direction. The second wiring WLb can shield the data line DL.

[0148] The upper driving voltage line PLb can be configured to branch into two branches in the region overlapping with the second conductive layer CL2. The upper driving voltage line PLb may include a first branch PLb1 and a second branch PLb2. Alternatively, the upper driving voltage line PLb can be configured with an opening PL_OP in the region overlapping with the second conductive layer CL2, the central portion of which is removed. The upper driving voltage lines PLb arranged on either side of the opening PL_OP can be referred to as the first branch PLb1 and the second branch PLb2, respectively. The first branch PLb1 may overlap with the third gate electrode G3 of the third transistor T3. The second branch PLb2 may overlap with the second gate electrode G2 of the second transistor T2.

[0149] The second conductive layer CL2 serves as the third holding electrode C23 for holding capacitor Chold, and the area of ​​the upper driving voltage line PLb that overlaps with the second conductive layer CL2 serves as the fourth holding electrode C24 for holding capacitor Chold. That is, the first branch PLb1 and the second branch PLb2 serve as the fourth holding electrode C24 for holding capacitor Chold.

[0150] The first pixel circuit PC1 and the second pixel circuit PC2 are respectively connected to the first-1 gate line GWL1 and the first-2 gate line GWL2, and receive the first gate signal independently. Due to this mechanism, a brightness difference may occur between the first light-emitting diode driven by the first pixel circuit PC1 and the second light-emitting diode driven by the second pixel circuit PC2.

[0151] To minimize such a brightness difference, in this embodiment, the capacitance of the storage capacitor Cst and / or the holding capacitor Chold of the first pixel circuit PC1 can be configured to be different from the capacitance of the storage capacitor Cst and / or the holding capacitor Chold of the second pixel circuit PC2.

[0152] Figure 11 This is a plan view showing a portion of the configuration of a display device 1 according to an embodiment of the present invention. Specifically, Figure 11 The diagram shows a portion of the storage capacitor Cst and the holding capacitor Chold included in the first pixel circuit PC1 and the second pixel circuit PC2 of the shared data line DL.

[0153] Reference Figure 11 The storage capacitor Cst can be configured with a first storage electrode C11, a second storage electrode C12, and a third storage electrode C13 overlapping. The first storage electrode C11 and the third storage electrode C13 can be connected through a first contact hole CNT1.

[0154] The holding capacitor Chold may include a first holding electrode C21, a second holding electrode C22, and a third holding electrode C23. The holding capacitor Chold may be configured with a first holding electrode C21, a second holding electrode C22, a third holding electrode C23, and a fourth holding electrode C24. Figure 5 )overlapping.

[0155] The first holding electrode C21 can be connected to the first storage electrode C11. The first holding electrode C21 can be integrated with the first storage electrode C11. The third holding electrode C23 can be connected to the third storage electrode C13. The third holding electrode C23 can be integrated with the third storage electrode C13. The first holding electrode C21 and the third holding electrode C23 can be connected through the first contact hole CNT1.

[0156] The storage capacitor Cst may overlap with the first transistor T1. The first storage electrode C11 may be connected to the first gate electrode G1 of the first transistor T1. The first storage electrode C11 may be integrated with the first gate electrode G1 of the first transistor T1. The first storage electrode C11 may be arranged to overlap with the first semiconductor layer A1 of the first transistor T1.

[0157] In this embodiment, the capacitance of the storage capacitor Cst of the first pixel circuit PC1 can be configured to be different from the capacitance of the storage capacitor Cst of the second pixel circuit PC2.

[0158] Therefore, the first width SW1 of the second storage electrode C12 of the first pixel circuit PC1 in the first direction (x direction) can be formed to be different from the second width SW2 of the second storage electrode C12 of the second pixel circuit PC2 in the first direction (x direction). For example, the first width SW1 can be configured to be smaller than the second width SW2. In this case, the first pixel circuit PC1 can be arranged to the left of the data line DL, and the second pixel circuit PC2 can be arranged to the right of the data line DL.

[0159] Conversely, the area of ​​the first storage electrode C11 of the first pixel circuit PC1 can be configured to be the same as the area of ​​the first storage electrode C11 of the second pixel circuit PC2, and the area of ​​the third storage electrode C13 of the first pixel circuit PC1 can be configured to be the same as the area of ​​the third storage electrode C13 of the second pixel circuit PC2.

[0160] The area of ​​the second storage electrode 12 can be configured to be smaller than the area of ​​the first storage electrode C11 and the area of ​​the third storage electrode C13. In a plane, the edge of the second storage electrode C12 can be arranged inside the edge of the first storage electrode C11. The edge of the second storage electrode C12 can also be arranged inside the edge of the third storage electrode C13. By adjusting the width of the second storage electrode C12 through the arrangement described above, process variations can be minimized while adjusting the capacitance of the storage capacitor Cst.

[0161] The first width SW1 and the second width SW2 can be set to values ​​that minimize the difference in brightness between the first light-emitting diode connected to the first pixel circuit PC1 and the second light-emitting diode connected to the second pixel circuit PC2. In this case, the first and second light-emitting diodes can emit light of the same color. In one embodiment, the difference between the second width SW2 and the first width SW1 can be in the range of approximately 0.7% to approximately 10% of the first width SW1.

[0162] Figure 12 This is a plan view showing a portion of the configuration of a display device 1 according to an embodiment of the present invention. Figure 12 In, with Figure 11 The same reference numerals in the figures indicate the same parts.

[0163] In this embodiment, the capacitance of the holding capacitor Chold of the first pixel circuit PC1 can be configured to be different from the capacitance of the holding capacitor Chold of the second pixel circuit PC2.

[0164] Therefore, the first width HW1 of the second holding electrode C22 of the first pixel circuit PC1 in the first direction (x direction) can be formed to be different from the second width HW2 of the second holding electrode C22 of the second pixel circuit PC2 in the first direction (x direction). For example, the first width HW1 can be configured to be smaller than the second width HW2. In this case, the first pixel circuit PC1 can be arranged to the left of the data line DL, and the second pixel circuit PC2 can be arranged to the right of the data line DL.

[0165] On a plane, the edge of the second holding electrode C22 can be arranged inside the edge of the first holding electrode C21. The edge of the second holding electrode C22 can be arranged inside the edge of the third holding electrode C23. By adjusting the width of the second holding electrode C22 through the arrangement described above, it is possible to minimize process deviations while adjusting the capacitance of the holding capacitor Chold.

[0166] The first width HW1 and the second width HW2 can be set to the following values: while adjusting the brightness of the first light-emitting diode connected to the first pixel circuit PC1 and the brightness of the second light-emitting diode connected to the second pixel circuit PC2, the difference based on each brightness is minimized. At this time, the first light-emitting diode and the second light-emitting diode can emit light with the same or similar brightness.

[0167] Figure 13 This is a plan view showing a portion of the configuration of a display device 1 according to an embodiment of the present invention. Specifically, Figure 13 The diagram shows a portion of the holding capacitor Chold included in the first pixel circuit PC1 and the second pixel circuit PC2 of the shared data line DL.

[0168] The holding capacitor Chold may include a third holding electrode C23 and a fourth holding electrode C24. The fourth holding electrode C24 may be connected to the upper drive voltage line PLb. The fourth holding electrode C24 may be integrated with the upper drive voltage line PLb. The upper drive voltage line PLb may branch into a first branch PLb1 and a second branch PLb2 in the region overlapping with the third holding electrode C23. The fourth holding electrode C24 may include the first branch PLb1 and the second branch PLb2.

[0169] In this embodiment, the capacitance of the holding capacitor Chold of the first pixel circuit PC1 can be configured to be different from the capacitance of the holding capacitor Chold of the second pixel circuit PC2. The area of ​​the holding capacitor Chold of the first pixel circuit PC1 can be configured to be different from the area of ​​the holding capacitor Chold of the second pixel circuit PC2.

[0170] Therefore, the first branch PLb1 and the second branch PLb2 in the fourth holding electrode C24 of the first pixel circuit PC1 extend continuously along the second direction (y direction), but either the first branch PLb1 or the second branch PLb2 in the fourth holding electrode C24 of the second pixel circuit PC2 can be disconnected in the region overlapping with the third holding electrode C23, thus having a gap g1. Here, as an example, the second branch PLb2 of the fourth holding electrode C24 of the second pixel circuit PC2 is disconnected in the second direction with a gap g1, but the direction of disconnection is not limited to the second direction as long as a gap can be formed. By forming the gap g1, the area of ​​the fourth holding electrode C24 is reduced. The capacitance of the holding capacitor Chold can be adjusted by adjusting the length of the gap g1. Accordingly, the capacitance of the holding capacitor Chold of the first pixel circuit PC1 can be configured to be greater than the capacitance of the holding capacitor Chold of the second pixel circuit PC2.

[0171] Figure 14 This is a plan view showing a portion of the configuration of a display device 1 according to an embodiment of the present invention. Figure 14 In, with Figure 13 The same reference numerals indicate the same parts.

[0172] In this embodiment, the capacitance of the holding capacitor Chold of the first pixel circuit PC1 can be configured to be different from the capacitance of the holding capacitor Chold of the second pixel circuit PC2. The area of ​​the holding capacitor Chold of the first pixel circuit PC1 can be configured to be different from the area of ​​the holding capacitor Chold of the second pixel circuit PC2.

[0173] Therefore, the widths PW1a and PW1b of the first branch PLb1 and / or the second branch PLb2 in the fourth holding electrode C24 of the first pixel circuit PC1 in the first direction (x direction) can be configured to be different from the widths PW2a and PW2b of the first branch PLb1 and / or the second branch PLb2 in the first direction (x direction) of the fourth holding electrode C24 of the second pixel circuit PC2. For example, the widths PW1a and PW1b of the first branch PLb1 and the second branch PLb2 in the first direction (x direction) can be configured to be greater than the widths PW2a and PW2b of the first branch PLb1 and the second branch PLb2 in the first direction (x direction) of the fourth holding electrode C24 of the second pixel circuit PC2. However, this is only exemplary, and the width of only one of the first branch PLb1 and the second branch PLb2 can be adjusted.

[0174] Figure 15 This is a plan view showing a portion of the configuration of a display device 1 according to an embodiment of the present invention. Specifically, a second storage electrode C12 is shown arranged in the pixel circuits PC1 to PC12 constituting a 2×6 array.

[0175] Reference Figure 15 In the first row, the first pixel circuit PC1 and the second pixel circuit PC2 are arranged with the first data line DL1 placed between them, and the third pixel circuit PC3 and the fourth pixel circuit PC4 are arranged with the second data line DL2 placed between them. Furthermore, the fifth pixel circuit PC5 and the sixth pixel circuit PC6 are arranged with the third data line DL3 placed between them.

[0176] In the second row, the seventh pixel circuit PC7 and the eighth pixel circuit PC8 are arranged with the first data line DL1 placed between them, and the ninth pixel circuit PC9 and the tenth pixel circuit PC10 are arranged with the second data line DL2 placed between them. Furthermore, the eleventh pixel circuit PC11 and the twelfth pixel circuit PC12 are arranged with the third data line DL3 placed between them.

[0177] The first pixel circuit PC1, the second pixel circuit PC2, the seventh pixel circuit PC7, and the eighth pixel circuit PC8 can be pixel circuits that drive LEDs that emit red light. The third pixel circuit PC3, the fourth pixel circuit PC4, the ninth pixel circuit PC9, and the tenth pixel circuit PC10 can be pixel circuits that drive LEDs that emit green light. The fifth pixel circuit PC5, the sixth pixel circuit PC6, the eleventh pixel circuit PC11, and the twelfth pixel circuit PC12 can be pixel circuits that drive LEDs that emit blue light.

[0178] In this embodiment, each of pixel circuits PC1 to PC12 includes a second storage electrode C12, and based on respective data lines DL1 to DL3, the width of the second storage electrode C12 arranged on the left side and the width of the second storage electrode C12 arranged on the right side can be configured to be different from each other. (w1≠w2, w3≠w4, w5≠w6, w7≠w8, w9≠w10, w11≠w12). In some embodiments, the width of the second storage electrode C12 arranged on the left side based on respective data lines DL1 to DL3 can be configured to be less than the width of the second storage electrode C12 arranged on the right side (w1<w2, w3<w4, w5<w6, w7<w8, w9<w10, w11<w12). Here, the width means the width in the first direction (x direction).

[0179] In the same column, the width of the second storage electrode C12 arranged in the first row can be configured to be different from the width of the second storage electrode C12 arranged in the second row. For example, the width w1 of the second storage electrode C12 included in the first pixel circuit PC1 can be configured to be different from the width w7 of the second storage electrode C12 included in the seventh pixel circuit PC7. In one embodiment, the widths of the second storage electrodes C12 included in the first pixel circuit PC1 to the twelfth pixel circuit PC12 can all have different values. However, it is not limited thereto. In one embodiment, at least a part of the widths of the second storage electrodes C12 included in the first pixel circuit PC1 to the twelfth pixel circuit PC12 can be configured to be the same.

[0180] Such an arrangement of the second storage electrode C12 can repeatedly arrange the pixel circuits PC constituting a 2×6 array as a unit cell throughout the display device 1.

[0181] Figure 16 is a plan view showing a part of the configuration of the display device 1 according to an embodiment of the present invention. Specifically, the fourth holding electrode C24 arranged in the pixel circuits PC1 to PC12 constituting a 2×6 array is shown. In Figure 16 In, the same reference numerals as Figure 15 denote the same components.

[0182] Referring to Figure 16 In, the fourth holding electrode C24 can include a first branch PLb1 and a second branch PLb2. In this embodiment, each of pixel circuits PC1 to PC12 includes a fourth holding electrode C24, and based on respective data lines DL1 to DL3, the shape of the fourth holding electrode C24 arranged on the left side and the shape of the fourth holding electrode C24 arranged on the right side can be configured to be different from each other.

[0183] The shape of the fourth holding electrode C24, which is included in the first pixel circuit PC1 to the twelfth pixel circuit PC12, can be varied. For example, in the first pixel circuit PC1, a gap can be formed in the second branch PLb2, while in the second pixel circuit PC2, a gap can be formed in the first branch PLb1. In the fourth pixel circuit PC4, it can extend continuously without forming a gap in either the first branch PLb1 or the second branch PLb2. The size of the gaps formed in each branch PLb1 and PLb2 can also be varied.

[0184] This arrangement of the fourth holding electrode C24 allows the pixel circuits PC constituting a 2×6 array to be repeatedly arranged as a unit throughout the entire display device 1.

[0185] refer to Figures 11 to 16 The described embodiments are capable of various modifications, including implementation individually or in combination with each other. According to the embodiments described above, the brightness difference between light-emitting diodes can be minimized by adjusting the capacitance values ​​of the storage capacitor and / or holding capacitor of the pixel circuit sharing the data line DL.

[0186] The display device according to the above embodiments can be applied to a variety of electronic devices. An electronic device according to one embodiment includes the above-described display device, and may further include modules or devices with other additional functions in addition to the display device.

[0187] Figure 17 This is a block diagram of an electronic device according to one embodiment. (Refer to...) Figure 17 According to one embodiment, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0188] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0189] The memory 13 can store the data information required for the operation of the processor 12 or the display module 11. If the processor 12 runs an application stored in the memory 13, the image data signal and / or input control signal can be transmitted to the display module 11, which can process the received signal and output the image information through the display screen.

[0190] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0191] At least one of the various components of the electronic device 10 described above may be included within the display device 1 according to the above embodiments. Furthermore, a portion of individual modules functionally included within a single module may be included within the display device 1, while another portion may be provided independently of the display device 1. For example, the display device 1 may include a display module 11, while the processor 12, memory 13, and power module 14 may be provided in the form of other devices within the electronic device 10 that differ from the display device 1.

[0192] Figure 18 This is a schematic diagram of an electronic device according to various embodiments.

[0193] Reference Figure 18 The various electronic devices that can be used with the display device 1 according to the embodiment may include not only electronic devices for displaying images (smartphone 10_1a, tablet PC 10_1b, laptop computer 10_1c, television (TV) 10_1d, desktop monitor 10_1e, etc.), but also wearable electronic devices including display modules (such as smart glasses 10_2a, head-mounted display 10_2b, smartwatch 10_2c, etc.) and vehicle electronic devices 10_3 including display modules (such as a car dashboard, center fascia, center information display (CID) arranged on the dashboard, room mirror display, etc.).

[0194] As described above, although the invention has been illustrated with reference to the embodiments shown in the accompanying drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true scope of protection of the invention should be determined by the technical concept described in the claims.

Claims

1. A display device, comprising: substrate; Gate lines 1-1 and 1-2 extend along a first direction on the substrate and are spaced apart from each other; The data cable extends along a second direction that intersects the first direction; The first pixel circuit and the second pixel circuit are configured such that the data line is placed between the first pixel circuit and the second pixel circuit and arranged along the first direction. The first pixel circuit is connected to the first-1 gate line, and the second pixel circuit is connected to the first-2 gate line. Each of the first pixel circuit and the second pixel circuit includes: The first transistor includes a first semiconductor layer and a first gate electrode; The storage capacitor includes a second storage electrode connected to the first gate electrode. The capacitance of the storage capacitor in the first pixel circuit is different from the capacitance of the storage capacitor in the second pixel circuit.

2. The display device as claimed in claim 1, wherein, The first pixel circuit and the second pixel circuit share the data line.

3. The display device as claimed in claim 1, further comprising: The first light-emitting diode is connected to the first pixel circuit; as well as The second light-emitting diode is connected to the second pixel circuit. The first LED and the second LED emit light of the same color.

4. The display device as claimed in claim 1, wherein, The storage capacitor further includes a third storage electrode, disposed above the second storage electrode. The third storage electrode is connected to the first storage electrode of the storage capacitor through a contact hole.

5. The display device as claimed in claim 4, wherein, The area of ​​the first storage electrode in the first pixel circuit is the same as the area of ​​the first storage electrode in the second pixel circuit. The area of ​​the third storage electrode of the first pixel circuit is the same as the area of ​​the third storage electrode of the second pixel circuit.

6. The display device as claimed in claim 1, wherein, The width of the second storage electrode of the first pixel circuit in the first direction is different from the width of the second storage electrode of the second pixel circuit in the first direction.

7. The display device as claimed in claim 6, wherein, On a plane, the edge of the second storage electrode is arranged inside the edge of the first storage electrode of the storage capacitor.

8. The display device as claimed in claim 1, wherein, Each of the first pixel circuit and the second pixel circuit further includes: A holding capacitor includes a first holding electrode connected to the first storage electrode of the storage capacitor. The capacitance of the holding capacitor in the first pixel circuit is different from the capacitance of the holding capacitor in the second pixel circuit.

9. The display device as claimed in claim 1, wherein, Each of the first pixel circuit and the second pixel circuit also includes a holding capacitor. The holding capacitor includes: The first holding electrode is connected to the first storage electrode of the storage capacitor, and The second holding electrode is disposed on the same layer as the first semiconductor layer. Wherein, the width of the second holding electrode of the first pixel circuit in the first direction is different from the width of the second holding electrode of the second pixel circuit in the first direction.

10. The display device as claimed in claim 1, wherein, Each of the first pixel circuit and the second pixel circuit also includes a holding capacitor. The holding capacitor includes: The first holding electrode is connected to the first storage electrode of the storage capacitor; The second holding electrode is disposed on the same layer as the first semiconductor layer; A third holding electrode is disposed above the first gate electrode; and The fourth holding electrode is disposed above the third holding electrode. The fourth holding electrode is configured as part of a drive voltage line extending along the second direction.

11. The display device as claimed in claim 10, wherein, The fourth holding electrode is configured to branch into a first branch and a second branch in the region overlapping with the third holding electrode. The first branch arranged in the first pixel circuit is arranged continuously. In this configuration, the first branch arranged in the second pixel circuit is disconnected and equipped with a gap.

12. The display device as claimed in claim 10, wherein, The fourth holding electrode is configured to branch into a first branch and a second branch in the region overlapping with the third holding electrode. Wherein, the width of at least one of the first branch and the second branch arranged in the first pixel circuit is configured to be different from the width of the first branch and the second branch arranged in the second pixel circuit.

13. The display device as claimed in claim 1, further comprising: The third and fourth pixel circuits are arranged in the next row after the first and second pixel circuits, and the data line is positioned between the third and fourth pixel circuits. The capacitance of the storage capacitor included in the third pixel circuit is different from the capacitance of the storage capacitor included in the first pixel circuit.

14. The display device of claim 13, further comprising: The first light-emitting diode is connected to the first pixel circuit; The second light-emitting diode is connected to the second pixel circuit; The third light-emitting diode is connected to the third pixel circuit; as well as The fourth light-emitting diode is connected to the fourth pixel circuit. The first light-emitting diode, the second light-emitting diode, the third light-emitting diode, and the fourth light-emitting diode emit light of the same color.

15. A display device, comprising: substrate; Gate lines 1-1 and 1-2 extend along a first direction on the substrate and are spaced apart from each other; The data cable extends along a second direction that intersects the first direction; The first pixel circuit and the second pixel circuit are arranged along the first direction and share the data line. The first pixel circuit is connected to the first-1 gate line, and the second pixel circuit is connected to the first-2 gate line. Each of the first pixel circuit and the second pixel circuit includes: The first transistor includes a first semiconductor layer and a first gate electrode; The storage capacitor includes a second storage electrode connected to the first gate electrode; and A holding capacitor includes a first holding electrode connected to the first storage electrode of the storage capacitor. The capacitance of the holding capacitor in the first pixel circuit is different from the capacitance of the holding capacitor in the second pixel circuit.

16. The display device as claimed in claim 15, wherein, The holding capacitor further includes: The second holding electrode is disposed on the same layer as the first semiconductor layer. Wherein, the width of the second holding electrode of the first pixel circuit in the first direction is different from the width of the second holding electrode of the second pixel circuit in the first direction.

17. The display device as claimed in claim 15, wherein, The holding capacitor includes: The second holding electrode is disposed on the same layer as the first semiconductor layer; A third holding electrode is disposed above the first gate electrode; and The fourth holding electrode is disposed above the third holding electrode. The fourth holding electrode is configured as part of a drive voltage line extending along the second direction.

18. The display device as claimed in claim 17, wherein, The area of ​​the fourth holding electrode of the first pixel circuit is different from the area of ​​the fourth holding electrode of the second pixel circuit.

19. An electronic device, comprising a display device, wherein, The display device includes: substrate; Gate lines 1-1 and 1-2 extend along a first direction on the substrate and are spaced apart from each other; The data cable extends along a second direction that intersects the first direction; The first pixel circuit and the second pixel circuit are configured such that the data line is placed between the first pixel circuit and the second pixel circuit and arranged along the first direction. The first pixel circuit is connected to the first-1 gate line, and the second pixel circuit is connected to the first-2 gate line. Each of the first pixel circuit and the second pixel circuit includes: The first transistor includes a first semiconductor layer and a first gate electrode; The storage capacitor includes a second storage electrode connected to the first gate electrode; and A holding capacitor includes a first holding electrode connected to the first storage electrode of the storage capacitor. Wherein, the capacitance of the storage capacitor in the first pixel circuit is different from the capacitance of the storage capacitor in the second pixel circuit, and / or The capacitance of the holding capacitor in the first pixel circuit is different from the capacitance of the holding capacitor in the second pixel circuit.

20. The electronic device of claim 19, wherein, The electronic device is one of the following: smartphone, tablet computer, laptop computer, television, desktop monitor, smart glasses, head-mounted display, smartwatch, car dashboard, center console, central information display, and interior mirror display.

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