Display device and electronic device

Abstract

The present disclosure relates to a display device and an electronic device. The display device includes a substrate including a first pixel circuit region and a second pixel circuit region, wherein the second pixel circuit region is adjacent to the first pixel circuit region in a first direction; a first drive transistor of a first pixel drive circuit portion, wherein the first drive transistor is provided in both the first pixel circuit region and the second pixel circuit region; a second drive transistor of a second pixel drive circuit portion, wherein the second drive transistor is provided in both the first pixel circuit region and the second pixel circuit region, and the second drive transistor is adjacent to the first drive transistor in a second direction intersecting the first direction; a first light emitting element connected to the first pixel drive circuit portion and provided in a first light emitting region; and a second light emitting element connected to the second pixel drive circuit portion and provided in a second light emitting region.

Description

Technical Field

[0001] This disclosure relates to display devices and electronic devices including display devices. More specifically, embodiments relate to display devices that provide visual information and electronic devices including display devices that provide visual information. Background Technology

[0002] With the development of information technology, the importance of display devices as communication media between users and information is becoming increasingly prominent. Therefore, the use of display devices such as liquid crystal displays, organic light-emitting diode displays, and plasma displays is increasing.

[0003] Recently, display devices using high-resolution miniature organic light-emitting diodes (OLEDs) have been manufactured. High-resolution miniature OLEDs can be organic light-emitting diodes on silicon (OLEDoS) formed using semiconductor processes based on silicon wafers. Summary of the Invention

[0004] One or more embodiments provide a display device with improved reliability.

[0005] One or more embodiments provide an electronic device including a display device.

[0006] According to one aspect of an embodiment, a display device includes: a substrate including a first pixel circuit region and a second pixel circuit region, wherein the second pixel circuit region is adjacent to the first pixel circuit region in a first direction; a first driving transistor of a first pixel driving circuit portion, wherein the first driving transistor is provided in both the first pixel circuit region and the second pixel circuit region; a second driving transistor of a second pixel driving circuit portion, wherein the second driving transistor is provided in both the first pixel circuit region and the second pixel circuit region, and the second driving transistor is adjacent to the first driving transistor in a second direction intersecting the first direction; a first light-emitting element connected to the first pixel driving circuit portion and provided in a first light-emitting region; and a second light-emitting element connected to the second pixel driving circuit portion and provided in a second light-emitting region, wherein the second light-emitting region is configured to emit light of a different color than the first light-emitting region.

[0007] At least one of the first driving transistor and the second driving transistor may include: an active portion of a substrate, including a source region, a drain region, and a channel region between the source region and the drain region; and a gate electrode, which overlaps with the channel region of the active portion in a planar view. The active portion and the gate electrode of at least one of the first driving transistor and the second driving transistor may be provided in both the first pixel circuit region and the second pixel circuit region.

[0008] The display device may further include: a first data write transistor of a first pixel driving circuit section, the first data write transistor being provided in the first pixel circuit region, being connected to the first driving transistor, and being able to receive a first data voltage in response to a first gate signal; a first emitter control transistor of the first pixel driving circuit section, the first emitter control transistor being provided in the first pixel circuit region, being connected to the first driving transistor, and being able to receive a driving voltage in response to an emitter signal; and a first initialization transistor of the first pixel driving circuit section, wherein the first initialization transistor being provided in the first pixel circuit region, being connected to the first driving transistor, and being able to receive a first initialization voltage in response to a second gate signal. The first data write transistor, the first emitter control transistor, the first driving transistor, and the first initialization transistor may be provided sequentially along a second direction.

[0009] The display device may further include: a second data write transistor of a second pixel driving circuit section, wherein the second data write transistor is provided in the second pixel circuit region, can be connected to the second driving transistor, and can receive a second data voltage in response to a first gate signal; a second emitter control transistor of the second pixel driving circuit section, wherein the second emitter control transistor is provided in the second pixel circuit region, can be connected to the second driving transistor, and can receive a driving voltage in response to an emitter signal; and a second initialization transistor of the second pixel driving circuit section, wherein the second initialization transistor is provided in the second pixel circuit region, can be connected to the second driving transistor, and can receive a second initialization voltage in response to a second gate signal. The second data write transistor, the second emitter control transistor, the second driving transistor, and the second initialization transistor may be provided sequentially along a second direction.

[0010] The substrate may further include a third pixel circuit region adjacent to the second pixel circuit region in a first direction and a fourth pixel circuit region adjacent to the third pixel circuit region in the first direction. The display device may further include: a third driving transistor in a third pixel driving circuit section, wherein the third driving transistor can be provided in both the third pixel circuit region and the fourth pixel circuit region; a fourth driving transistor in a fourth pixel driving circuit section, wherein the fourth driving transistor can be provided in both the third pixel circuit region and the fourth pixel circuit region, and can be adjacent to the third driving transistor in a second direction; a third light-emitting element connected to the third pixel driving circuit section and provided in the third light-emitting region; and a fourth light-emitting element connected to the fourth pixel driving circuit section and provided in the fourth light-emitting region, wherein the fourth light-emitting region is configured to emit light of a different color than the third light-emitting region.

[0011] The third driving transistor and the fourth driving transistor can be offset relative to the first driving transistor and the second driving transistor in the first pixel circuit region and the second pixel circuit region, respectively, along the first direction and the second direction.

[0012] The third driving transistor and the first driving transistor can be located in the Nth row (where N is a natural number greater than 0) parallel to the first direction, and the fourth driving transistor and the second driving transistor can be located in the N+1th row parallel to the first direction and adjacent to the Nth row in the second direction.

[0013] The fourth driving transistor and the first driving transistor can be located in the Nth row (where N is a natural number greater than 0) parallel to the first direction, and the third driving transistor and the second driving transistor can be located in the N+1th row parallel to the first direction and adjacent to the Nth row in the second direction.

[0014] The substrate may further include a third pixel circuit region adjacent to the second pixel circuit region in a first direction. The display device may further include: a third driving transistor in a third pixel driving circuit section, wherein the third driving transistor is provided in each of the first pixel circuit region, the second pixel circuit region, and the third pixel circuit region, and the third driving transistor may be adjacent to the second driving transistor in a second direction; and a third light-emitting element connected to the third pixel driving circuit section and provided in the third light-emitting region, the third light-emitting region being configured to emit light of a different color than the first light-emitting region and the second light-emitting region. At least one of the first driving transistor and the second driving transistor may extend from the first pixel circuit region and the second pixel circuit region to the third pixel circuit region.

[0015] The first driving transistor may include: a first-first driving transistor provided in the first pixel circuit region; and a first-second driving transistor provided in both the first pixel circuit region and the second pixel circuit region, wherein the first-second driving transistor may be connected to the first-first driving transistor, and the first-second driving transistor may be adjacent to the first-first driving transistor in a second direction. The second driving transistor may include: a second-first driving transistor provided in the second pixel circuit region; and a second-second driving transistor provided in both the first pixel circuit region and the second pixel circuit region, wherein the second-second driving transistor may be connected to the second-first driving transistor, and the second-second driving transistor may be adjacent to the second-first driving transistor in a direction opposite to the second direction.

[0016] The first-first driving transistor may include a first-first active portion of a substrate provided in a first pixel circuit region and a first-first gate electrode overlapping a channel region of the first-first active portion in a planar view. The first-second driving transistor may include a first-second active portion of a substrate provided in both the first and second pixel circuit regions and a first-second gate electrode overlapping a channel region of the first-second active portion in a planar view. The second-first driving transistor may include a second-first active portion of a substrate provided in a second pixel circuit region and a second-first gate electrode overlapping a channel region of the second-first active portion in a planar view. The second-second driving transistor may include a second-second active portion of a substrate provided in both the first and second pixel circuit regions and a second-second gate electrode overlapping a channel region of the second-second active portion in a planar view.

[0017] The display device may further include: a first connection pattern for connecting the drain region of the first-first active portion and the source region of the first-second active portion; and a second connection pattern for connecting the drain region of the second-first active portion and the source region of the second-second active portion.

[0018] The first-first gate electrode and the first-second gate electrode can be configured as a single body, and the second-first gate electrode and the second-second gate electrode can be configured as a single body.

[0019] The display device may further include: a first gate connection pattern for connecting a first-first gate electrode and a first-second gate electrode; and a second gate connection pattern for connecting a second-first gate electrode and a second-second gate electrode.

[0020] The display device may further include: a first data write transistor of a first pixel driving circuit section, wherein the first data write transistor is provided in the first pixel circuit region, is connected to the first driving transistor, and can receive a first data voltage in response to a gate signal; and a first emitter control transistor of the first pixel driving circuit section, wherein the first emitter control transistor is provided in the first pixel circuit region, is connected to the first driving transistor, and can receive a driving voltage in response to an emitter signal. The first data write transistor, the first driving transistor, and the first emitter control transistor may be provided sequentially along a second direction.

[0021] The display device may further include: a second data write transistor in a second pixel driving circuit section, wherein the second data write transistor is provided in the second pixel circuit region, can be connected to the second driving transistor, and can receive a second data voltage in response to a gate signal; and a second emitter control transistor in the second pixel driving circuit section, wherein the second emitter control transistor is provided in the second pixel circuit region, can be connected to the second driving transistor, and can receive a driving voltage in response to an emitter signal. The second data write transistor, the second emitter control transistor, and the second driving transistor may be provided sequentially along a second direction.

[0022] The substrate may include a silicon wafer substrate.

[0023] The first driving transistor and the second driving transistor can be P-type metal-oxide-semiconductor (PMOS) transistors.

[0024] According to another aspect of the embodiments, an electronic device includes: a display panel (display device), comprising: a substrate including a first pixel circuit region and a second pixel circuit region, wherein the second pixel circuit region is adjacent to the first pixel circuit region in a first direction; a first driving transistor of a first pixel driving circuit portion, wherein the first driving transistor is provided in both the first pixel circuit region and the second pixel circuit region; a second driving transistor of a second pixel driving circuit portion, wherein the second driving transistor is provided in both the first pixel circuit region and the second pixel circuit region, and the second driving transistor is adjacent to the first driving transistor in a second direction intersecting the first direction; a first light-emitting element connected to the first pixel driving circuit portion and provided in a first light-emitting region; a second light-emitting element connected to the second pixel driving circuit portion and provided in a second light-emitting region, the second light-emitting region being configured to emit light of a different color than the first light-emitting region; a controller configured to control the operation of the display panel based on input image data and control signals; and a processor configured to provide the input image data and control signals to the controller.

[0025] At least one of the first driving transistor and the second driving transistor may include: an active portion of a substrate, including a source region, a drain region, and a channel region between the source region and the drain region; and a gate electrode, which overlaps with the channel region of the active portion in a planar view. The active portion and the gate electrode of at least one of the first driving transistor and the second driving transistor may be provided in both the first pixel circuit region and the second pixel circuit region.

[0026] In the display device according to the embodiment, two driving transistors in two pixel driving circuit sections respectively disposed in a first pixel circuit region and a second pixel circuit region adjacent to each other can be disposed in both the first pixel circuit region and the second pixel circuit region. In the display device according to the embodiment, three driving transistors in three pixel driving circuit sections respectively disposed in a first pixel circuit region, a second pixel circuit region, and a third pixel circuit region adjacent to each other can be disposed in all the first pixel circuit regions, the second pixel circuit region, and the third pixel circuit region. Each of the plurality of driving transistors can have a sufficiently long channel length. Therefore, the driving transistors can have a structure robust to variations. Therefore, the display device can achieve high resolution and improve display quality. Attached Figure Description

[0027] The above and other aspects will become more apparent from the following description of embodiments in conjunction with the accompanying drawings.

[0028] Figure 1 This is a block diagram schematically illustrating a display device according to an embodiment.

[0029] Figure 2 It is shown schematically. Figure 1 Cross-sectional view of the display panel and the packaging substrate.

[0030] Figure 3 It is shown Figure 1 A circuit diagram illustrating an example of a circuit structure for a single pixel.

[0031] Figure 4 It is shown that it includes Figure 2 A cross-sectional view of the transistors in the pixel driving circuit.

[0032] Figure 5 It is shown Figure 2 A plan view of the transistor array.

[0033] Figure 6 It is shown that it includes Figure 5 A layout diagram of an example of a first pixel driving circuit section and a second pixel driving circuit section in a transistor array.

[0034] Figure 7 This is a plan view illustrating an example of the connection relationship between the driving transistor and the data writing transistor.

[0035] Figure 8 It is shown that it includes Figure 5 An example layout diagram of the first pixel driving circuit section, the second pixel driving circuit section, the third pixel driving circuit section, the fourth pixel driving circuit section, the fifth pixel driving circuit section, and the sixth pixel driving circuit section in a transistor array.

[0036] Figure 9 It is shown that it includes Figure 5 An example layout diagram of the first pixel driving circuit section, the second pixel driving circuit section, the third pixel driving circuit section, the fourth pixel driving circuit section, the fifth pixel driving circuit section, and the sixth pixel driving circuit section in a transistor array.

[0037] Figure 10 It is shown that it includes Figure 5 A layout diagram of an example of a first pixel driving circuit section, a second pixel driving circuit section, and a third pixel driving circuit section in a transistor array.

[0038] Figure 11 It is shown Figure 1 A circuit diagram of another example of a circuit structure for a single pixel.

[0039] Figure 12 It is shown that it includes Figure 5 A layout diagram of another example of the first pixel driving circuit section and the second pixel driving circuit section in a transistor array.

[0040] Figure 13 It is shown that it includes Figure 5 A layout diagram of another example of the first pixel driving circuit section and the second pixel driving circuit section in a transistor array.

[0041] Figure 14 It is shown that it includes Figure 5 A layout diagram of another example of the first pixel driving circuit section and the second pixel driving circuit section in a transistor array.

[0042] Figure 15 It is shown that it includes Figure 5 Another example layout diagram of the first pixel driving circuit section, the second pixel driving circuit section, and the third pixel driving circuit section in a transistor array.

[0043] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment.

[0044] Figure 17 This is a schematic diagram illustrating an electronic device according to various embodiments. Detailed Implementation

[0045] In the following, embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same components, and redundant descriptions of the same components will be omitted.

[0046] Figure 1This is a block diagram schematically illustrating a display device according to an embodiment. It will be understood that when an element or layer is referred to as "on" another element or layer, "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or an intermediary element or layer may be present. In contrast, when an element or layer is referred to as "directly on" another element or layer, "directly connected to," or "directly coupled to" another element or layer, no intermediary element or layer is present. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and can be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with this disclosure.

[0047] refer to Figure 1 The display device DD according to the embodiment may include a display panel 110, a gate driver (e.g., a gate driver circuit system) 120, a transmitter driver (e.g., a transmitter driver circuit system) 130, a data driver (e.g., a data driver circuit system) 140, and a controller (e.g., a controller circuit system) 150.

[0048] The display panel 110 may include multiple gate signal lines GL1 to GLn, multiple data lines DL1 to DLm, multiple transmit control lines EL1 to ELn, and multiple pixels PX (where n and m are integers of 2 or greater). The gate signal lines GL1 to GLn, the transmit control lines EL1 to ELn, and the data lines DL1 to DLm may be electrically connected to the pixels PX. The gate signal lines GL1 to GLn may receive a gate signal GS, the transmit control lines EL1 to ELn may receive a transmit signal EM, and the data lines DL1 to DLm may receive a data voltage DATA. For example, the gate signal GS may include... Figure 3 The gate signals GW and EB in Figure 11 The gate signal GW in the system.

[0049] Each of the gate signal lines GL1 to GLn and each of the transmit control lines EL1 to ELn may extend in a first direction (e.g., the row direction). Each of the data lines DL1 to DLm may extend in a second direction (e.g., the column direction) intersecting the first direction. The gate signal lines GL1 to GLn, the transmit control lines EL1 to ELn, and the data lines DL1 to DLm may be insulated from each other. Pixels PX may be arranged in the region where the gate signal lines GL1 to GLn (or the transmit control lines EL1 to ELn) and the data lines DL1 to DLm intersect.

[0050] In an embodiment, each of the plurality of pixels PX may include a switching transistor that provides a data voltage DATA in response to a gate signal GS (e.g., Figure 3 The light source includes a second transistor T2, a storage capacitor storing a data voltage DATA provided by a switching transistor, a driving transistor generating a driving current based on the stored data voltage DATA, and a light-emitting element emitting light based on the driving current generated by the driving transistor. For example, the light-emitting element may include a light-emitting diode (LED), an organic light-emitting diode (OLED), or a quantum dot (QD) light-emitting element.

[0051] Pixel PX can receive a driving voltage ELVDD and a common voltage ELVSS. Pixel PX can receive a data voltage DATA in response to a gate signal GS and a transmit signal EM, and can use the driving voltage ELVDD and the common voltage ELVSS to generate light with a gray level corresponding to the data voltage DATA.

[0052] Gate driver 120 can provide gate signal GS to pixel PX via gate signal lines GL1 to GLn based on gate control signal GCTRL received from controller 150. In embodiments, gate driver 120 can provide gate signal GS sequentially to pixel PX on a row-by-row basis. Gate control signal GCTRL may include gate start signal and gate clock signal, etc., however, embodiments are not limited thereto. For example, gate driver 120 may be integrated or formed in a peripheral portion of display panel 110. Alternatively, gate driver 120 may be implemented using one or more integrated circuits (ICs).

[0053] The transmit driver 130 can provide the transmit signal EM to the pixel PX via transmit control lines EL1 to ELn based on the transmit control signal ECTRL received from the controller 150. In an embodiment, the transmit driver 130 can provide the transmit signal EM sequentially to the pixel PX on a row-by-row basis. The transmit control signal ECTRL may include a transmit start signal and a transmit clock signal, etc., however, the embodiment is not limited to this. For example, the transmit driver 130 may be integrated or formed in the peripheral portion of the display panel 110. Alternatively, the transmit driver 130 may be implemented using one or more integrated circuits (ICs).

[0054] Data driver 140 can receive data control signal DCTRL and output image data ODAT from controller 150, and can provide data voltage DATA to pixel PX via data lines DL1 to DLm based on data control signal DCTRL and output image data ODAT. Data control signal DCTRL may include output data enable signal, level start signal, and load signal, etc., however, embodiments are not limited to these. For example, data driver 140 can be implemented as a single integrated circuit, and said integrated circuit may be referred to as a timing controller embedded data driver (TED). Alternatively, data driver 140 can be implemented using multiple separate integrated circuits.

[0055] The controller 150 can receive input image data IDAT and control signal CTRL from an external processor. For example, the controller 150 may be a timing controller, and the processor may be an application processor (AP), a graphics processing unit (GPU), or a graphics card. In an embodiment, the input image data IDAT may be red-green-blue (RGB) image data including red image data, green image data, and blue image data. The control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and a master clock signal, etc., however, the embodiment is not limited to these.

[0056] The controller 150 can generate a gate control signal GCTRL, a transmit control signal ECTRL, a data control signal DCTRL, and output image data ODAT based on the input image data IDAT and the control signal CTRL. The controller 150 can control the operation of the gate driver 120 by providing the gate control signal GCTRL, control the operation of the transmit driver 130 by providing the transmit control signal ECTRL, and control the operation of the data driver 140 by providing the output image data ODAT and the data control signal DCTRL. In other words, the controller 150 can control the operation of the display panel 110.

[0057] Figure 2 It is shown schematically. Figure 1 Cross-sectional view of the display panel and the packaging substrate.

[0058] refer to Figure 1 and Figure 2 The display device DD according to the embodiment may further include an encapsulation substrate ES disposed on the display panel 110. The display panel 110 may include a transistor array TA, a circuit insulating layer PC_IL, a first light-emitting element LED1, a second light-emitting element LED2 and a third light-emitting element LED3, a partition wall PW, an encapsulation layer TFE, a first color filter layer CF1, a second color filter layer CF2 and a third color filter layer CF3, a light blocking layer BM, and a lens layer.

[0059] Here, the transistor array TA may include a substrate SUB and multiple pixel driving circuit sections (i.e., pixel driving circuits) PC. The first light-emitting element LED1 may include a first pixel electrode PE1, a light-emitting layer EML, and a common electrode CE; the second light-emitting element LED2 may include a second pixel electrode PE2, a light-emitting layer EML, and a common electrode CE; and the third light-emitting element LED3 may include a third pixel electrode PE3, a light-emitting layer EML, and a common electrode CE.

[0060] The substrate SUB may include a first pixel circuit region PCAa, a second pixel circuit region PCAb, and a third pixel circuit region PCAc.

[0061] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB can serve as a support member for supporting other components of the display device DD. For example, the substrate SUB may include semiconductor materials (e.g., group IV semiconductors, group III-V compound semiconductors, and group II-VI compound semiconductors, etc.). However, the embodiments are not limited thereto.

[0062] A pixel driving circuit section PC can be disposed in a substrate SUB. Multiple pixel driving circuit sections PC can overlap with a first pixel circuit region PCAa, a second pixel circuit region PCAb, and a third pixel circuit region PCAc respectively in a planar view. For example, the overlap can be along a third direction DR3 (e.g., a vertical direction) intersecting with a first direction DR1 and a second direction DR2. The pixel driving circuit section PC can include various driving elements for driving a first light-emitting element LED1, a second light-emitting element LED2, and a third light-emitting element LED3 respectively. For example, each of the multiple pixel driving circuit sections PC can include at least one transistor formed by a semiconductor process and at least one capacitor formed by a semiconductor process. Each of the multiple pixel driving circuit sections PC can correspond to... Figure 3 The pixel driving circuit PC is shown in the figure. That is, each of the plurality of pixel driving circuit PCs may include four transistors and three (or two) capacitors.

[0063] A circuit insulating layer PC_IL may be disposed on the pixel driving circuit section PC. The circuit insulating layer PC_IL prevents contact between the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 and the pixel driving circuit section PC. The circuit insulating layer PC_IL may comprise organic and / or inorganic materials. For example, the circuit insulating layer PC_IL may comprise multiple layers formed of various insulating materials.

[0064] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 can be disposed on the circuit insulating layer PC_IL. The first pixel electrode PE1 can be disposed in a first emitting region EAa that emits light of a first color, the second pixel electrode PE2 can be disposed in a second emitting region EAb that emits light of a second color, and the third pixel electrode PE3 can be disposed in a third emitting region EAc that emits light of a third color. For example, the first color can be red, the second color can be green, and the third color can be blue. However, the embodiments are not limited to this.

[0065] For example, along the third direction DR3, the first light-emitting region EAa may at least partially overlap with the first pixel circuit region PCAa, the second light-emitting region EAb may at least partially overlap with the second pixel circuit region PCAb, and the third light-emitting region EAc may at least partially overlap with the third pixel circuit region PCAc.

[0066] The first pixel electrode PE1 can be electrically connected to the pixel driving circuit PC in the first pixel circuit region PCAa through the contact hole of the through-circuit insulating layer PC_IL. The second pixel electrode PE2 can be electrically connected to the pixel driving circuit PC in the second pixel circuit region PCAb through the contact hole. The third pixel electrode PE3 can be electrically connected to the pixel driving circuit PC in the third pixel circuit region PCAc through the contact hole.

[0067] exist Figure 2 In this illustration, for ease of explanation, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 are shown as being directly connected to the pixel driving circuit PC. However, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 can be electrically connected to the pixel driving circuit PC through at least one conductive pattern.

[0068] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may comprise metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials, etc. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may comprise the same material and may be formed using the same process. For example, each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a multilayer structure including ITO / Ag / ITO. However, the embodiments are not limited to this. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be an anode electrode. Each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be a reflective electrode. However, the embodiments are not limited to this.

[0069] The separator wall PW can be disposed on the circuit insulating layer PC_IL. The separator wall PW can cover the edge of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. The separator wall PW can also expose at least a portion of the upper surface of each of the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3. For example, the separator wall PW can include inorganic materials such as silicon oxide, silicon nitride, and silicon oxynitride. These materials can be used alone or in combination with each other. Alternatively, the separator wall PW can include organic materials. In this embodiment, the separator wall PW can have a multilayer structure; however, the embodiments are not limited thereto.

[0070] The light-emitting layer (EML) can be disposed on the first pixel electrode PE1, the second pixel electrode PE2, the third pixel electrode PE3, and the separator wall PW. The EML can be a common layer formed over the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc. That is, the EML can extend continuously over the entire first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc. For example, the EML can include a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron injection layer, and an electron transport layer. In an embodiment, the organic light-emitting layer can include a light-emitting material that emits white light. For example, white light can be a mixture of blue, green, and red light. Alternatively, white light can be a mixture of blue and yellow light.

[0071] However, the embodiments are not limited to this. The emissive layer EML may include a first emissive layer that overlaps with the first emissive region EAa in the planar view (i.e., along the third direction DR3) and contains a material that emits light of a first color (e.g., red light), a second emissive layer that overlaps with the second emissive region EAb in the planar view (i.e., along the third direction DR3) and contains a material that emits light of a second color (e.g., green light), and a third emissive layer that overlaps with the third emissive region EAC in the planar view (i.e., along the third direction DR3) and contains a material that emits light of a third color (e.g., blue light). In this case, the first, second, and third emissive layers may be separated from each other, and the first color filter layer CF1, the second color filter layer CF2, the third color filter layer CF3, and the light blocking layer BM may be omitted.

[0072] The common electrode CE can be disposed on the light-emitting layer EML. The common electrode CE can be a common layer formed across the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc. That is, the common electrode CE can extend continuously throughout the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc. For example, the common electrode CE can include metals, alloys, metal nitrides, conductive metal oxides, and transparent conductive materials. These materials can be used individually or in combination. The common electrode CE can be a cathode electrode. The common electrode CE can be a transmission electrode or a semi-transmission electrode.

[0073] Therefore, the first pixel electrode PE1, the emissive layer EML, and the common electrode CE can form the first light-emitting element LED1, the second pixel electrode PE2, the emissive layer EML, and the common electrode CE can form the second light-emitting element LED2, and the third pixel electrode PE3, the emissive layer EML, and the common electrode CE can form the third light-emitting element LED3. The first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 can be electrically connected to the pixel driving circuit PC of the first pixel circuit region PCAa, the pixel driving circuit PC of the second pixel circuit region PCAb, and the pixel driving circuit PC of the third pixel circuit region PCAc, respectively.

[0074] The encapsulation layer TFE can be disposed on the common electrode CE. The encapsulation layer TFE can extend continuously throughout the entire first pixel circuit region PCAa, the second pixel circuit region PCAb, and the third pixel circuit region PCAc. The encapsulation layer TFE can prevent impurities and moisture from penetrating into the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 from the outside.

[0075] The encapsulation layer TFE may include at least one inorganic layer and at least one organic layer. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2 disposed on the first inorganic encapsulation layer TFE1, and a second inorganic encapsulation layer TFE3 disposed on the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may have a substantially flat upper surface.

[0076] For example, the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may include silicon oxide, silicon nitride, and silicon oxynitride, etc. These materials may be used alone or in combination with each other. The organic encapsulation layer TFE2 may include a polymer-cured material such as polyacrylate.

[0077] The first color filter layer CF1, the second color filter layer CF2, and the third color filter layer CF3 can be disposed on the encapsulation layer TFE. Along the third direction DR3, the first color filter layer CF1 can overlap with the first light-emitting region EAa, the second color filter layer CF2 can overlap with the second light-emitting region EAb, and the third color filter layer CF3 can overlap with the third light-emitting region EAc.

[0078] Each of the first color filter layer CF1, the second color filter layer CF2, and the third color filter layer CF3 can selectively transmit light of a specific wavelength and absorb light of other wavelengths. For example, red light can pass through the first color filter layer CF1, green light can pass through the second color filter layer CF2, and blue light can pass through the third color filter layer CF3. Therefore, the first emitting region EAa can emit red light, the second emitting region EAb can emit green light, and the third emitting region EAc can emit blue light.

[0079] A light-blocking layer BM can be disposed on the encapsulation layer TFE. The light-blocking layer BM can be disposed between the first color filter layer CF1, the second color filter layer CF2, and the third color filter layer CF3. That is, the light-blocking layer BM can be positioned along the third direction DR3 without overlapping with the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAC. The light-blocking layer BM can block light incident on itself. Therefore, the light-blocking layer BM can prevent color mixing between the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAC. For example, the light-blocking layer BM can include organic and / or inorganic materials containing black pigments and black dyes.

[0080] The lens layer can be disposed on the first color filter layer CF1, the second color filter layer CF2, and the third color filter layer CF3, as well as the light-blocking layer BM. The lens layer may include multiple microlenses ML. The microlenses ML can improve light extraction efficiency. Each of the multiple microlenses ML can overlap with the first color filter layer CF1, the second color filter layer CF2, or the third color filter layer CF3 along a third direction DR3. The microlenses ML can have a predetermined refractive index for visible light. For example, the microlenses ML can have a refractive index of about 1.5 to about 1.7 for visible light. However, the embodiments are not limited to this. For example, each of the multiple microlenses ML can have a convex cross-sectional shape.

[0081] The encapsulation substrate ES can be disposed on the lens layer. The encapsulation substrate ES can be attached to the display panel 110 via an adhesive layer ADL. The encapsulation substrate ES can protect the display panel 110 from moisture penetration or gas intrusion. The encapsulation substrate ES may include a transparent insulating substrate. For example, the encapsulation substrate ES may include glass. For example, the adhesive layer ADL may include optically clear adhesive (OCA), pressure-sensitive adhesive (PSA), photocurable resin, or thermosetting resin, etc.

[0082] Figure 3 It is shown Figure 1 A circuit diagram illustrating an example of a circuit structure for a single pixel.

[0083] refer to Figure 3 Each pixel PX may include a pixel driving circuit PC and a light-emitting element LED electrically connected to the pixel driving circuit PC. The pixel driving circuit PC can generate a driving current, and the light-emitting element LED can emit light based on the driving current.

[0084] In an embodiment, the pixel driving circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0085] In the embodiment, the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 can all be MOSFETs (metal-oxide-semiconductor field-effect transistors) formed by semiconductor processes.

[0086] In this embodiment, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can all be P-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) or PMOS transistors. However, the embodiment is not limited to this, and some of the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 can be PMOS transistors, while the remaining transistors can be N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs) or NMOS transistors.

[0087] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. The source electrode of the first transistor T1 may be connected to a second node N2. The drain electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 can provide drive current to the light-emitting element LED. The first transistor T1 may be referred to as a drive transistor.

[0088] The first transistor T1 may further include a body electrode. The body electrode of the first transistor T1 may receive a drive voltage ELVDD. For example, a drive voltage line ELVDL receiving the drive voltage ELVDD may be connected to the body electrode of the first transistor T1. Alternatively, a separate voltage other than the drive voltage ELVDD may be applied to the body electrode of the first transistor T1.

[0089] The second transistor T2 may include a gate electrode, a source electrode, and a drain electrode. A first gate signal line GWL, which receives the first gate signal GW, can be connected to the gate electrode of the second transistor T2. A data line DL, which receives the data voltage DATA, can be connected to the source electrode of the second transistor T2. The drain electrode of the second transistor T2 can be connected to the first node N1. In other words, the second transistor T2 can be electrically connected to the first transistor T1. The second transistor T2 can be referred to as a data write transistor.

[0090] The second transistor T2 may also include a body electrode. The body electrode of the second transistor T2 may receive a drive voltage ELVDD. For example, a drive voltage line ELVDL receiving the drive voltage ELVDD may be connected to the body electrode of the second transistor T2. Alternatively, a separate voltage other than the drive voltage ELVDD may be applied to the body electrode of the second transistor T2.

[0091] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the first gate signal GW has an active level, the second transistor T2 can be turned on. In this case, the second transistor T2 can supply the data voltage DATA to the first node N1. Conversely, when the first gate signal GW has an inactive level, the second transistor T2 can be turned off. In this case, the second transistor T2 can prevent the supply of the data voltage DATA.

[0092] The third transistor T3 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third transistor T3 can be connected to the emitter control line EL for receiving the emitter signal EM. The source electrode of the third transistor T3 can be connected to the drive voltage line ELVDL for receiving the drive voltage ELVDD. The drain electrode of the third transistor T3 can be connected to the second node N2. That is, the third transistor T3 can be electrically connected to the first transistor T1. The third transistor T3 can be referred to as the emitter control transistor.

[0093] The third transistor T3 may also include a body electrode. The body electrode of the third transistor T3 may receive a drive voltage ELVDD. For example, a drive voltage line ELVDL that receives the drive voltage ELVDD may be connected to the body electrode of the third transistor T3. Alternatively, a separate voltage other than the drive voltage ELVDD may be applied to the body electrode of the third transistor T3.

[0094] The third transistor T3 can be turned on or off in response to the transmit signal EM. For example, when the transmit signal EM has an active level, the third transistor T3 can be turned on. In this case, the third transistor T3 can provide the drive voltage ELVDD to the second node N2. Conversely, when the transmit signal EM has an inactive level, the third transistor T3 can be turned off. In this case, the third transistor T3 can block the supply of the drive voltage ELVDD.

[0095] The fourth transistor T4 may include a gate electrode, a source electrode, and a drain electrode. The second gate signal line EBL, which receives the second gate signal EB, can be connected to the gate electrode of the fourth transistor T4. The initialization voltage line INL, which receives the initialization voltage VINT, can be connected to the source electrode of the fourth transistor T4. The drain electrode of the fourth transistor T4 can be connected to the third node N3. That is, the fourth transistor T4 can be electrically connected to the first transistor T1. The fourth transistor T4 can be referred to as the initialization transistor.

[0096] The fourth transistor T4 may also include a body electrode. The body electrode of the fourth transistor T4 may receive a drive voltage ELVDD. For example, a drive voltage line ELVDL receiving the drive voltage ELVDD may be connected to the body electrode of the fourth transistor T4. Alternatively, a separate voltage other than the drive voltage ELVDD may be applied to the body electrode of the fourth transistor T4.

[0097] The fourth transistor T4 can be turned on or off in response to the second gate signal EB. For example, when the second gate signal EB has an active level, the fourth transistor T4 can be turned on. In this case, the fourth transistor T4 can provide the initialization voltage VINT to the third node N3. Conversely, when the second gate signal EB has a disabled level, the fourth transistor T4 can be turned off. In this case, the fourth transistor T4 can prevent the supply of the initialization voltage VINT.

[0098] The first capacitor C1 may include a first electrode and a second electrode. The first electrode of the first capacitor C1 may be connected to a first node N1, and the second electrode of the first capacitor C1 may be connected to a second node N2.

[0099] The second capacitor C2 may include a first electrode and a second electrode. A reference voltage line REL receiving the reference voltage VREF may be connected to the first electrode of the second capacitor C2. The second electrode of the second capacitor C2 may be connected to the first node N1.

[0100] The third capacitor C3 may include a first electrode and a second electrode. The first electrode of the third capacitor C3 may be connected between the second capacitor C2 and the first node N1. The second electrode of the third capacitor C3 may be connected to the third node N3. Alternatively, the third capacitor C3 may be omitted.

[0101] A light-emitting element (LED) may include an anode electrode and a cathode electrode. The anode electrode of the LED may be connected to a third node N3. A common voltage line ELVSL, which receives a common voltage ELVSS, may be connected to the cathode electrode of the LED. The common voltage ELVSS may have a lower voltage level than the drive voltage ELVDD.

[0102] although Figure 3 A pixel driving circuit PC is shown, comprising four transistors and three capacitors, but embodiments are not necessarily limited to this.

[0103] Figure 4 It is shown that it includes Figure 2 A cross-sectional view of the transistors in the pixel driving circuit.

[0104] refer to Figure 2 and Figure 4 The pixel driving circuit PC may include at least one transistor TR formed by a semiconductor process. The transistor TR may correspond to... Figure 3 The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 in the transistor.

[0105] The transistor TR may include an active portion, an insulating layer IL, and a gate electrode GE. A portion of the substrate SUB may define the active portion. That is, the substrate SUB may include the active portion. The active portion may include a source region SR, a drain region DR, and a channel region CH.

[0106] The substrate SUB may include a semiconductor material. In an embodiment, the substrate SUB may be an N-type semiconductor substrate doped with N-type impurities or a P-type semiconductor substrate doped with P-type impurities.

[0107] The source region SR and drain region DR can be disposed within the active portion. Specifically, the source region SR can be disposed on one side of the interior of the active portion, and the drain region DR can be disposed on the other side of the interior of the active portion. For example, the source region SR and drain region DR can comprise the same semiconductor material as the substrate SUB. The source region SR and drain region DR can be used as the source electrode and drain electrode of the transistor TR, respectively.

[0108] Impurities can be doped into the source region (SR) and drain region (DR). Therefore, the source region (SR) and drain region (DR) can be conductive regions. The doping concentration of the source region (SR) and drain region (DR) can be higher than the doping concentration of the substrate (SUB). In an embodiment, the source region (SR) and drain region (DR) can be doped with P-type impurities. However, the embodiments are not limited to this.

[0109] At least a portion of the contact source region SR and drain region DR of the substrate SUB may be doped with impurities of the opposite type to those in the source region SR and drain region DR. For example, a well region doped with impurities of the opposite type to those in the source region SR and drain region DR may be formed in the substrate SUB, and this well region may contact the source region SR and drain region DR. In this case, the substrate SUB may be a semiconductor substrate doped with impurities of the same type as those in the source region SR and drain region DR. Alternatively, the well region may not be formed in the substrate SUB. In this case, the substrate SUB may be a semiconductor substrate doped with impurities of the opposite type to those in the source region SR and drain region DR.

[0110] In an embodiment, when the source region SR and drain region DR are doped with P-type impurities, at least a portion of the contact source region SR and drain region DR of the substrate SUB may be doped with N-type impurities.

[0111] The channel region CH can be located in the substrate SUB between the source region SR and the drain region DR. For example, the channel region CH can comprise the same semiconductor material as the substrate SUB. When a voltage is applied to the gate electrode GE, the channel region CH can be a region of the substrate SUB in which charge carriers are conducted.

[0112] The channel region CH can be defined as a current path formed between the source region SR and the drain region DR. For example, when the source region SR and the drain region DR are doped with P-type impurities, the channel region CH can be formed when a negative voltage is applied to the gate electrode GE and can transport current through the movement of holes.

[0113] An insulating layer IL can be disposed on a substrate SUB. Specifically, the insulating layer IL can overlap with the channel region CH in a planar view. The insulating layer IL can include silicon oxide (e.g., SiO2), silicon nitride, or a dielectric material with a high dielectric constant (i.e., a high-κ dielectric constant material). A material with a high dielectric constant can refer to a dielectric material with a higher dielectric constant than silicon oxide. For example, materials with a high dielectric constant can include alumina (Al2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2) and hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y Hafnium aluminum oxide (HfAl) x O y Materials such as praseodymium oxide (Pr₂O₃) and others. These materials can be used alone or in combination with each other. However, the examples are not limited to these.

[0114] The gate electrode GE can be disposed on the insulating layer IL. The gate electrode GE can overlap with the channel region CH in a planar view (i.e., along the third direction DR3). The gate electrode GE can include a metal or a metal nitride. Examples of metals can include aluminum, tungsten, copper, and molybdenum. Examples of metal nitrides can include titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). These materials can be used alone or in combination with each other. Alternatively, the gate electrode GE can include a semiconductor material such as doped polycrystalline silicon. The gate electrode GE can have a single-layer structure or a multilayer structure comprising multiple layers.

[0115] Figure 5 It is shown Figure 2 A plan view of the transistor array.

[0116] refer to Figure 2 and Figure 5 As described above, the transistor array TA may include a substrate SUB and a pixel driving circuit PC.

[0117] The substrate SUB may also include a fourth pixel circuit region PCAa', a fifth pixel circuit region PCAb', and a sixth pixel circuit region PCAc'.

[0118] The second pixel circuit region PCAb can be adjacent to the first pixel circuit region PCAa in the first direction DR1, and the third pixel circuit region PCAc can be adjacent to the second pixel circuit region PCAb in the first direction DR1. Furthermore, the fourth pixel circuit region PCAa' can be adjacent to the third pixel circuit region PCAc in the first direction DR1, the fifth pixel circuit region PCAb' can be adjacent to the fourth pixel circuit region PCAa' in the first direction DR1, and the sixth pixel circuit region PCAc' can be adjacent to the fifth pixel circuit region PCAb' in the first direction DR1. That is, the first pixel circuit region PCAa, the second pixel circuit region PCAb, the third pixel circuit region PCAc, the fourth pixel circuit region PCAa', the fifth pixel circuit region PCAb', and the sixth pixel circuit region PCAc' can be arranged sequentially along the first direction DR1. For example, the first pixel circuit region PCAa, the second pixel circuit region PCAb, the third pixel circuit region PCAc, the fourth pixel circuit region PCAa', the fifth pixel circuit region PCAb', and the sixth pixel circuit region PCAc' can have a common (e.g., identical) size along each of the first direction DR1 and the second direction DR2.

[0119] The pixel driving circuit PC may include a first pixel driving circuit PCa, a second pixel driving circuit PCb, a third pixel driving circuit PCc, a fourth pixel driving circuit PCa', a fifth pixel driving circuit PCb', and a sixth pixel driving circuit PCc'.

[0120] The first pixel driving circuit PCa can be disposed in the first pixel circuit region PCAa and electrically connected to the first light-emitting element LED1 disposed in the first light-emitting region EAa. The second pixel driving circuit PCb can be disposed in the second pixel circuit region PCAb and electrically connected to the second light-emitting element LED2 disposed in the second light-emitting region EAb. The third pixel driving circuit PCc can be disposed in the third pixel circuit region PCAc and electrically connected to the third light-emitting element LED3 disposed in the third light-emitting region EAc.

[0121] Furthermore, the fourth pixel driving circuit PCa' can be disposed in the fourth pixel circuit region PCAa' and can be electrically connected to the fourth light-emitting element disposed in the fourth light-emitting region. The fifth pixel driving circuit PCb' can be disposed in the fifth pixel circuit region PCAb' and can be electrically connected to the fifth light-emitting element disposed in the fifth light-emitting region. The sixth pixel driving circuit PCc' can be disposed in the sixth pixel circuit region PCAc' and can be electrically connected to the sixth light-emitting element disposed in the sixth light-emitting region.

[0122] The first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc can emit light of different colors, and the fourth, fifth, and sixth light-emitting regions can also emit light of different colors. For example, the first light-emitting region EAa and the fourth light-emitting region can emit light of a first color (e.g., red light), the second light-emitting region EAb and the fifth light-emitting region can emit light of a second color (e.g., green light), and the third light-emitting region EAc and the sixth light-emitting region can emit light of a third color (e.g., blue light). However, the embodiments are not limited to this.

[0123] The first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 can emit light of the same color, and the fourth, fifth, and sixth light-emitting elements can also emit light of the same color. For example, the first light-emitting element LED1, the second light-emitting element LED2, and the third light-emitting element LED3 can emit white light, and the fourth, fifth, and sixth light-emitting elements can also emit white light. In this case, the color filter layer (e.g., Figure 2 The first color filter layer CF1, the second color filter layer CF2, and the third color filter layer CF3 can be disposed on the first light-emitting element LED1, the second light-emitting element LED2, the third light-emitting element LED3, and the fourth, fifth, and sixth light-emitting elements. However, the embodiments are not limited thereto.

[0124] Figure 6 It is shown that it includes Figure 5 A layout diagram of an example of a first pixel driving circuit section and a second pixel driving circuit section in a transistor array. Figure 7 This is a plan view illustrating an example of the connection relationship between the driving transistor and the data writing transistor.

[0125] The following will describe in more detail the transistor array TA (see [link to TA]). Figure 5 This section provides an example of the transistor arrangement structure in the first pixel driving circuit section PCa and the second pixel driving circuit section PCb. Furthermore, the descriptions of the first pixel driving circuit section PCa and the second pixel driving circuit section PCb described below can be applied substantially equivalently to... Figure 5 The third pixel driving circuit PCc, the fourth pixel driving circuit PCa', the fifth pixel driving circuit PCb', and the sixth pixel driving circuit PCc'.

[0126] refer to Figure 6 and Figure 7The first pixel driving circuit PCa may include a first driving transistor T1a, a first data writing transistor T2a, a first emission control transistor T3a, and a first initialization transistor T4a disposed in the first pixel circuit region PCAa. Similarly, the second pixel driving circuit PCb may include a second driving transistor T1b, a second data writing transistor T2b, a second emission control transistor T3b, and a second initialization transistor T4b disposed in the second pixel circuit region PCAb.

[0127] The first driving transistor T1a, the first data writing transistor T2a, the first emitter control transistor T3a, and the first initialization transistor T4a can be arranged in a row along the second direction DR2. In an embodiment, the first data writing transistor T2a, the first emitter control transistor T3a, the first driving transistor T1a, and the first initialization transistor T4a can be arranged sequentially along a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the transistors disposed in the first pixel circuit region PCAa can be interchanged.

[0128] The second driving transistor T1b, the second data writing transistor T2b, the second emitter control transistor T3b, and the second initialization transistor T4b can be arranged in a row along the second direction DR2. In an embodiment, the second data writing transistor T2b, the second emitter control transistor T3b, the second driving transistor T1b, and the second initialization transistor T4b can be arranged sequentially in a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the transistors disposed in the second pixel circuit region PCAb can be interchanged with each other.

[0129] The second data write transistor T2b can be adjacent to the first data write transistor T2a in the first direction DR1, the second emitter control transistor T3b can be adjacent to the first emitter control transistor T3a in the first direction DR1, and the second initialization transistor T4b can be adjacent to the first initialization transistor T4a in the first direction DR1.

[0130] In one embodiment, the second driving transistor T1b may be adjacent to the first driving transistor T1a in a direction opposite to the second direction DR2. Specifically, the first driving transistor T1a may be located in the Nth row (where N is a natural number greater than 0) parallel to the first direction DR1, and the second driving transistor T1b may be located in the (N+1)th row parallel to the first direction DR1 and adjacent to the Nth row in a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the first driving transistor T1a and the second driving transistor T1b may be interchanged.

[0131] In one embodiment, the first driving transistor T1a can extend from the first pixel circuit region PCAa to the second pixel circuit region PCAb, and the second driving transistor T1b can extend from the second pixel circuit region PCAb to the first pixel circuit region PCAa. That is, each of the first driving transistor T1a and the second driving transistor T1b can be located in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0132] Here, each of the first driving transistor T1a and the second driving transistor T1b can correspond to Figure 3 Each of the first transistor T1, the first data write transistor T2a, and the second data write transistor T2b can correspond to Figure 3 Each of the second transistor T2, the first emitter control transistor T3a, and the second emitter control transistor T3b can correspond to Figure 3 The third transistor T3, and each of the first initialization transistor T4a and the second initialization transistor T4b can correspond to Figure 3 The fourth transistor T4 in the process.

[0133] In other words, the first driving transistor T1a and the second driving transistor T1b can generate a driving current, and the first emitter control transistor T3a and the second emitter control transistor T3b can respond to an emitter signal (e.g., Figure 3 The transmitted signal EM in the signal receives the driving voltage (e.g., Figure 3 The driving voltage ELVDD in the middle). In addition, each of the first data write transistor T2a and the second data write transistor T2b can respond to the first gate signal (e.g., Figure 3 The first gate signal GW in the transistor receives the first data voltage and the second data voltage, and each of the first initialization transistor T4a and the second initialization transistor T4b can respond to the second gate signal (e.g., Figure 3 The second gate signal (EB) receives the first initialization voltage and the second initialization voltage. The first data voltage and the second data voltage can be applied through different data lines, and the first initialization voltage and the second initialization voltage can be applied through different initialization lines.

[0134] The first driving transistor T1a, the first data writing transistor T2a, the first emitter control transistor T3a, and the first initialization transistor T4a may each include a first active portion A1a, a second active portion A2a, a third active portion A3a, and a fourth active portion A4a spaced apart from each other on the substrate SUB. The second driving transistor T1b, the second data writing transistor T2b, the second emitter control transistor T3b, and the second initialization transistor T4b may each include a fifth active portion A1b, a sixth active portion A2b, a seventh active portion A3b, and an eighth active portion A4b spaced apart from each other on the substrate SUB. In an embodiment, each of the first active portion A1a, the second active portion A2a, the third active portion A3a, the fourth active portion A4a, the fifth active portion A1b, the sixth active portion A2b, the seventh active portion A3b, and the eighth active portion A4b may extend in a first direction DR1.

[0135] In this embodiment, the second active portion A2a, the third active portion A3a, the first active portion A1a, and the fourth active portion A4a may be arranged sequentially in a direction opposite to the second direction DR2. Furthermore, the sixth active portion A2b, the seventh active portion A3b, the fifth active portion A1b, and the eighth active portion A4b may be arranged sequentially in a direction opposite to the second direction DR2.

[0136] In this embodiment, the fifth active portion A1b may be adjacent to the first active portion A1a in a direction opposite to the second direction DR2. Specifically, the first active portion A1a may be located in the Nth row parallel to the first direction DR1, and the fifth active portion A1b may be located in the (N+1)th row adjacent to the Nth row in a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the first active portion A1a and the fifth active portion A1b may be interchanged.

[0137] In an embodiment, each of the first active portion A1a and the fifth active portion A1b may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0138] The first active portion A1a may include a first source region SR1a, a first drain region DR1a, and a first channel region CH1a between the first source region SR1a and the first drain region DR1a. For example, the first source region SR1a and the first drain region DR1a may be doped with P-type impurities. The first source region SR1a may be the source electrode of the first driving transistor T1a, and the first drain region DR1a may be the drain electrode of the first driving transistor T1a.

[0139] The second active portion A2a may include a second source region SR2a, a second drain region DR2a, and a second channel region CH2a between the second source region SR2a and the second drain region DR2a. For example, the second source region SR2a and the second drain region DR2a may be doped with P-type impurities. The second source region SR2a may be the source electrode of the first data writing transistor T2a, and the second drain region DR2a may be the drain electrode of the first data writing transistor T2a.

[0140] The third active portion A3a may include a third source region SR3a, a third drain region DR3a, and a third channel region CH3a between the third source region SR3a and the third drain region DR3a. For example, the third source region SR3a and the third drain region DR3a may be doped with P-type impurities. The third source region SR3a may be the source electrode of the first emitter control transistor T3a, and the third drain region DR3a may be the drain electrode of the first emitter control transistor T3a.

[0141] The fourth active portion A4a may include a fourth source region SR4a, a fourth drain region DR4a, and a fourth channel region CH4a between the fourth source region SR4a and the fourth drain region DR4a. For example, the fourth source region SR4a and the fourth drain region DR4a may be doped with P-type impurities. The fourth source region SR4a may be the source electrode of the first initialization transistor T4a, and the fourth drain region DR4a may be the drain electrode of the first initialization transistor T4a.

[0142] The fifth active portion A1b may include a fifth source region SR1b, a fifth drain region DR1b, and a fifth channel region CH1b between the fifth source region SR1b and the fifth drain region DR1b. For example, the fifth source region SR1b and the fifth drain region DR1b may be doped with P-type impurities. The fifth source region SR1b may be the source electrode of the second driving transistor T1b, and the fifth drain region DR1b may be the drain electrode of the second driving transistor T1b.

[0143] The sixth active portion A2b may include a sixth source region SR2b, a sixth drain region DR2b, and a sixth channel region CH2b between the sixth source region SR2b and the sixth drain region DR2b. For example, the sixth source region SR2b and the sixth drain region DR2b may be doped with P-type impurities. The sixth source region SR2b may be the source electrode of the second data write transistor T2b, and the sixth drain region DR2b may be the drain electrode of the second data write transistor T2b.

[0144] The seventh active portion A3b may include a seventh source region SR3b, a seventh drain region DR3b, and a seventh channel region CH3b between the seventh source region SR3b and the seventh drain region DR3b. For example, the seventh source region SR3b and the seventh drain region DR3b may be doped with P-type impurities. The seventh source region SR3b may be the source electrode of the second emitter control transistor T3b, and the seventh drain region DR3b may be the drain electrode of the second emitter control transistor T3b.

[0145] The eighth active portion A4b may include an eighth source region SR4b, an eighth drain region DR4b, and an eighth channel region CH4b between the eighth source region SR4b and the eighth drain region DR4b. For example, the eighth source region SR4b and the eighth drain region DR4b may be doped with P-type impurities. The eighth source region SR4b may be the source electrode of the second initialization transistor T4b, and the eighth drain region DR4b may be the drain electrode of the second initialization transistor T4b.

[0146] The first driving transistor T1a, extending across multiple circuit regions (i.e., both the first pixel circuit region PCAa and the second pixel circuit region PCAb), may have a channel length longer than the channel length of each of the first data write transistor T2a, the first emitter control transistor T3a, and the first initialization transistor T4a provided in a single pixel circuit region (i.e., the first pixel circuit region PCAa). Similarly, the second driving transistor T1b, extending across multiple circuit regions (i.e., both the first pixel circuit region PCAa and the second pixel circuit region PCAb), may have a channel length longer than the channel length of each of the second data write transistor T2b, the second emitter control transistor T3b, and the second initialization transistor T4b provided in a single pixel circuit region (i.e., the second pixel circuit region PCAb).

[0147] In an embodiment, an element isolation layer comprising an insulating material may be formed between the first active portion A1a, the second active portion A2a, the third active portion A3a, the fourth active portion A4a, the fifth active portion A1b, the sixth active portion A2b, the seventh active portion A3b, and the eighth active portion A4b.

[0148] The first driving transistor T1a, the first data writing transistor T2a, the first emitter control transistor T3a, and the first initialization transistor T4a may further include a first gate electrode GE1a, a second gate electrode GE2a, a third gate electrode GE3a, and a fourth gate electrode GE4a spaced apart from each other. Furthermore, the second driving transistor T1b, the second data writing transistor T2b, the second emitter control transistor T3b, and the second initialization transistor T4b may further include a fifth gate electrode GE1b, a sixth gate electrode GE2b, a seventh gate electrode GE3b, and an eighth gate electrode GE4b spaced apart from each other. In an embodiment, each of the first gate electrode GE1a, the second gate electrode GE2a, the third gate electrode GE3a, the fourth gate electrode GE4a, the fifth gate electrode GE1b, the sixth gate electrode GE2b, the seventh gate electrode GE3b, and the eighth gate electrode GE4b may extend in the first direction DR1.

[0149] In an embodiment, each of the first gate electrode GE1a and the fifth gate electrode GE1b may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0150] The first gate electrode GE1a may overlap with the first channel region CH1a of the first active portion A1a in a planar view (i.e., along the third direction DR3). The first gate electrode GE1a may be the gate electrode of the first driving transistor T1a. Similarly, the fifth gate electrode GE1b may overlap with the fifth channel region CH1b of the fifth active portion A1b in a planar view (i.e., along the third direction DR3). The fifth gate electrode GE1b may be the gate electrode of the second driving transistor T1b.

[0151] The second gate electrode GE2a may overlap with the second channel region CH2a of the second active portion A2a in a planar view (i.e., along the third direction DR3). The second gate electrode GE2a may be the gate electrode of the first data write transistor T2a. Similarly, the sixth gate electrode GE2b may overlap with the sixth channel region CH2b of the sixth active portion A2b in a planar view (i.e., along the third direction DR3). The sixth gate electrode GE2b may be the gate electrode of the second data write transistor T2b.

[0152] The third gate electrode GE3a may overlap with the third channel region CH3a of the third active portion A3a in a planar view (i.e., along the third direction DR3). The third gate electrode GE3a may be the gate electrode of the first emitter control transistor T3a. Similarly, the seventh gate electrode GE3b may overlap with the seventh channel region CH3b of the seventh active portion A3b in a planar view (i.e., along the third direction DR3). The seventh gate electrode GE3b may be the gate electrode of the second emitter control transistor T3b.

[0153] The fourth gate electrode GE4a may overlap with the fourth channel region CH4a of the fourth active portion A4a in a planar view (i.e., along the third direction DR3). The fourth gate electrode GE4a may be the gate electrode of the first initialization transistor T4a. Similarly, the eighth gate electrode GE4b may overlap with the eighth channel region CH4b of the eighth active portion A4b in a planar view (i.e., along the third direction DR3). The eighth gate electrode GE4b may be the gate electrode of the second initialization transistor T4b.

[0154] The first gate electrode GE1a may include a first contact portion CPa, and the fifth gate electrode GE1b may include a second contact portion CPb. The first contact portion CPa can be electrically connected to the first data write transistor T2a via a first connection line CLa, and the second contact portion CPb can be electrically connected to the second data write transistor T2b via a second connection line CLb. For example, the first connection line CLa can directly connect the first contact portion CPa and the first data write transistor T2a, or it can connect the first contact portion CPa and the first data write transistor T2a via another conductive pattern. Similarly, the second connection line CLb can directly connect the second contact portion CPb and the second data write transistor T2b, or it can connect the second contact portion CPb and the second data write transistor T2b via another conductive pattern.

[0155] In an embodiment, the first contact portion CPa may be located in the first pixel circuit region PCAa, and the second contact portion CPb may be located in the second pixel circuit region PCAb.

[0156] Figure 8 It is shown that it includes Figure 5 An example layout diagram of the first pixel driving circuit section, the second pixel driving circuit section, the third pixel driving circuit section, the fourth pixel driving circuit section, the fifth pixel driving circuit section, and the sixth pixel driving circuit section in a transistor array. Figure 9 It is shown that it includes Figure 5An example layout diagram of the first pixel driving circuit section, the second pixel driving circuit section, the third pixel driving circuit section, the fourth pixel driving circuit section, the fifth pixel driving circuit section, and the sixth pixel driving circuit section in a transistor array.

[0157] In the following text, including references Figure 8 and Figure 9 The arrangement of transistors in the first pixel driving circuit section PCa and the second pixel driving circuit section PCb described herein can be consistent with that included in the reference. Figure 6 and Figure 7 The transistors in the first pixel driving circuit section PCa and the second pixel driving circuit section PCb have the same arrangement structure. Therefore, redundant descriptions will be omitted or simplified.

[0158] refer to Figure 8 and Figure 9 The third pixel driving circuit PCc may include a third driving transistor T1c, a third data writing transistor T2c, a third emission control transistor T3c and a third initialization transistor T4c disposed in the third pixel circuit region PCAc.

[0159] Here, the third driving transistor T1c can correspond to Figure 3 The first transistor T1 and the third data write transistor T2c can correspond to Figure 3 The second transistor T2 and the third emitter control transistor T3c can correspond to Figure 3 The third transistor T3 in the middle, and the third initialization transistor T4c can correspond to Figure 3 The fourth transistor T4 in the process.

[0160] The fourth pixel driving circuit PCa' may include a fourth driving transistor T1a', a fourth data writing transistor T2a', a fourth emission control transistor T3a', and a fourth initialization transistor T4a'; the fifth pixel driving circuit PCb' may include a fifth driving transistor T1b', a fifth data writing transistor T2b', a fifth emission control transistor T3b', and a fifth initialization transistor T4b'; and the sixth pixel driving circuit PCc' may include a sixth driving transistor T1c', a sixth data writing transistor T2c', a sixth emission control transistor T3c', and a sixth initialization transistor T4c'. The fourth driving transistor T1a', the fifth driving transistor T1b', and the sixth driving transistor T1c' may each include substantially the same components as their corresponding first driving transistor T1a, second driving transistor T1b, and third driving transistor T1c. The fourth data writing transistor T2a', the fifth data writing transistor T2b', and the sixth data writing transistor T2c' may each include substantially the same components as their corresponding first data writing transistor T2a, second data writing transistor T2b, and third data writing transistor T2c. The fourth emitter control transistor T3a', the fifth emitter control transistor T3b', and the sixth emitter control transistor T3c' may each include substantially the same components as their corresponding first emitter control transistor T3a, second emitter control transistor T3b, and third emitter control transistor T3c. Furthermore, the fourth initialization transistor T4a', the fifth initialization transistor T4b', and the sixth initialization transistor T4c' may each include substantially the same components as their corresponding first initialization transistor T4a, second initialization transistor T4b, and third initialization transistor T4c.

[0161] The first data writing transistor T2a, the second data writing transistor T2b, the third data writing transistor T2c, the fourth data writing transistor T2a', the fifth data writing transistor T2b', and the sixth data writing transistor T2c' can be arranged sequentially along the first direction DR1. The first emitter control transistor T3a, the second emitter control transistor T3b, the third emitter control transistor T3c, the fourth emitter control transistor T3a', the fifth emitter control transistor T3b', and the sixth emitter control transistor T3c' can be arranged sequentially along the first direction DR1. The first initialization transistor T4a, the second initialization transistor T4b, the third initialization transistor T4c, the fourth initialization transistor T4a', the fifth initialization transistor T4b', and the sixth initialization transistor T4c' can be arranged sequentially along the first direction DR1.

[0162] In an embodiment, each of the third driving transistor T1c and the fourth driving transistor T1a' may be disposed in both the third pixel circuit region PCAc and the fourth pixel circuit region PCAa', and each of the fifth driving transistor T1b' and the sixth driving transistor T1c' may be disposed in both the fifth pixel circuit region PCAb' and the sixth pixel circuit region PCAc'. In an embodiment, the third driving transistor T1c and the fourth driving transistor T1a' may be offset relative to the first driving transistor T1a and the second driving transistor T1b in the first pixel circuit region PCAa and the second pixel circuit region PCAb, respectively, along the first direction DR1 and the direction opposite to the second direction DR2.

[0163] like Figure 8 As shown in the embodiment, the first driving transistor T1a, the third driving transistor T1c, and the fifth driving transistor T1b' can be located in the Nth row (where N is a natural number greater than 0) parallel to the first direction DR1, and the second driving transistor T1b, the fourth driving transistor T1a', and the sixth driving transistor T1c' can be located in the (N+1)th row, which is parallel to the first direction DR1 and adjacent to the Nth row in the direction opposite to the second direction DR2. That is, the third driving transistor T1c can be adjacent to the fourth driving transistor T1a' in the second direction DR2, and the fifth driving transistor T1b' can be adjacent to the sixth driving transistor T1c' in the second direction DR2.

[0164] However, the embodiments are not limited to this. For example... Figure 9 As shown in the embodiment, the first driving transistor T1a, the fourth driving transistor T1a', and the sixth driving transistor T1c' can be located in the Nth row parallel to the first direction DR1, and the second driving transistor T1b, the third driving transistor T1c, and the fifth driving transistor T1b' can be located in the (N+1)th row. That is, the third driving transistor T1c can be adjacent to the fourth driving transistor T1a' in a direction opposite to the second direction DR2, and the fifth driving transistor T1b' can be adjacent to the sixth driving transistor T1c' in a direction opposite to the second direction DR2.

[0165] The third driving transistor T1c may include the ninth active portion A1c and the ninth gate electrode GE1c of the substrate SUB; the third data writing transistor T2c may include the tenth active portion A2c and the tenth gate electrode GE2c of the substrate SUB; the third emitter control transistor T3c may include the eleventh active portion A3c and the eleventh gate electrode GE3c of the substrate SUB; and the third initialization transistor T4c may include the twelfth active portion A4c and the twelfth gate electrode GE4c of the substrate SUB.

[0166] Each of the ninth active portion A1c, the tenth active portion A2c, the eleventh active portion A3c, and the twelfth active portion A4c may include a source region, a drain region, and a channel region between the source and drain regions. For example, the source and drain regions may be doped with P-type impurities. The ninth gate electrode GE1c, the tenth gate electrode GE2c, the eleventh gate electrode GE3c, and the twelfth gate electrode GE4c may overlap with the channel regions of the ninth active portion A1c, the tenth active portion A2c, the eleventh active portion A3c, and the twelfth active portion A4c, respectively, in a planar view (i.e., along the third direction DR3).

[0167] The ninth gate electrode GE1c may include a third contact portion CPc. The third contact portion CPc may be electrically connected to the third data write transistor T2c via a third connection line. In an embodiment, the third contact portion CPc may be located in the third pixel circuit region PCAc.

[0168] Figure 10 It is shown that it includes Figure 5 A layout diagram of an example of a first pixel driving circuit section, a second pixel driving circuit section, and a third pixel driving circuit section in a transistor array.

[0169] References will be omitted or simplified in the following text. Figure 6 , Figure 7 , Figure 8 and Figure 9 The description is redundant. Furthermore, the following descriptions of the first pixel driving circuit PCa, the second pixel driving circuit PCb, and the third pixel driving circuit PCc can be applied substantially equivalently to... Figure 5 The fourth pixel driving circuit PCa', the fifth pixel driving circuit PCb', and the sixth pixel driving circuit PCc' are in the middle.

[0170] refer to Figure 10 The first data writing transistor T2a, the first emitter control transistor T3a, the first drive transistor T1a, and the first initialization transistor T4a can be arranged sequentially in the direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the transistors arranged in the first pixel circuit region PCAa can be interchanged. The arrangement order of the transistors included in each of the second pixel drive circuit section PCb and the third pixel drive circuit section PCc in the direction opposite to the second direction DR2 can be the same as the arrangement order of the transistors included in the first pixel drive circuit section PCa in the direction opposite to the second direction DR2.

[0171] The first data writing transistor T2a, the second data writing transistor T2b, and the third data writing transistor T2c can be arranged sequentially along the first direction DR1. The first emitter control transistor T3a, the second emitter control transistor T3b, and the third emitter control transistor T3c can be arranged sequentially along the first direction DR1. The first initialization transistor T4a, the second initialization transistor T4b, and the third initialization transistor T4c can also be arranged sequentially along the first direction DR1.

[0172] In one embodiment, the second driving transistor T1b may be adjacent to the first driving transistor T1a in a direction opposite to the second direction DR2, and the third driving transistor T1c may be adjacent to the second driving transistor T1b in a direction opposite to the second direction DR2. Specifically, the first driving transistor T1a, the second driving transistor T1b, and the third driving transistor T1c may be arranged in different rows parallel to the first direction DR1. However, the embodiment is not limited to this, and the positions of the first driving transistor T1a, the second driving transistor T1b, and the third driving transistor T1c may be interchanged.

[0173] In an embodiment, each of the first driving transistor T1a, the second driving transistor T1b, and the third driving transistor T1c may be disposed in the first pixel circuit region PCAa, the second pixel circuit region PCAb, and the third pixel circuit region PCAc. In another embodiment, at least one of the first driving transistor T1a and the second driving transistor T1b may extend from the first pixel circuit region PCAa and the second pixel circuit region PCAb to the third pixel circuit region PCAc. In this case, each of the first active portion A1a and the first gate electrode GE1a of the first driving transistor T1a may be disposed in the first pixel circuit region PCAa, the second pixel circuit region PCAb, and the third pixel circuit region PCAc; each of the fifth active portion A1b and the fifth gate electrode GE1b of the second driving transistor T1b may be disposed in the first pixel circuit region PCAa, the second pixel circuit region PCAb, and the third pixel circuit region PCAc; and each of the ninth active portion A1c and the ninth gate electrode GE1c of the third driving transistor T1c may be disposed in the first pixel circuit region PCAa, the second pixel circuit region PCAb, and the third pixel circuit region PCAc.

[0174] Figure 11 It is shown Figure 1 A circuit diagram of another example of the circuit structure for one pixel. Except for omitting the fourth transistor T4, the second capacitor C2, and the third capacitor C3, refer to... Figure 11 The described pixel PX can be compared with the reference. Figure 3The described pixels PX are essentially the same or similar. Therefore, redundant descriptions will be omitted or simplified.

[0175] refer to Figure 11 Each pixel PX may include a pixel driving circuit PC' and a light-emitting element LED electrically connected to the pixel driving circuit PC'. The pixel driving circuit PC' can generate a driving current, and the light-emitting element LED can emit light based on the driving current.

[0176] In an embodiment, the pixel driving circuit PC' may include a first transistor T1, a second transistor T2, a third transistor T3, and a first capacitor C1.

[0177] In this embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 can all be MOSFETs formed using semiconductor processes.

[0178] In this embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 may all be PMOS transistors. However, the embodiment is not limited to this, and some of the first transistor T1, the second transistor T2, and the third transistor T3 may be PMOS transistors, while the others may be NMOS transistors.

[0179] The first transistor T1 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor T1 may be connected to a first node N1. The source electrode of the first transistor T1 may be connected to a second node N2. The drain electrode of the first transistor T1 may be connected to the anode electrode of the light-emitting element LED. The first transistor T1 can provide drive current to the light-emitting element LED. The first transistor T1 may be referred to as a drive transistor.

[0180] The second transistor T2 may include a gate electrode, a source electrode, and a drain electrode. A first gate signal line GWL, which receives the first gate signal GW, can be connected to the gate electrode of the second transistor T2. A data line DL, which receives the data voltage DATA, can be connected to the source electrode of the second transistor T2. The drain electrode of the second transistor T2 can be connected to the first node N1. That is, the second transistor T2 can be electrically connected to the first transistor T1. The second transistor T2 can be turned on or off in response to the first gate signal GW. The second transistor T2 can be referred to as a data write transistor.

[0181] The third transistor T3 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the third transistor T3 may be connected to the emitter control line EL for receiving the emitter signal EM. The source electrode of the third transistor T3 may be connected to the drive voltage line ELVDL for receiving the drive voltage ELVDD. The drain electrode of the third transistor T3 may be connected to the second node N2. That is, the third transistor T3 may be electrically connected to the first transistor T1. The third transistor T3 may be turned on or off in response to the emitter signal EM. The third transistor T3 may be referred to as the emitter control transistor.

[0182] Each of the first transistor T1, the second transistor T2, and the third transistor T3 may further include a body electrode. The body electrode of each of the first transistor T1, the second transistor T2, and the third transistor T3 may receive a drive voltage ELVDD. For example, the body electrode of each of the first transistor T1, the second transistor T2, and the third transistor T3 may be connected to a drive voltage line ELVDL that receives the drive voltage ELVDD. Alternatively, a separate voltage other than the drive voltage ELVDD may be applied to the body electrode of each of the first transistor T1, the second transistor T2, and the third transistor T3.

[0183] The first capacitor C1 may include a first electrode and a second electrode. The first electrode of the first capacitor C1 may be connected to a first node N1. The second electrode of the first capacitor C1 may be connected to a second node N2.

[0184] A light-emitting element (LED) may include an anode electrode and a cathode electrode. The anode electrode of the LED may be connected to the drain electrode of a first transistor T1. A common voltage line ELVSL, which receives a common voltage ELVSS, may be connected to the cathode electrode of the LED. The common voltage ELVSS may have a lower voltage level than the drive voltage ELVDD.

[0185] although Figure 11 A pixel driving circuit section PC' comprising three transistors and a capacitor is shown, but embodiments are not necessarily limited thereto.

[0186] Figure 12 It is shown that it includes Figure 5 A layout diagram of another example of the first pixel driving circuit section and the second pixel driving circuit section in a transistor array.

[0187] In the following text, except for the omission of the first initialization transistor T4a and the second initialization transistor T4b, refer to Figure 12 The first pixel driving circuit section PCa and the second pixel driving circuit section PCb described herein can be compared with the reference. Figure 6 and Figure 7The first pixel driving circuit PCa and the second pixel driving circuit PCb are substantially the same or similar. Therefore, redundant descriptions will be omitted or simplified.

[0188] Furthermore, the following descriptions of the first pixel driving circuit section PCa and the second pixel driving circuit section PCb can be applied substantially equivalently to... Figure 5 The third pixel driving circuit PCc, the fourth pixel driving circuit PCa', the fifth pixel driving circuit PCb', and the sixth pixel driving circuit PCc'.

[0189] refer to Figure 12 The first pixel driving circuit PCa may include a first driving transistor T1a, a first data writing transistor T2a, and a first emission control transistor T3a disposed in the first pixel circuit region PCAa. Similarly, the second pixel driving circuit PCb may include a second driving transistor T1b, a second data writing transistor T2b, and a second emission control transistor T3b disposed in the second pixel circuit region PCAb.

[0190] The first driving transistor T1a, the first data writing transistor T2a, and the first emitter control transistor T3a can be arranged in a row along the second direction DR2. In an embodiment, the first data writing transistor T2a, the first driving transistor T1a, and the first emitter control transistor T3a can be arranged sequentially along a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the transistors disposed in the first pixel circuit region PCAa can be interchanged. The arrangement order of the transistors included in the second pixel driving circuit section PCb in the direction opposite to the second direction DR2 can be the same as the arrangement order of the transistors included in the first pixel driving circuit section PCa in the direction opposite to the second direction DR2.

[0191] The second data write transistor T2b can be adjacent to the first data write transistor T2a in the first direction DR1, and the second emitter control transistor T3b can be adjacent to the first emitter control transistor T3a in the first direction DR1.

[0192] In one embodiment, the second driving transistor T1b may be adjacent to the first driving transistor T1a in a direction opposite to the second direction DR2. Specifically, the first driving transistor T1a may be located in the Nth row (where N is a natural number greater than 0) parallel to the first direction DR1, and the second driving transistor T1b may be located in the (N+1)th row parallel to the first direction DR1 and adjacent to the Nth row in a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the first driving transistor T1a and the second driving transistor T1b may be interchanged.

[0193] In one embodiment, the first driving transistor T1a can extend from the first pixel circuit region PCAa to the second pixel circuit region PCAb, and the second driving transistor T1b can extend from the second pixel circuit region PCAb to the first pixel circuit region PCAa. That is, each of the first driving transistor T1a and the second driving transistor T1b can be located in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0194] Each of the first pixel driving circuit PCa and the second pixel driving circuit PCb can correspond to Figure 11 The pixel driving circuit PC' in the middle. That is, the first driving transistor T1a and the second driving transistor T1b can correspond to Figure 11 The first transistor T1, the first data write transistor T2a, and the second data write transistor T2b in the diagram can correspond to... Figure 11 The second transistor T2 in the middle, and the first emitter control transistor T3a and the second emitter control transistor T3b can correspond to Figure 11 The third transistor T3 in the process.

[0195] In other words, the first driving transistor T1a and the second driving transistor T1b can generate a driving current, and the first emitter control transistor T3a and the second emitter control transistor T3b can respond to an emitter signal (e.g., Figure 11 The transmitted signal EM in the signal receives the driving voltage (e.g., Figure 11 The driving voltage ELVDD in the data). Furthermore, the first data write transistor T2a and the second data write transistor T2b can respectively respond to the first gate signal (e.g., Figure 11 The first gate signal (GW) receives the first data voltage and the second data voltage. The first data voltage and the second data voltage can be supplied through different data lines.

[0196] The first driving transistor T1a, the first data writing transistor T2a, and the first emitter control transistor T3a may each include a first active portion A1a, a second active portion A2a, and a third active portion A3a spaced apart from each other on the substrate SUB. Similarly, the second driving transistor T1b, the second data writing transistor T2b, and the second emitter control transistor T3b may each include a fifth active portion A1b, a sixth active portion A2b, and a seventh active portion A3b spaced apart from each other on the substrate SUB. In an embodiment, each of the first active portion A1a, the second active portion A2a, and the third active portion A3a, and each of the fifth active portion A1b, the sixth active portion A2b, and the seventh active portion A3b may extend in the first direction DR1.

[0197] The first driving transistor T1a, the first data writing transistor T2a, and the first emitter control transistor T3a may also include a first gate electrode GE1a, a second gate electrode GE2a, and a third gate electrode GE3a spaced apart from each other. Similarly, the second driving transistor T1b, the second data writing transistor T2b, and the second emitter control transistor T3b may also include a fifth gate electrode GE1b, a sixth gate electrode GE2b, and a seventh gate electrode GE3b spaced apart from each other.

[0198] The first active portion A1a, the second active portion A2a, and the third active portion A3a may each include source regions SR1a, SR2a, and SR3a, drain regions DR1a, DR2a, and DR3a, and channel regions CH1a, CH2a, and CH3a between the source regions SR1a, SR2a, and SR3a and the drain regions DR1a, DR2a, and DR3a. For example, the source regions SR1a, SR2a, and SR3a and the drain regions DR1a, DR2a, and DR3a may be doped with P-type impurities. The first gate electrode GE1a, the second gate electrode GE2a, and the third gate electrode GE3a may overlap with the channel regions CH1a, CH2a, and CH3a respectively in a planar view (i.e., along the third direction DR3).

[0199] The fifth active portion A1b, the sixth active portion A2b, and the seventh active portion A3b may each include source regions SR1b, SR2b, and SR3b, drain regions DR1b, DR2b, and DR3b, and channel regions CH1b, CH2b, and CH3b between the source regions SR1a, SR2a, and SR3a and the drain regions DR1a, DR2a, and DR3a. For example, the source regions SR1b, SR2b, and SR3b, and the drain regions DR1b, DR2b, and DR3b may be doped with P-type impurities. The fifth gate electrode GE1b, the sixth gate electrode GE2b, and the seventh gate electrode GE3b may overlap with the channel regions CH1b, CH2b, and CH3b, respectively, in a planar view (i.e., along the third direction DR3).

[0200] In an embodiment, each of the first active portion A1a and the first gate electrode GE1a of the first driving transistor T1a may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb. Similarly, each of the fifth active portion A1b and the fifth gate electrode GE1b of the second driving transistor T1b may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0201] Figure 13 It is shown that it includes Figure 5 A layout diagram of another example of the first pixel driving circuit section and the second pixel driving circuit section in a transistor array.

[0202] In the following text, apart from the structures of the first driving transistor T1a and the second driving transistor T1b, refer to Figure 13 The first pixel driving circuit section PCa and the second pixel driving circuit section PCb described herein can be compared with the reference. Figure 12 The first pixel driving circuit PCa and the second pixel driving circuit PCb are substantially the same or similar. Therefore, redundant descriptions will be omitted or simplified.

[0203] refer to Figure 13 The first driving transistor T1a, the first data writing transistor T2a, and the first emitter control transistor T3a can be arranged in a row along the second direction DR2. In an embodiment, the first data writing transistor T2a, the first driving transistor T1a, and the first emitter control transistor T3a can be arranged sequentially along a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the transistors arranged in the first pixel circuit region PCAa can be interchanged.

[0204] The second driving transistor T1b, the second data writing transistor T2b, and the second emitter control transistor T3b can also be arranged in a row along the second direction DR2. In an embodiment, the second data writing transistor T2b, the second emitter control transistor T3b, and the second driving transistor T1b can be arranged sequentially along a direction opposite to the second direction DR2. However, the embodiment is not limited to this, and the positions of the transistors disposed in the second pixel circuit region PCAb can be interchanged with each other.

[0205] In an embodiment, the first driving transistor T1a may include a first-first driving transistor T1-1a and a first-second driving transistor T1-2a. The first-first driving transistor T1-1a is disposed in the first pixel circuit region PCAa, and the first-second driving transistor T1-2a is disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb. The first-second driving transistor T1-2a is connected to the first-first driving transistor T1-1a and is adjacent to the first-first driving transistor T1-1a in a direction opposite to the second direction DR2. Similarly, the second driving transistor T1b may include a second-first driving transistor T1-1b and a second-second driving transistor T1-2b. The second-first driving transistor T1-1b is disposed in the second pixel circuit region PCAb, and the second-second driving transistor T1-2b is disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb. The second-second driving transistor T1-2b is connected to the second-first driving transistor T1-1b and is adjacent to the second-first driving transistor T1-1b in the second direction DR2.

[0206] The first-first driving transistor T1-1a, the first-second driving transistor T1-2a, the second-first driving transistor T1-1b, and the second-second driving transistor T1-2b may each include a first-first active portion A1-1a, a first-second active portion A1-2a, a fifth-first active portion A1-1b, and a fifth-second active portion A1-2b spaced apart from each other on the substrate SUB. In an embodiment, each of the active portions A1-1a, A1-2a, A1-1b, and A1-2b may extend in the first direction DR1.

[0207] In this embodiment, the first active portion A1-1a may be disposed in the first pixel circuit region PCAa, and the first active portion A1-2a may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb. Furthermore, the fifth active portion A1-1b may be disposed in the second pixel circuit region PCAb, and the fifth active portion A1-2b may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0208] The first-first active portion A1-1a may include a first-first source region SR1-1a, a first-first drain region DR1-1a, and a first-first channel region CH1-1a between the first-first source region SR1-1a and the first-first drain region DR1-1a. For example, the first-first source region SR1-1a and the first-first drain region DR1-1a may be doped with P-type impurities. The first-first source region SR1-1a and the first-first drain region DR1-1a may be the source electrode and drain electrode of the first-first driving transistor T1-1a, respectively.

[0209] The first-second active portion A1-2a may include a first-second source region SR1-2a, a first-second drain region DR1-2a, and a first-second channel region CH1-2a between the first-second source region SR1-2a and the first-second drain region DR1-2a. For example, the first-second source region SR1-2a and the first-second drain region DR1-2a may be doped with P-type impurities. The first-second source region SR1-2a and the first-second drain region DR1-2a may be the source electrode and drain electrode of the first-second driving transistor T1-2a, respectively.

[0210] The fifth-first active portion A1-1b may include a fifth-first source region SR1-1b, a fifth-first drain region DR1-1b, and a fifth-first channel region CH1-1b between the fifth-first source region SR1-1b and the fifth-first drain region DR1-1b. For example, the fifth-first source region SR1-1b and the fifth-first drain region DR1-1b may be doped with P-type impurities. The fifth-first source region SR1-1b and the fifth-first drain region DR1-1b may be the source electrode and drain electrode of the second-first driving transistor T1-1b, respectively.

[0211] The fifth-second active portion A1-2b may include a fifth-second source region SR1-2b, a fifth-second drain region DR1-2b, and a fifth-second channel region CH1-2b between the fifth-second source region SR1-2b and the fifth-second drain region DR1-2b. For example, the fifth-second source region SR1-2b and the fifth-second drain region DR1-2b may be doped with P-type impurities. The fifth-second source region SR1-2b and the fifth-second drain region DR1-2b may be the source electrode and drain electrode of the second-second driving transistor T1-2b, respectively.

[0212] The first-first driving transistor T1-1a and the first-second driving transistor T1-2a may also include a first-first gate electrode and a first-second gate electrode, respectively, and the second-first driving transistor T1-1b and the second-second driving transistor T1-2b may also include a fifth-first gate electrode and a fifth-second gate electrode, respectively.

[0213] The first-first gate electrode and the first-second gate electrode may overlap with the first-first channel region CH1-1a and the first-second channel region CH1-2a respectively in the plan view (i.e., along the third direction DR3), and the fifth-first gate electrode and the fifth-second gate electrode may overlap with the fifth-first channel region CH1-1b and the fifth-second channel region CH1-2b respectively in the plan view (i.e., along the third direction DR3).

[0214] In this embodiment, the first-first gate electrode and the first-second gate electrode can be configured as a single body, and the fifth-first gate electrode and the fifth-second gate electrode can be configured as a single body. That is, the first-first gate electrode and the first-second gate electrode can be configured as a first gate electrode GE1a, and the fifth-first gate electrode and the fifth-second gate electrode can be configured as a fifth gate electrode GE1b.

[0215] In an embodiment, the first gate electrode GE1a may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb, and the fifth gate electrode GE1b may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0216] In one embodiment, the first gate electrode GE1a may be L-shaped in a plan view, and the fifth gate electrode GE1b may be L-shaped rotated 180 degrees in a plan view. However, the embodiment is not limited to this.

[0217] In an embodiment, the transistor array TA (see...) Figure 5 It may also include a first connection pattern CNPa connecting the drain region DR1-1a of the first-first active portion A1-1a and the source region SR1-2a of the first-second active portion A1-2a, and a second connection pattern CNPb connecting the drain region DR1-1b of the fifth-first active portion A1-1b and the source region SR1-2b of the fifth-second active portion A1-2b. Therefore, the first-first driving transistor T1-1a and the first-second driving transistor T1-2a can be electrically connected to each other, and the second-first driving transistor T1-1b and the second-second driving transistor T1-2b can be electrically connected to each other.

[0218] Figure 14 It is shown that it includes Figure 5 A layout diagram of another example of the first pixel driving circuit section and the second pixel driving circuit section in a transistor array.

[0219] In the following text, except for the structure of the gate electrodes of the first driving transistor T1a and the second driving transistor T1b, refer to Figure 14 The first pixel driving circuit section PCa and the second pixel driving circuit section PCb described herein can be compared with the reference. Figure 13 The first pixel driving circuit PCa and the second pixel driving circuit PCb are substantially the same or similar. Therefore, redundant descriptions will be omitted or simplified.

[0220] refer to Figure 14 The first-first driving transistor T1-1a, the first-second driving transistor T1-2a, the second-first driving transistor T1-1b, and the second-second driving transistor T1-2b may each include a first-first active portion A1-1a, a first-second active portion A1-2a, a fifth-first active portion A1-1b, and a fifth-second active portion A1-2b spaced apart from each other on the substrate SUB.

[0221] The first-first driving transistor T1-1a and the first-second driving transistor T1-2a may also include a first-first gate electrode GE1-1a and a first-second gate electrode GE1-2a, respectively, and the second-first driving transistor T1-1b and the second-second driving transistor T1-2b may also include a fifth-first gate electrode GE1-1b and a fifth-second gate electrode GE1-2b, respectively.

[0222] In an embodiment, the first-first gate electrode GE1-1a and the first-second gate electrode GE1-2a may be spaced apart from each other, and the fifth-first gate electrode GE1-1b and the fifth-second gate electrode GE1-2b may be spaced apart from each other.

[0223] Combination Figure 13 The first-first gate electrode GE1-1a and the first-second gate electrode GE1-2a can overlap with the first-first channel region CH1-1a and the first-second channel region CH1-2a respectively in the planar view (i.e., along the third direction DR3), and the fifth-first gate electrode GE1-1b and the fifth-second gate electrode GE1-2b can overlap with the fifth-first channel region CH1-1b and the fifth-second channel region CH1-2b respectively in the planar view (i.e., along the third direction DR3).

[0224] In an embodiment, the first-first gate electrode GE1-1a may be disposed in the first pixel circuit region PCAa, the fifth-first gate electrode GE1-1b may be disposed in the second pixel circuit region PCAb, and each of the first-second gate electrode GE1-2a and the fifth-second gate electrode GE1-2b may be disposed in both the first pixel circuit region PCAa and the second pixel circuit region PCAb.

[0225] In an embodiment, the transistor array TA (see...) Figure 5 It may also include a first gate connection pattern GCPa that connects the first-first gate electrode GE1-1a and the first-second gate electrode GE1-2a, and a second gate connection pattern GCPb that connects the fifth-first gate electrode GE1-1b and the fifth-second gate electrode GE1-2b.

[0226] Figure 15 It is shown that it includes Figure 5 Another example layout diagram of the first pixel driving circuit section, the second pixel driving circuit section, and the third pixel driving circuit section in a transistor array.

[0227] In the following text, except for the omission of the first initialization transistor T4a, the second initialization transistor T4b, and the third initialization transistor T4c, refer to Figure 15The first pixel driving circuit PCa, the second pixel driving circuit PCb, and the third pixel driving circuit PCc described herein can be compared with the reference. Figure 10 The first pixel driving circuit PCa, the second pixel driving circuit PCb, and the third pixel driving circuit PCc are substantially the same or similar. Therefore, redundant descriptions will be omitted or simplified.

[0228] Furthermore, the following descriptions of the first pixel driving circuit section PCa, the second pixel driving circuit section PCb, and the third pixel driving circuit section PCc can be applied substantially equivalently to... Figure 5 The fourth pixel driving circuit PCa', the fifth pixel driving circuit PCb', and the sixth pixel driving circuit PCc' are in the middle.

[0229] refer to Figure 15 The first data writing transistor T2a, the first driving transistor T1a, and the first emitter control transistor T3a can be arranged sequentially in the direction opposite to the second direction DR2. However, the embodiments are not limited to this, and the positions of the transistors arranged in the first pixel circuit region PCAa can be interchanged. The arrangement order of the transistors included in each of the second pixel driving circuit section PCb and the third pixel driving circuit section PCc in the direction opposite to the second direction DR2 can be the same as the arrangement order of the transistors included in the first pixel driving circuit section PCa in the direction opposite to the second direction DR2.

[0230] The first data write transistor T2a, the second data write transistor T2b, and the third data write transistor T2c can be arranged sequentially along the first direction DR1, and the first emitter control transistor T3a, the second emitter control transistor T3b, and the third emitter control transistor T3c can be arranged sequentially along the first direction DR1.

[0231] In one embodiment, the second driving transistor T1b may be adjacent to the first driving transistor T1a in a direction opposite to the second direction DR2, and the third driving transistor T1c may be adjacent to the second driving transistor T1b in a direction opposite to the second direction DR2. Specifically, the first driving transistor T1a, the second driving transistor T1b, and the third driving transistor T1c may be arranged in different rows parallel to the first direction DR1. However, the embodiment is not limited to this, and the positions of the first driving transistor T1a, the second driving transistor T1b, and the third driving transistor T1c may be interchanged.

[0232] In an embodiment, each of the first driving transistor T1a, the second driving transistor T1b, and the third driving transistor T1c may be disposed in the first pixel circuit region PCAa, the second pixel circuit region PCAb, and the third pixel circuit region PCAc.

[0233] The third pixel driving circuit PCc can correspond to Figure 11 The pixel driving circuit PC' in the middle. That is to say, the third driving transistor T1c can correspond to Figure 11 The first transistor T1 and the third data write transistor T2c can correspond to Figure 11 The second transistor T2 in the middle, and the third emitter control transistor T3c can correspond to Figure 11 The third transistor T3 in the process.

[0234] Refer again Figures 5 to 15 In the display device DD according to the embodiment (see Figure 1 In this design, the two driving transistors of two pixel driving circuit sections respectively disposed in the first pixel circuit region and the second pixel circuit region, which are adjacent to each other, can be disposed in both the first pixel circuit region and the second pixel circuit region. Alternatively, the three driving transistors of three pixel driving circuit sections respectively disposed in the first pixel circuit region, the second pixel circuit region, and the third pixel circuit region, can be disposed in all the first pixel circuit region, the second pixel circuit region, and the third pixel circuit region. In this case, each of the multiple driving transistors can have a sufficiently long channel length. Therefore, the driving transistors can have a structure robust to changes. Therefore, the display device DD can achieve high resolution and improve display quality.

[0235] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment.

[0236] refer to Figure 16 The electronic device 10 according to the embodiment may include a display module 11, a processor 12, a memory 13, and a power module (e.g., a power circuit system) 14.

[0237] The display device according to the embodiment (e.g., Figure 1 The display device (DD) can be applied to various electronic devices. Electronic device 10 may include the display device described above, and may also include modules or devices with additional functions in addition to the display device.

[0238] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0239] Memory 13 can store data information required for the operation of processor 12 or display module 11. When processor 12 executes an application stored in memory 13, input image data (e.g., ...) is processed. Figure 1Input image data (IDAT) and / or control signals (e.g., Figure 1 The control signal (CTRL) can be transmitted to the display module 11, and the display module 11 can process the received signal and output image information through the display screen.

[0240] The power module 14 may include a power source such as a power adapter or battery device and a power conversion circuit that converts the power supplied by the power source to generate the power required for the operation of the electronic device 10.

[0241] At least one of the multiple components of the electronic device 10 described above may be included in the display device according to the above embodiments. Furthermore, some of the individual modules that are functionally included in a single module may be included in the display device, and other parts may be provided separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices within the electronic device 10 besides the display device.

[0242] Figure 17 This is a schematic diagram illustrating an electronic device according to various embodiments.

[0243] refer to Figure 16 and Figure 17 The various electronic devices 10 to which the display device according to the embodiment is applied may include not only image display electronic devices such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b and smartwatches 10_2c, or vehicle electronic devices 10_3 including display modules such as car dashboards, central instrument panels, central information displays (CIDs) mounted on dashboards and interior mirror displays.

[0244] As described above, although this disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various modifications and changes may be made thereto without departing from the spirit and scope of the invention as defined in the appended claims.

[0245] This disclosure can be applied to various electronic devices that are equipped with a display device. For example, this disclosure can be applied to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer monitors, and laptop computers.

Claims

1. A display device, wherein, The display device includes: The substrate includes a first pixel circuit region and a second pixel circuit region, wherein the second pixel circuit region is adjacent to the first pixel circuit region in a first direction. The first driving transistor of the first pixel driving circuit section is provided in both the first pixel circuit region and the second pixel circuit region. The second driving transistor of the second pixel driving circuit section is provided in both the first pixel circuit region and the second pixel circuit region, and the second driving transistor is adjacent to the first driving transistor in a second direction intersecting the first direction. A first light-emitting element is connected to the first pixel driving circuit and provided in the first light-emitting region; and A second light-emitting element is connected to the second pixel driving circuit and provided in the second light-emitting area, wherein the second light-emitting area is configured to emit light of a different color than the first light-emitting area.

2. The display device according to claim 1, wherein, At least one of the first driving transistor and the second driving transistor includes: The active portion of the substrate includes a source region, a drain region, and a channel region between the source region and the drain region; and The gate electrode overlaps with the channel region of the active portion in the plan view, and The active portion of at least one of the first driving transistor and the second driving transistor and the gate electrode are provided in both the first pixel circuit region and the second pixel circuit region.

3. The display device according to claim 1 or 2, wherein, The display device further includes: The first data write transistor of the first pixel driving circuit section is provided in the first pixel circuit region, connected to the first driving transistor, and receives a first data voltage in response to a first gate signal; The first emitter control transistor of the first pixel driving circuit section, wherein the first emitter control transistor is provided in the first pixel circuit region, connected to the first driving transistor, and receives a driving voltage in response to an emitter signal; and The first initialization transistor of the first pixel driving circuit section is provided in the first pixel circuit region, connected to the first driving transistor, and receives a first initialization voltage in response to a second gate signal. The first data write transistor, the first emit control transistor, the first drive transistor, and the first initialization transistor are provided sequentially along the second direction.

4. The display device according to claim 3, wherein, The display device further includes: The second data write transistor of the second pixel driving circuit section is provided in the second pixel circuit region, connected to the second driving transistor, and receives a second data voltage in response to the first gate signal; The second emitter control transistor of the second pixel driving circuit section, wherein the second emitter control transistor is provided in the second pixel circuit region, connected to the second driving transistor, and receives the driving voltage in response to the emitter signal; and The second initialization transistor of the second pixel driving circuit section is provided in the second pixel circuit region, connected to the second driving transistor, and receives a second initialization voltage in response to the second gate signal. The second data write transistor, the second emit control transistor, the second drive transistor, and the second initialization transistor are provided sequentially along the second direction.

5. The display device according to claim 1, wherein, The substrate further includes a third pixel circuit region adjacent to the second pixel circuit region in the first direction and a fourth pixel circuit region adjacent to the third pixel circuit region in the first direction. The display device further includes: The third driving transistor of the third pixel driving circuit section is provided in both the third pixel circuit region and the fourth pixel circuit region; The fourth driving transistor of the fourth pixel driving circuit section is provided in both the third pixel circuit region and the fourth pixel circuit region, and the fourth driving transistor is adjacent to the third driving transistor in the second direction; A third light-emitting element is connected to the third pixel driving circuit and is provided in the third light-emitting region; and A fourth light-emitting element is connected to the fourth pixel driving circuit and provided in the fourth light-emitting region, the fourth light-emitting region being configured to emit light of a different color than the third light-emitting region.

6. The display device according to claim 5, wherein, The third driving transistor and the fourth driving transistor are offset relative to the first driving transistor and the second driving transistor in the first pixel circuit region and the second pixel circuit region, respectively, along the first direction and the second direction.

7. The display device according to claim 5 or 6, wherein, The third driving transistor and the first driving transistor are located in the Nth row parallel to the first direction, where N is a natural number greater than 0. The fourth driving transistor and the second driving transistor are located in the N+1th row, which is parallel to the first direction and adjacent to the Nth row in the second direction.

8. The display device according to claim 5 or 6, wherein, The fourth driving transistor and the first driving transistor are located in the Nth row parallel to the first direction, where N is a natural number greater than 0, and The third driving transistor and the second driving transistor are located in the N+1th row, which is parallel to the first direction and adjacent to the Nth row in the second direction.

9. The display device according to claim 1, wherein, The substrate further includes a third pixel circuit region adjacent to the second pixel circuit region in the first direction. The display device further includes: A third driving transistor in a third pixel driving circuit section, wherein the third driving transistor is provided in each of the first pixel circuit region, the second pixel circuit region, and the third pixel circuit region, and the third driving transistor is adjacent to the second driving transistor in the second direction; and A third light-emitting element is connected to the third pixel driving circuit and provided in the third light-emitting region. The third light-emitting region is configured to emit light of a different color than the first light-emitting region and the second light-emitting region. Wherein, at least one of the first driving transistor and the second driving transistor extends from the first pixel circuit region and the second pixel circuit region to the third pixel circuit region.

10. The display device according to claim 1, wherein, The first driving transistor includes: A first driving transistor is provided in the first pixel circuit region; and A first and a second driving transistor are provided in both the first pixel circuit region and the second pixel circuit region, wherein the first and second driving transistors are connected to the first and second driving transistors, and the first and second driving transistors are adjacent to the first and second driving transistors in the second direction. The second driving transistor includes: A second-first driving transistor is provided in the second pixel circuit region; and A second driving transistor is provided in both the first pixel circuit region and the second pixel circuit region, wherein the second driving transistor is connected to the second driving transistor and is adjacent to the second driving transistor in a direction opposite to the second direction.

11. The display device according to claim 10, wherein, The first-first driving transistor includes a first-first active portion of the substrate provided in the first pixel circuit region and a first-first gate electrode overlapping the channel region of the first-first active portion in a planar view. The first and second driving transistors include first and second active portions of the substrate provided in both the first pixel circuit region and the second pixel circuit region, and first and second gate electrodes that overlap with the channel regions of the first and second active portions in a planar view. The second-first driving transistor includes a second-first active portion of the substrate provided in the second pixel circuit region and a second-first gate electrode that overlaps with the channel region of the second-first active portion in a planar view. The second-second driving transistor includes a second-second active portion of the substrate provided in both the first pixel circuit region and the second pixel circuit region, and a second-second gate electrode that overlaps with the channel region of the second-second active portion in a planar view.

12. The display device according to claim 11, wherein, The display device further includes: A first connection pattern connects the drain region of the first-first active portion and the source region of the first-second active portion; and The second connection pattern connects the drain region of the second-first active portion and the source region of the second-second active portion.

13. The display device according to claim 12, wherein, The first-first gate electrode and the first-second gate electrode are configured as a single body, and The second-first gate electrode and the second-second gate electrode are configured as a single body.

14. The display device according to claim 12, wherein, The display device further includes: A first gate connection pattern connects the first-first gate electrode and the first-second gate electrode; and The second gate connection pattern connects the second-first gate electrode and the second-second gate electrode.

15. The display device according to claim 10, wherein, The display device further includes: The first data write transistor of the first pixel driving circuit section, wherein the first data write transistor is provided in the first pixel circuit region, connected to the first driving transistor, and receives a first data voltage in response to a gate signal; and The first emitter control transistor of the first pixel driving circuit section is provided in the first pixel circuit region, connected to the first driving transistor, and receives a driving voltage in response to an emitter signal. The first data writing transistor, the first driving transistor, and the first emitter control transistor are provided sequentially along the second direction.

16. The display device according to claim 15, wherein, The display device further includes: The second data write transistor of the second pixel driving circuit section, wherein the second data write transistor is provided in the second pixel circuit region, connected to the second driving transistor, and receives a second data voltage in response to the gate signal; and The second emitter control transistor of the second pixel driving circuit section is provided in the second pixel circuit region, connected to the second driving transistor, and receives the driving voltage in response to the emitter signal. The second data write transistor, the second emit control transistor, and the second drive transistor are provided sequentially along the second direction.

17. The display device according to claim 1, wherein, The substrate includes a silicon wafer substrate.

18. The display device according to claim 1, wherein, The first driving transistor and the second driving transistor are P-type metal-oxide-semiconductor transistors.

19. An electronic device, wherein, The electronic device includes: The display panel includes: The substrate includes a first pixel circuit region and a second pixel circuit region, wherein the second pixel circuit region is adjacent to the first pixel circuit region in a first direction. The first driving transistor of the first pixel driving circuit section is provided in both the first pixel circuit region and the second pixel circuit region. The second driving transistor of the second pixel driving circuit section is provided in both the first pixel circuit region and the second pixel circuit region, and the second driving transistor is adjacent to the first driving transistor in a second direction intersecting the first direction. A first light-emitting element is connected to the first pixel driving circuit and provided in the first light-emitting area; A second light-emitting element is connected to the second pixel driving circuit and provided in the second light-emitting region, wherein the second light-emitting region is configured to emit light of a different color than the first light-emitting region; The controller is configured to control the operation of the display panel based on input image data and control signals; and The processor is configured to provide the input image data and the control signals to the controller.

20. The electronic device according to claim 19, wherein, At least one of the first driving transistor and the second driving transistor includes: The active portion of the substrate includes a source region, a drain region, and a channel region between the source region and the drain region; and The gate electrode overlaps with the channel region of the active portion in the plan view, and The active portion of at least one of the first driving transistor and the second driving transistor and the gate electrode are provided in both the first pixel circuit region and the second pixel circuit region.

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