Method of forming a semiconductor structure
By removing the sacrificial layer through etching and liquid-phase stripping processes, combined with ion implantation, the high cost of silicon-on-insulator (SOI) substrate fabrication was solved, resulting in cost reduction, improved surface uniformity, and enhanced semiconductor device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (BEIJING) CORP
- Filing Date
- 2025-01-20
- Publication Date
- 2026-07-24
Smart Images
Figure CN122458764A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] The structure of a silicon-on-insulator (SOI) substrate is as follows: there is an ultra-thin insulating layer, such as SiO2, on the silicon wafer. On top of the insulating layer is another thin silicon layer. This structure separates the active silicon layer from the substrate silicon layer, which can reduce the parasitic capacitance between the two by half.
[0003] With the development of integrated circuits, the requirements for substrates of chips are becoming increasingly stringent. In addition to traditional bulk silicon substrates, many new types of substrates have gradually emerged, such as high-resistivity silicon substrates, SOI substrates, and integrated passive device (IPD) substrates. Among them, SOI substrates (i.e., silicon-on-insulator substrates) have high resistance, thin top silicon and buried oxide structure, which are very beneficial to radio frequency front-end chips. They have advantages that bulk silicon does not have, such as low radio frequency loss, high isolation and low harmonics.
[0004] However, the current cost of fabricating silicon-on-insulator substrates is relatively high. Summary of the Invention
[0005] The technical problem solved by this invention is how to reduce the fabrication cost of silicon-on-insulator substrates.
[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a first silicon substrate and a second silicon substrate, the first silicon substrate including opposing first and second surfaces; performing thermal oxidation on the first silicon substrate to form an insulating oxide layer, the insulating oxide layer being located on the second surface of the first silicon substrate; implanting ions into the first surface of the first silicon substrate to form a sacrificial layer; bonding the second surface of the first silicon substrate to the second silicon substrate; and removing the sacrificial layer using an etching stripping process or a liquid phase stripping process to form a top silicon layer, the top silicon layer, the insulating oxide layer, and the second silicon substrate constituting a silicon-on-insulator substrate.
[0007] Optionally, the process parameters of the corrosion stripping process are as follows: the reaction solution is a phosphoric acid solution, nitric acid or hydrofluoric acid, the concentration of the reaction solution is 20% to 98%, and the reaction temperature is above 160°C.
[0008] Optionally, the process parameters for the liquid phase stripping process are: the reaction solution is water, isopropanol, or N-methylpyrrolidone.
[0009] Optionally, the process parameters for implanting ions onto the first surface of the first silicon substrate are: implantation energy range of 10MeV to 10KeV, and implanted ions of nitrogen, helium, or argon.
[0010] Optionally, the thickness of the sacrificial layer ranges from 50 nanometers to 50 micrometers, and the thickness of the top silicon layer ranges from 10 nanometers to 500 nanometers.
[0011] Optionally, after the step of implanting ions into the first surface of the first silicon substrate, the method further includes: annealing the first silicon substrate to form a first sacrificial layer on the surface of the first silicon substrate.
[0012] Optionally, after bonding the first silicon substrate and the second silicon substrate, the method further includes: removing the first sacrificial layer using an etching stripping process or a liquid phase stripping process.
[0013] Optionally, before bonding the first silicon substrate and the second silicon substrate, the method further includes pre-treating the surfaces of the first silicon substrate and the second silicon substrate.
[0014] Optionally, after removing the sacrificial layer and part of the insulating oxide layer to expose the top silicon surface to form silicon-on-insulator, the method further includes: continuing to use the sacrificial layer as a first silicon substrate and providing a second silicon substrate; repeating the above steps on the first silicon substrate and the second silicon substrate until a silicon-on-insulator substrate is formed again.
[0015] Optionally, after the step of removing the sacrificial layer and part of the insulating oxide layer to expose the surface of the top silicon layer, the method further includes: using a wet etching process to remove the insulating oxide layer of the sidewall of the top silicon layer to expose the surface of the sidewall of the top silicon layer, forming an insulating oxide layer located on the bottom surface of the top silicon layer.
[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0017] This invention removes the sacrificial layer within the first silicon substrate using an etching and stripping process, breaking the Si-Si bonds within the first silicon substrate and transforming interatomic forces into smaller van der Waals forces. This separates the sacrificial layer from the top silicon layer, simplifying the separation process. Compared to existing technologies that use high-temperature annealing for separation, this invention effectively reduces manufacturing costs. Furthermore, this invention can also remove the sacrificial layer within the first silicon substrate using a liquid-phase stripping process, achieving separation between the sacrificial layer and the top silicon layer solely through the surface tension of the solution, further simplifying the separation process and reducing manufacturing costs. In addition, this invention forms the sacrificial layer through ion implantation, allowing for precise control of the top silicon layer thickness during subsequent separation processes and ensuring the uniformity of the top silicon surface.
[0018] Furthermore, this invention uses nitrogen ions for ion implantation, which effectively reduces preparation costs compared to the prior art's use of hydrogen ions for ion implantation.
[0019] Furthermore, the present invention performs annealing treatment on the first silicon substrate after ion implantation, which enables the implanted ions to better combine with the first silicon substrate at high temperature and exist in the form of a compound, rather than existing independently in the form of two ions.
[0020] Furthermore, this invention reduces process costs by recycling the separated sacrificial layer to form a silicon-on-insulator substrate.
[0021] Furthermore, by pretreating the surfaces of the first and second silicon substrates before bonding, the present invention increases the activity of the surfaces of the first and second silicon substrates, improves permeability, enhances bonding effect, and ensures the performance of semiconductor devices. Attached Figure Description
[0022] Figures 1 to 7 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention. Detailed Implementation
[0023] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0024] With the development of integrated circuits, the requirements for substrates of chips are becoming increasingly stringent. In addition to traditional bulk silicon substrates, many new types of substrates have gradually emerged, such as high-resistivity silicon substrates, SOI substrates, and integrated passive device (IPD) substrates. Among them, SOI substrates (i.e., silicon-on-insulator substrates) have high resistance, thin top silicon and buried oxide structure, which are very beneficial to radio frequency front-end chips. They have advantages that bulk silicon does not have, such as low radio frequency loss, high isolation and low harmonics.
[0025] Current methods for fabricating silicon-on-insulator substrates (SiS) employ the smart cut method. Specifically, two wafers, A and B, are provided. Wafer A undergoes thermo-oxidation to form a silicon oxide layer, i.e., an insulating layer. H ions are implanted into the surface of wafer A at a certain depth. After bonding wafers A and B, a high-temperature annealing process is performed. The depth of H ion implantation in wafer A is then stripped, separating the H-implanted portion of the wafer from the bonded wafers. Therefore, by adjusting the H implantation depth, precise control of the top silicon thickness layer can be achieved.
[0026] However, in the above scheme, the use of high-temperature annealing to separate the H-ion-implanted wafer from the two bonded wafers increases the preparation cost, and the use of H-ions for ion implantation further increases the preparation cost.
[0027] Currently, to reduce manufacturing costs, the top silicon layer is typically thinned after bonding two wafers using direct mechanical polishing (CMP) to fabricate SOI wafers. This process is simple in principle and avoids the patent issues associated with smart cups. However, CMP cannot guarantee the uniformity of the SOI substrate surface, and the thickness of the top silicon layer varies significantly between different wafers, negatively impacting the performance uniformity of subsequent devices.
[0028] To address the aforementioned technical problems, this invention provides a method for forming a semiconductor structure. The method employs an etching and stripping process to remove the sacrificial layer within a first silicon substrate, breaking the Si-Si bonds within the first silicon substrate and transforming interatomic forces into smaller van der Waals forces. This separates the sacrificial layer from the top silicon layer, simplifying the separation process. Compared to existing techniques that use high-temperature annealing for separation, this invention effectively reduces manufacturing costs. Furthermore, this invention can also remove the sacrificial layer within the first silicon substrate using a liquid-phase stripping process, achieving separation between the sacrificial layer and the top silicon layer solely through the surface tension of the solution, further simplifying the separation process and reducing manufacturing costs. In addition, this invention forms the sacrificial layer through ion implantation, allowing for precise control of the top silicon thickness during subsequent separation processes and ensuring the uniformity of the top silicon surface.
[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0030] Figures 1 to 7This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention.
[0031] Please refer to Figure 1 A first silicon substrate 100 is provided, the first silicon substrate 100 including a first surface b and a second surface a opposite each other.
[0032] In this embodiment, the material of the first silicon substrate 100 is silicon.
[0033] In other embodiments, the material of the first silicon substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0034] In one embodiment of the present invention, the thickness of the first silicon substrate 100 ranges from 200 micrometers to 1000 micrometers.
[0035] Please refer to Figure 2 The first silicon substrate 100 is subjected to thermal oxidation treatment to form an insulating oxide layer 101.
[0036] In one embodiment of the present invention, the process parameters of the thermal oxidation treatment are: oxidation temperature of 900 degrees Celsius to 1200 degrees Celsius, oxygen gas, and gas flow rate of 1 L / min.
[0037] In this embodiment, the insulating oxide layer 101 is formed on all surfaces of the first silicon substrate 100, including the upper surface, the lower surface, and the sidewall surface.
[0038] In other embodiments, the process for forming the insulating oxide layer is: APCVD, UHVCVD, LPCVD, RTCVD or PECVD.
[0039] In one embodiment, the thickness of the insulating oxide layer 101 ranges from 10 nanometers to 500 nanometers.
[0040] Please refer to Figure 3 Ions are implanted into the first surface b of the first silicon substrate 100 to form a sacrificial layer 102.
[0041] In one embodiment of the present invention, the process parameters for implanting ions into the first surface b of the first silicon substrate 100 are as follows: the implantation energy range is 10MeV to 10KeV, and the implanted ions are nitrogen ions, helium ions, or argon ions.
[0042] In one embodiment, the thickness of the sacrificial layer 102 ranges from 50 nanometers to 50 micrometers.
[0043] In this embodiment, the first surface b is the lower surface of the first silicon substrate 100. During the process of injecting ions into the first surface b of the first silicon substrate 100, due to the effect of gravity, the injected ions will be uniformly formed on the lower surface of the first silicon substrate 100, thereby ensuring the purity of the top silicon 105 and the flatness of the surface of the top silicon 105.
[0044] In the above scheme, the present invention uses nitrogen ions for ion implantation, which can effectively reduce the preparation cost compared with the prior art which uses hydrogen ions for ion implantation.
[0045] Furthermore, the present invention forms a sacrificial layer 102 through ion implantation, which allows for precise control of the thickness of the top silicon layer 105 during subsequent separation processes, and ensures the uniformity of the surface of the top silicon layer 105.
[0046] Please refer to Figure 4 The first silicon substrate 100 is annealed to form a first sacrificial layer 103 on the surface of the first silicon substrate 100.
[0047] Specifically, the material of the first sacrificial layer 103 is SiNx.
[0048] In one embodiment of the present invention, the process parameters of the annealing treatment include: an annealing temperature of 800°C to 2000°C, an annealing time of 15 minutes to 12 hours, and an annealing atmosphere of nitrogen, hydrogen, or argon.
[0049] In this embodiment, the first silicon substrate 100 is annealed after ion implantation, which enables the implanted ions to better combine with the first silicon substrate 100 at high temperature and exist in the form of a compound, rather than existing independently as two ions.
[0050] Please refer to Figure 5 A second silicon substrate 104 is provided; the second surface a of the first silicon substrate 100 is bonded to the second silicon substrate 104.
[0051] In this embodiment, the material of the second silicon substrate 104 is silicon.
[0052] In other embodiments, the material of the second silicon substrate 104 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0053] In one embodiment of the present invention, the thickness of the second silicon substrate 104 ranges from 200 micrometers to 1000 micrometers.
[0054] In one embodiment of the present invention, before the step of bonding the first silicon substrate 100 and the second silicon substrate 104, the method further includes: pre-treating the surfaces of the first silicon substrate 100 and the second silicon substrate 104.
[0055] In one embodiment of the present invention, the pretreatment is a hydrophilic treatment. Specifically, after the hydrophilic treatment, the hydroxyl groups adsorbed on the wafer surface will combine with the dangling bonds on other wafer surfaces. These groups will adsorb water molecules on the wafer surface to form corner water groups. When the distance between two hydrophilically treated wafers is close to the range of action of the dipole moment present in the corner water groups, the two wafers will come into contact with each other and bond together under the action of van der Waals forces.
[0056] The hydrophilic treatment process is as follows: soaking in a mixture of NH4OH:H2O2:H2O (1:1:10) at 55°C for 3 minutes.
[0057] In other embodiments, the pretreatment is a dry pretreatment, specifically a plasma pretreatment, implemented in a closed cavity using vacuum plasma technology or atmospheric pressure plasma technology; the pretreatment is a wet pretreatment, specifically, implemented by spraying chemical reagents or deionized water above the rotating wafer surface using a mechanical device that moves back and forth.
[0058] In the above scheme, the present invention pre-treats the surfaces of the first silicon substrate 100 and the second silicon substrate 104 before bonding, thereby increasing the activity of the surfaces of the first silicon substrate 100 and the second silicon substrate 104, improving permeability, improving bonding effect, and ensuring the performance of semiconductor devices.
[0059] Please refer to Figure 6 The first sacrificial layer 103 is removed by an etching or liquid phase stripping process to form a top silicon layer 105. The top silicon layer 105, the insulating oxide layer 101, and the second silicon substrate 104 constitute a silicon-on-insulator substrate 106.
[0060] In one embodiment of the present invention, the process parameters of the corrosion stripping process are as follows: the reaction solution is a phosphoric acid solution, nitric acid or hydrofluoric acid, the concentration of the reaction solution is 20% to 98%, and the reaction temperature is above 160°C.
[0061] In one embodiment of the present invention, the process parameters of the liquid phase stripping process are: the reaction solution is water, isopropanol or N-methylpyrrolidone.
[0062] In one embodiment of the present invention, the thickness of the top silicon 105 ranges from 10 nanometers to 500 nanometers.
[0063] Specifically, the liquid-phase exfoliation process is as follows: The cavitation effect and shear force generated by ultrasound disrupt the van der Waals forces between material layers, thereby achieving material exfoliation. The power and time of the ultrasonic treatment need to be precisely controlled to avoid excessive exfoliation and material damage. After ultrasonic treatment, the exfoliated sacrificial layer material is separated by centrifugation. Centrifugation helps remove unexfoliated lumps and excess solvent, obtaining a relatively pure sacrificial layer material suspension. The supernatant after centrifugation is collected, and the solvent is removed through a drying process to obtain powder or film of the sacrificial layer material.
[0064] In other embodiments, after the step of removing the first sacrificial layer and a portion of the insulating oxide layer to expose the top silicon surface to form a silicon-on-insulator substrate, the method further includes: continuing to use the first sacrificial layer as a first silicon substrate and providing a second silicon substrate; repeating the above steps on the first silicon substrate and the second silicon substrate until a silicon-on-insulator substrate is formed again.
[0065] In a specific embodiment, the first sacrificial layer is used as a first silicon substrate; the first silicon substrate is subjected to thermal oxidation to form an insulating oxide layer; ions are implanted into the first surface of the first silicon substrate to form a sacrificial layer; the first silicon substrate is subjected to annealing to form a first sacrificial layer located on the surface of the first silicon substrate; a second silicon substrate is provided; the second surface of the first silicon substrate is bonded to the second silicon substrate; the first sacrificial layer is removed using an etching process or a liquid phase stripping process to form a top silicon layer, wherein the top silicon layer, the insulating oxide layer, and the second silicon substrate constitute a silicon-on-insulator substrate; the insulating oxide layer on the sidewalls of the top silicon layer is removed using a wet etching process to expose the surface of the sidewalls of the top silicon layer, forming an insulating oxide layer located on the bottom surface of the top silicon layer.
[0066] In the above scheme, the present invention reduces the process cost by recycling the separated first sacrificial layer 102 to form a silicon-on-insulator substrate 106.
[0067] Please refer to Figure 7 The insulating oxide layer 101 on the sidewall of the top silicon 105 is removed by a wet etching process until the surface of the sidewall of the top silicon 105 is exposed, forming an insulating oxide layer 101 on the bottom surface of the top silicon 105.
[0068] In this embodiment, the parameters of the wet etching process are as follows: the etching solution includes one or more combinations of hydrofluoric acid solution, ammonia solution and water, the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius, and the reaction time is 3 minutes to 4 minutes.
[0069] In other embodiments of the present invention, since the top silicon 105 is thin, the insulating oxide layer 101 on the sidewall of the top silicon 105 can be ignored.
[0070] In summary, this invention removes the sacrificial layer 102 within the first silicon substrate 100 through an etching and stripping process, breaking the Si-Si bonds within the first silicon substrate 100 and transforming interatomic forces into smaller van der Waals forces. This separates the sacrificial layer 102 from the top silicon 105, simplifying the separation process between the sacrificial layer 102 and the top silicon 105. Compared to the existing technology that uses high-temperature annealing for separation, this invention effectively reduces manufacturing costs. Furthermore, this invention can also remove the sacrificial layer 102 within the first silicon substrate 100 through a liquid-phase stripping process, achieving separation between the sacrificial layer 102 and the top silicon 105 through the surface tension of the solution, further simplifying the separation process and reducing manufacturing costs. In addition, this invention forms the sacrificial layer 102 through ion implantation, allowing for precise control of the thickness of the top silicon 105 during subsequent separation processes and ensuring the uniformity of the top silicon 105 surface.
[0071] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A first silicon substrate and a second silicon substrate are provided, wherein the first silicon substrate includes opposing first and second surfaces; The first silicon substrate is subjected to thermal oxidation to form an insulating oxide layer, which is located on the second surface of the first silicon substrate. Ions are implanted into the first surface of the first silicon substrate to form a sacrificial layer; The second surface of the first silicon substrate is bonded to the second silicon substrate; The sacrificial layer is removed by an etching or liquid-phase stripping process to form a top silicon layer. The top silicon layer, the insulating oxide layer, and the second silicon substrate constitute a silicon-on-insulator substrate.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for the corrosion stripping process are as follows: the reaction solution is phosphoric acid solution, nitric acid or hydrofluoric acid, the concentration of the reaction solution is 20% to 98%, and the reaction temperature is above 160°C.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for the liquid phase stripping process are as follows: the reaction solution is water, isopropanol, or N-methylpyrrolidone.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for implanting ions onto the first surface of the first silicon substrate are as follows: the implantation energy range is 10MeV to 10KeV, and the implanted ions are nitrogen ions, helium ions, or argon ions.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The thickness of the sacrificial layer ranges from 50 nanometers to 50 micrometers, and the thickness of the top silicon layer ranges from 10 nanometers to 500 nanometers.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, Following the step of implanting ions onto the first surface of the first silicon substrate, the method further includes: The first silicon substrate is annealed to form a first sacrificial layer on the surface of the first silicon substrate.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, After the step of bonding the first silicon substrate and the second silicon substrate, the method further includes: The first sacrificial layer is removed by an etching stripping process or a liquid phase stripping process.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Before the step of bonding the first silicon substrate and the second silicon substrate, the method further includes: The surfaces of the first silicon substrate and the second silicon substrate are pretreated.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the step of removing the sacrificial layer and a portion of the insulating oxide layer to expose the top silicon surface to form silicon-on-insulator, the method further includes: The sacrificial layer continues to serve as the first silicon substrate, and a second silicon substrate is provided; The above steps are repeated on the first silicon substrate and the second silicon substrate until a silicon-on-insulator substrate is formed again.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the step of removing the sacrificial layer and part of the insulating oxide layer to expose the top silicon surface, the method further includes: A wet etching process is used to remove the insulating oxide layer on the sidewall of the top silicon layer until the surface of the sidewall of the top silicon layer is exposed, forming an insulating oxide layer on the bottom surface of the top silicon layer.