Method of forming a semiconductor structure
By forming a multilayer structure on a silicon substrate and performing thermal oxidation, ion implantation, and bonding processes, the problem of low efficiency in silicon substrate fabrication on insulators has been solved, enabling efficient and low-cost semiconductor processes and the fabrication of diverse substrates.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SEMICON MFG INT (BEIJING) CORP
- Filing Date
- 2025-01-20
- Publication Date
- 2026-07-24
AI Technical Summary
The current technology has low fabrication efficiency for silicon-on-insulator substrates, which makes it difficult to meet the requirements of integrated circuits for high-efficiency fabrication.
By forming two top silicon layers and two insulating oxide layers on a first silicon substrate, and using thermal oxidation, ion implantation, bonding and stripping processes, two silicon-on-insulator substrates are formed, enabling the fabrication of multiple substrates in a single process.
It improves the efficiency of semiconductor manufacturing processes, reduces process costs, and increases the flexibility of semiconductor structures and the diversity of wafer types by precisely controlling the thickness and uniformity of the top silicon layer through ion implantation.
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Figure CN122458765A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Technology
[0002] The structure of a silicon-on-insulator (SOI) substrate is as follows: there is an ultra-thin insulating layer, such as SiO2, on the silicon wafer. On top of the insulating layer is another thin silicon layer. This structure separates the active silicon layer from the substrate silicon layer, which can reduce the parasitic capacitance between the two by half.
[0003] With the development of integrated circuits, the requirements for substrates of chips are becoming increasingly stringent. In addition to traditional bulk silicon substrates, many new types of substrates have gradually emerged, such as high-resistivity silicon substrates, SOI substrates, and integrated passive device (IPD) substrates. Among them, SOI substrates (i.e., silicon-on-insulator substrates) have high resistance, thin top silicon and buried oxide structure, which are very beneficial to radio frequency front-end chips. They have advantages that bulk silicon does not have, such as low radio frequency loss, high isolation and low harmonics.
[0004] However, the current fabrication efficiency of silicon-on-insulator substrates is relatively low. Summary of the Invention
[0005] The technical problem solved by this invention is how to improve the fabrication efficiency of silicon-on-insulator substrates.
[0006] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a first silicon substrate, a second silicon substrate, and a third silicon substrate, wherein the first silicon substrate includes opposing first and second surfaces; performing thermal oxidation on the first silicon substrate to form a first insulating oxide layer on the first surface of the first silicon substrate and a second insulating oxide layer on the second surface of the first silicon substrate; implanting ions into the first and second surfaces of the first silicon substrate to form a first top silicon layer, a second top silicon layer, and a sacrificial layer located between the first top silicon layer and the second top silicon layer; using a first bonding process to bond the first surface of the first silicon substrate to the second silicon substrate; using a second bonding process to bond the second surface of the first silicon substrate to the third silicon substrate; and using a stripping process to remove the sacrificial layer to expose the first top silicon surface and the second top silicon surface, wherein the first top silicon layer, the first insulating oxide layer, and the second silicon substrate constitute a first silicon-on-insulator (SiI) substrate, and the second top silicon layer, the second insulating oxide layer, and the third silicon substrate constitute a second SiI substrate.
[0007] Optionally, the material of the second silicon substrate includes silicon or germanium, and the material of the third silicon substrate includes silicon or germanium.
[0008] Optionally, the first bonding process and the second bonding process are hydrophilic bonding processes, and the process parameters of the hydrophilic bonding process include: the bonding solution is a hydrophilic group containing hydroxyl groups.
[0009] Optionally, the peeling process includes high-temperature heating peeling.
[0010] Optionally, the process parameters for implanting ions onto the first surface of the first silicon substrate are: an implantation energy range of 0.2 keV to 2000 keV, and implanted ions are nitrogen ions, hydrogen ions, or helium ions; the process parameters for implanting ions onto the second surface of the first silicon substrate are: an implantation energy range of 0.2 keV to 2000 keV, and implanted ions are nitrogen ions, hydrogen ions, or helium ions.
[0011] Optionally, the thickness of the first top silicon layer ranges from 10 nanometers to 500 nanometers, and the thickness of the second top silicon layer ranges from 10 nanometers to 500 nanometers.
[0012] Optionally, the process parameters for forming the first insulating oxide layer include: an oxidation temperature range of 500°C to 2000°C, an oxidation time range of 10 seconds to 24 hours, and an oxidation atmosphere of O2, H2O, or HCl; the process parameters for forming the second insulating oxide layer include: an oxidation temperature range of 500°C to 2000°C, an oxidation time range of 10 seconds to 24 hours, and an oxidation atmosphere of O2, H2O, or HCl.
[0013] Optionally, the thickness of the first insulating oxide layer ranges from 10 nanometers to 500 nanometers, and the thickness of the second insulating oxide layer ranges from 10 nanometers to 500 nanometers.
[0014] Optionally, after removing the sacrificial layer to expose the first top silicon surface and the second top silicon surface, the method further includes: continuing to use the sacrificial layer as a first silicon substrate, and providing a second silicon substrate and a third silicon substrate; repeating the above steps on the first silicon substrate, the second silicon substrate and the third silicon substrate until the first silicon-on-insulator substrate and the second silicon-on-insulator substrate are formed again.
[0015] Optionally, after the step of removing the sacrificial layer to expose the first top silicon surface and the second top silicon surface, the method further includes: using a wet etching process to remove the first insulating oxide layer of the first top silicon sidewall and the second insulating oxide layer of the second top silicon sidewall to expose the first top silicon sidewall surface and the first top silicon sidewall surface.
[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0017] In this invention, a first insulating oxide layer is formed on the first surface of the first silicon substrate by thermal oxidation, and a second insulating oxide layer is formed on the second surface of the first silicon substrate. Ions are implanted into the first and second surfaces of the first silicon substrate to form a first top silicon layer and a second top silicon layer. The first top silicon layer, the first insulating oxide layer, and the second silicon substrate constitute a first silicon-on-insulator (SiI) substrate, and the second top silicon layer, the second insulating oxide layer, and the third silicon substrate constitute a second SiI substrate. This allows two SiI substrates to be formed in a single thermal oxidation, ion implantation, and bonding process, improving the efficiency of semiconductor manufacturing and reducing manufacturing costs. Furthermore, the ion implantation process used in this invention to form the top silicon layer allows for precise control of the top silicon layer thickness and ensures the uniformity of the top silicon surface.
[0018] Furthermore, the technical solution of the present invention can adjust the process parameters of the thermal oxidation process to make the thickness of the insulating oxide layer on the first surface and the second surface different, thereby obtaining insulating oxide layers of different thicknesses after one thermal oxidation process, which increases the flexibility of forming semiconductor structures.
[0019] Furthermore, the present invention can adjust the process parameters of ion implantation to make the thicknesses of the first top silicon layer and the second top silicon layer different, thereby achieving top silicon layers of different thicknesses after one ion implantation process, which increases the flexibility of forming semiconductor structures.
[0020] Furthermore, the present invention uses nitrogen ions for ion implantation, which can effectively reduce the preparation cost.
[0021] Furthermore, the second silicon substrate and the third silicon substrate are made of different materials, which increases the diversity of wafer types.
[0022] Furthermore, this invention reduces process costs by recycling the separated sacrificial layer to form a silicon-on-insulator substrate. Attached Figure Description
[0023] Figures 1 to 7 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention. Detailed Implementation
[0024] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0025] With the development of integrated circuits, the requirements for substrates of chips are becoming increasingly stringent. In addition to traditional bulk silicon substrates, many new types of substrates have gradually emerged, such as high-resistivity silicon substrates, SOI substrates, and integrated passive device (IPD) substrates. Among them, SOI substrates (i.e., silicon-on-insulator substrates) have high resistance, thin top silicon and buried oxide structure, which are very beneficial to radio frequency front-end chips. They have advantages that bulk silicon does not have, such as low radio frequency loss, high isolation and low harmonics.
[0026] Currently, the preparation method of silicon-on-insulator substrates (SiS) employs the smart cut method, which involves providing two wafers, namely wafer A and wafer B. Wafer A is thermo-oxidized to form a silicon oxide layer, i.e., an insulating layer. Hydrogen (H) elements are implanted into the surface of wafer A at a certain depth. After bonding wafers A and B, high-temperature annealing is performed, and the depth of H implantation in wafer A is stripped, allowing the portion of the wafer with H implantation to be separated from the two bonded wafers. Therefore, by adjusting the H implantation depth, precise control of the top silicon thickness layer can be achieved.
[0027] However, the above method can only bond two wafers at a time, meaning it can only fabricate one silicon-on-insulator substrate at a time, so there is still room for improvement in fabrication efficiency.
[0028] To address the aforementioned technical problems, this invention provides a method for forming a semiconductor structure. By forming two top silicon layers and two insulating oxide layers in a first silicon substrate, wherein the first top silicon layer, the first insulating oxide layer, and the second silicon substrate constitute a first silicon-on-insulator (SiI) substrate, and the second top silicon layer, the second insulating oxide layer, and the third silicon substrate constitute a second SiI substrate, this method achieves the formation of two SiI substrates in a single thermal oxidation process, ion implantation, and bonding process. This improves the efficiency of the semiconductor manufacturing process and reduces manufacturing costs. Furthermore, this invention forms the top silicon layer through ion implantation, enabling precise control of the top silicon layer thickness and ensuring the uniformity of the top silicon surface.
[0029] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0030] Figures 1 to 7 This is a schematic diagram of the formation process of a semiconductor structure in one embodiment of the present invention.
[0031] Please refer to Figure 1 A first silicon substrate 100 is provided, the first silicon substrate 100 including a first surface a and a second surface b opposite to each other.
[0032] In this embodiment, the material of the first silicon substrate 100 is silicon.
[0033] In other embodiments, the material of the first silicon substrate 100 may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.
[0034] In one embodiment of the present invention, the thickness of the first silicon substrate 100 ranges from 200 micrometers to 1000 micrometers.
[0035] Please refer to Figure 2 The first silicon substrate 100 is subjected to thermal oxidation treatment to form an initial insulating oxide layer 101.
[0036] In one embodiment of the present invention, the process parameters for forming the initial insulating oxide layer 101 of the first surface a are: oxidation temperature range of 500°C to 2000°C, oxidation time range of 10 seconds to 24 hours, and oxidation atmosphere of O2, H2O or HCl.
[0037] In one embodiment of the present invention, the process parameters for forming the initial insulating oxide layer 101 of the second surface b are: oxidation temperature range of 500°C to 2000°C, oxidation time range of 10 seconds to 24 hours, and oxidation atmosphere of O2, H2O or HCl.
[0038] In this embodiment, the initial insulating oxide layer 101 is formed on all surfaces of the first silicon substrate 100, including the upper surface, the lower surface, and the sidewall surface.
[0039] In other embodiments, the process for forming the insulating oxide layer is: APCVD, UHVCVD, LPCVD, RTCVD or PECVD.
[0040] In one embodiment, the thickness of the initial insulating oxide layer 101 on the first surface a formed using the above-described thermal oxidation process parameters ranges from 10 nanometers to 500 nanometers, and the thickness of the initial insulating oxide layer 101 on the second surface b ranges from 10 nanometers to 500 nanometers.
[0041] This invention enables the insulation oxide layer on the first surface a and the second surface b to have different thicknesses by adjusting the process parameters of the thermal oxidation process, thereby obtaining insulation oxide layers of different thicknesses after a single thermal oxidation process, which increases the flexibility of forming semiconductor structures.
[0042] Please refer to Figure 3 Ions are implanted into the first surface a and the second surface b of the first silicon substrate 100 to form a first top silicon layer 102, a second top silicon layer 103, and a sacrificial layer 1001 located between the first top silicon layer 102 and the second top silicon layer 103.
[0043] In one embodiment of the present invention, the process parameters for implanting ions into the first surface a of the first silicon substrate 100 are: implantation energy range of 0.2 keV to 2000 keV; implanted ions are nitrogen ions, hydrogen ions, or helium ions; the process parameters for implanting ions into the second surface b of the first silicon substrate 100 are: implantation energy range of 0.2 keV to 2000 keV; implanted ions are nitrogen ions, hydrogen ions, or helium ions.
[0044] This invention uses nitrogen ions for ion implantation, which can effectively reduce preparation costs.
[0045] In one embodiment, the thickness of the first top silicon 102 formed using the above-described ion implantation process parameters ranges from 10 nanometers to 500 nanometers, the thickness of the second top silicon 103 ranges from 10 nanometers to 500 nanometers, and the thickness of the sacrificial layer 1001 ranges from 50 nanometers to 50 micrometers.
[0046] In this embodiment, the wafer is rotated so that the first surface a of the first silicon substrate 100 becomes the lower surface of the first silicon substrate 100. Ions are then implanted into the first surface a of the first silicon substrate 100. Due to gravity, the implanted ions will be uniformly formed on the lower surface of the first silicon substrate 100, thereby ensuring the purity of the first top silicon 102 and the flatness of the surface of the first top silicon 102. The wafer is rotated so that the second surface b of the first silicon substrate 100 becomes the lower surface of the first silicon substrate 100. Ions are then implanted into the second surface b of the first silicon substrate 100. Due to gravity, the implanted ions will be uniformly formed on the lower surface of the first silicon substrate 100, thereby ensuring the purity of the second top silicon 103 and the flatness of the surface of the second top silicon 103.
[0047] This invention forms a first top silicon layer 102 and a second top silicon layer 103 through ion implantation, which can precisely control the thickness of the top silicon layer and ensure the uniformity of the top silicon layer surface. Furthermore, this invention can adjust the ion implantation process parameters to make the thickness of the first top silicon layer 102 and the second top silicon layer 103 different, thereby obtaining top silicon layers of different thicknesses after a single ion implantation process, increasing the flexibility of semiconductor structure formation.
[0048] Please refer to Figure 4 The system provides a second silicon substrate 104 and a third silicon substrate 105; a first bonding process is used to bond the first surface a of the first silicon substrate 100 to the second silicon substrate 104; and a second bonding process is used to bond the second surface b of the first silicon substrate 100 to the third silicon substrate 105.
[0049] In some embodiments of the present invention, the material of the second silicon substrate 104 includes silicon or germanium, and the material of the third silicon substrate 105 includes silicon or germanium.
[0050] The second silicon substrate 104 and the third silicon substrate 105 are made of different materials. For example, the second silicon substrate 104 is Si and the third silicon substrate 105 is Ge, thereby enabling the simultaneous fabrication of SOI and SOG wafers and increasing the diversity of wafer types.
[0051] In some embodiments of the present invention, the first bonding process and the second bonding process are hydrophilic bonding processes, and the process parameters of the hydrophilic bonding process include: the bonding solution is a hydrophilic group containing hydroxyl groups.
[0052] In a specific embodiment, the hydrophilic bonding process is as follows: when two wafer surfaces with hydroxyl-containing hydrophilic groups come into contact, they will immediately bond together due to the effect of hydrogen bonds. Subsequently, through a high-temperature annealing step, the weak intermolecular forces (such as van der Waals forces and hydrogen bonds) between the interfaces will be transformed into stronger Si-O-Si covalent bonds, thereby obtaining a strong bonding interface.
[0053] In one embodiment of the present invention, the thickness of the second silicon substrate 104 and the third silicon substrate 105 ranges from 200 micrometers to 1000 micrometers.
[0054] In one embodiment of the present invention, before the steps of bonding the first silicon substrate 100 and the second silicon substrate 104 and bonding the first silicon substrate 100 and the third silicon substrate 105, the method further includes: pre-treating the surfaces of the first silicon substrate 100, the second silicon substrate 104 and the third silicon substrate 105.
[0055] In one embodiment of the present invention, the pretreatment is a hydrophilic treatment. Specifically, after the hydrophilic treatment, the hydroxyl groups adsorbed on the wafer surface will combine with the dangling bonds on other wafer surfaces. These groups will adsorb water molecules on the wafer surface to form corner water groups. When the distance between two hydrophilically treated wafers is close to the range of action of the dipole moment present in the corner water groups, the two wafers will come into contact with each other and bond together under the action of van der Waals forces.
[0056] The hydrophilic treatment process is as follows: soaking in a mixture of NH4OH:H2O2:H2O (1:1:10) at 55°C for 3 minutes.
[0057] In other embodiments, the pretreatment is a dry pretreatment, specifically a plasma pretreatment, implemented in a closed cavity using vacuum plasma technology or atmospheric pressure plasma technology; the pretreatment is a wet pretreatment, specifically, implemented by spraying chemical reagents or deionized water above the rotating wafer surface using a mechanical device that moves back and forth.
[0058] In the above scheme, the present invention pre-treats the surfaces of the first silicon substrate 100, the second silicon substrate 104, and the third silicon substrate 105 before bonding, thereby increasing the activity of the surfaces of the first silicon substrate 100, the second silicon substrate 104, and the third silicon substrate 105, improving permeability, improving bonding effect, and ensuring the performance of semiconductor devices.
[0059] Please refer to Figure 5 The sacrificial layer 1001 is removed using a stripping process to expose the surfaces of the first top silicon layer 102 and the second top silicon layer 103.
[0060] In some embodiments of the present invention, the peeling process includes high-temperature heating peeling.
[0061] In other embodiments, after removing the sacrificial layer 1001 to expose the surfaces of the first top silicon 102 and the second top silicon 103, the method further includes: continuing to use the sacrificial layer 1001 as the first silicon substrate 100, and providing a second silicon substrate 104 and a third silicon substrate 105; repeating the above steps on the first silicon substrate 100, the second silicon substrate 104 and the third silicon substrate 105 until the first silicon-on-insulator substrate 108 and the second silicon-on-insulator substrate 109 are formed again.
[0062] In a specific embodiment, the sacrificial layer 1001 is used as a first silicon substrate 100; the first silicon substrate 100 is subjected to thermal oxidation to form a first insulating oxide layer 106 on a first surface a and a second insulating oxide layer 107 on a second surface b; ions are implanted into the first surface a and the second surface b of the first silicon substrate 100 to form a first top silicon layer 102, a second top silicon layer 103, and a sacrificial layer 1001 between the first top silicon layer 102 and the second top silicon layer 103; a first bonding process is used to bond the first silicon substrate... The first surface a of the first silicon substrate 100 is bonded to the second silicon substrate 104; using a second bonding process, the second surface b of the first silicon substrate 100 is bonded to the third silicon substrate 105; using a stripping process, the sacrificial layer 1001 is removed to expose the surface of the first top silicon layer 102 and the surface of the second top silicon layer 103. The first top silicon layer 102, the first insulating oxide layer 106, and the second silicon substrate 104 constitute a first silicon-on-insulator substrate 108, and the second top silicon layer 103, the second insulating oxide layer 107, and the third silicon substrate 105 constitute a second silicon-on-insulator substrate 109.
[0063] In the above scheme, the present invention reduces the process cost by recycling the separated sacrificial layer 1001 to form a silicon-on-insulator substrate.
[0064] Please refer to Figure 6 A wet etching process is used to remove the initial insulating oxide layer 101 on the sidewall of the first top silicon 102 until the surface of the sidewall of the first top silicon 102 is exposed, forming a first insulating oxide layer 106 on the first surface a of the first silicon substrate 100.
[0065] In this embodiment, the parameters of the wet etching process are as follows: the etching solution includes one or more combinations of hydrofluoric acid solution, ammonia solution and water, the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius, and the reaction time is 3 minutes to 4 minutes.
[0066] In other embodiments of the present invention, since the first top silicon 102 is relatively thin, the first insulating oxide layer 106 on the sidewall of the first top silicon 102 can be ignored.
[0067] The first top silicon layer 102, the first insulating oxide layer 106, and the second silicon substrate 104 constitute the first silicon-on-insulator substrate 108.
[0068] Please refer to Figure 7A wet etching process is used to remove the initial insulating oxide layer 101 on the sidewall of the second top silicon 103 until the surface of the sidewall of the second top silicon 103 is exposed, forming a second insulating oxide layer 107 on the second surface b of the first silicon substrate 100.
[0069] In this embodiment, the parameters of the wet etching process are as follows: the etching solution includes one or more combinations of hydrofluoric acid solution, ammonia solution and water, the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius, and the reaction time is 3 minutes to 4 minutes.
[0070] In other embodiments of the present invention, since the second top silicon 103 is thin, the second insulating oxide layer 107 on the sidewall of the second top silicon 103 can be ignored.
[0071] The second top silicon layer 103, the second insulating oxide layer 107, and the third silicon substrate 105 constitute the second silicon-on-insulator substrate 109.
[0072] In summary, by performing thermal oxidation on the first silicon substrate to form a first insulating oxide layer on the first surface and a second insulating oxide layer on the second surface, and then implanting ions into the first and second surfaces of the first silicon substrate respectively, a first top silicon layer and a second top silicon layer are formed. The first top silicon layer, the first insulating oxide layer, and the second silicon substrate constitute a first silicon-on-insulator (SiI) substrate, and the second top silicon layer, the second insulating oxide layer, and the third silicon substrate constitute a second SiI substrate. This allows for the formation of two SiI substrates in a single thermal oxidation, ion implantation, and bonding process, improving the efficiency of semiconductor manufacturing and reducing process costs. Furthermore, the ion implantation process used in this invention to form the top silicon layer allows for precise control of the top silicon layer thickness and ensures the uniformity of the top silicon surface.
[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A first silicon substrate, a second silicon substrate, and a third silicon substrate are provided, wherein the first silicon substrate includes opposing first and second surfaces; The first silicon substrate is subjected to thermal oxidation treatment to form a first insulating oxide layer on the first surface of the first silicon substrate and a second insulating oxide layer on the second surface of the first silicon substrate. Ions are implanted into the first and second surfaces of the first silicon substrate to form a first top silicon layer, a second top silicon layer, and a sacrificial layer located between the first top silicon layer and the second top silicon layer; A first bonding process is used to bond the first surface of the first silicon substrate to the second silicon substrate; A second bonding process is used to bond the second surface of the first silicon substrate to the third silicon substrate; A stripping process is used to remove the sacrificial layer until the first top silicon surface and the second top silicon surface are exposed. The first top silicon, the first insulating oxide layer and the second silicon substrate constitute a first silicon-on-insulator substrate, and the second top silicon, the second insulating oxide layer and the third silicon substrate constitute a second silicon-on-insulator substrate.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the second silicon substrate includes silicon or germanium, and the material of the third silicon substrate includes silicon or germanium.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first bonding process and the second bonding process are hydrophilic bonding processes. The process parameters of the hydrophilic bonding process include: the bonding solution is a hydrophilic group containing hydroxyl groups and water.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The peeling process includes high-temperature heating peeling.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for implanting ions onto the first surface of the first silicon substrate are: implantation energy range of 0.2 keV to 2000 keV, and implanted ions are nitrogen ions, hydrogen ions, or helium ions; the process parameters for implanting ions onto the second surface of the first silicon substrate are: implantation energy range of 0.2 keV to 2000 keV, and implanted ions are nitrogen ions, hydrogen ions, or helium ions.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The thickness of the first top silicon layer ranges from 5 nanometers to 5 micrometers, and the thickness of the second top silicon layer ranges from 5 nanometers to 1 micrometer.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process parameters for forming the first insulating oxide layer include: an oxidation temperature range of 500°C to 2000°C, an oxidation time range of 10 seconds to 24 hours, and an oxidation atmosphere of O2, H2O, or HCl; the process parameters for forming the second insulating oxide layer include: an oxidation temperature range of 500°C to 2000°C, an oxidation time range of 10 seconds to 24 hours, and an oxidation atmosphere of O2, H2O, or HCl.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The thickness of the first insulating oxide layer ranges from 10 nanometers to 500 nanometers, and the thickness of the second insulating oxide layer ranges from 10 nanometers to 500 nanometers.
9. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the step of removing the sacrificial layer to expose the first top silicon surface and the second top silicon surface, the method further includes: The sacrificial layer continues to serve as the first silicon substrate, and a second silicon substrate and a third silicon substrate are provided; The above steps are repeated on the first silicon substrate, the second silicon substrate, and the third silicon substrate until the first silicon-on-insulator substrate and the second silicon-on-insulator substrate are formed again.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, After the step of removing the sacrificial layer to expose the first top silicon surface and the second top silicon surface, the method further includes: A wet etching process is used to remove the first insulating oxide layer of the first top silicon sidewall and the second insulating oxide layer of the second top silicon sidewall until the surface of the first top silicon sidewall and the surface of the first top silicon sidewall are exposed.