Control program compiling method, electronic device, and storage medium

Abstract

The application relates to the technical field of industrial automation control, in particular to a control program compiling method, an electronic device and a storage medium. According to the control program compiling method, a ladder program to be compiled is acquired first; the ladder program contains multiple types of element representation graphs; a structural analysis is performed on the logical connection relationship between the element representation graphs in the ladder program, so that tree program structure data is obtained; a program instruction mapping operation is performed based on the tree program structure data, so that multiple program assembly codes corresponding to the tree program structure data are obtained; and the multiple program assembly codes are translated and interpreted, so that a binary executable program is obtained. In this way, the operation efficiency, real-time performance and compilation process can be improved in the process of industrial automation control.

Description

Technical Field

[0001] This application relates to the field of industrial automation control technology, and in particular to a control program compilation method, electronic device, and storage medium. Background Technology

[0002] Programmable Logic Controllers (PLCs), as the core control units of industrial automation control systems, execute logic operations and sequential control instructions through programmable memory, controlling machinery or production processes via digital or analog input / output interfaces. Among the various programming languages ​​supported by industrial control programming platforms, ladder diagrams are a classic programming language in the field of industrial control. However, in practical applications, when the control logic involves multiple nested layers, complex conditional judgments, or loops, the connections in ladder diagrams become lengthy and difficult to trace. This is especially true in scenarios implementing PID algorithms or matrix operations, significantly reducing readability and increasing the difficulty of troubleshooting.

[0003] Furthermore, current large-scale models on the market struggle to automate ladder diagram programming, only generating text-based ladder diagrams. These text-based diagrams are not only difficult to read but also cannot be directly imported into industrial control programming platforms for compilation and debugging. Engineers still need to manually copy and rebuild them, failing to truly reduce programming workload. Therefore, improving operational efficiency, real-time performance, and streamlining the compilation process in industrial automation control has become a pressing issue in the industry. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a control program compilation method, electronic device, and storage medium, which can improve operating efficiency, real-time performance, and simplify the compilation process in the process of industrial automation control.

[0005] The control program compilation method according to the first aspect of this application includes: Obtain the ladder diagram program to be compiled; wherein the ladder diagram program contains various types of component representation graphics; The logical connection relationships between the component representation graphics in the ladder diagram program are structured and parsed to obtain tree-shaped program structure data; Based on the tree-shaped program structure data, a program instruction mapping operation is performed to obtain multiple program assembly codes corresponding to the tree-shaped program structure data; The assembly code of the multiple programs is decoded to obtain a binary executable program.

[0006] In some embodiments of this application, the step of performing structured parsing of the logical connection relationships between the component representation graphics in the ladder diagram program to obtain tree-shaped program structure data includes: The component representation graphics in the ladder diagram program are identified to obtain various types of component unit objects and the component arrangement characteristics of each component representation graphic in the ladder diagram program; Based on the component arrangement characteristics in the ladder diagram program, the program logic characteristics between each component unit object are determined. Based on the program logic characteristics between each of the component unit objects, the corresponding component unit objects are mapped to the target two-dimensional array; The tree-shaped program structure data is generated based on each element unit object in the target two-dimensional array and the program logic features.

[0007] In some embodiments of this application, determining the program logic features between each of the component unit objects based on the component arrangement features in the ladder diagram program according to the component representation graphics of each of the component units includes: Based on the element arrangement characteristics of each element representation graphic in the ladder diagram program, determine the row connection state, column connection state, graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost column vertical line and the rightmost column vertical line. Based on the row connection state and column connection state of each element representation graphic, the graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost column vertical line and the rightmost column vertical line, the program logic features between each element unit object are determined.

[0008] In some embodiments of this application, determining the program logic features between each element unit object based on the row connection state, column connection state, graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost and rightmost vertical lines includes: When there are rows that do not have vertical lines connecting downwards, it is determined that the corresponding element unit object has the program logic characteristics of a container structure. When there is an output coil or an executable function block, and there is a set of row coordinates to the right of the leftmost column vertical line that is not connected to the next row, it is determined that the corresponding element unit object has the program logic feature of a branch structure. When there are equal-length leftmost and rightmost vertical lines and no other logical elements on both sides, it is determined that the corresponding element unit object has the program logic characteristics of an OR logic structure. When there is a column with only a single horizontal line or a single logical element connected left and right, it is determined that the corresponding element unit object has the program logic characteristics of the logical structure. When only a single logical element is contained, the corresponding element unit object is determined to have the program logic characteristics of a unit structure.

[0009] In some embodiments of this application, generating the tree-shaped program structure data based on each element unit object in the target two-dimensional array and the program logic features includes: In the target two-dimensional array, the program logic features corresponding to each of the component unit objects are sorted out; Based on the program logic features described above, each component unit object is recursively divided into various tree-shaped node data. The tree-shaped program structure data is generated based on the various tree node data.

[0010] In some embodiments of this application, the various tree-shaped node data include container child node data, common condition child node data, branch output child node data, parallel child node data, serial child node data, and unit child node data. The recursive division of each element unit object into various tree-shaped node data based on the program logic features includes: For the program logic features with container structure, the corresponding element unit objects are divided into mutually independent container sub-node data; For the program logic feature with a branch structure, the corresponding component unit object is divided into the common condition sub-node data and multiple branch output sub-node data; For the program logic features with OR logic structure, the corresponding element unit object is divided into multiple parallel sub-node data; For the program logic features with logical structure, the corresponding element unit object is divided into multiple serial sub-node data; For the program logic feature with a unit structure, the corresponding element unit object is determined as the unit sub-node data.

[0011] In some embodiments of this application, the step of performing a program instruction mapping operation based on the tree-shaped program structure data to obtain multiple program assembly codes corresponding to the tree-shaped program structure data includes: For a container structure that contains container child node data in the tree-shaped program structure data, an independent container program segment is generated according to each container child node data. For the branch structure that includes the common condition sub-node data and the branch output sub-node data in the tree program structure data, multiple registers are called as logical scheduling registers, and corresponding condition judgment program segments and condition response program segments are generated based on the cooperation of each logical scheduling register. For the tree-shaped program structure data containing multiple parallel child node data or logical structures, multiple registers are called as logical scheduling registers, and corresponding logical response program segments are generated based on the cooperation of each logical scheduling register. For the logical structure containing multiple serial child node data in the tree program structure data, multiple registers are called as logical scheduling registers, and corresponding logical response program segments are generated based on the cooperation of each logical scheduling register. For the tree-shaped program structure data containing unit sub-node data, corresponding unit function program segments are generated according to the unit type of the unit sub-node data; By integrating the container program segment, the condition determination program segment, the condition response program segment, the OR logic response program segment, the AND logic response program segment, and the unit function program segment, multiple program assembly codes are obtained.

[0012] In some embodiments of this application, the step of deciphering the assembly code of the plurality of programs to obtain a binary executable program includes: Soft component memory access instructions and flow control jump instructions are extracted from multiple program assembly codes; wherein, the flow control jump instructions include the current tag address and the target tag address; The soft device memory access instructions are mapped to actual memory storage addresses according to a preset constant table to update the soft device memory access instructions; wherein, the preset constant table stores a plurality of pre-configured candidate memory storage addresses; Calculate the address offset difference between the current tag address and the target tag address in the flow control jump instruction, and configure the end operand of the flow control jump instruction based on the address offset difference to update the flow control jump instruction; After mapping the soft element memory access instructions to the actual memory storage address and configuring the end operand for the flow control jump instructions, the multiple program assembly codes, the updated soft element memory access instructions, and the updated flow control jump instructions are integrated to obtain the binary executable program.

[0013] Thirdly, embodiments of this application provide an electronic device, including: a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the control program compilation method as described in any one of the embodiments of the first aspect of this application.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing a program that is executed by a processor to implement the control program compilation method as described in any one of the embodiments of the first aspect of this application.

[0015] The control program compilation method, electronic device, and storage medium according to the embodiments of this application have at least the following beneficial effects: The control program compilation method according to the embodiments of this application requires first obtaining the ladder diagram program to be compiled; wherein, the ladder diagram program contains various types of component representation graphics; the logical connection relationships between the component representation graphics in the ladder diagram program are structured and parsed to obtain tree-shaped program structure data; based on the tree-shaped program structure data, a program instruction mapping operation is performed to obtain multiple program assembly codes corresponding to the tree-shaped program structure data; the multiple program assembly codes are decrypted to obtain a binary executable program. In this way, operational efficiency, real-time performance, and the compilation process can be simplified in the process of industrial automation control.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A flowchart illustrating the control program compilation method provided in this application embodiment; Figure 2 Another flowchart illustrating the control program compilation method provided in this application embodiment; Figure 3 Another flowchart illustrating the control program compilation method provided in this application embodiment; Figure 4 Another flowchart illustrating the control program compilation method provided in this application embodiment; Figure 5 Another flowchart illustrating the control program compilation method provided in this application embodiment; Figure 6 Another flowchart illustrating the control program compilation method provided in this application embodiment; Figure 7 Another flowchart illustrating the control program compilation method provided in this application embodiment; Figure 8 Another flowchart illustrating the control program compilation method provided in this application embodiment; Figure 9 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0020] In the description of this application, it should be understood that the orientation descriptions, such as up, down, left, right, front, and back, are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0022] In the description of this application, it should be noted that, unless otherwise explicitly defined, terms such as "setting," "installation," and "connection" should be interpreted broadly. Those skilled in the art can reasonably determine the specific meaning of the above terms in this application based on the specific content of the technical solution. Furthermore, the identification of specific steps in the following text does not imply a limitation on the order of steps or execution logic. The execution order and logic between each step should be understood and inferred from the content described in the embodiments.

[0023] Programmable Logic Controllers (PLCs), as the core control units of industrial automation control systems, execute logic operations and sequential control instructions through programmable memory, controlling machinery or production processes via digital or analog input / output interfaces. Among the various programming languages ​​supported by industrial control programming platforms, ladder diagrams, whose syntax directly borrows from the relay circuit diagrams of traditional electrical control systems, use graphical elements such as contacts, coils, and function blocks connected by horizontal wires to form ladders. This high level of intuitiveness and engineering practicality makes them the most classic programming language in the field of industrial control. Engineers using ladder diagrams need both knowledge of electrical control principles and logical thinking skills to break down complex control requirements into multiple independent logic modules and to be proficient in using Boolean algebra to design control logic. However, ladder diagrams have significant limitations in practical applications. When the control logic involves multiple nested layers, complex conditional judgments, or loops, the connections in the ladder diagram become lengthy and difficult to trace, especially in scenarios such as implementing PID algorithms or matrix operations, significantly reducing readability and increasing the difficulty of troubleshooting.

[0024] Furthermore, typical large models currently on the market cannot achieve automatic programming of ladder diagrams; they can only generate ladder diagrams in text form. This type of ladder diagram is not only difficult to read, but also cannot be directly imported into the industrial control programming platform for compilation and debugging. Engineers still need to manually copy and rebuild, which fails to truly reduce the programming workload.

[0025] Regarding the technical approach of PLC executing ladder diagram programs, there are two main modes in the existing technology.

[0026] Interpretive execution PLCs are currently the most common type. Their core is an interpretation engine running on a real-time operating system, which cycles through input sampling, instruction reading, instruction parsing, logic execution, and output refresh within a fixed scan cycle. While flexible, this approach incurs significant interpretation overhead. The CPU needs to constantly read intermediate code, analyze opcodes, and jump to execution, resulting in low execution efficiency. Furthermore, the operating system's task scheduling and interrupt latency introduce time jitter, making it difficult to meet the stringent microsecond-level determinism requirements of high-end industrial control scenarios.

[0027] Compiled execution PLCs use a path of converting ladder diagrams into high-level languages ​​such as C / C++, and then calling third-party compilers such as GCC to generate machine code. This approach relies on a large toolchain, has a long compilation process and a complex environment deployment. In addition, in order to ensure generality, the code generated by general compilers often contains redundant instructions and is not the optimal solution for specific PLC logic, resulting in a large program size and room for improvement in running efficiency.

[0028] Against this backdrop, existing technologies have significant shortcomings in terms of execution efficiency and real-time performance of ladder diagram programs. Interpreted execution mode is limited by software-level interpretation overhead and scheduling jitter, while compiled execution mode is limited by lengthy toolchains and suboptimal code generated by general-purpose compilers.

[0029] Therefore, there is an urgent need for a ladder diagram processing method that can eliminate intermediate steps, does not rely on a general compiler, and directly generate efficient machine code, in order to solve the technical problems of low running efficiency, poor real-time performance, and cumbersome compilation process in the existing technology.

[0030] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a control program compilation method, electronic device, and storage medium, which can improve operating efficiency, real-time performance, and simplify the compilation process in the process of industrial automation control.

[0031] The following explanation is based on the accompanying drawings.

[0032] Reference Figure 1 The control program compilation method according to the embodiments of this application may include: Step S101: Obtain the ladder diagram program to be compiled; wherein, the ladder diagram program contains various types of component representation graphics; Step S102: Perform structured analysis on the logical connection relationship between the representation graphics of each element in the ladder diagram program to obtain tree program structure data; Step S103: Perform a program instruction mapping operation based on the tree program structure data to obtain multiple program assembly codes corresponding to the tree program structure data; Step S104: Decode multiple program assembly codes to obtain a binary executable program.

[0033] The control program compilation method according to the embodiments of this application requires first obtaining the ladder diagram program to be compiled; wherein, the ladder diagram program contains various types of component representation graphics; the logical connection relationships between the component representation graphics in the ladder diagram program are structured and parsed to obtain tree-shaped program structure data; based on the tree-shaped program structure data, a program instruction mapping operation is performed to obtain multiple program assembly codes corresponding to the tree-shaped program structure data; the multiple program assembly codes are decrypted to obtain a binary executable program. In this way, operational efficiency, real-time performance, and the compilation process can be simplified in the process of industrial automation control.

[0034] In some embodiments, step S101 involves obtaining the ladder diagram program to be compiled; wherein the ladder diagram program contains various types of component representation graphics; It should be noted that the embodiments in this application represent the initial stage of the entire compilation process, and the object of processing is the ladder diagram program commonly used in the field of industrial control. Ladder diagram programs consist of various graphical symbols, which in the context of industrial control typically represent normally open contacts, normally closed contacts, output coils, function blocks, and other components; these are summarized in the claims as component representation graphics. These graphical symbols are interconnected by wires, collectively expressing a complete set of industrial control logic. Obtaining this program means reading this set of graphical control logic from the corresponding storage location or programming environment, allowing it to enter the subsequent processing stages. The purpose of this embodiment is to provide the original input for the entire compilation process, ensuring that subsequent processing has a clear operational object. From some embodiments provided in this application, it can be seen that this application differs from the traditional PLC path of requiring interpretation or first converting the ladder diagram into a high-level language and then using a general-purpose compiler for processing. Instead, it chooses to start processing directly from the graphical source of the ladder diagram, thus laying the foundation for eliminating intermediate conversion stages and achieving direct compilation.

[0035] In some specific embodiments of this application, the ladder diagram program includes various types of component representation graphics, which may include, but are not limited to, the following: Normally open contacts are one of the most basic component representations. Their symbol is typically a horizontal line connecting two parallel vertical lines, similar to a normally open switch in a traditional relay control circuit. When the corresponding input signal or internal relay state is true, the contact is closed, allowing energy to flow; conversely, it is open, blocking energy flow. The corresponding normally closed contact is represented by an additional diagonal line, indicating that the contact is normally closed but opens when the corresponding signal is true.

[0036] The output coil is a graphical representation of the execution result in a ladder diagram. Its graphic symbol is typically represented by parentheses or a pair of parentheses containing an identifier, located on the far right of the ladder rung. It indicates that when all the logic conditions on the left side of that rung are met, the coil is energized, driving the corresponding external output or internal relay to set. A similar function is the reset coil, whose graphic symbol is similar to the output coil but with a specific identifier, used to reset the target relay or register to its initial state.

[0037] Function blocks are graphical representations of components in ladder diagrams used to express complex calculations or specific control functions. Their graphical symbols are typically represented by a rectangle with the function name labeled inside, such as a data transfer function block, a mathematical operation function block, a timer function block, or a counter function block. These component representations have input and output terminals, can receive preceding logic conditions as enable signals, and execute internally preset algorithms or timing / counting operations when the conditions are met.

[0038] In addition, ladder diagrams also include graphical representations of components used to express signal edge detection, such as rising edge and falling edge instructions. These are typically represented by contacts with upward or downward arrows, used to detect the transition moments of the corresponding signals from low to high or high to low. Invert instructions use specific symbols to represent a logical inversion of the current power flow state. Various comparison instructions, such as single-word comparison, double-word comparison, and floating-point comparison, are typically represented by rectangles with comparison operators and parameters. They are used to determine the size or equality relationship of two operands and pass the comparison result as a power flow condition to subsequent logic.

[0039] In some embodiments, step S102 involves performing structured parsing on the logical connection relationships between the representation graphics of each element in the ladder diagram program to obtain tree-shaped program structure data. It's important to note that after obtaining the ladder diagram program, it needs to be structured and parsed. The core of this process is identifying the logical relationships formed by the connections between the various components in the ladder diagram. A ladder diagram is not simply a collection of graphics; it's internally connected by horizontal wires to form series connections and vertical lines to form parallel connections. These connections collectively determine the order and hierarchy of the control logic. Structured parsing involves explicitly extracting these implicit, planar logical relationships and reorganizing them into a tree-like program structure data. A tree-like program structure data is a hierarchical data organization form where nodes at different levels correspond to different granularities of logic blocks in the ladder diagram, such as the entire program, conditional branches, parallel logic, series logic, and individual components. This embodiment transforms the graphical program, originally presented as a two-dimensional grid, into structured data that the computer can traverse and process according to hierarchical relationships, thus providing an operable intermediate representation for the subsequent conversion of the logical structure into processor instructions. As can be seen from some embodiments provided in this application, although the ladder diagram is presented as a planar graphic, its inherent logical control relationship is naturally hierarchical. By abstracting it through a tree structure, the logical operation hierarchy and the dependency relationship between components of the original ladder diagram can be accurately preserved, avoiding the logical confusion that may be caused by planar analysis.

[0040] Reference Figure 2 In some embodiments of this application, step S102 performs structured parsing of the logical connection relationships between the graphical representations of each element in the ladder diagram program to obtain tree-shaped program structure data, which may include: Step S201: Identify the representation graphics of each component in the ladder diagram program to obtain various types of component unit objects and the component arrangement characteristics of each component representation graphics in the ladder diagram program. Step S202: Determine the program logic characteristics between each component unit object based on the component arrangement characteristics of each component representation graphic in the ladder diagram program. Step S203: Based on the program logic characteristics between each component unit object, map the corresponding component unit objects to the target two-dimensional array; Step S204: Generate tree-shaped program structure data based on the element unit objects in the target two-dimensional array and the program logic characteristics.

[0041] In some embodiments, step S201 involves identifying the representation graphics of each element in the ladder diagram program to obtain various types of element unit objects and the element arrangement characteristics of each element representation graphics in the ladder diagram program. It should be noted that the embodiments of this application aim to transform graphical ladder diagram programs into data objects that can be processed by subsequent algorithms. Various component representation graphics in ladder diagram programs, such as normally open contacts, normally closed contacts, output coils, and function blocks, are presented in specific symbolic forms in the graphical interface, but computers cannot directly perform logical analysis on these graphic symbols. Therefore, it is necessary to identify these component representation graphics, abstracting them from graphic symbols into component unit objects with type attributes, and simultaneously recording the component arrangement characteristics of each component representation graphic in the ladder diagram program, that is, the spatial distribution information such as the row and column positions and adjacency relationships of each graphic symbol in the ladder diagram grid. The purpose of this embodiment is to complete the first abstraction from visual graphics to data objects, transforming graphic symbols that originally existed in pixel or vector form into structured data units with type labels and positional attributes, thereby providing computable operation objects for subsequent analysis. From some embodiments provided in this application, although ladder diagrams express control logic in an intuitive graphical way, to achieve automated compilation processing, it is necessary to first break through the graphical layer's appearance and transform it into a data entity that the computer can recognize. This is the prerequisite for all subsequent automated processing.

[0042] In step S202 of some embodiments, the program logic features between each component unit object are determined based on the component arrangement features of each component representation graphic in the ladder diagram program. It should be noted that after obtaining the component unit objects and their arrangement characteristics, it is necessary to further extract the program logic characteristics from them. The component arrangement characteristics only reflect the spatial position of each graphic symbol on a two-dimensional plane, while the core value of the ladder diagram lies in the logical operation relationship formed by the connection of these symbols through wires. The program logic characteristics refer to the logical connection relationship implied by the component arrangement characteristics, such as which components form a series path through horizontal wires, which components form a parallel branch through vertical lines, and what path the energy flow takes from the left bus to the right output. The purpose of this embodiment is to parse the logical operation relationship from the spatial distribution information, elevating the planar position data into logical data that expresses cause and effect and the order of operation. From some embodiments provided in this application, it can be seen that the essence of the ladder diagram is a logical language rather than a simple circuit diagram. Its graphic arrangement strictly follows the logical execution order from left to right and from top to bottom. Therefore, by analyzing the spatial arrangement, its inherent control logic can be restored, which is the key link connecting the graphic representation and the program structure.

[0043] Reference Figure 3 In some embodiments of this application, step S202, based on the component arrangement characteristics of each component representation graphic in the ladder diagram program, determines the program logic characteristics between each component unit object, which may include: Step S301: Based on the component arrangement characteristics of each component representation graphic in the ladder diagram program, determine the row connection state, column connection state, graphic arrangement position corresponding to each component representation graphic, and the length relationship between the leftmost column vertical line and the rightmost column vertical line. Step S302: Based on the row connection status and column connection status of each component's representation graphics, the graphic arrangement position corresponding to each component's representation graphics, and the length relationship between the leftmost column vertical line and the rightmost column vertical line, determine the program logic features between each component unit object.

[0044] In step S301 of some embodiments, based on the component arrangement characteristics of each component representation graphic in the ladder diagram program, the row connection state, column connection state, graphic arrangement position corresponding to each component representation graphic, and the length relationship between the leftmost column vertical line and the rightmost column vertical line are determined. It should be noted that the embodiments of this application aim to extract specific indicators that can express logical connection relationships from the component arrangement features. The component arrangement features record the spatial distribution of the component representation graphics in the ladder diagram grid, but these distributions are not directly equivalent to logical operation relationships. The row connection state describes whether there are vertical connecting lines between different rows, that is, whether vertical lines form parallel paths across rows between adjacent ladder steps; the column connection state describes whether horizontal lines form series paths between components in the same column; the graphic arrangement position precisely records the row and column coordinates of each component representation graphic in the ladder diagram, used to define the spatial boundaries of the logic block; the length relationship between the leftmost and rightmost vertical lines reflects whether there are parallel logic blocks that enclose multiple rows in the ladder diagram, and the start and end range of such parallel blocks. The purpose of this embodiment is to transform planar spatial distribution information into structural parameters with clear logical meaning, upgrading the arrangement data that originally only represented position into intermediate information that can express logical relationships such as series, parallel, and branching. As can be seen from some embodiments provided in this application, ladder diagrams, as a graphical programming language, implicitly express logical relationships through the arrangement and connection of graphical elements. Therefore, systematic geometric feature extraction is necessary to restore the visualized circuit layout into computable logical structure parameters.

[0045] In step S302 of some embodiments, the program logic features between each element unit object are determined based on the row connection state and column connection state of each element representation graphic, the graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost column vertical line and the rightmost column vertical line.

[0046] It should be noted that the embodiments of this application aim to utilize the aforementioned extracted structural parameters to ultimately determine the program logic characteristics between each component unit object. Row connection states reveal whether there is a parallel relationship between different ladder levels; when multiple rows are connected by vertical lines, it indicates that these rows logically constitute parallel branches. Column connection states reveal whether there is a series relationship between components within the same ladder level; when multiple components are connected sequentially by horizontal wires, it indicates that these components logically constitute a series path. The graphic arrangement position helps define the scope and boundaries of logic blocks and identify which components belong to the same logical operation unit. The length relationship between the leftmost and rightmost vertical lines helps identify whether there are parallel logic blocks enclosing multiple rows, i.e., OR logic structures. Combining these structural parameters, it can be determined whether each component unit object constitutes an AND logic, OR logic, branch output, or independent container logic relationship. The purpose of this embodiment is to complete the final mapping from geometric features to logical relationships, giving the extracted structural parameters clear logical semantics, thereby providing a logical judgment basis for the subsequent reorganization of the planar ladder diagram into a hierarchical data structure. As can be seen from some embodiments provided in this application, the graphic arrangement of the ladder diagram is not drawn arbitrarily, but strictly follows the logical execution order from left to right and from top to bottom. Therefore, by analyzing geometric features such as row connections, column connections, component positions and vertical line ranges, the Boolean logic relationship and control flow structure intended by the designer can be accurately restored.

[0047] Reference Figure 4 In some embodiments of this application, step S302, based on the row connection state and column connection state of each element representation graphic, the graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost and rightmost vertical lines, determines the program logic characteristics between each element unit object, which may include: Step S401: When there are rows without vertical lines connecting downwards, determine that the corresponding element unit object has the program logic characteristics of a container structure. Step S402: When there is an output coil or an executable function block, and there is a set of row coordinates on the right side of the leftmost column vertical line that is not connected to the next row, determine that the corresponding component unit object has the program logic characteristics of a branch structure. Step S403: When there are equal-length leftmost and rightmost vertical lines and no other logical elements on both sides, determine that the corresponding element unit object has the program logic characteristics of an OR logic structure. Step S404: When there is a column with only a single horizontal line or a single logical element connected left and right, determine that the corresponding element unit object has the program logic characteristics of the logical structure. Step S405: When only a single logical element is included, determine that the corresponding component unit object has the program logic characteristics of a unit structure.

[0048] In step S401 of some embodiments, when there are rows without vertical lines connecting downwards, it is determined that the corresponding element unit object has the program logic feature of a container structure. It should be noted that in the embodiments of this application, when a row in the ladder diagram is found to have no vertical line connecting it to the next row, it is determined that the area has the program logic characteristics of a container structure. In the graphical representation of a ladder diagram, vertical lines are parallel wires connecting components between different rows. If a row lacks such vertical connections, it indicates that the row is electrically isolated from the row below it, each constituting an independent logical segment. When multiple such isolated rows appear in the ladder diagram, it means that the entire program can be divided into multiple independent functional segments. The purpose of determining the container structure is to separate the independent program segments from the whole, so that subsequent processing can be performed on each independent segment separately, avoiding the forced merging and analysis of program segments that have no logical connection. From some embodiments provided in this application, a ladder diagram program can be composed of multiple logical segments that perform different tasks. These logical segments each have independent input conditions and output targets. By identifying rows without vertical line connections to define the container boundaries, it conforms to the natural structure of the modular design of ladder diagram programs.

[0049] In step S402 of some embodiments, when there is an output coil or an executable function block, and there is a set of row coordinates to the right of the leftmost column vertical line that is not connected to the next row, it is determined that the corresponding element unit object has the program logic feature of a branch structure. It should be noted that in this embodiment, when an output coil or executable function block is detected in the ladder diagram, and several rows to the right of the leftmost vertical line are not connected to the next row by vertical lines, it is determined that the area has the program logic characteristics of a branch structure. The leftmost vertical line is usually the main power flow path leading from the left bus, representing the general condition for entering the logic block; in the set of row coordinates to its right, if there are rows that are not connected downwards, it means that these rows each have independent output elements, but share the same entry condition on the left. This layout is represented in the ladder diagram as a common condition followed by multiple parallel outputs, and each output is executed depending on whether the common condition is met. The purpose of determining the branch structure is to distinguish the hierarchical relationship between the common condition and the branch outputs, and to clarify which elements constitute the shared pre-logic and which elements constitute independent subsequent actions. From some embodiments provided in this application, it can be seen that the multi-output scenario commonly seen in industrial control, such as multiple actuators controlled by the same start condition, is expressed in the ladder diagram by a common condition plus multiple branch outputs. Therefore, by identifying the distribution of the leftmost vertical line and the independent rows to its right, this one-to-many control logic can be accurately reconstructed.

[0050] In step S403 of some embodiments, when there are equal-length leftmost and rightmost vertical lines and no other logical elements on both sides, it is determined that the corresponding element unit object has the program logic feature of an OR logic structure. It should be noted that in this embodiment, when the leftmost and rightmost vertical lines in the ladder diagram are found to be of equal length, and there are no other logical elements outside these two vertical lines, the region is determined to have the program logic characteristics of an OR logic structure. A rectangular region is enclosed between the two equal-length vertical lines, and the rows within this region are connected in parallel by the vertical lines to form a parallel logic block. The absence of other logical elements outside the vertical lines ensures that the boundary of this parallel region is clear and will not be confused with other external logic. This structure corresponds to the situation in the ladder diagram where multiple parallel branches jointly determine an output result; that is, as long as any one branch is active, the overall logic is true. The role of determining the OR logic structure is to identify the parallel relationships in the ladder diagram, grouping the originally flat parallel rows into a unified logical operation node. From some embodiments provided in this application, parallel contact groups in the ladder diagram are a typical way to implement OR operations. By identifying the equal-length double vertical lines and their clear boundaries, the scattered parallel branches can be abstracted into a single OR logic node, thereby simplifying the subsequent structured representation.

[0051] In step S404 of some embodiments, when there is a column with only a single horizontal line or a single logical element connected left and right, it is determined that the corresponding element unit object has the program logic characteristics of the logical structure. It should be noted that in the embodiments of this application, when a column in the ladder diagram is identified as having only a single horizontal line or only a single logical element connected horizontally, it is determined that the area has the program logic characteristics of an AND logic structure. In a ladder diagram, horizontal wires or elements represent the power flow path from left to right. When the elements in each row of a column are connected by horizontal lines, or when the column itself is a vertical arrangement of single elements, it indicates that these elements logically constitute a series relationship, and all conditions must be met simultaneously for power flow to pass through. The purpose of determining the AND logic structure is to identify the series logic chains in the ladder diagram and group the horizontally arranged elements into a sequence of AND operations that need to be judged sequentially. From some embodiments provided in this application, the basic logic unit of the ladder diagram is the AND operation implemented by connecting contacts. Identifying columns with only a single horizontal line or a single element connected is precisely capturing this most basic series logic characteristic, providing basic nodes for the subsequent construction of a hierarchical logic tree.

[0052] In some embodiments, step S405, when only a single logical element is included, determines that the corresponding element unit object has the program logic characteristics of a unit structure.

[0053] It should be noted that in the embodiments of this application, when a region within a ladder diagram is identified to contain only a single logical element, such as a single normally open contact, normally closed contact, output coil, or functional block, it is determined that the region possesses the program logic characteristics of a unit structure. This means that the logical function of this region is indivisible and is the most basic unit of operation in the entire ladder diagram. The purpose of determining the unit structure is to provide a termination condition for the recursive structural division. When the structural analysis delves into a single element that cannot be further subdivided, further subdivision can be stopped, and that element can be used as a leaf node in the tree structure. From some embodiments provided in this application, any complex control logic ultimately boils down to reading, operating on, or writing to a single element. The unit structure, as the smallest granularity node in the tree structure, represents the atomic operation of the ladder diagram logic and is the final landing point connecting the high-level logic structure and the low-level processor instructions.

[0054] In some embodiments, step S203 maps each element unit object to a target two-dimensional array based on the program logic characteristics between each element unit object. It should be noted that, based on the program logic characteristics between each component unit object, it is necessary to map each corresponding component unit object to a target two-dimensional array. The target two-dimensional array is a numerical matrix corresponding to the ladder diagram grid layout, where the row coordinates correspond to the ladder step numbers, the column coordinates correspond to the vertical position numbers, and each array element stores whether a component unit object exists at the corresponding position and its type information. Through this mapping, the originally scattered component unit objects are organized into a unified data framework with row and column coordinates, and the adjacency and connection relationships between components can be directly reflected through the relative positions of the array indices. This embodiment provides an operable data foundation for subsequent structured analysis, transforming the original visual recognition-dependent graphical analysis process into an automated process achievable through array traversal and index calculation. From some embodiments provided in this application, mapping the ladder diagram to a two-dimensional array is equivalent to establishing a standardized numerical coordinate system for the graphical program, preserving the original layout information while facilitating systematic structural scanning and partitioning through algorithms.

[0055] In some embodiments, step S204 generates tree-shaped program structure data based on each element unit object in the target two-dimensional array and the program logic features.

[0056] It should be noted that after establishing the target two-dimensional array, a tree-structured program data needs to be generated based on the element units and program logic characteristics within the array. Tree-structured program data is a hierarchical data organization form, where nodes at different levels correspond to logical functional units of different granularities in the ladder diagram. By analyzing the distribution patterns and connection characteristics of the elements in the two-dimensional array, the planar ladder diagram is gradually abstracted into tree nodes with parent-child relationships, thereby constructing structured data that can fully express the logical hierarchy and dependencies of the original ladder diagram. The purpose of this embodiment is to complete the final abstraction from planar layout to logical hierarchy, transforming the program, originally existing in a two-dimensional grid form, into a tree structure that the computer can traverse and process according to hierarchical relationships. As can be seen from some embodiments provided in this application, the logical control relationship of ladder diagrams is inherently hierarchical. The overall program consists of multiple independent functional blocks, and each functional block contains conditional branches, parallel logic, and serial logic, which are ultimately implemented in a single element. This hierarchical feature from coarse to fine is exactly in line with the tree data structure. Therefore, after performing structural analysis through a two-dimensional array, the generated tree program structure data can most accurately preserve the hierarchy and nesting relationship of the original control logic.

[0057] Reference Figure 5 In some embodiments of this application, step S204, which generates tree-shaped program structure data based on each element unit object in the target two-dimensional array and program logic characteristics, may include: Step S501: In the target two-dimensional array, sort out the program logic features corresponding to each element unit object; Step S502: Based on the characteristics of each program logic, each component unit object is recursively divided into multiple tree-shaped node data. Step S503: Generate tree-shaped program structure data based on various tree node data.

[0058] In step S501 of some embodiments, the program logic features corresponding to each element unit object are sorted out in the target two-dimensional array. It should be noted that in this embodiment, sorting out the program logic features corresponding to each element unit object in the target two-dimensional array means organizing and confirming the logical attributes corresponding to each element unit object in the numerical matrix where the element mapping has been completed. The target two-dimensional array stores the type information and position coordinates of each element unit object, but the structural role played by each element in the overall control logic is not yet clear. Sorting out the program logic features means associating the structural attributes previously determined based on row connection status, column connection status, graphic layout position, and vertical line length relationship with the element unit objects at the corresponding positions in the two-dimensional array, so that each element unit object not only has type and position attributes, but also has clear logical structure attributes. The purpose of this embodiment is to give each data unit in the two-dimensional array logical semantics, elevating the spatial data that originally only represented physical layout to structured data that expresses the role of logical operation. From some embodiments provided in this application, although the two-dimensional array completely records the planar layout of the ladder diagram, in order to realize the compilation from graphics to program, each element must know its belonging in the logical hierarchy. Therefore, it is necessary to complete the collection and correspondence of logical features at the array level.

[0059] In step S502 of some embodiments, each component unit object is recursively divided into multiple tree-shaped node data based on the characteristics of each program logic. It should be noted that in this embodiment, each component unit object is recursively divided into various tree-shaped node data based on the logical characteristics of each program. That is, according to the logical structure attributes of each component unit object, the planarly dispersed component unit objects are classified and organized according to their logical hierarchy. Specifically, component unit objects with container structure attributes are organized as container nodes, those with branch structure attributes are organized as branch nodes, those with OR logic structure attributes are organized as OR logic nodes, those with AND logic structure attributes are organized as AND logic nodes, and those with unit structure attributes are organized as unit nodes. Recursive division means that for each sub-region, the same structure identification and classification operation is repeatedly performed until all regions are decomposed into indivisible unit nodes. The purpose of this embodiment is to reorganize the planar two-dimensional array data into a set of nodes with parent-child relationships according to logical hierarchical relationships, so that the component data that originally existed in row and column coordinates is transformed into node data organized by logical hierarchical relationships. As can be seen from some embodiments provided in this application, the logical expression of ladder diagrams naturally has hierarchical characteristics from the whole to the part and from composite to single. By recursively abstracting two-dimensional planar data into different types of nodes layer by layer, it can accurately restore the nested logic and control flow expressed by the designer's intention.

[0060] Reference Figure 6In some embodiments of this application, the various tree-shaped node data includes container child node data, common condition child node data, branch output child node data, parallel child node data, serial child node data, and unit child node data. Step S502, based on the characteristics of each program logic, recursively divides each component unit object into various tree-shaped node data, which may include: Step S601: For program logic features with container structure, the corresponding component unit objects are divided into mutually independent container sub-node data. Step S602: For program logic features with branching structures, the corresponding component unit objects are divided into common condition sub-node data and multiple branch output sub-node data. Step S603: For program logic features with OR logic structure, divide the corresponding component unit object into multiple parallel sub-node data. Step S604: For program logic features with logical structure, divide the corresponding component unit object into multiple serial sub-node data. Step S605: For program logic features with a unit structure, the corresponding component unit object is determined as unit sub-node data.

[0061] In step S601 of some embodiments, for program logic features with container structures, the corresponding component unit objects are divided into mutually independent container sub-node data. It should be noted that, in this embodiment, for program logic features with a container structure, the corresponding component unit objects are divided into mutually independent container sub-node data. The container structure originates from the existence of isolated rows in the ladder diagram without vertical lines connecting them downwards. These rows each constitute an independent logical segment, and they do not interfere with each other in the electrical path. The container sub-node data is the encapsulation unit for these independent logical segments. Each container sub-node data contains a complete, independently compileable subroutine logic. The purpose of this embodiment is to separate mutually independent functional modules in the ladder diagram program from the whole, so that each module enters the subsequent process as an independent processing unit, avoiding logical confusion and cross-interference between different functional segments. From some embodiments provided in this application, a ladder diagram program can be composed of multiple logical segments that complete different control tasks. These logical segments each have independent input conditions and output targets. They are encapsulated at the top level through container sub-nodes, which conforms to the natural structure of the modular design of ladder diagram programs and also provides a clear entry boundary for subsequent top-down traversal.

[0062] In step S602 of some embodiments, for program logic features with branch structures, the corresponding component unit object is divided into common condition sub-node data and multiple branch output sub-node data. It should be noted that, in this embodiment, for program logic features with a branching structure, the corresponding component unit objects are divided into common condition sub-node data and multiple branch output sub-node data. The branching structure originates from the existence of multiple rows that are not connected downwards to the right of the leftmost vertical line in the ladder diagram. These rows share the same entry condition on the left but each has an independent output element. The common condition sub-node data stores the pre-processing logic judgment part shared by all branches, while the branch output sub-node data stores the subsequent execution actions in each independent row. The purpose of this embodiment is to clearly distinguish the hierarchical relationship between the shared condition and the independent output, accurately expressing the one-to-many control logic as the condition node and multiple output nodes under the parent node. From some embodiments provided in this application, it can be seen that in industrial control scenarios, multiple actuators are often controlled by the same start condition. The ladder diagram expresses this logic by using a common condition followed by multiple parallel outputs. By dividing it into common condition sub-nodes and branch output sub-nodes, the hierarchical control structure intended by the designer can be accurately reproduced.

[0063] In step S603 of some embodiments, for program logic features with OR logic structure, the corresponding component unit object is divided into multiple parallel sub-node data. It should be noted that, in the embodiments of this application, for program logic features with an OR logic structure, the corresponding component unit objects are divided into multiple parallel child node data. The OR logic structure originates from a region in the ladder diagram where there are equal-length leftmost and rightmost vertical lines and no other logical elements on either side. Within this region, rows are connected in parallel by vertical lines, forming parallel contact groups. The parallel child node data is an encapsulation of each component unit object in these parallel branches; each parallel child node data represents an independent parallel path. The purpose of this embodiment is to consolidate the scattered parallel rows in the ladder diagram into a unified logical operation node, so that the originally flat multiple parallel branches are organized into parallel child nodes under the same parent node in the data structure. From some embodiments provided in this application, the parallel contact group in the ladder diagram is a typical way to implement logical OR operations. As long as any one branch is connected, the whole is true. By abstracting through the form of parallel child node data, this multi-choice-one-connection logical relationship can be accurately transformed into an OR operation expression in the data structure.

[0064] In step S604 of some embodiments, for program logic features with AND logic structure, the corresponding element unit object is divided into multiple serial sub-node data; It should be noted that, in this embodiment, for program logic features with an AND logic structure, the corresponding component unit objects are divided into multiple serial sub-node data. The AND logic structure originates from columns in a ladder diagram where only a single horizontal line or a single logical element is connected left and right. The components in these columns form serial paths through horizontal wires, and power flow must be enabled only if these paths are satisfied sequentially. The serial sub-node data encapsulates each component unit object in these serial paths, with each serial sub-node representing a link in the serial chain. This embodiment aims to group the serially arranged components in the horizontal direction of the ladder diagram into a logical sequence that needs to be judged sequentially, organizing the serial relationships originally scattered in a two-dimensional array into sequential child nodes under the same parent node in the data structure. From some embodiments provided in this application, the most basic logical unit in a ladder diagram is the AND operation implemented through contact connections. By abstracting this sequential logical relationship through serial sub-node data, the sequentially connected logical relationship can be accurately transformed into an AND operation expression in the data structure.

[0065] In step S605 of some embodiments, for program logic features with a unit structure, the corresponding element unit object is determined as unit sub-node data.

[0066] It should be noted that, in the embodiments of this application, for program logic features with a unit structure, the corresponding component unit object is determined as unit sub-node data. The unit structure originates from a region in the ladder diagram containing only a single logic element, such as a single normally open contact, normally closed contact, output coil, or functional block, which cannot be further decomposed into smaller logic combinations. The unit sub-node data is a direct mapping of this smallest granularity logic element and no longer contains lower-level sub-nodes. The purpose of this embodiment is to provide a termination condition for recursive structure partitioning. When the structure analysis delves into an indivisible single component, further partitioning can be stopped, and that component is treated as a leaf node in the tree structure. From some embodiments provided in this application, any complex control logic ultimately boils down to reading, calculating, or writing operations on a single component. The unit sub-node data, as the smallest node in the tree structure, represents the atomic operation of the ladder diagram logic and is the final point connecting the high-level logic structure and the low-level processor instructions.

[0067] In some embodiments, step S503 generates tree-shaped program structure data based on various tree node data.

[0068] It should be noted that in this embodiment, the tree-structured program data is generated based on various tree-shaped node data. This means that the various types of node data obtained from recursive partitioning are organized into a complete tree-shaped data structure according to their logical hierarchy and dependencies. In the tree-structured program data, the container node serves as the top-level encapsulation, containing intermediate-level nodes such as branch nodes, logical nodes, and AND logical nodes. These intermediate-level nodes can further contain lower-level AND logical nodes, logical nodes, or unit nodes. Ultimately, all branches are implemented at the leaf level of the unit node. The parent-child relationship between nodes expresses the inclusion relationship and execution order between the logical blocks in the original ladder diagram. The purpose of this embodiment is to complete the final integration from scattered nodes to a unified structure, so that the various nodes generated by recursive partitioning no longer exist in isolation, but form a complete hierarchical data body that can be traversed and processed by the computer from top to bottom. As can be seen from some embodiments provided in this application, the compilation process requires a systematic traversal and transformation of the entire program. The scattered node type definitions alone are insufficient to support the subsequent instruction generation. These nodes must be connected into a complete tree according to the logical architecture of the original ladder diagram in order to ensure the accurate transmission of logical order and nesting relationship during subsequent processing.

[0069] In some more specific embodiments, the structured parsing process first maps the graphical representations of each element in the ladder diagram program to a gridded representation with row and column coordinates, so that each element has a definite position index on the two-dimensional plane. Based on this, the embodiments of this application perform recursive structural checks and hierarchical divisions on the ladder diagram according to the vertical and horizontal connection states between each element and the row and column boundary features.

[0070] When a ladder diagram is found to have a row without a vertical line connecting to the next row, it indicates that these rows are isolated from each other in the vertical electrical path and each constitutes an independent logical segment. In this case, this embodiment uses all rows that meet this condition as boundaries to divide the ladder diagram into multiple independent sub-ladder diagrams, and defines the current parent ladder diagram as a container structure. A container structure means that there is no logical dependency between its subordinate sub-ladder diagrams, and they can be processed separately. After the division is completed, this embodiment repeats the same structural check process for each sub-ladder diagram.

[0071] If the aforementioned container features are not present, the ladder diagram is further checked to see if it contains an output coil or an executive function block. If it does, the leftmost vertical column is located, and the set of row coordinates to the right of this vertical column that is not connected to the next row by a vertical column is identified. Each row in this set represents an independent output path. In this embodiment, the portion to the left of the vertical column is divided into a common condition sub-ladder diagram, and the portion to the right of the vertical column is divided into multiple branch output sub-ladder diagrams according to the row coordinates in this set. The current parent ladder diagram is defined as a branch structure. If the leftmost vertical column is not present, or the set of row coordinates to the right of the leftmost vertical column is empty, the system defines the output coil or executive function block itself as a single branch output sub-ladder diagram, and the remaining portion is divided into condition sub-ladder diagrams. The parent ladder diagram is also defined as a branch structure. After the division is completed, the structure check is repeated for all sub-ladder diagrams.

[0072] If none of the above conditions are met, then check if there are two vertical lines in the leftmost and rightmost columns, both of equal length, and if there are no other logical elements to the left of the leftmost vertical line and only horizontal lines to the right of the rightmost vertical line. If this condition is met, it indicates that a parallel logical region is enclosed between the two vertical lines. In this embodiment, the row coordinates of all rows between the two vertical lines that are not connected to the next row are used as the basis for dividing the parent ladder diagram into multiple sub-ladder diagrams, and the current parent ladder diagram is defined as an OR logic structure. After the division is completed, this embodiment repeats the OR logic structure check process for all sub-ladder diagrams.

[0073] If the above conditions are still not met, then all column coordinates containing only a single horizontal line or only a single logical element connected left and right are searched. These columns are used as dividing boundaries to divide the parent ladder diagram into multiple sub-ladder diagrams, excluding those that do not contain logical elements. The current parent ladder diagram is defined as an AND logic structure. AND logic structures correspond to serial logic relationships, and their subordinate sub-ladder diagrams are sequentially connected in the power flow path. After the division is completed, this embodiment of the application repeats the aforementioned OR logic structure check on these sub-ladder diagrams to ensure that deeper parallel characteristics can be further identified.

[0074] If none of the above conditions are met, and the current ladder diagram contains only a single logic element, such as a single normally open contact, normally closed contact, output coil, or functional block, the system defines the ladder diagram as a unit structure, as a leaf node in the tree structure, and does not further divide it. If the current ladder diagram neither satisfies any of the above structural characteristics nor belongs to a single logic element, the system determines that it has a structural error, such as an open circuit, short circuit, or mixed connection, and terminates the compilation process, reporting an error.

[0075] Through the above recursive layer-by-layer checking and division, the ladder diagram program, which originally existed in the form of a planar grid, is gradually abstracted into a tree-shaped program structure data containing container structure, branch structure, or logical structure, and logical structure and unit structure. The parent-child relationship between each node accurately reflects the hierarchical nesting and dependency relationship between each logical block in the original ladder diagram.

[0076] In some embodiments, step S103 involves performing a program instruction mapping operation based on the tree-structured program data to obtain multiple program assembly codes corresponding to the tree-structured program data. It should be noted that after obtaining the tree-structured program data, a program instruction mapping operation needs to be performed. The essence of this embodiment is to convert the logical functions represented by each node in the tree structure into assembly instructions that the processor can recognize and execute. Since each node type in the tree structure corresponds to different logical operation characteristics—for example, some nodes express parallel relationships, some express serial relationships, and some correspond to read or write operations of a single element—corresponding instruction generation strategies are needed for different types of nodes. By traversing the tree structure from top to bottom, this embodiment processes each node sequentially, generating a corresponding sequence of assembly instructions, ultimately obtaining multiple program assembly codes. These assembly codes are the concrete manifestations of each logical block in the tree structure at the instruction level. The purpose of this embodiment is to complete the conversion from abstract logic to concrete code, transforming graphical control intentions into a sequence of instructions executable by the processor. From some embodiments provided in this application, it can be seen that using the hierarchical traversal characteristics of the tree structure for instruction generation ensures that the order and nesting of logical relationships are accurately translated into operational, jump, and storage relationships between instructions, thereby achieving a direct correspondence between ladder diagram logic and processor instructions.

[0077] Reference Figure 7 In some embodiments of this application, step S103, which performs a program instruction mapping operation based on the tree-structured program data to obtain multiple program assembly codes corresponding to the tree-structured program data, may include: Step S701: For a container structure containing container child node data in a tree-shaped program structure data, generate an independent container program segment based on each container child node data. Step S702: For a branch structure in which the tree program structure data contains common condition child node data and branch output child node data, multiple registers are called as logical scheduling registers, and corresponding condition judgment program segments and condition response program segments are generated based on the cooperation of each logical scheduling register. Step S703: For a tree-shaped program structure data containing multiple parallel child node data or a logical structure, multiple registers are called as logical scheduling registers, and corresponding logical response program segments are generated based on the cooperation of each logical scheduling register. Step S704: For a tree-shaped program structure containing multiple serial child node data, call multiple registers as logic scheduling registers, and generate corresponding AND logic response program segments based on the cooperation of each logic scheduling register. Step S705: For tree-structured program data containing unit sub-node data, generate corresponding unit function program segments according to the unit type of the unit sub-node data. Step S706: Integrate the container program segment, condition determination program segment, condition response program segment, OR logic response program segment, AND logic response program segment, and unit function program segment to obtain multiple program assembly codes.

[0078] In step S701 of some embodiments, for a container structure containing container child node data in the tree program structure data, an independent container program segment is generated according to each container child node data. It should be noted that in this embodiment, the container structure originates from independent logical segments in the ladder diagram, and the container child node data is the encapsulation unit of these independent segments in the tree structure. The container program segment is the assembly code segment generated for each container child node data. Each container program segment remains independent at the code level and does not interfere with each other. The purpose of this embodiment is to isolate and generate the code of different functional modules in the ladder diagram program, ensuring that the compilation results of each independent logical segment can be processed separately, providing a modular code foundation for subsequent integration. As can be seen from some embodiments provided in this application, the ladder diagram program can be composed of multiple logical segments that perform different control tasks. These logical segments are electrically isolated from each other. Therefore, generating independent program segments for the container structure conforms to the natural characteristics of the modular design of ladder diagrams and also enables the overall compilation process to be decomposed in an orderly manner according to logical boundaries.

[0079] In step S702 of some embodiments, for a branch structure in which the tree program structure data contains common condition child node data and branch output child node data, multiple registers are called as logical scheduling registers, and corresponding condition judgment program segments and condition response program segments are generated based on the cooperation of each logical scheduling register. It should be noted that in this embodiment, the branch structure includes common condition sub-node data and branch output sub-node data. The former corresponds to the pre-condition logic judgment part shared by all branches, and the latter corresponds to the output action part of each independent branch. The logic scheduling register is a register resource in the ARM processor used to temporarily store the intermediate state of logic operations. The condition judgment program segment corresponds to the calculation code of the common condition and is responsible for temporarily storing the result of the common logic judgment in the register; the condition response program segment corresponds to the execution code of each branch output and is responsible for executing the corresponding output action according to the judgment result of the common condition. The purpose of this embodiment is to realize the unified calculation of the common condition and the separate response of the branch output through the cooperation of register resources, accurately converting the one-to-many control logic in the ladder diagram into a processor instruction sequence. From some embodiments provided in this application, the core feature of the branch structure is that it shares the entry condition but has an independent output. By using the logic scheduling register to store the intermediate power flow state, it can efficiently realize the reuse of conditions and the selection of branches, avoid repeated calculation of the common condition, and thus improve the code execution efficiency.

[0080] In step S703 of some embodiments, for a tree program structure data containing multiple parallel child node data or a logical structure, multiple registers are called as logical scheduling registers, and corresponding logical response program segments are generated based on the cooperation of each logical scheduling register. It should be noted that in this embodiment, the OR logic structure contains multiple parallel child node data, representing multiple branches connected in parallel by vertical lines in the ladder diagram. The OR logic response program segment is assembly code that implements parallel logic operations. Its logical meaning is that as long as one condition in the multiple parallel branches is met, the overall result is true. The purpose of this embodiment is to transform the parallel contact group in the ladder diagram into a processor-executable OR operation instruction sequence, realizing the parallel judgment of multiple conditions. From some embodiments provided in this application, the parallel relationship in the ladder diagram corresponds to the OR operation in Boolean algebra. By calling the logic scheduling register in conjunction with the generation of the response program segment, the scattered parallel branches can be abstracted into a unified OR logic operation, thereby accurately restoring the multi-select control logic intended by the designer at the instruction level.

[0081] In step S704 of some embodiments, for a logical structure containing multiple serial child node data in a tree program structure data, multiple registers are called as logical scheduling registers, and corresponding logical response program segments are generated based on the cooperation of each logical scheduling register. It should be noted that in this embodiment, the AND logic structure includes multiple serial sub-node data, representing multiple components connected in series by horizontal wires in the ladder diagram. The AND logic response program segment is assembly code that implements serial logic operations. Its logical meaning is that the conditions of all serial components must be satisfied sequentially for power flow to pass. The purpose of this embodiment is to transform the serial contact chain in the ladder diagram into a processor-executable AND operation instruction sequence, realizing sequential judgment of multiple conditions. From some embodiments provided in this application, the serial relationship in the ladder diagram corresponds to the AND operation in Boolean algebra. By calling the logic scheduling register to store and pass intermediate power flow states, the conduction status of each link in the serial chain can be passed sequentially, thereby accurately restoring the sequential conduction control logic intended by the designer at the instruction level.

[0082] In step S705 of some embodiments, for tree program structure data containing unit sub-node data, a corresponding unit function program segment is generated according to the unit type of the unit sub-node data. It should be noted that in this embodiment, the unit sub-node data are leaf nodes in a tree structure, representing indivisible single logical elements in the ladder diagram, such as a single contact, coil, or function block. The unit function program segment is an assembly instruction directly mapped to the component type corresponding to the unit sub-node data. The purpose of this embodiment is to transform the most basic logical elements into corresponding processor instructions, completing the code generation for atomic-level operations. As seen from some embodiments provided in this application, any complex control logic ultimately boils down to reading, calculating, or writing operations on individual components. Directly mapping the unit type to the corresponding processor instructions is the fundamental step in realizing the direct conversion from ladder diagram logic to assembly code, ensuring that the lowest-level graphical symbols can accurately correspond to the lowest-level machine instructions.

[0083] In some embodiments, step S706 integrates the container program segment, the condition determination program segment, the condition response program segment, the logic response program segment, the logic response program segment, and the unit function program segment to obtain multiple program assembly codes.

[0084] It should be noted that in this embodiment, the container program segments, condition judgment program segments, condition response program segments, or logic response program segments, and unit function program segments generated for different tree node types are combined according to the hierarchical relationship and logical order in the tree program structure data. The purpose of this embodiment is to integrate the various scattered code fragments into a complete assembly program, so that the code originally generated independently for different node types forms a coherent instruction sequence at the overall level. From some embodiments provided in this application, the traversal of the tree structure follows a top-down order. Integrating code fragments according to the hierarchical relationship of nodes ensures that the final generated assembly program maintains the same logical execution order as the original ladder diagram, thereby completing the overall conversion from graphical control logic to textual assembly code.

[0085] In some more specific embodiments, for the container structure in the tree-like program structure data, the container child node data under it corresponds to independent logical segments in the ladder diagram. Generating independent container program segments based on each container child node data means that each independent logical module is generated in isolation at the code level, forming its own complete code unit. The purpose of this embodiment is to separate the code of different functional modules in the ladder diagram program, ensuring that the compilation results of each independent logical segment do not interfere with each other, providing a modular code foundation for subsequent integration. From the embodiments of this application, a ladder diagram program can consist of multiple logical segments that perform different control tasks. These logical segments are electrically isolated from each other. Through the independent generation of container program segments, this modular boundary can be accurately restored, allowing the overall compilation process to be decomposed in an orderly manner according to the logical boundaries.

[0086] For the branch structure in the tree-like program structure data, it includes common condition child node data and branch output child node data. The former corresponds to the pre-condition logic judgment shared by all branches, and the latter corresponds to the output action of each independent branch. Multiple registers are called as logic scheduling registers, one of which serves as an intermediate power flow storage register to temporarily store the intermediate state of the logic operation. The condition judgment program segment is responsible for calculating the common condition and storing the result in the power flow register; the condition response program segment determines whether to execute or skip the output of each branch based on the state in the power flow register. The purpose of this embodiment is to achieve unified calculation of the common condition and separate response of the branch output through the cooperation of register resources, transforming the one-to-many control logic in the ladder diagram into a processor instruction sequence. From the embodiment of this application, the core feature of the branch structure is that it shares the entry condition but has independent output. By using the logic scheduling register to store the intermediate power flow state, it can efficiently realize the reuse of conditions and the selection of branches, avoiding repeated calculation of the common condition.

[0087] For the OR logic structure in the tree-like program structure data, it contains multiple parallel child node data, corresponding to multiple branches connected in parallel by vertical lines in the ladder diagram. The logic scheduling register is called to generate the OR logic response program segment, the logical meaning of which is that if any one of the conditions in the multiple parallel branches is met, the overall result is true. The judgment results of each parallel branch are stored and transmitted through the register, realizing the code expression of the parallel logic. The purpose of this embodiment is to transform the parallel contact group in the ladder diagram into a processor-executable OR operation instruction sequence, realizing the parallel judgment of multiple conditions. From the embodiment of this application, the parallel relationship in the ladder diagram corresponds to the OR operation in Boolean algebra. By using registers to complete the parallel judgment of multiple conditions, the dispersed parallel branches can be abstracted into a unified logical operation, thereby accurately restoring the control logic of multiple-choice-one-pass at the instruction level.

[0088] For the AND logic structure in the tree-like program structure data, it contains multiple serial child node data, corresponding to multiple components connected in series by horizontal wires in the ladder diagram. Calling the logic scheduling register to generate the AND logic response program segment means that the conditions of all serial components must be satisfied sequentially for energy flow to pass. The intermediate energy flow states are stored and passed through registers to realize the code expression of the serial logic. The purpose of this embodiment is to transform the serial contact chain in the ladder diagram into a processor-executable AND operation instruction sequence, realizing sequential judgment of multiple conditions. From the embodiment of this application, the serial relationship in the ladder diagram corresponds to the AND operation in Boolean algebra. By sequentially passing the conduction state through registers, the conduction status of each link in the serial chain can be passed sequentially, thereby accurately reconstructing the sequential conduction control logic at the instruction level.

[0089] In a tree-structured program data, the unit child node data is the leaf node of the tree structure, representing an indivisible single logical element in the ladder diagram, such as a single contact, coil, or function block. Based on the unit type of the unit child node data, a corresponding unit function program segment is generated, that is, different component types are mapped to different processor instructions. This embodiment aims to complete the code generation for atomic-level operations, converting the most basic graphical symbols into basic instructions that the processor can directly execute. From the embodiments of this application, any complex control logic ultimately boils down to reading, calculating, or writing operations on individual components. Directly mapping the unit type to the corresponding processor instructions is the fundamental step in realizing the direct conversion from ladder diagram logic to assembly code, ensuring that the lowest-level graphical symbols accurately correspond to the lowest-level machine instructions.

[0090] By integrating the aforementioned container program segments, conditional decision program segments, conditional response program segments, logical response program segments, and unit function program segments generated for different tree node types, multiple program assembly codes are obtained. Integration refers to combining the various code fragments generated in a scattered manner into a complete assembly program according to the hierarchical relationship and logical order in the tree program structure data. The purpose of this embodiment is to complete the convergence from scattered code to a unified program, so that the code generated independently for different node types forms a coherent instruction sequence at the overall level. As can be seen from the embodiments of this application, the traversal of the tree structure follows a top-down order. Integrating code fragments according to the hierarchical relationship of nodes can ensure that the final generated assembly program maintains the same logical execution order as the original ladder diagram in terms of execution order, thereby completing the overall conversion from graphical control logic to textual assembly code.

[0091] In some embodiments, step S104 involves deciphering multiple program assembly codes to obtain a binary executable program.

[0092] It should be noted that after obtaining multiple assembly codes, they need to be decoded to obtain a binary executable program. The essence of this embodiment is to convert the text-based assembly instructions into binary machine code that the processor can directly recognize, while simultaneously resolving the symbolic address references to determine their location in actual memory, calculating the offset between jump instructions and target locations, and finally integrating them into a complete binary executable program. The role of this embodiment is to complete the final solidification of the compilation process, enabling the generated program to move beyond text form and become machine code that can be directly loaded and run on the target processor hardware. From some embodiments provided in this application, it can be seen that this application aims to achieve a direct path from ladder logic to hardware execution, and this decoding embodiment is the key step in solidifying the previously generated assembly instructions into native processor instructions, ensuring that the output of the entire compilation process can run directly on ARM architecture processors without further processing by an interpreter engine or general-purpose compiler.

[0093] Reference Figure 8 In some embodiments of this application, step S104, which decodes multiple assembly codes to obtain a binary executable program, may include: Step S801: Extract soft component memory access instructions and flow control jump instructions from multiple program assembly codes; wherein, the flow control jump instructions include the current tag address and the target tag address; Step S802: Map the soft device memory access instructions to the actual memory storage addresses according to the preset constant table to update the soft device memory access instructions; wherein, the preset constant table stores a number of pre-configured candidate memory storage addresses. Step S803: Calculate the address offset difference between the current tag address and the target tag address in the flow control jump instruction, and configure the end operand of the flow control jump instruction based on the address offset difference to update the flow control jump instruction; Step S804: After mapping the soft device memory access instructions to the actual memory storage address and configuring the end operand for the flow control jump instructions, multiple program assembly codes, the updated soft device memory access instructions, and the updated flow control jump instructions are integrated to obtain a binary executable program.

[0094] In some embodiments, step S801 involves extracting soft component memory access instructions and flow control jump instructions from multiple program assembly codes; wherein the flow control jump instructions include the current tag address and the target tag address; It should be noted that in this embodiment, soft element memory access instructions and flow control jump instructions are extracted from multiple program assembly codes. Soft element memory access instructions refer to memory read and write instructions that access ladder diagram soft elements; these instructions typically exist in symbolic address form during the generation stage. Flow control jump instructions refer to branch or jump instructions that control the direction of program execution; these instructions typically use label names as jump targets during the generation stage. The current label address and the target label address refer to the code location of the jump instruction itself and the code location of the jump destination, respectively. The purpose of this embodiment is to identify two types of instructions from the generated assembly code that have not yet completed address resolution, thus determining the processing objects for subsequent address translation operations. From some embodiments provided in this application, most of the previously generated assembly code already contains true instructions that can directly correspond to the processor instruction set; however, instructions involving soft element memory access and program flow control still retain symbolic representations. Therefore, it is necessary to first identify these two special types of instructions from the code for targeted address resolution.

[0095] In some embodiments, step S802 maps the soft device memory access instruction to the actual memory storage address according to a preset constant table to update the soft device memory access instruction; wherein, the preset constant table stores a plurality of pre-configured candidate memory storage addresses; It should be noted that in this embodiment, the soft device memory access instructions are mapped to actual memory storage addresses according to a preset constant table to update the soft device memory access instructions. The preset constant table is a pre-configured data structure that stores multiple candidate memory storage addresses, each address corresponding to the actual location of a specific soft device in physical memory. Mapping the soft device memory access instructions to actual memory storage addresses means replacing the symbolic soft device identifier in the instruction with the corresponding physical address value in the preset constant table. The purpose of this embodiment is to transform abstract logical element access into specific physical memory access, enabling the soft device memory access instructions to be correctly addressed and executed by the processor. From some embodiments provided in this application, the soft devices in the ladder diagram are logical abstractions oriented towards control logic, and there is a mapping relationship between them and the processor's physical memory addresses. By uniformly managing this mapping through the preset constant table, logical-level element access can be accurately converted into hardware-level memory operations without modifying the instruction format.

[0096] In some embodiments, step S803 involves calculating the address offset difference between the current tag address and the target tag address in the flow control jump instruction, and configuring the end operand of the flow control jump instruction based on the address offset difference to update the flow control jump instruction. It should be noted that in this embodiment, the address offset difference between the current tag address and the target tag address in the flow control jump instruction is calculated, and the end operand of the flow control jump instruction is configured based on the address offset difference to update the flow control jump instruction. The address offset difference refers to the distance between the code location where the jump instruction is located and the jump target code location, and the end operand refers to the operand field in the jump instruction used to specify the jump target. The purpose of this embodiment is to convert the text-based tag name into a relative offset value that the processor can directly recognize, so that the jump instruction can accurately point to the target code location. From some embodiments provided in this application, it can be seen that the conditional jump instructions in the ARM Thumb-2 instruction set usually adopt a relative addressing mode, that is, the jump destination is determined by the offset between the current instruction location and the target location, rather than using an absolute address or tag name. Therefore, it is necessary to replace the symbolic tag with a specific offset value through address calculation so that the flow control instruction can be correctly executed at the hardware level.

[0097] In some embodiments, step S804 involves mapping the soft element memory access instructions to actual memory storage addresses and configuring the end operand for the flow control jump instructions. Then, multiple program assembly codes, the updated soft element memory access instructions, and the updated flow control jump instructions are integrated to obtain a binary executable program.

[0098] It should be noted that in this embodiment, after mapping the soft element memory access instructions to actual memory storage addresses and configuring the end operands for the flow control jump instructions, multiple program assembly codes, updated soft element memory access instructions, and updated flow control jump instructions are integrated to obtain a binary executable program. Integration refers to merging and encapsulating various instruction fragments after address resolution and offset calculation according to the execution order of program logic and memory layout requirements. The purpose of this embodiment is to complete the final output of the compilation process, solidifying the scattered, updated instruction fragments into a unified binary executable file. As can be seen from some embodiments provided in this application, the various program segments generated in the early stage and the instructions that have been decoded and updated need to be organized into a complete program image that conforms to the executable file format of the target processor before it can be loaded into the ARM architecture processor for direct execution. Therefore, the integration operation is a necessary step to bring together all the results of the early processing into the final product, marking the closure of the complete compilation path from the ladder diagram to the binary executable program.

[0099] In some specific embodiments, soft-element memory access instructions and flow control jump instructions are extracted from multiple program assembly codes. Soft-element memory access instructions refer to memory read / write instructions that access ladder diagram soft elements, while flow control jump instructions refer to branch or jump instructions that control the direction of program execution. According to the technical disclosure, most of the assembly code generated during the program instruction mapping stage is already a true instruction that can directly correspond to the ARM Thumb-2 instruction set. However, the two types of instructions involving soft-element memory access and program flow control still retain symbolic representations. The final operand of soft-element memory access instructions exists in the form of address symbols, while the final operand of flow control jump instructions exists in the form of label names. The purpose of this embodiment is to identify pseudo-instructions that have not yet completed address resolution from the generated assembly code, thus determining the specific processing objects for subsequent address translation operations. From the embodiments of this application, in the code directly mapped in the early stages, only instructions involving external memory addressing and program flow jumps cannot have their final values ​​determined at that time. Therefore, they must be identified through extraction operations for targeted address resolution.

[0100] In this embodiment, soft-element memory access instructions are mapped to actual memory storage addresses according to a preset constant table to update the soft-element memory access instructions. The preset constant table is a pre-configured data structure that stores multiple candidate memory storage addresses, each address corresponding to the actual location of a specific soft-element in physical memory. During the generation phase, soft-element memory access instructions use symbolic addresses as the final operands, such as the address symbol corresponding to a contact read bit or function block parameter. Mapping the soft-element memory access instructions to actual memory storage addresses means replacing the symbolic addresses in the instructions with the corresponding physical address values ​​in the preset constant table. This embodiment transforms abstract logical element access into concrete physical memory access, enabling the processor to correctly address and execute soft-element memory access instructions. From this embodiment, the soft elements in the ladder diagram are logical abstractions oriented towards control logic, and there is a mapping relationship between them and the processor's physical memory addresses. By uniformly managing this mapping through the preset constant table, logical-level element access can be accurately converted into hardware-level memory operations without modifying the instruction format.

[0101] In this embodiment, the address offset difference between the current tag address and the target tag address in the flow control jump instruction is calculated, and the end operand of the flow control jump instruction is configured based on the address offset difference to update the flow control jump instruction. The current tag address refers to the code location where the jump instruction itself is located, and the target tag address refers to the code location where the jump destination is located. The address offset difference is the distance between the two. According to the technical disclosure, the end operand of the jump instruction exists in the form of a tag name during the generation stage, which needs to be replaced with the jump offset difference. The purpose of this embodiment is to convert the text-based tag name into a relative offset value that the processor can directly recognize, so that the jump instruction can accurately point to the target code location. From this embodiment, it can be seen that the conditional jump instructions in the ARM Thumb-2 instruction set adopt a relative addressing method, that is, the jump destination is determined by the offset between the current instruction location and the target location, rather than using an absolute address or tag name. Therefore, it is necessary to replace the symbolic tag with a specific offset value through address calculation so that the flow control instruction can be correctly executed at the hardware level.

[0102] In this embodiment, after mapping soft element memory access instructions to actual memory storage addresses and configuring end operands for flow control jump instructions, multiple program assembly codes, updated soft element memory access instructions, and updated flow control jump instructions are integrated to obtain a binary executable program. Integration refers to merging and encapsulating the instructions after address resolution and offset calculation with the previously generated true instructions according to the execution order of program logic and memory layout requirements. The purpose of this embodiment is to complete the final output of the compilation process, solidifying the scattered, updated instruction fragments into a unified binary executable file. As seen in this embodiment, the various program segments generated in the early stages and the decoded and updated instructions need to be organized into a complete program image that conforms to the executable file format of the target processor before it can be loaded into the ARM architecture processor for direct execution. Therefore, the integration operation is a necessary step to bring together all the results of the early processing into the final product, marking the closure of the complete compilation path from ladder diagram to binary executable program.

[0103] Reference Figure 9 , Figure 9 This illustration shows the hardware structure of an electronic device according to another embodiment. The electronic device may include: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 902 can be implemented as a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901 using the control program compilation method of the embodiments of this application. The input / output interface 903 is used to implement information input and output; The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904); The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0104] This application also provides a computer program product, which includes a computer program. A processor of a computer device reads and executes the computer program, causing the computer device to perform the control program compilation method described above.

[0105] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in this disclosure and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “including,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatuses.

[0106] It should be understood that in this disclosure, "at least one item" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0107] It should be understood that in the description of the embodiments of this application, "multiple" means two or more, "greater than", "less than", "exceeding" etc. are understood to exclude the number itself, and "above", "below", "within" etc. are understood to include the number itself.

[0108] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0109] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0110] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0111] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this disclosure. The aforementioned storage medium may include: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code.

[0112] It should also be understood that the various implementation methods provided in this application can be combined arbitrarily to achieve different technical effects.

[0113] The above is a detailed description of the embodiments of this disclosure. However, this disclosure is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this disclosure. All such equivalent modifications or substitutions are included within the scope defined by the claims of this disclosure.

Claims

1. A method for compiling a control program, characterized in that, include: Obtain the ladder diagram program to be compiled; wherein the ladder diagram program contains various types of component representation graphics; The component representation graphics in the ladder diagram program are identified to obtain various types of component unit objects and the component arrangement characteristics of each component representation graphic in the ladder diagram program; Based on the component arrangement characteristics in the ladder diagram program, the program logic characteristics between each component unit object are determined. Based on the program logic characteristics between each of the component unit objects, the corresponding component unit objects are mapped to the target two-dimensional array; Based on the element unit objects in the target two-dimensional array and the program logic features, a tree-shaped program structure data is generated. Based on the tree-shaped program structure data, a program instruction mapping operation is performed to obtain multiple program assembly codes corresponding to the tree-shaped program structure data; The assembly code of the multiple programs is decoded to obtain a binary executable program.

2. The method according to claim 1, characterized in that, The step of determining the program logic features between each component unit object based on the component arrangement features in the ladder diagram program according to the component representation graphics of each component includes: Based on the element arrangement characteristics of each element representation graphic in the ladder diagram program, determine the row connection state, column connection state, graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost column vertical line and the rightmost column vertical line. Based on the row connection state and column connection state of each element representation graphic, the graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost column vertical line and the rightmost column vertical line, the program logic features between each element unit object are determined.

3. The method according to claim 2, characterized in that, The step of determining the program logic features between each element unit object based on the row connection state, column connection state, graphic arrangement position corresponding to each element representation graphic, and the length relationship between the leftmost and rightmost vertical lines of each element representation graphic includes: When there are rows that do not have vertical lines connecting downwards, it is determined that the corresponding element unit object has the program logic characteristics of a container structure. When there is an output coil or an executable function block, and there is a set of row coordinates to the right of the leftmost column vertical line that is not connected to the next row, it is determined that the corresponding element unit object has the program logic feature of a branch structure. When there are equal-length leftmost and rightmost vertical lines and no other logical elements on both sides, it is determined that the corresponding element unit object has the program logic characteristics of an OR logic structure. When there is a column with only a single horizontal line or a single logical element connected left and right, it is determined that the corresponding element unit object has the program logic characteristics of the logical structure. When only a single logical element is contained, the corresponding element unit object is determined to have the program logic characteristics of a unit structure.

4. The method according to claim 1, characterized in that, The step of generating the tree-shaped program structure data based on each element unit object in the target two-dimensional array and the program logic features includes: In the target two-dimensional array, the program logic features corresponding to each of the component unit objects are sorted out; Based on the program logic features described above, each component unit object is recursively divided into various tree-shaped node data. The tree-shaped program structure data is generated based on the various tree node data.

5. The method according to claim 4, characterized in that, The various tree-shaped node data include container child node data, common condition child node data, branch output child node data, parallel child node data, serial child node data, and unit child node data. Based on the program logic features, each component unit object is recursively divided into various tree-shaped node data, including: For the program logic features with container structure, the corresponding element unit objects are divided into mutually independent container sub-node data; For the program logic feature with a branch structure, the corresponding component unit object is divided into the common condition sub-node data and multiple branch output sub-node data; For the program logic features with OR logic structure, the corresponding element unit object is divided into multiple parallel sub-node data; For the program logic features with logical structure, the corresponding element unit object is divided into multiple serial sub-node data; For the program logic feature with a unit structure, the corresponding element unit object is determined as the unit sub-node data.

6. The method according to claim 5, characterized in that, The step of performing a program instruction mapping operation based on the tree-shaped program structure data to obtain multiple program assembly codes corresponding to the tree-shaped program structure data includes: For a container structure that contains container child node data in the tree-shaped program structure data, an independent container program segment is generated according to each container child node data. For the branch structure that includes the common condition sub-node data and the branch output sub-node data in the tree program structure data, multiple registers are called as logical scheduling registers, and corresponding condition judgment program segments and condition response program segments are generated based on the cooperation of each logical scheduling register. For the tree-shaped program structure data containing multiple parallel child node data or logical structures, multiple registers are called as logical scheduling registers, and corresponding logical response program segments are generated based on the cooperation of each logical scheduling register. For the logical structure containing multiple serial child node data in the tree program structure data, multiple registers are called as logical scheduling registers, and corresponding logical response program segments are generated based on the cooperation of each logical scheduling register. For the tree-shaped program structure data containing unit sub-node data, corresponding unit function program segments are generated according to the unit type of the unit sub-node data; By integrating the container program segment, the condition determination program segment, the condition response program segment, the OR logic response program segment, the AND logic response program segment, and the unit function program segment, multiple program assembly codes are obtained.

7. The method according to claim 1, characterized in that, The process of decoding multiple sets of assembly code to obtain a binary executable program includes: Soft component memory access instructions and flow control jump instructions are extracted from multiple program assembly codes; wherein, the flow control jump instructions include the current tag address and the target tag address; The soft device memory access instructions are mapped to actual memory storage addresses according to a preset constant table to update the soft device memory access instructions; wherein, the preset constant table stores a plurality of pre-configured candidate memory storage addresses; Calculate the address offset difference between the current tag address and the target tag address in the flow control jump instruction, and configure the end operand of the flow control jump instruction based on the address offset difference to update the flow control jump instruction; After mapping the soft element memory access instructions to the actual memory storage address and configuring the end operand for the flow control jump instructions, the multiple program assembly codes, the updated soft element memory access instructions, and the updated flow control jump instructions are integrated to obtain the binary executable program.

8. An electronic device, characterized in that, include: A memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the control program compilation method as described in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The storage medium stores a program, which is executed by a processor to implement the control program compilation method as described in any one of claims 1 to 7.

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