A multi-channel memory card parallel test system and method based on FPGA
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NEUMONDA TECHNOLOGY (JINAN) CO LTD
- Filing Date
- 2026-07-07
- Publication Date
- 2026-08-04
AI Technical Summary
[0005]但是，这种方式仅设计为针对单张存储卡进行测试
本发明通过部署多个完全相同的测试通道并采用全局共享的中央资源池（如中央译码及分发模块、可编程时钟管理模块等）进行协同，实现了对多张存储卡的真正并行测试。在理想情况下，系统对多张卡完成相同测试项的总耗时，接近于单通道系统测试一张卡的耗时，使得整体测试吞吐量明显提升，避免了简单复制多套独立测试单元所带来的资源冗余。这从根本上解决了背景技术中单通道测试系统在面对批量卡校验时效率低下的瓶颈问题，尤其适用于生产线终端测试与大规模来料检验，可大幅缩短测试周期，降低时间成本。
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Figure CN122507569A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of multi-channel memory card testing technology, and in particular to a parallel testing system and method for multi-channel memory cards based on FPGA. Background Technology
[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.
[0003] With the increasing demands for storage capacity and performance from mobile devices, IoT terminals, and data centers, embedded memory cards such as SD cards and eMMC are being used more and more widely. Their performance and reliability directly affect the stability of the entire system. Therefore, efficient and comprehensive automated testing of memory cards is crucial in the manufacturing, incoming material inspection, and R&D verification stages.
[0004] Currently, most FPGA-based memory card testing solutions employ dedicated FPGA-based testing systems. For example, test circuits are built within the FPGA, including modules for command control, data processing, and PRBS (pseudo-random binary sequence) pattern generation. Controlled by a host computer, these systems can perform functional instruction testing and bit error rate testing on a single SD card. This approach leverages the parallel processing capabilities of the FPGA, achieving a higher testing speed and greater flexibility compared to purely software-based solutions.
[0005] However, this method is only designed for testing a single memory card. When facing batch verification on the production line or scenarios in R&D where multiple cards need to be compared for consistency, it can only rely on manually replacing the cards under test one by one or deploying multiple independent devices, resulting in a high cost due to the linear increase in test throughput, and it cannot achieve true synchronous parallel testing and instantaneous state comparison.
[0006] Furthermore, the system architecture serves a single card under test, and the FPGA's internal resources (such as clock management, data buffer memory, and command generation logic) cannot be shared among multiple test tasks. Simply replicating multiple sets of this architecture to achieve multi-card testing would result in a serious waste of FPGA logic, storage, and interface resources, and each test unit would be independent of each other, lacking collaborative scheduling capabilities. Summary of the Invention
[0007] To address the aforementioned issues, this invention proposes a parallel testing system and method for multi-channel memory cards based on FPGA. This system can simultaneously interface with multiple memory cards, achieve intelligent scheduling and sharing of test resources, and support highly efficient and highly integrated testing with flexible parallel and comparative testing modes.
[0008] In some implementations, the following technical solutions are adopted: A parallel testing system for multi-channel memory cards based on FPGA, comprising: The main control processor is configured to receive test firmware commands and send them to the central decoding and distribution module; The central decoding and distribution module is configured to communicate with the main control processor, receive test commands issued by the main control processor, decode them, generate command frames and channel enable masks, and distribute them to each controller. Multiple controllers, each connected to a memory card, are configured to determine whether they are enabled based on the received command frame and channel enable mask. If they are enabled, they send commands to the memory card via physical pins and receive responses from the memory card. The programmable clock management module is configured to receive frequency configuration commands from the central decoding and distribution module, output a clock, and drive the clock input ports of all controllers through a clock tree formed by the global clock buffer of the FPGA.
[0009] As a further option, it also includes: The central test data distributor is configured to asynchronously FIFO-cached test data in the test firmware; in response to the data synchronization write command, it reads the cached data through the data stream scheduler and fills the data transmission buffer of each target channel controller in a round-robin manner; so that each controller writes the data in its respective buffer to the corresponding memory card after receiving the transmission start pulse.
[0010] The data stream scheduler is configured to respond to data requests from each channel using a round-robin algorithm, and to schedule cached data in the central test data distributor to the target channel in an orderly manner.
[0011] As a further option, the central test data distributor is implemented using the block random access memory of the FPGA.
[0012] As a further solution, the central decoding and distribution module includes: The instruction decoding unit is configured to communicate with the main control processor via the AXI interface, receive test instructions issued by the main control processor, and decode them.
[0013] The protocol command frame generation unit is configured to receive decoded instructions and convert them into commands that conform to the memory card protocol requirements; The channel address mapping table is configured to store the relative address of the memory card corresponding to each controller; The channel enable mask generator is configured to generate a corresponding channel enable mask signal based on the target channel configuration issued by the software.
[0014] As a further embodiment, the controller includes: The command control unit includes a command shift register and a response receiving state machine. The command shift register is used to shift the command frame and enable mask from the central decoding and distribution module to the CMD bus when it is enabled. The response receiving state machine is used to receive different responses returned by the SD card and verify whether the CRC at the end of the response is correct. The data transceiver unit includes parallel-to-serial conversion and shift logic and CRC16 verification logic, which is used to connect to the data pins of the memory card through a physical interface to realize data transmission and reception verification.
[0015] As a further solution, the programmable clock management module supports dynamic frequency switching triggered by software.
[0016] In other embodiments, the following technical solutions are adopted: A test method utilizing the aforementioned FPGA-based multi-channel memory card parallel test system includes: In response to the system initialization command issued by the test firmware, all memory cards synchronously enter the ready state; When performing a memory card synchronization data write test, the test data of the test firmware is written to the main control processor and the central test data distributor respectively; In response to the synchronous write test command issued by the test firmware, the central decoding and distribution module sends a set block address command to all controllers and specifies the test start address; The central decoding and distribution module issues write commands and channel enable masks; After receiving the write command, the data stream scheduler determines the target channel based on the channel enable mask, retrieves data from the central test data distributor, and sequentially fills the data transmission buffer of each target channel controller in a polling manner. After each target channel controller finishes receiving data in its data buffer, it responds to the transmit start pulse command issued by the central decoding and distribution module, writes the data in its data buffer to the corresponding memory card, and summarizes and reports the write status.
[0017] As a further solution, when performing memory card consistency testing, in response to the synchronous read test command issued by the test firmware, the central decoding and distribution module sends read commands and unified address parameters to all target channel controllers in parallel. All target channel controllers receive the return data from the corresponding memory cards and perform data conversion; Once a piece of data has been read, the central decoding and distribution module reads out the data generated by multiple channels in sequence and compares it with the data generated by the hardware. Based on the comparison results, latch the current erroneous block number and word offset within the block, and summarize and report them; The data generated by the hardware is generated based on the same logic as the test data of the test firmware.
[0018] As a further solution, in response to the system initialization command issued by the test firmware, all memory cards synchronously enter the ready state, specifically as follows: The main control processor transmits the initialization command to the central decoding and distribution module; the central decoding and distribution module simultaneously sends the reset command frame and the full-channel enable mask to all channel controllers; all channel controllers execute the reset command in parallel, putting their respective memory cards into an idle state; The central decoding and distribution module sequentially generates and broadcasts a sequence of instructions for checking voltage and activating card initialization; all channel controllers continue to execute the corresponding instructions in parallel. The central decoding and distribution module sends a CID acquisition command, and all memory cards return their respective CID information to the corresponding channel controller via a response; each channel controller transmits the received CID response back to the central decoding and distribution module; so as to record the CID information in the channel address mapping table and assign a software-managed logical number to each memory card; The central decoding and distribution module sends an RCA acquisition command, and all memory cards return their respective RCA information to the corresponding channel controller via a response; each channel controller transmits the received RCA back to the central decoding and distribution module to store the mapping relationship between channel number and RCA in the channel address mapping table; At this point, all memory cards are simultaneously ready.
[0019] In other embodiments, the following technical solutions are adopted: An FPGA chip includes the aforementioned FPGA-based multi-channel memory card parallel test system.
[0020] Compared with the prior art, the beneficial effects of the present invention are: This invention achieves true parallel testing of multiple memory cards by deploying multiple identical test channels and coordinating them using a globally shared central resource pool (such as a central decoding and distribution module and a programmable clock management module). Ideally, the total time the system takes to complete the same test items on multiple cards is close to the time required for a single-channel system to test one card, significantly improving overall test throughput and avoiding resource redundancy caused by simply replicating multiple independent test units. This fundamentally solves the bottleneck problem of low efficiency in single-channel test systems when dealing with batch card verification in the background technology, and is particularly suitable for production line terminal testing and large-scale incoming material inspection, significantly shortening the testing cycle and reducing time costs.
[0021] Other features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of the structure of a multi-channel memory card parallel testing system based on FPGA in an embodiment of the present invention. Detailed Implementation
[0023] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.
[0024] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0025] Terminology Explanation: CID: is the identification number of the memory card (globally unique and assigned at the factory).
[0026] RCA: is the temporary communication address of the memory card (dynamically generated, valid only for this power-on).
[0027] Verilog is a hardware description language used for the design, modeling, and verification of digital systems, and is widely used in the development of field-programmable gate arrays (FPGAs).
[0028] FW: Firmware refers to the low-level software stored in hardware devices (such as routers, microcontrollers, mobile phones, hard drives, and smart home appliances), responsible for directly controlling and driving the hardware. Test firmware refers to firmware versions specifically used for testing.
[0029] AXI interface: full name is Advanced eXtensible Interface.
[0030] FIFO: usually refers to a first-in, first-out data buffer or queue; SD bus: This is the physical communication interface between the host and the SD card; CMD bus: This is a signal line in the SD bus specifically used for transmitting commands and responses.
[0031] Example 1 In one or more embodiments, a parallel testing system for multi-channel memory cards based on a Field Programmable Gate Array (FPGA) is disclosed. All logic functions of the system are implemented within a single FPGA device, combined with... Figure 1 Specifically, it includes a main control processor, a central decoding and distribution module, a programmable clock management module, a central test data distributor, a data stream scheduler, and multiple controllers, each of which is connected to a memory card.
[0032] Specifically, the main control processor is implemented based on the Xilinx MicroBlaze soft-core processor, serving as the system's software execution core and overall scheduler. The test firmware is written and compiled on the development host using Vitis software and then downloaded to the main control processor for execution. The main control processor is connected to the central decoding and distribution module via an on-chip bus; the on-chip bus uses the Advanced eXtensible Interface (AXI) bus protocol to enable register read / write and data transfer between the main control processor and various hardware logic modules. The main control processor is configured to receive test firmware commands and distribute them to the central decoding and distribution module.
[0033] The central decoding and distribution module, implemented in Verilog hardware description language, is the core of the system's hardware scheduling. It is configured to communicate with the main control processor, receive test commands from the main control processor, decode them, generate command frames and channel enable masks, and distribute them to each controller.
[0034] In this embodiment, the central decoding and distribution module specifically includes: The instruction decoding unit is configured to communicate with the main control processor via the AXI interface, receive test instructions issued by the main control processor, and decode them.
[0035] After the software design and parameter configuration of the test firmware are completed, the command is transmitted to the FPGA via the AXI protocol. At this time, the received command data is in the AXI protocol. The FPGA's instruction decoding unit extracts useful data from it, such as the command number and command parameters, and then uses it for subsequent command generation.
[0036] The protocol command frame generation unit is signal-connected to the instruction decoding unit and is configured to receive decoded instructions and convert them into commands that conform to the memory card protocol requirements. The data length of the command frame is 48 bits, including a start bit, command identifier (CMD ID), command parameters, a 7-bit cyclic redundancy check (CRC) check code, and an end bit.
[0037] The channel address mapping table is configured to store the relative address (RCA, Relative Card Address) of the memory card corresponding to each controller, and is connected to the protocol command frame generation unit signal to provide address parameters for command frame generation.
[0038] The channel enable mask generator, connected to the instruction decoding unit, is configured to generate the corresponding channel enable mask signal based on the target channel configuration issued by the software.
[0039] The channel enable mask signal is an 8-bit mask signal. When the mask signal is 8'b11111111, it means that the command is broadcast to all eight channels. When the mask signal is 8'b00000001, it means that the command is sent only to channel 0.
[0040] The central decoding and distribution module is connected to each controller signal, sends command frames and channel enable masks to the controller, and receives status information reported by the controller.
[0041] The programmable clock management module is signal-connected to the central decoding and distribution module to receive frequency configuration commands. The programmable clock management module is configured to receive the frequency configuration commands issued by the central decoding and distribution module, output a clock, and drive it to the clock input ports of all controllers through a clock tree composed of the FPGA's global clock buffer (BUFG).
[0042] The programmable clock management module utilizes the FPGA's internal Mixed-Mode Clock Manager (MMCM) to generate a high-frequency reference clock of 208MHz. The frequency divider unit receives the division factor configuration signal from the central decoding and distribution module, and divides the high-frequency reference clock according to the division factor to output a low-frequency clock. The low-frequency clock ranges from 400kHz to 25MHz and is used for memory card initialization and low-speed testing scenarios. The programmable clock management module supports software-triggered dynamic frequency switching, meaning the main control processor can trigger the programmable clock management module to perform dynamic frequency switching via the on-chip bus. The switched clock signal is synchronously driven to the clock inputs of all controllers through the clock tree, ensuring the synchronization and consistency of the clock signals across all channels.
[0043] The central test data distributor is an asynchronous first-in-first-out (FIFO) buffer implemented by the FPGA's block random access memory (BRAM). The data width is 32 bits, and the depth can be configured via the on-chip bus through the main control processor. It serves as a shared test data source for the entire system. The central test data distributor is configured to asynchronously buffer test data in the test firmware using FIFO. In response to the data synchronization write command, the buffered data is read by the data stream scheduler and sequentially filled into the data transmission buffer of each target channel controller in a polling manner, so that each controller writes the data in its respective buffer to the corresponding memory card after receiving the transmission start pulse.
[0044] The data flow scheduler connects the central test data distributor to each controller. It uses a round-robin algorithm to respond to data requests from each channel and schedules the cached data in the central test data distributor to the target channel in an orderly manner. When multiple controllers send data requests at the same time, the data flow scheduler fills the data sending buffer of each controller in the order of the round-robin to ensure the orderliness and fairness of multi-channel data access and avoid access conflicts.
[0045] Each controller is connected to a memory card. Each controller is configured to determine whether it is enabled based on the received command frame and channel enable mask. If it is enabled, it sends commands to the memory card through physical pins and receives the response from the memory card.
[0046] Each controller contains a command control unit and a data transceiver unit. The command control unit is signal-connected to the central decoding and distribution module, and the data transceiver unit is data-connected to the data stream scheduler. The controller's physical interface is electrically connected to the command control unit and the data transceiver unit, and also electrically connected to the corresponding memory card.
[0047] In a specific implementation, the command control unit includes a command shift register and a response receiving state machine. The command shift register receives command frames and channel enable masks issued by the central decoding and distribution module. If it is enabled, it sends commands through the CMD physical pin. The response receiving state machine receives responses returned by the memory card through the CMD physical pin (which can be divided into long responses of 136 bits and short responses of 48 bits, depending on the bit width), and verifies the 7-bit cyclic redundancy check code in the response to confirm the correctness of the command transmission.
[0048] The data transceiver unit includes parallel-to-serial conversion and shift logic, as well as Cyclic Redundancy Check (CRC16) logic. During a write operation, the data transceiver unit obtains 32-bit parallel data from the data stream scheduler, converts it from parallel to serial, and then serially sends it to the corresponding memory card as a 4-bit wide data stream through the data pins (DAT[3:0] pins) of the physical interface. During a read operation, the data transceiver unit reassembles the 4-bit wide serial data stream received from the data pins into a 32-bit data word after serial-to-parallel conversion, and performs a 16-bit cyclic redundancy check on the 32-bit data word to verify the integrity of the read data.
[0049] In this embodiment, all functional modules of the system are integrated into a single FPGA device, realizing a highly integrated multi-channel parallel test architecture. The main control processor serves as the software execution core, the central decoding and distribution module serves as the hardware scheduling core, the programmable clock management module provides a globally unified clock, the central test data distributor and data stream scheduler serve as shared data resources, and multiple controllers serve as parallel execution units. All modules work together to achieve efficient parallel testing of multiple memory cards.
[0050] This embodiment utilizes a globally shared central resource pool (such as a single clock management, central decoding and distribution, and a shared data buffer FIFO) to serve all channels, supplemented by efficient arbitration and distribution logic, avoiding resource redundancy caused by simply replicating multiple independent test units. Compared to deploying N sets of single-channel test systems as described in the background technology, this embodiment significantly saves logic resources, block RAM (BRAM), and clock management units within the FPGA. While achieving the same channel scale, it reduces hardware complexity and power consumption, and improves the utilization efficiency of FPGA resources and the overall system integration.
[0051] Thanks to the multiple parallel testing modes supported by the central decoding and distribution module, this embodiment can execute complex testing scenarios that are impossible for a single-channel system, such as: Synchronous consistency test: It can apply the same command and data stimulus to all channels synchronously and compare the response and return data of each channel in real time, which can quickly and accurately screen out memory cards with abnormal performance or poor consistency.
[0052] This embodiment of the FPGA-based multi-channel memory card parallel test system effectively overcomes the technical defects of existing single-channel test systems, such as low efficiency, poor scalability, and lack of test functions in general controllers, through architectural innovation. It provides a high-efficiency, high-resource-utilization, highly flexible, and easy-to-manage multi-channel parallel test solution.
[0053] Example 2 Based on the FPGA-based multi-channel memory card parallel test system in Embodiment 1, a test method for the FPGA-based multi-channel memory card parallel test system is disclosed in one or more embodiments, specifically including a system initialization process, a synchronous data write test process, and a synchronous read and centralized comparison process.
[0054] As a specific implementation method, the purpose of initialization is to put all memory cards (hereinafter referred to as SD cards) into the transmission state and obtain their identity information; this reflects the parallel scheduling capability of the test system.
[0055] I. The specific initialization process is as follows: Step S101: Test firmware issues system initialization command. After receiving the system initialization command, the main control processor transmits the initialization command to the central decoding and distribution module via the on-chip bus.
[0056] Step S102: The central decoding and distribution module simultaneously sends the reset command frame (CMD0) and the full-channel enable mask (8'b11111111) to all channel controllers.
[0057] Step S103: All channel controllers execute the reset instruction (CMD0) in parallel, sending a reset command frame to the corresponding memory card through their respective physical pins, so that their respective memory cards enter the idle state.
[0058] Step S104: The central decoding and distribution module sequentially generates and broadcasts the voltage check (CMD8) and activation card (CMD55+ACMD41) initialization instruction sequence; the channel enable mask keeps all channels enabled; all channel controllers continue to execute the above initialization instruction sequence in parallel to complete the voltage verification and activation operation of the memory card.
[0059] Step S105: The central decoding and distribution module sends a Card Identification (CID) command (CMD2); all memory cards return their respective CID information to the corresponding channel controller via a response; each channel controller transmits the received CID response back to the central decoding and distribution module; the channel address mapping table records the CID information and assigns a software-managed logical number to each memory card.
[0060] Step S106: The central decoding and distribution module sends a Relative Card Address (RCA) acquisition command (CMD3); all memory cards return their respective RCA information to the corresponding channel controller via a response; each channel controller transmits the received RCA back to the central decoding and distribution module; the channel address mapping table stores the mapping relationship between channel number and RCA; At this point, all memory cards have entered the ready state simultaneously. The system has completed the parallel enumeration and addressing settings of all memory cards. The entire initialization process takes almost the same amount of time as the initialization time of a single memory card.
[0061] II. The specific test process for synchronous data writing is as follows: Step S201: When performing the memory card synchronous data write test, the test data of the test firmware is written to the main control processor and the central test data distributor respectively; the central test data distributor stores the data to be tested in an asynchronous first-in-first-out buffer implemented by BRAM with a data width of 32 bits, as the data source for this write test.
[0062] Step S202: The test firmware sends a synchronous write test command to the central decoding and distribution module through the main control processor; in response to the synchronous write test command, the central decoding and distribution module sends a set block address command (CMD24 / CMD25) to all controllers, specifying a unified test start address, and writes data from the set sector. The command control unit of each target channel controller executes the set block address command when its corresponding mask bit is enabled.
[0063] Step S203: The central decoding and distribution module sends write commands and channel enable masks to each target channel controller.
[0064] Step S204: After receiving the write command, the data flow scheduler determines the target channel based on the channel enable mask, retrieves data from the central test data distributor, and fills the data transmission buffer of each target channel controller in a round-robin manner. When multiple target channel controllers issue data requests at the same time, the data flow scheduler fills the data transmission buffer of each target channel controller in a round-robin order to ensure the orderly distribution of data.
[0065] Step S205: After the data buffer of each target channel controller has finished receiving data, in response to the transmit start pulse (START_PULSE) command issued by the central decoding and distribution module, each target channel controller writes the data in its respective data buffer to its corresponding memory card through the DAT[3:0] pins of its respective physical interface in the form of a 4-bit wide data stream, realizing true synchronous parallel writing of multiple channels.
[0066] Step S206: After the write operation is completed, each channel controller will summarize the write status (including success, cyclic redundancy check error or timeout) and report it to the main control processor through the on-chip bus; the main control processor will report the write operation status information to the test firmware.
[0067] III. The synchronous readout and centralized comparison process is used to verify whether multiple memory cards produce completely consistent data output under the same stimulus, thus realizing memory card consistency testing; the specific implementation process is as follows: Step S301: The test firmware sends a synchronous read test command to the central decoding and distribution module through the main control processor, specifying the target channel and the starting address to be read; the starting address for reading is the same as the starting address used for writing test to ensure the correspondence between read and write data.
[0068] Step S302: In response to the synchronous read test command, the central decoding and distribution module sends read commands (CMD17 / CMD18) and unified address parameters to all target channel controllers in parallel; the command control units of all target channel controllers send read commands to their respective memory cards in parallel.
[0069] Step S303: All target channel controllers receive the return data from the corresponding memory cards; the data transceiver units of each target channel controller start the receiving logic in parallel, combine the serial 4-bit wide data stream into a 32-bit data word after serial-to-parallel conversion, and perform data conversion; the data transceiver unit performs a 16-bit cyclic redundancy check on the 32-bit data word to verify data integrity.
[0070] Step S304: After a block of data is read, the central decoding and distribution module coordinates the sequential reading of buffered data from multiple channels and compares it directly with the reference data generated by the hardware in this module. If the comparison is inconsistent, an error message is output.
[0071] The reference data generated by the central decoding and distribution module hardware and the test data of the test firmware are generated based on the same logic.
[0072] In this embodiment, the reference data is generated in real time by the hardware logic of the central decoding and distribution module. Each channel does not require an additional reference data cache memory. It receives 32-bit data and compares it with the hardware-generated data. After the comparison, the data is discarded and not retained, thus eliminating the need for a cache module and saving FPGA internal block memory resources.
[0073] Step S305: Based on the comparison results, once any channel has a mismatch on any data word, the error status register of the channel controller is immediately set; the error location counter latches the current faulty block number and the word offset within the block, and waits for the entire read operation to be completed before reporting it.
[0074] After the read operation is completed, the main control processor collects the read / write status, error flags, and error location information of all channel controllers, packages them, and reports them to the test firmware. By reading the error location information, the test firmware can accurately locate which memory card has a data error in which storage location.
[0075] The method in this embodiment can simultaneously interface with multiple memory cards, realize intelligent scheduling and sharing of test resources, and support high-efficiency and high-integration testing with flexible parallel and comparative test modes. Under the premise of achieving the same channel scale, it reduces hardware complexity and power consumption, and improves the utilization efficiency of FPGA resources and the overall integration of the system.
[0076] Example 3 In one or more embodiments, an FPGA chip is disclosed, which integrates the FPGA-based multi-channel memory card parallel test system described in Embodiment 1.
[0077] The FPGA chip internally implements a main control processor, a central decoding and distribution module, a programmable clock management module, a central test data distributor, a data stream scheduler, and multiple controllers. All modules are integrated into the programmable logic resources of the FPGA chip.
[0078] FPGA chips can be used directly as the core component of memory card testing equipment. They can be electrically connected to multiple memory cards through an external physical interface to achieve highly integrated multi-channel parallel testing functions.
[0079] Compared to the approach of using multiple discrete chips to build a test system, the FPGA chip in this embodiment integrates all test logic into a single device, which significantly reduces the size, power consumption and hardware complexity of the test equipment. At the same time, through the reconfigurable characteristics of the FPGA, the test firmware and hardware logic can be flexibly upgraded to adapt to the test requirements of different types of memory cards.
[0080] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.
Claims
1. A parallel testing system for multi-channel memory cards based on FPGA, characterized in that, include: The main control processor is configured to receive test firmware commands and send them to the central decoding and distribution module; The central decoding and distribution module is configured to communicate with the main control processor, receive test commands issued by the main control processor, decode them, generate command frames and channel enable masks, and distribute them to each controller. Multiple controllers, each connected to a memory card, are configured to determine whether they are enabled based on the received command frame and channel enable mask. If they are enabled, they send commands to the memory card via physical pins and receive responses from the memory card. The programmable clock management module is configured to receive frequency configuration commands from the central decoding and distribution module, output a clock, and drive the clock input ports of all controllers through a clock tree formed by the global clock buffer of the FPGA.
2. The FPGA-based multi-channel memory card parallel testing system as described in claim 1, characterized in that, Also includes: The central test data distributor is configured to perform asynchronous FIFO data caching of test data in the test firmware; In response to the data synchronization write command, the data stream scheduler reads the cached data and fills it into the data transmission buffer of each target channel controller in a round-robin manner; so that each controller writes the data in its buffer to the corresponding memory card after receiving the transmission start pulse. The data stream scheduler is configured to respond to data requests from each channel using a round-robin algorithm, and to schedule cached data in the central test data distributor to the target channel in an orderly manner.
3. The FPGA-based multi-channel memory card parallel testing system as described in claim 2, characterized in that, The central test data distributor is implemented using the block random access memory of the FPGA.
4. The FPGA-based multi-channel memory card parallel testing system as described in claim 1, characterized in that, The central decoding and distribution module includes: The instruction decoding unit is configured to communicate with the main control processor via the AXI interface, receive test instructions issued by the main control processor, and decode them. The protocol command frame generation unit is configured to receive decoded instructions and convert them into commands that conform to the memory card protocol requirements; The channel address mapping table is configured to store the relative address of the memory card corresponding to each controller; The channel enable mask generator is configured to generate a corresponding channel enable mask signal based on the target channel configuration issued by the software.
5. The FPGA-based multi-channel memory card parallel testing system as described in claim 1, characterized in that, The controller includes: The command control unit includes a command shift register and a response receiving state machine. The command shift register is used to shift the command frame and enable mask from the central decoding and distribution module to the CMD bus when it is enabled. The response receiving state machine is used to receive different responses returned by the SD card and verify whether the CRC at the end of the response is correct. The data transceiver unit includes parallel-to-serial conversion and shift logic and CRC16 verification logic, which is used to connect to the data pins of the memory card through a physical interface to realize data transmission and reception verification.
6. The FPGA-based multi-channel memory card parallel testing system as described in claim 1, characterized in that, The programmable clock management module supports dynamic frequency switching triggered by software.
7. A test method for a parallel test system for multi-channel memory cards based on FPGA as described in claim 2, characterized in that, include: In response to the system initialization command issued by the test firmware, all memory cards synchronously enter the ready state; When performing a memory card synchronization data write test, the test data of the test firmware is written to the main control processor and the central test data distributor respectively; In response to the synchronous write test command issued by the test firmware, the central decoding and distribution module sends a set block address command to all controllers and specifies the test start address; The central decoding and distribution module issues write commands and channel enable masks; After receiving the write command, the data stream scheduler determines the target channel based on the channel enable mask, retrieves data from the central test data distributor, and sequentially fills the data transmission buffer of each target channel controller in a polling manner. After each target channel controller finishes receiving data in its data buffer, it responds to the transmit start pulse command issued by the central decoding and distribution module, writes the data in its data buffer to the corresponding memory card, and summarizes and reports the write status.
8. The test method as described in claim 7, characterized in that, During memory card conformance testing, in response to the synchronous read test command issued by the test firmware, the central decoding and distribution module sends read commands and unified address parameters to all target channel controllers in parallel. All target channel controllers receive the return data from the corresponding memory cards and perform data conversion; Once a piece of data has been read, the central decoding and distribution module reads out the data generated by multiple channels in sequence and compares it with the data generated by the hardware. Based on the comparison results, latch the current erroneous block number and word offset within the block, and summarize and report them; The data generated by the hardware is generated based on the same logic as the test data of the test firmware.
9. The test method as described in claim 7, characterized in that, In response to the system initialization command issued by the test firmware, all memory cards synchronously enter the ready state, specifically as follows: The main control processor transmits the initialization command to the central decoding and distribution module; the central decoding and distribution module simultaneously sends the reset command frame and the full-channel enable mask to all channel controllers; all channel controllers execute the reset command in parallel, putting their respective memory cards into an idle state; The central decoding and distribution module sequentially generates and broadcasts a sequence of instructions for checking voltage and activating card initialization; all channel controllers continue to execute the corresponding instructions in parallel. The central decoding and distribution module sends a CID acquisition command, and all memory cards return their respective CID information to the corresponding channel controller via a response; each channel controller transmits the received CID response back to the central decoding and distribution module; so as to record the CID information in the channel address mapping table and assign a software-managed logical number to each memory card; The central decoding and distribution module sends an RCA acquisition command, and all memory cards return their respective RCA information to the corresponding channel controller via a response; each channel controller transmits the received RCA back to the central decoding and distribution module. The mapping relationship between channel number and RCA is stored in the channel address mapping table; At this point, all memory cards are simultaneously ready.
10. An FPGA chip, characterized in that, The system includes the FPGA-based multi-channel memory card parallel testing system as described in any one of claims 1-6.