Dither injection circuit for chip high-speed interface, dither injection method, chip and test system thereof

Abstract

This invention provides a jitter injection circuit, a jitter injection method, a chip, and a testing system for high-speed chip interfaces, belonging to the field of chip testing technology. The jitter injection circuit includes: a signal input terminal for receiving a clock signal input to the chip; multiple series-connected buffer units, each including at least one inverter to buffer the clock signal; multiple switching elements corresponding to the buffer units and connected to the link between the node of the corresponding buffer unit and ground, changing the equivalent load of the buffer unit node by switching it on and off; and a control signal of the control unit synchronized with the clock signal and having a preset period multiple relationship, changing the propagation delay of the buffer units by switching different on and off combinations within different periods, thus forming a clock signal edge time distribution with different jitter amplitudes at the signal output terminal. The circuit architecture of this invention is simple, easy to integrate, and enables programmable multi-level jitter adjustment.

Description

Technical Field

[0001] This invention relates to the technical field of chip testing, and in particular to a jitter injection circuit, a jitter injection method, a chip, and a testing system for high-speed chip interfaces. Background Technology

[0002] In high-speed interface systems for chips such as DDR and LPDDR, the timing accuracy of clock or data signals directly affects the system's data sampling reliability and transmission bit error rate. Signal jitter describes the time-domain uncertainty of a signal edge relative to its ideal position, and its magnitude directly determines the sampling window width at the receiver and the system's bit error rate performance. As data rates continue to increase and interface timing margins continue to narrow, the receiver circuit's tolerance to jitter becomes a key indicator for measuring system reliability.

[0003] During chip design and mass production testing, it is usually necessary to comprehensively evaluate the jitter tolerance of the receiver circuit to verify its performance boundaries under extreme operating conditions. However, under normal test conditions, the input signal jitter is small, and the system can often operate stably, making it difficult to effectively expose potential failures of the receiver under extreme timing conditions.

[0004] Currently, jitter tolerance testing typically relies on external test equipment (such as an arbitrary waveform generator (AWG) or a bit error rate analyzer (BERT)) to inject controllable jitter signals into the chip under test (DUT). In this approach, the test controller and the DUT work together, with the external equipment performing signal excitation and performance evaluation. However, this approach has significant limitations: First, external test equipment is expensive, and the test chain is complex; the collaboration of multiple devices increases the difficulty and uncertainty of system setup. Second, the accuracy and flexibility of jitter adjustment are limited, making it difficult to meet the needs of refined stress testing. Third, there is a lack of integrable on-chip controllable jitter injection structures, making it difficult to achieve on-chip self-test (BIST) and large-scale mass production testing. Fourth, although existing chips have signal transmission or delay adjustment circuits, they lack a dedicated programmable structure for jitter injection, making it impossible to achieve systematic stress testing of the receiving link. Existing technologies have researched on-chip jitter injection using variable delay lines, but the adjustment range of the jitter amplitude is limited by the absolute size of the physical delay unit, making it difficult to achieve wide-range, multi-level adjustable jitter injection with a simple structure.

[0005] In view of this, a novel jitter injection circuit, jitter injection method, chip, and testing system for high-speed chip interfaces are proposed to solve all or part of the above problems. Summary of the Invention

[0006] To address at least one of the aforementioned problems and deficiencies in the prior art, embodiments of the present invention provide a jitter injection circuit, a jitter injection method, a chip thereof, and a testing system for a high-speed chip interface. A simple on-chip controllable jitter injection architecture is constructed. By connecting multiple levels of buffer units (e.g., capacitors or resistors) to form an equivalent load, controllable expansion of the edge time distribution is achieved. The control unit adjusts the equivalent load by changing the on / off combinations of switching elements, thereby altering the signal propagation delay. Different switching combinations correspond to different delay states, forming clock signal edge time distributions with different jitter amplitudes at the signal output. This basic architecture is simple in structure and easy to integrate, laying the hardware foundation for subsequent programmable multi-level jitter adjustment. The technical solution is as follows:

[0007] According to one aspect of the present invention, a jitter injection circuit for a high-speed chip interface is provided, the jitter injection circuit comprising:

[0008] The signal input terminal is used to receive the clock signal input to the chip;

[0009] A multi-stage series buffer unit, wherein each stage of the buffer unit includes at least one inverter to buffer the clock signal.

[0010] Multiple switching elements are configured to correspond to multi-level series buffer units, wherein each switching element is connected to the link between the node of each buffer unit and the ground, and the equivalent load of the node of the buffer unit is changed by turning the switching elements on and off.

[0011] The control unit generates control signals to control the combination of turning on and off of multiple switching elements;

[0012] The signal output terminal is connected to the output terminal of the last buffer unit in a multi-stage series buffer unit, and outputs a clock signal with controllable jitter.

[0013] The control signal is synchronized with the clock signal input to the chip, and the two have a preset period multiple relationship. By switching different switching elements on and off in different periods, the propagation delay of the multi-level series buffer unit is changed, and a clock signal edge time distribution with different jitter amplitude is formed at the signal output end.

[0014] According to another aspect of the present invention, a jitter injection method for a high-speed chip interface is provided, the jitter injection method being used in the jitter injection circuit described above. The jitter injection method includes:

[0015] Receives clock signals input to the chip;

[0016] Generate a control signal that is synchronized with the clock signal input to the chip and has a preset period multiple relationship;

[0017] The control signal controls the combination of turning on and off of multiple switching elements to change the equivalent load of the multi-stage series buffer unit.

[0018] The clock signal input to the chip is buffered by a multi-stage series buffer unit, and a clock signal with controllable jitter is output at the signal output terminal.

[0019] According to another aspect of the present invention, a chip is provided that integrates the jitter injection circuit described above. The signal input terminal of the jitter injection circuit is connected to the reference clock input terminal of the chip or the chip's internal clock network to perform adjustable jitter injection on the chip's internal clock signal.

[0020] In some embodiments, the chip is a memory interface controller chip, a high-speed serial communication chip, or a system-on-a-chip. The jitter injection circuit performs jitter tolerance testing or transmission performance optimization on the chip's interface circuitry.

[0021] According to another aspect of the present invention, a test system for a high-speed chip interface is provided. The test system includes a test device and a device under test (DUT). The test device integrates a jitter injection circuit as described above, which sends a test clock signal with controllable jitter to the DUT. The DUT receives the test clock signal and performs data processing. The test device evaluates the transmission performance of the DUT based on the output of the DUT.

[0022] The jitter injection circuit, jitter injection method, chip, and testing system for high-speed chip interfaces provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0023] (1) A simple on-chip controllable jitter injection basic architecture is proposed. The architecture consists of multi-level series buffer units and equivalent loads set on the nodes of the buffer units, combined with a control unit that generates a clock signal that is synchronized with the input clock signal and has a preset period multiple relationship. The control unit switches the combination of multiple switching elements on and off in different clock cycles, so that the multi-level series buffer units present different propagation delays in different clock cycles, thereby forming a clock signal edge time distribution with different jitter amplitudes at the signal output end. This mechanism of generating jitter by "periodically switching the discrete delay state of the same path in the time domain" achieves a simple structure, easy on-chip integration and programmable multi-level adjustment of jitter amplitude;

[0024] (2) By concretizing the multi-stage series buffer unit into an inverter cascade structure and implementing the switching element as a MOS transistor, and connecting one end of it to the inverter output node and the other end to ground, a low-cost digital load regulation scheme that can be realized using mature CMOS technology is provided. The equivalent load can be turned on and off by controlling the gate of the MOS transistor. The response speed is fast and the control accuracy is high.

[0025] (3) The control unit can generate a control signal with a period of nT (n≥1) by using a frequency divider and logic combination circuit. By configuring the value of the frequency division ratio n and the combination of the on and off of multiple switching elements, the propagation delay of the multi-level series buffer unit can be periodically switched between at least two different discrete delay values, thereby realizing programmable, multi-level jitter amplitude control from fine adjustment (n=1) to multiple-level expansion (n≥2), providing flexible configuration capabilities for different test scenarios;

[0026] (4) By setting up multiple buffer branches in parallel, and the number of buffer units in each buffer branch is different, different delay steps and jitter resolutions are achieved. By controlling the combination of the on and off of the switching elements in different buffer branches, it can work in conjunction with the main link, providing users with a more flexible jitter configuration scheme, which can meet the different requirements of jitter accuracy for different test scenarios from fine scanning to rapid coarse adjustment.

[0027] (5) By configuring the control signal generated by the control unit to have a preset duty cycle, it is ensured that the combination of the switching element on and off has sufficient response time (e.g., charging and discharging time) to stably establish a new delay state in each control cycle, thereby ensuring that the actual jitter amplitude can accurately meet the preset delay change requirements and improving the reliability of jitter injection.

[0028] (6) By setting up a storage unit in the control unit to store the mapping relationship table between the on and off combinations of switching elements and the jitter amplitude injected by jitter, the user or test program can directly set the current required switching combination and control parameters according to the target jitter amplitude by looking up the mapping relationship table, without the need for complicated real-time calculation, which greatly simplifies the configuration process and improves the test efficiency.

[0029] (7) By connecting the monitoring circuit at the signal output terminal and feeding the monitoring results back to the control unit, the closed-loop adjustable control of the jitter amplitude is realized, which can effectively compensate for the influence of changes in process, voltage, temperature, etc. on the jitter injection accuracy, and adjust the control signal in real time to ensure that the output jitter amplitude is consistent with the target value, which greatly improves the robustness and test reliability of the system.

[0030] (8) By switching the on and off combinations of switching elements in different clock cycles, the propagation delay of the multi-level series buffer unit is periodically switched between multiple discrete delay values. In the calibration stage (n=1), the jitter injection method achieves small-range jitter injection by finely adjusting the switching combination to find the best sampling point and perform fine timing margin scanning. In the testing stage (n≥2), the jitter tolerance and transmission performance of the high-speed interface are evaluated by large-range jitter injection, realizing a standardized and automated testing process from chip calibration to extreme stress testing.

[0031] (9) By integrating the jitter injection circuit of the present invention into a memory interface controller chip, a high-speed serial communication chip or a system-on-a-chip, the internal reference clock or internal clock network can be injected with adjustable jitter, thereby realizing jitter tolerance testing or transmission performance optimization of its own interface circuit, thus improving the reliability and robustness of the chip.

[0032] (10) By integrating a jitter injection circuit into the test equipment, it can directly send a test clock signal with controllable jitter to the device under test and evaluate its transmission performance based on the output results of the device under test. This integrated test solution effectively reduces the dependence on expensive external instruments such as automated test equipment (ATE), significantly shortens the test time and reduces the test cost, and is particularly suitable for large-scale mass production test scenarios. Attached Figure Description

[0033] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 This is a schematic diagram of a jitter injection circuit based on a switchable capacitive load according to an embodiment of the present invention;

[0035] Figure 2 This is a flowchart of a jitter injection method for a high-speed chip interface according to an embodiment of the present invention;

[0036] Figure 3 This is a circuit diagram of a dithering injection method for capacitor adjustment according to an embodiment of the present invention;

[0037] Figure 4 for Figure 3 The simulated eye diagram of the jitter injection circuit is shown.

[0038] Figure 5 for Figure 3 The timing waveforms of the jitter injection circuit under different configuration states are shown.

[0039] Figure 6 This is a circuit diagram of a jitter injection method for resistance adjustment according to an embodiment of the present invention. Detailed Implementation

[0040] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0041] This invention provides an adjustable jitter injection circuit and method for high-speed interfaces. Unlike existing technologies that use multiple parallel fixed-delay paths for spatial combination and continuously adjust volume bias to calibrate clock characteristics, this invention achieves multi-level programmable dynamic jitter injection by periodically switching the equivalent load at each node along a series buffer unit path. This results in a discrete and controllable distribution of the propagation delay of the same signal path on the time axis, thus realizing a simple and easily integrated on-chip architecture.

[0042] In some specific embodiments, the present invention can typically include two independent implementation methods: one is a dithering injection method based on capacitance adjustment, and the other is a dithering injection method based on resistance adjustment. The following detailed description is provided in conjunction with specific implementation methods.

[0043] See Figure 1 The diagram shows a schematic of an example jitter injection circuit based on a switchable capacitive load.

[0044] like Figure 1 As shown, taking capacitor regulation as an example, the jitter injection circuit includes: a signal input terminal (CLK_IN) for receiving the clock signal input to the chip; a multi-stage series buffer unit, each stage of which includes at least one inverter (INV) for buffering the clock signal; multiple switching elements (S1-S4) corresponding to the multi-stage series buffer unit, wherein each switching element is connected to the link between the node of each corresponding buffer unit and ground, and the equivalent load of the node of the buffer unit is changed by turning the switching element on and off; and a control unit ( Figure 1 Not directly shown, its output terminal is connected to the control terminals of S1-S4, and controls the combination of conduction and cutoff of multiple switching elements by generating control signals; the signal output terminal (CLK_OUT) is connected to the output terminal of the last stage of the multi-stage series buffer unit, and outputs a clock signal with controllable jitter.

[0045] In this embodiment, the control signal is synchronized with the clock signal input to the chip, and the two have a preset period multiple relationship. For example, the period of the control signal is nT, where n is an integer greater than or equal to 1, and T is the input clock period.

[0046] The control unit switches different combinations of switching elements on and off within different cycles, causing the multi-stage series buffer unit to exhibit different propagation delays in different clock cycles. These different propagation delays cause the position of each edge of the output clock signal on the time axis to change periodically, thus forming a clock signal edge time distribution with a specific amplitude distribution on a macroscopic scale, achieving controllable jitter injection. This basic architecture is simple in structure and easy to integrate, laying the hardware foundation for subsequent programmable multi-stage jitter adjustment.

[0047] This method of generating jitter by periodically switching the discrete delay states of the same path is fundamentally different from existing technologies that generate different delays through multiple parallel paths and then combine them, or that continuously change the delay through analog control. This architecture significantly reduces circuit complexity and on-chip area overhead while achieving the same or even better jitter adjustment range.

[0048] In one example, specifically, the multi-stage cascaded buffer units employ an inverter cascade structure (CMOS inverter chain). Figure 1 Taking the capacitor regulation method shown as an example, a switchable capacitor branch is connected in parallel at the output node of each inverter stage. Multiple switching elements are NMOS transistors or PMOS transistors. Figure 1 Taking the NMOS transistor as an example, the source or drain of each NMOS transistor is connected to the output node of its corresponding inverter, and the other end of the NMOS transistor is grounded through a capacitor.

[0049] The control signal output by the control unit is connected to the gate of the NMOS transistor, and the switching element is turned on or off by controlling the gate voltage. In this embodiment, the number of inverter stages can be set according to the target speed, basic delay, and load capacity; a typical embodiment uses 2-4 stages of buffer units. The drive strength of each inverter stage can be amplified step by step, or the same size can be used, depending on the design requirements.

[0050] In one example, specifically, the control signal generated by the control unit has a period of nT, where n is an integer greater than or equal to 1, and T is the period of the clock signal input to the chip. By configuring the value of n (e.g., 1, 2, 4, 8, etc.) and the on / off combinations of multiple switching elements, jitter injections with different jitter amplitudes can be generated.

[0051] Specifically, with Figure 1Taking the capacitor adjustment method shown as an example, when n=1, the control signal period is equal to the input clock period, indicating that the delay state within each clock cycle is the same. The jitter of the output edge is mainly determined by the static delay difference generated by different switch combinations, which is used for fine jitter adjustment. When n=2, the control signal period is 2T, indicating that the delay state of the buffer unit alternates between two configurations in two adjacent clock cycles, and the output edge alternates between the two delay states, expanding the edge time distribution range, and the jitter amplitude is approximately twice that under the condition of n=1. When n=4, the control signal period is 4T, and every four clock cycles constitute a complete switching cycle. The output edge cycles between four delay states, and the jitter amplitude is expanded by approximately four times. By adjusting the value of the frequency division ratio n, the jitter amplitude can be expanded by multiples. Please refer to Table 1 for relevant jitter amplitude values.

[0052] The core of the aforementioned adjustment mechanism lies in actively and discretely altering the delay of the same signal path through a periodic control signal that has a definite multiple relationship with the input clock, artificially creating a controllable time offset at the clock edge, i.e., controllable jitter. This differs from the passive calibration or compensation of delays to stabilize the clock in existing technologies. In other words, the "active" and "programmable" generation of "unstable" jitter signals in this embodiment of the invention is particularly suitable for stress testing.

[0053] Table 1. True values ​​of jitter amplitude under different switch combinations and cycle configurations.

[0054]

[0055] In one example, specifically, the control unit includes a frequency divider and a logic combination circuit. The frequency divider divides the clock signal (CLK_IN) input to the chip, generating multiple clock signals with different phases (e.g., divided by 2, 4, and 8). The logic combination circuit combines these multiple clock signals according to a preset logic relationship to generate control signals for controlling multiple switching elements. In this embodiment, the logic combination circuit can be a state machine that sequentially outputs different switching control codes according to a predetermined timing sequence, driving the periodic switching of different RC load configuration states. Users or test programs can flexibly set the periodic mode and switching sequence of the control signals by configuring the division coefficient of the frequency divider and the combination logic relationship of the logic combination circuit.

[0056] In one example, the control unit also receives configuration parameters from external input. By setting the division ratio of the frequency divider (e.g., selecting different cycle modes such as 2T, 4T, and 8T via DIV_SEL[1:0]) and the logic relationship of the logic combination circuit (e.g., selecting the switch combination of S1-S4 via SW_CTRL[3:0], such as only S1 is on, S1+S3 is on, S2+S4 is on, or all are on), the programmable control of the jitter amplitude is realized.

[0057] External configuration parameters can be input to the control unit by the user through register write operations, boundary scan interface, or other standard configuration interfaces. In this way, test engineers can flexibly adjust the amplitude and mode of jitter injection according to different test requirements, and can switch between various jitter tolerance test scenarios without modifying the hardware design.

[0058] In one example, the jitter injection circuit specifically includes multiple buffer branches connected in parallel, each buffer branch comprising a buffer unit and a switching element connected in series. The input of each buffer branch is connected to the signal input, and the output of each buffer branch is connected to the signal output. By controlling the on and off combinations of the switching elements in different buffer branches, different delay combinations can be achieved at the signal output, thereby achieving different jitter injection effects.

[0059] For example, taking a parallel four-branch configuration, the first branch includes a single-stage buffer and a series switch, the second branch includes two stages of buffers and a series switch, and so on. When the control unit turns on the switches in different branches, the input clock signal propagates to the output through buffer paths of different lengths or drive strengths. Each path has a different delay, resulting in a mixture or switching of different delay states at the output, thus achieving jitter injection. This structure can work in conjunction with the main link's switch control mechanism, providing a more flexible jitter configuration scheme.

[0060] In one example, specifically, the delay step size of the parallel buffer branches can be differentiated. The number of buffer units in the multiple parallel buffer branches varies to achieve different delay step sizes and different jitter resolutions.

[0061] For example, the first branch has a single-stage buffer to provide the minimum delay step size; the second branch has two-stage buffers to provide a medium delay step size; the third branch has four-stage buffers to provide a larger delay step size; and the fourth branch has eight-stage buffers to provide the maximum delay step size. By combining the switching elements in different branches, multi-stage, adjustable delay step size combinations can be achieved to meet the jitter injection requirements of different precisions. Users can select a jitter injection mode of fine scanning (small step size) or rapid coarse adjustment (large step size) according to the test scenario.

[0062] In one example, specifically, the control signal generated by the control unit has a preset duty cycle, such that the response time of the combination of turning on and off of the switching element meets the preset delay variation requirement in each control cycle.

[0063] Typically, a switching element requires a certain settling time to fully integrate the additional RC load into the signal path when it is turned on. If the high-level pulse width of the control signal is too short, the switch may not be able to conduct stably, causing the actual jitter amplitude to deviate from the expected value. In various embodiments of the present invention, the control unit reasonably sets the duty cycle of the control signal (e.g., set to 50% or higher to ensure that the switch has sufficient time to reliably turn on in each cycle) based on the charging and discharging characteristics of the buffer node (e.g., the RC load time constant) and the conduction response speed of the MOS switch.

[0064] In simulation analysis, based on typical TSMC 28nm process conditions (TT corner, power supply voltage 0.9V, temperature 85℃), the high-level pulse width of the control signal can be set to be no less than 3-5 times the propagation delay of the inverter to ensure that the configuration state of each switch combination is stably established and to meet the preset delay variation requirements.

[0065] In one example, the control unit further includes a storage unit (e.g., a register array or a small read-only memory) that stores a mapping table between the on / off combinations of switching elements and the jitter amplitude injected by the jitter. The specific form of the mapping table can be found in Table 1 above.

[0066] The simulation results and typical application scenarios are taken as examples, using the capacitor regulation method with nT=2 configuration.

[0067] Users or test programs can set the required jitter amplitude for the current jitter injection by looking up the mapping table, without the need for real-time calculation. The pre-set mapping table in the storage unit can be pre-loaded based on simulation results, for example, loaded from non-volatile memory during chip initialization or embedded in the logic circuit during the design phase. In practice, the user writes the target jitter amplitude value, and the control unit automatically queries the mapping table to obtain the corresponding DIV_SEL and SW_CTRL configuration codes, thereby completing the rapid configuration of the switch combination, greatly simplifying the configuration process and improving testing efficiency.

[0068] In one example, a feedback mechanism can be introduced into the jitter injection circuit to achieve closed-loop control. A monitoring circuit is also connected to the signal output terminal. This monitoring circuit monitors the jitter amplitude of the output clock signal and feeds the monitoring results back to the control unit.

[0069] The monitoring circuit can employ an on-chip jitter measurement module, such as a jitter measurement circuit based on a time-to-digital converter (TDC) architecture, to digitally measure the edge position of the output clock relative to a reference clock. After receiving the monitoring results, the control unit compares the measured jitter amplitude with the target jitter amplitude and adjusts the control signals (e.g., DIV_SEL, SW_CTRL) based on the comparison result, thereby achieving closed-loop adjustable control of the jitter amplitude. This feedback mechanism effectively compensates for the impact of process-voltage-temperature fluctuations on jitter injection accuracy, ensuring that the expected jitter amplitude can be obtained under different operating conditions, thus improving the robustness and testing reliability of the jitter injection circuit and the test system integrating this circuit.

[0070] See Figure 2 The diagram shows a flowchart of a jitter injection method for a high-speed interface according to one embodiment.

[0071] This invention also provides a jitter injection method for high-speed interfaces, which is implemented based on the aforementioned jitter injection circuit. The jitter injection method includes the following steps:

[0072] Step S101: Receive the clock signal input to the chip through the signal input terminal CLK_IN;

[0073] Step S102: The control unit generates a control signal that is synchronized with the clock signal input to the chip and has a preset period multiple relationship (e.g., the period is 2T, 4T or 8T, where T is the input clock period).

[0074] Step S103: Control the combination of turning on and off of multiple switching elements (S1-S4) according to the control signal to change the equivalent load of the multi-stage series buffer unit (for example, by switching the access state of different capacitor branches to change the equivalent load capacitance of the node).

[0075] Step S104: The clock signal input to the chip is buffered through a multi-level series buffer unit, and a clock signal with controllable jitter is output at the signal output terminal CLK_OUT.

[0076] In the implementation scenario of capacitor regulation, when the control signal period is 2T, the switching combinations in even and odd periods are different, causing the propagation delay of adjacent clock cycles to alternate between the two states, ultimately forming a clock signal with alternating edge positions at the output. When the control signal period is 4T, the output edge cycles between four delay states, and the jitter amplitude is further expanded, realizing controllable jitter injection.

[0077] In one example, specifically, the invention further distinguishes between the calibration and testing phases. The period of the control signal is nT, where n is an integer greater than or equal to 1, and T is the period of the clock signal input to the chip. By switching different combinations of switching elements on and off within different periods, jitter injection of different jitter amplitudes is achieved.

[0078] During the calibration phase (e.g., DRAM read DQS gate training, write leveling, or DQ / DQS alignment calibration), n=1 is set, meaning the control signal period equals the input clock period. At this time, a small range of jitter injection is performed by finely adjusting the on / off combinations of the switching elements (e.g., SW_CTRL=01 enables S1, jitter approximately 2.73ps; SW_CTRL=10 enables S1+S3, jitter approximately 4.14ps; SW_CTRL=11 is fully on, jitter approximately 5.81ps). This is used to find the optimal sampling point and perform fine timing margin scanning, requiring a jitter range of approximately 0-6ps. A typical application scenario during the calibration phase is using finely tuned jitter injection to locate the center position of the eye diagram to obtain the optimal sampling margin.

[0079] During the testing phase (e.g., DRAM aging / stress testing), n ≥ 2 (e.g., n = 2), and the control signal period is 2T. A wide range of jitter injection is performed by adjusting the on / off combinations of switching elements (e.g., jitter can reach 17.9ps when all switches are on) to evaluate the jitter tolerance and transmission performance of high-speed interfaces. Specific applications include: burn-in aging testing, retention testing, high-temperature jitter stress testing, and bit error rate testing. By compressing timing margins, potential failures at the receiver under extreme conditions are exposed, thereby comprehensively evaluating the system's reliability.

[0080] Example 1:

[0081] See Figure 3 The diagram shows a specific example of a dithering injection circuit for capacitor regulation.

[0082] See Figure 4 , showed Figure 3 Simulated eye diagram of the jitter injection circuit.

[0083] See Figure 5 , showed Figure 3 Timing waveforms of the jitter injection circuit under different configuration states.

[0084] Circuit structure: combined Figure 1 and Figure 3It is based on a jitter injection circuit structure with switchable capacitive load. The multi-stage buffer unit adopts a CMOS inverter chain structure. Figure 3 The diagram shows a 4-stage inverter, but the invention is not limited to this; the number of stages can be set to 2-4 stages or other numbers depending on the target rate, base delay, and load capacity. Switchable capacitor branches are connected in parallel at the output nodes of each inverter stage. Figure 3 There are four switchable capacitor branches in total. Each branch includes an NMOS switching transistor and a capacitor, with the capacitance value typically on the order of fF. One end of the source / drain of the NMOS switch is connected to the buffer node, and the other end is grounded through a capacitor. The gate receives control signals from the control unit.

[0085] Working Principle: When the switch is closed, the capacitor of the corresponding branch is connected to the buffer node, increasing the node's load capacitance and thus increasing the signal propagation delay at that node. Different switch combinations correspond to different additional load capacitances, resulting in different propagation delays. By switching the switch combinations within different clock cycles, the output edge jumps between multiple discrete time positions, forming an edge time distribution, i.e., jitter injection is achieved. The control unit divides CLK_IN using a frequency divider to generate a control signal with an nT period, driving the switch combinations to switch in a periodic mode. For example, when the control signal period is 2T, the switch combination alternates between odd and even periods, and the output edge alternates between two delay states, with a jitter amplitude of approximately 1 times the single delay difference and a peak jitter of approximately 2 times the delay difference. When the control signal period is 4T, the switch combination cycles between four configuration states, and the output edge is distributed between four delay positions, further increasing the jitter amplitude.

[0086] Simulation results: combined Figure 4 and Figure 5 As shown, based on TSMC's 28nm process, under simulation conditions of TT corner, power supply voltage of 0.9V, and temperature of 85℃, the jitter amplitude under different configuration states of capacitor regulation is as follows: when all are off (S1-S4 are all off), the jitter is approximately 0.13ps; when only S1 is on, the jitter is approximately Δt1=4.58ps (as the baseline jitter); when S1 and S3 are on, the jitter is approximately Δt2=7.48ps (approximately 1.63×); when all are on (S1-S4), the jitter is approximately Δt3=17.9ps (approximately 3.91×). It can be seen that as the number of connected capacitors increases, the node load increases, and the delay dispersion range expands, thereby achieving a gradual increase in jitter amplitude.

[0087] In this embodiment, by switching the switch combination within different clock cycles, the output edge is no longer fixed at a single point in time, but jumps between multiple discrete time positions. This "jump" in edge position constitutes controllable jitter.

[0088] Example 2:

[0089] See Figure 6 The diagram shows a specific example of a dithering injection circuit using a resistor adjustment method.

[0090] Circuit structure: such as Figure 6 The diagram shown is a schematic of a jitter injection circuit based on a switchable resistive load. In this embodiment, the jitter adjustment unit is implemented using a resistor. Figure 6 There are a total of 8 switchable resistor branches. Each resistor branch includes two MOSFET switches, such as the PMOS transistor next to S1 and CLK_IN in the pull-up branch, and the NMOS transistor next to S2 and CLK_IN in the pull-down branch. By constructing a controllable resistor path through the MOSFETs, the equivalent resistance of the pull-up / pull-down can be changed, thereby altering the charging / discharging speed and edge position.

[0091] Specifically, S1, S3, S5, and S7 are pull-up resistor control switches, and S2, S4, S6, and S8 are pull-down resistor control switches. For each node, two MOSFETs are connected in series between the signal path and ground / power supply: the gate of one MOSFET is controlled by a control signal (e.g., S1), and the gate of the other MOSFET is controlled by the input clock CLK_IN (or its inverted signal).

[0092] Working principle: When the control MOSFET of the pull-down branch (e.g., S2) is turned on, another MOSFET connected to CLK_IN will turn on when CLK_IN is high, providing an additional discharge path to ground for this node, thereby accelerating the falling edge and reducing propagation delay. Conversely, when the control MOSFET of the pull-up branch (e.g., S1) is turned on, another MOSFET connected to CLK_IN will turn on when CLK_IN is low, accelerating charging. Different conduction combinations correspond to different equivalent resistance values, thereby changing the charging and discharging time constant and producing different propagation delays. By switching different resistance combinations in different cycles by the control unit, the output edge jumps between discrete delay states, achieving jitter injection.

[0093] Simulation results: Based on TSMC's 28nm process, the jitter amplitude under different configuration states with resistance adjustment is as follows: when all are off (S1-S8 are off), the jitter is approximately 0.984ps (approximately 0.17×); when S1 and S2 are on, the jitter is approximately 5.9ps (approximately 1×, used as the reference jitter); when S1, S2, S5, and S6 are on, the jitter is approximately 11ps (approximately 1.86×); and when all are on (S1-S8), the jitter is approximately 16.5ps (approximately 2.80×). As the conduction path increases, the range of equivalent resistance variation expands, and the edge time distribution range gradually expands, thereby achieving jitter amplitude adjustment.

[0094] In one example, the present invention also provides a chip integrating the jitter injection circuit of the aforementioned embodiments. The signal input terminal of the jitter injection circuit is connected to the chip's reference clock input terminal or the chip's internal clock network, for adjustable jitter injection of the chip's internal clock signal. The chip can be a memory interface controller chip (e.g., a DDR / LPDDR controller chip), a high-speed serial communication chip (e.g., a SerDes transceiver chip, a PCIe interface chip, etc.), or a system-on-a-chip (SoC). The jitter injection circuit can perform jitter tolerance testing or transmission performance optimization on the chip's interface circuitry. Specific implementation scenarios include:

[0095] Scenario 1: In chip mass production testing, the on-chip integrated jitter injection circuit is used to perform jitter tolerance testing on the DDR PHY interface. The test program injects jitter signals of different amplitudes from 2.73ps to 17.9ps (based on typical values ​​provided in Table 1) sequentially by configuring the DIV_SEL and SW_CTRL parameters of the control unit, while simultaneously running the built-in self-test (BIST) circuit to perform bit error detection, thereby evaluating the jitter tolerance performance of the DDR interface.

[0096] Scenario 2: Before the chip operates normally, during the power-on initialization phase, the chip performs self-calibration using a jitter injection circuit. A controllable small-amplitude jitter is injected into the clock signal using an n=1 cycle mode and a fine-switch combination (e.g., S1 alone or S1+S3 combined). By observing changes in the sampling error rate at the receiver, the optimal sampling phase of the internal clock data recovery (CDR) circuit is calibrated. The required jitter range for this scenario is 0-6 ps, used to locate the center position of the eye diagram.

[0097] Scenario 3: In chip burn-in or stress testing, configure an n=2 cycle mode and select a wide-range jitter injection (e.g., S1-S4 fully open). Under high temperature / high pressure conditions, inject significant jitter to compress signal timing margins and expose potential timing failure risks in advance. The jitter range required for this scenario can reach 0-18ps or more, evaluating the chip's operational reliability under extreme conditions.

[0098] In one example, the present invention also provides a test system for high-speed chip interfaces. The test system includes a test device and a device under test (e.g., a DUT). The test device integrates a jitter injection circuit as described in the preceding embodiments. The jitter injection circuit sends a test clock signal with controllable jitter to the DUT; the DUT receives the test clock signal and performs data processing; the test device evaluates the transmission performance of the DUT based on the output results. Specific implementation scenarios are as follows:

[0099] The test equipment can be implemented using an FPGA or a dedicated test chip, which integrates the jitter injection circuit of this invention. During testing, the jitter injection circuit inside the test controller (e.g., FPGA) receives a reference clock (CLK_IN). The control unit configures different nT periods and switching combinations according to a preset test sequence to generate a clock signal with controllable jitter. This clock signal drives the test data transmission module to generate a jitter data stream. This jitter data stream is transmitted to the device under test (DUT) via a high-speed interface (e.g., DDR interface, PCIe interface, or SerDes link). The DUT receives and processes the data stream, and its output response (e.g., bit error rate, data integrity verification result, etc.) is sent back to the test equipment. The test equipment calculates the jitter tolerance of the DUT based on the output result (e.g., by gradually increasing the injected jitter amplitude until the DUT experiences bit errors, and recording this critical jitter value).

[0100] Because the test equipment integrates a jitter injection circuit, the entire test system eliminates the need for an expensive external arbitrary waveform generator (AWG) or bit error rate analyzer (BERT), significantly reducing test costs. Simultaneously, the shorter signal link between the jitter injection circuit and the device under test (on-chip or board interconnect) reduces external interference and signal attenuation, resulting in higher accuracy and repeatability of test results. This system architecture is particularly suitable for chip mass production testing, effectively shortening test time and reducing test costs.

[0101] Furthermore, this testing system can be integrated into the loadboard of an automated test equipment (ATE) to supplement the ATE test channels and provide more flexible jitter injection capabilities. The test equipment can be configured to automatically switch nT cycles and switching combinations at different test stages (e.g., wafer test and final test) to sequentially complete fine calibration and extreme stress testing, meeting the full-process requirements from wafer-level testing to package-level mass production testing.

[0102] The jitter injection circuit, jitter injection method, chip, and testing system for high-speed chip interfaces provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0103] (1) A simple on-chip controllable jitter injection basic architecture is proposed. The architecture consists of multi-level series buffer units and equivalent loads set on the nodes of the buffer units, combined with a control unit that generates a clock signal that is synchronized with the input clock signal and has a preset period multiple relationship. The control unit switches the combination of multiple switching elements on and off in different clock cycles, so that the multi-level series buffer units present different propagation delays in different clock cycles, thereby forming a clock signal edge time distribution with different jitter amplitudes at the signal output end. This mechanism of generating jitter by "periodically switching the discrete delay state of the same path in the time domain" achieves a simple structure, easy on-chip integration and programmable multi-level adjustment of jitter amplitude;

[0104] (2) By concretizing the multi-stage series buffer unit into an inverter cascade structure and implementing the switching element as a MOS transistor, and connecting one end of it to the inverter output node and the other end to ground, a low-cost digital load regulation scheme that can be realized using mature CMOS technology is provided. The equivalent load can be turned on and off by controlling the gate of the MOS transistor. The response speed is fast and the control accuracy is high.

[0105] (3) The control unit can generate a control signal with a period of nT (n≥1) by using a frequency divider and logic combination circuit. By configuring the value of the frequency division ratio n and the combination of the on and off of multiple switching elements, the propagation delay of the multi-level series buffer unit can be periodically switched between at least two different discrete delay values, thereby realizing programmable, multi-level jitter amplitude control from fine adjustment (n=1) to multiple-level expansion (n≥2), providing flexible configuration capabilities for different test scenarios;

[0106] (4) By setting up multiple buffer branches in parallel, and the number of buffer units in each buffer branch is different, different delay steps and jitter resolutions are achieved. By controlling the combination of the on and off of the switching elements in different buffer branches, it can work in conjunction with the main link, providing users with a more flexible jitter configuration scheme, which can meet the different requirements of jitter accuracy for different test scenarios from fine scanning to rapid coarse adjustment.

[0107] (5) By configuring the control signal generated by the control unit to have a preset duty cycle, it is ensured that the combination of the switching element on and off has sufficient response time (e.g., charging and discharging time) to stably establish a new delay state in each control cycle, thereby ensuring that the actual jitter amplitude can accurately meet the preset delay change requirements and improving the reliability of jitter injection.

[0108] (6) By setting up a storage unit in the control unit to store the mapping relationship table between the on and off combinations of switching elements and the jitter amplitude injected by jitter, the user or test program can directly set the current required switching combination and control parameters according to the target jitter amplitude by looking up the mapping relationship table, without the need for complicated real-time calculation, which greatly simplifies the configuration process and improves the test efficiency.

[0109] (7) By connecting the monitoring circuit at the signal output terminal and feeding the monitoring results back to the control unit, the closed-loop adjustable control of the jitter amplitude is realized, which can effectively compensate for the influence of changes in process, voltage, temperature, etc. on the jitter injection accuracy, and adjust the control signal in real time to ensure that the output jitter amplitude is consistent with the target value, which greatly improves the robustness and test reliability of the system.

[0110] (8) By switching the on and off combinations of switching elements in different clock cycles, the propagation delay of the multi-level series buffer unit is periodically switched between multiple discrete delay values. In the calibration stage (n=1), the jitter injection method achieves small-range jitter injection by finely adjusting the switching combination to find the best sampling point and perform fine timing margin scanning. In the testing stage (n≥2), the jitter tolerance and transmission performance of the high-speed interface are evaluated by large-range jitter injection, realizing a standardized and automated testing process from chip calibration to extreme stress testing.

[0111] (9) By integrating the jitter injection circuit of the present invention into a memory interface controller chip, a high-speed serial communication chip or a system-on-a-chip, the internal reference clock or internal clock network can be injected with adjustable jitter, thereby realizing jitter tolerance testing or transmission performance optimization of its own interface circuit, thus improving the reliability and robustness of the chip.

[0112] (10) By integrating a jitter injection circuit into the test equipment, it can directly send a test clock signal with controllable jitter to the device under test and evaluate its transmission performance based on the output results of the device under test. This integrated test solution effectively reduces the dependence on expensive external instruments such as automated test equipment (e.g., ATE), significantly shortens the test time and reduces the test cost, and is particularly suitable for large-scale mass production test scenarios.

[0113] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A jitter injection circuit for a high-speed chip interface, characterized in that, The jitter injection circuit includes: The signal input terminal is used to receive the clock signal input to the chip; A multi-stage cascaded buffer unit, wherein each stage of the multi-stage cascaded buffer unit includes at least one inverter, the inverter being used to buffer the clock signal. Multiple switching elements are provided, which correspond to the multi-level series buffer units. Each switching element is connected to the link between the node of each buffer unit and the ground. The equivalent load of the node of the buffer unit is changed by turning the switching elements on and off. The control unit controls the on / off combinations of the multiple switching elements by generating control signals; The signal output terminal is connected to the output terminal of the last buffer unit in the multi-stage series buffer unit, and outputs a clock signal with controllable jitter. The control signal is synchronized with the clock signal input to the chip, and the two have a preset period multiple relationship. By switching different switching elements on and off in different periods, the multi-level series buffer unit exhibits different propagation delays in different clock cycles, forming a clock signal edge time distribution with different jitter amplitudes at the signal output end.

2. The jitter injection circuit according to claim 1, characterized in that, The multi-stage series buffer unit is an inverter cascade structure; The plurality of switching elements are MOS transistors, the source or drain of the MOS transistor is connected to the output node of the corresponding inverter, and the other end of the MOS transistor is grounded through a capacitor or directly grounded; The gate of the MOS transistor is controlled by the control signal of the control unit to realize the switching element being turned on or off.

3. The jitter injection circuit according to claim 2, characterized in that, The period of the control signal generated by the control unit is nT, where n is an integer greater than or equal to 1, and T is the period of the clock signal input to the chip; By configuring the value of n and the combination of turning on and off of the plurality of switching elements, the control unit causes the propagation delay of the multi-stage series buffer unit to periodically switch between at least two different discrete delay values, generating jitter injections with different jitter amplitudes.

4. The jitter injection circuit according to claim 3, characterized in that, The control unit includes a frequency divider and a logic combination circuit; The frequency divider divides the clock signal input to the chip to generate multiple clock signals with different phases. The logic combination circuit combines the multiple clock signals according to a preset logic relationship to generate control signals for controlling the multiple switching elements.

5. The jitter injection circuit according to claim 4, characterized in that, The control unit also receives configuration parameters from external input, and sets the division ratio of the frequency divider and the logic relationship of the logic combination circuit through the configuration parameters to achieve programmable control of the jitter amplitude.

6. The jitter injection circuit according to any one of claims 1-5, characterized in that, The jitter injection circuit also includes multiple buffer branches connected in parallel. Each of the multiple buffer branches connected in parallel includes a buffer unit and a switching element connected in series. The input terminal of each buffer branch is connected to the signal input terminal. The output of each buffer branch is connected to the signal output. Different delays and different jitter injections can be achieved by controlling the on and off combinations of switching elements in different buffer branches.

7. The jitter injection circuit according to claim 6, characterized in that, The number of buffer units in the multiple parallel buffer branches is different, so as to achieve different delay steps and different jitter resolutions.

8. The jitter injection circuit according to claim 6, characterized in that, The control signal generated by the control unit has a preset duty cycle, so that the response time of the combination of the switching element's on and off states in each control cycle meets the preset delay variation requirement.

9. The jitter injection circuit according to claim 8, characterized in that, The control unit also includes a storage unit that stores a mapping table between the on and off combinations of switching elements and the jitter amplitude of jitter injection. The jitter amplitude required for the current jitter injection is set by looking up the mapping table.

10. The jitter injection circuit according to claim 6, characterized in that, The signal output terminal is also connected to a monitoring circuit, which monitors the jitter amplitude of the output clock signal and feeds the monitoring result back to the control unit. The control unit adjusts the control signal based on the monitoring results to achieve closed-loop adjustable control of the jitter amplitude.

11. A jitter injection method for a high-speed chip interface, the jitter injection method being used in a jitter injection circuit according to any one of claims 1-10, characterized in that, The jitter injection method includes: Receives clock signals input to the chip; Generate a control signal that is synchronized with the clock signal input to the chip and has a preset period multiple relationship; According to the control signal, the combination of on and off of multiple switching elements is switched in different clock cycles to change the equivalent load of the multi-stage series buffer unit in different clock cycles, so that the multi-stage series buffer unit exhibits different propagation delays in different clock cycles. The clock signal input to the chip is buffered by the multi-level series buffer unit, and a clock signal with controllable jitter is output at the signal output terminal.

12. The jitter injection method according to claim 11, characterized in that, The period of the control signal is nT, where n is an integer greater than or equal to 1, and T is the period of the clock signal input to the chip. By switching different combinations of switching elements on and off within different periods, jitter injection with different jitter amplitudes can be achieved. During the calibration phase, n=1 is set, and a small range of jitter is injected by adjusting the combination of the on and off states of the switching elements to find the optimal sampling point; During the testing phase, with n≥2, a wide range of jitter injections were performed by adjusting the on and off combinations of the switching elements to evaluate the jitter tolerance and transmission performance of the chip's high-speed interface.

13. A chip, said chip integrating a dithering injection circuit according to any one of claims 1-10, characterized in that, The signal input terminal of the jitter injection circuit is connected to the reference clock input terminal of the chip or the internal clock network of the chip, and performs adjustable jitter injection on the clock signal inside the chip. The chip is a memory interface controller chip, a high-speed serial communication chip, or a system-on-a-chip. The jitter injection circuit performs jitter tolerance testing or transmission performance optimization on the chip's interface circuit.

14. A testing system for high-speed chip interfaces, characterized in that, The testing system includes testing equipment and the device under test. The test equipment integrates a jitter injection circuit according to any one of claims 1-10, wherein the jitter injection circuit sends a test clock signal with controllable jitter to the device under test; The device under test receives the test clock signal and processes the data. The testing equipment evaluates the transmission performance of the device under test based on the output results of the device under test.

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