Dither injection circuit for chip high-speed interface, dither injection method, chip and test system thereof

By designing a combination of multi-level buffer units and switching elements inside the chip, a low-cost and easily integrated jitter injection circuit is realized, which solves the problems of high cost and limited flexibility in existing jitter tolerance testing, improves testing efficiency and reliability, and is suitable for fine stress testing of high-speed chip interfaces.

CN122507571AActive Publication Date: 2026-08-04KINGTIGER TESTING TECH (SZ) LTD
5 Cites 0 Cited by

Patent Information

Application Number
CN202610963732.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-06-30
Publication Date
2026-08-04
Estimated Expiration
2046-06-30

AI Technical Summary

Technical Problem

In existing technologies, jitter tolerance testing of high-speed chip interface systems relies on external equipment, which is costly and has limited flexibility and accuracy. It is difficult to achieve on-chip self-testing and large-scale mass production testing, and it lacks a programmable jitter injection structure, which cannot meet the needs of refined stress testing.

Method used

Design a simple on-chip controllable jitter injection circuit. By combining multi-level buffer units and switching elements, a synchronous control signal is generated by the control unit to switch the on and off combinations of the switching elements, thereby realizing multi-level programmable jitter adjustment and forming clock signal edge time distributions with different jitter amplitudes.

Benefits of technology

It achieves low-cost, easy-to-integrate jitter injection, can precisely adjust the jitter amplitude, adapt to flexible configurations for different testing scenarios, improves testing efficiency and reliability, reduces dependence on external instruments, and is suitable for large-scale mass production testing.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

This invention provides a jitter injection circuit, a jitter injection method, a chip, and a testing system for high-speed chip interfaces, belonging to the field of chip testing technology. The jitter injection circuit includes: a signal input terminal for receiving a clock signal input to the chip; multiple series-connected buffer units, each including at least one inverter to buffer the clock signal; multiple switching elements corresponding to the buffer units and connected to the link between the node of the corresponding buffer unit and ground, changing the equivalent load of the buffer unit node by switching it on and off; and a control signal of the control unit synchronized with the clock signal and having a preset period multiple relationship, changing the propagation delay of the buffer units by switching different on and off combinations within different periods, thus forming a clock signal edge time distribution with different jitter amplitudes at the signal output terminal. The circuit architecture of this invention is simple, easy to integrate, and enables programmable multi-level jitter adjustment.
Need to check novelty before this filing date? Find Prior Art