An AI chip performance data acquisition method

Abstract

This invention relates to the field of big data acquisition and discloses a method for acquiring performance data of an AI chip. The method includes acquiring multi-source monitoring data during the operation of the AI ​​chip to generate state feature information and corresponding state confidence levels; extracting sensitive features from the dimensions of computing power execution, memory access, and power consumption scheduling based on the state feature information and state confidence levels to generate a lightweight verification workload task; embedding the lightweight verification workload task into the chip execution cycle to form dual-source performance observation data; establishing consistency constraints between the sampled data and the verification response based on the dual-source performance observation data to identify performance observation conflict areas; and outputting AI chip performance data after dual-source consistency correction and time offset compensation for the performance observation conflict areas, combined with DVFS constraints, resource boundaries, and performance coupling relationships. This invention has the advantage of improving the time consistency of AI chip performance data acquisition results.

Description

Technical Field

[0001] This invention relates to the field of big data acquisition, specifically to a method for acquiring performance data of an AI chip. Background Technology

[0002] With the rapid development of artificial intelligence technology, AI chips are increasingly widely used in deep learning training and inference tasks. In order to effectively evaluate and optimize the operation status of AI chips, it is usually necessary to continuously and in real time collect and analyze the chip's performance data. In the existing technology, AI chip performance data collection is usually achieved through on-chip monitoring modules or external monitoring systems. The chip's power consumption, operating frequency, temperature, computing power utilization, and memory access bandwidth are periodically sampled, and the sampled data is uploaded to a data processing platform for unified analysis.

[0003] However, in practical applications, AI chips often employ a Dynamic Voltage and Frequency Adjustment (DVFS) mechanism to adapt to different load changes. During the transient process of DVFS state switching, the chip's internal clock frequency and voltage level are in an unstable transition state. Existing performance data acquisition methods are usually still based on fixed sampling periods for data acquisition, which leads to sampling window misalignment problems at the moment of frequency switching. When the chip switches from a high-frequency state to a low-frequency state or vice versa, the following problems are likely to occur: on the one hand, key performance fluctuation data during the transient process are not fully captured; on the other hand, the data acquired under different sampling periods have implicit offsets on the time axis, which can lead to short-term anomalies being smoothed out or misjudged during subsequent big data analysis.

[0004] Therefore, the existing AI chip performance acquisition mechanism suffers from a time coupling mismatch between the sampling period and the DVFS transient switching process, resulting in the loss of transient performance characteristics and the offset of time-series data, which in turn affects the accuracy of performance evaluation and dynamic scheduling decisions based on the acquired data. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for acquiring performance data of AI chips, which has the advantage of improving the time consistency of AI chip performance data acquisition results and solves the problems mentioned in the background technology.

[0006] To achieve the aforementioned goal of improving the time consistency of AI chip performance data acquisition results, this invention provides the following technical solution: A method for acquiring performance data of an AI chip, comprising the following steps: Multi-source monitoring data is collected during the operation of the AI ​​chip, and combined with historical operation sequences and DVFS state switching trajectories, the collected data is processed for time alignment and state encoding to generate state feature information and corresponding state confidence. Based on state feature information and state confidence, sensitive features in the dimensions of computing power execution, memory access and power scheduling are extracted. Combined with the characteristics of DVFS switching phase, state-aware constraints are formed. The type and parameters of the verification load are determined by the feature-load mapping rules, and a lightweight verification load task is generated. Lightweight verification workload tasks are embedded into the chip execution cycle and time-aligned with the real-time performance sampling process. Response characteristic data and monitoring sampling data of the verification workload are collected synchronously to form dual-source performance observation data. Based on dual-source performance observation data, a consistency constraint relationship is established between the sampled data and the verification response. By inverting the verification response and processing the feature mapping of the sampled data, the time offset and state deviation between the two are calculated, and the conflict area of ​​performance observation is identified. For areas of performance observation conflict, the sampling data and verification response data are weighted, fused, and time-off compensated by combining DVFS constraints, resource boundaries, and performance coupling relationships. The resulting AI chip performance data is then output after dual-source consistency correction and time-off compensation.

[0007] Preferably, the process of generating state feature information and corresponding state confidence is as follows: The on-chip performance monitoring unit and external monitoring interface synchronously collect the computing power utilization, memory access bandwidth, power consumption, voltage, frequency and temperature of the AI ​​chip to form the raw monitoring data stream. Timestamp reconstruction and clock domain alignment are performed on multi-source monitoring data streams based on a unified time reference. By combining the time location and duration information of DVFS state transitions in historical operation sequences, the monitoring data stream is segmented and marked to construct a state segmentation that includes stable and transitional segments; For state segmentation, segmented normalization and sliding window statistical methods are used to extract basic statistical features, and DVFS switching direction and switching rate are introduced as auxiliary coding variables. The extracted features are mapped to a state representation vector of a unified dimension. The corresponding state confidence coefficient is calculated by combining the historical stability distribution and the current fluctuation amplitude, and the state feature information and state confidence are output.

[0008] Preferably, the process of extracting sensitive features from the dimensions of computing power execution, memory access, and power consumption scheduling is as follows: The state feature information is reorganized according to three dimensions: computing power execution, memory access, and power consumption scheduling to construct multi-dimensional features; In the computing power execution dimension, the indicators of computing unit utilization, instruction throughput and execution pause ratio are extracted, and abnormal fluctuations are amplified by combining state confidence. In the memory access dimension, cache hit rate, bandwidth utilization and access latency distribution are extracted, and low reliability interval data is suppressed through a confidence gating mechanism. In the power consumption scheduling dimension, the power change gradient, voltage-frequency coordinated change trend and energy efficiency ratio index are extracted to form a power consumption dynamic feature vector. A unified sensitive feature vector is constructed by concatenating and standardizing the three types of features. Different weights are assigned to each dimension according to the confidence level, and the sensitive features are output.

[0009] Preferably, the process of generating a lightweight verification workload task is as follows: Based on the DVFS state segmentation, the frequency rise phase, frequency fall phase, and stable operation phase are identified. State-aware constraints are constructed based on the feature boundaries of each stage, including the computing power occupancy threshold range, memory access pressure range, and power consumption change rate limit. Establish mapping rules between features and load behavior, combine and map sensitive features according to the dimensions of computing power execution, memory access, and power consumption scheduling, and determine the corresponding compute-intensive, memory-intensive, or combined verification load types; Based on the current state characteristics and constraints, match the corresponding load template in the mapping rules; By combining the weight distribution of sensitive features, the parameters of load size, execution time and trigger frequency are adjusted to generate a lightweight verification load task that meets the constraints and has little disturbance to chip operation.

[0010] Preferably, the time-aligned scheduling process with the real-time performance sampling process is as follows: In the chip scheduling and control layer, a low-priority execution channel is allocated for the verification workload task, and the insertable time window is determined in combination with the current task queue status; Based on the DVFS switching time node, the triggering time of the verification load is aligned with the critical time slices before and after the state transition; Within the insertable time window, the execution cycle of the verification load and the performance sampling cycle are jointly scheduled; The system dynamically adjusts its workload based on chip resource usage. When the system load exceeds a preset threshold, the execution scale of the verification load is delayed or reduced, thus completing the embedding and time-aligned scheduling of the verification load task within the chip execution cycle.

[0011] Preferably, the process of generating dual-source performance observation data is as follows: During the verification load execution, execution response data, including execution latency, throughput changes, and power consumption response curves, are collected through a dedicated monitoring channel. Multi-source monitoring sampling data within the corresponding time window is obtained through the conventional performance sampling channel; Both types of data are uniformly labeled with time tags and status identifiers, and time alignment processing is performed to form paired observation data units; The paired observation data units are encapsulated in a structured manner to output dual-source performance observation data containing both the reference source and the observed source.

[0012] Preferably, the process of establishing a consistency constraint relationship between the sampled data and the verification response is as follows: Based on dual-source performance observation data, combined with the known input characteristics and expected execution behavior of the verification load, a theoretical response curve is generated. The actual verification response data is compared and matched with the theoretical response curve to obtain the reference response deviation range; Based on the reference response deviation range and state confidence, a correspondence between the sampled data and the verification response is constructed to form a mapping relationship; Introducing DVFS state parameters as constraint variables into the mapping relationship limits the allowable deviation range under different states; Based on constraint variables, establish consistency constraint relationships between sampled data and verification responses.

[0013] Preferably, the process for identifying conflict areas in performance observation is as follows: Based on the input-output relationship of the verification load in the dual-source performance observation data, the verification response data is reverse-derived to obtain the corresponding theoretical performance state; Align and match the theoretical performance state with the state features corresponding to the sampled data, calculate the optimal alignment position on the time axis, and obtain the time offset accordingly. Based on the aforementioned consistency constraint relationship, calculate the state deviation values ​​between the sampled data and the verification response in terms of computing power, memory access, and power consumption. When the time offset or state deviation exceeds a preset threshold, the corresponding time segment will be marked as a performance observation conflict area.

[0014] Preferably, the process of outputting AI chip performance data after dual-source consistency correction and time offset compensation is as follows: For the marked performance observation conflict areas, the weight allocation coefficients of the sampled data and the verification response data are determined by combining the current state of DVFS and the state confidence. By combining the upper limit of chip resource usage and the coupling relationship between various performance indicators, data that does not meet the resource boundary constraints are filtered and corrected. Based on the corrected data and weight allocation results, time axis compensation processing is performed on the sampled data according to the calculated time offset. After completing time axis compensation, the aligned sampled data and verification response data are weighted and fused based on the weight allocation coefficients to output AI chip performance data that has completed dual-source consistency correction and time offset compensation.

[0015] Compared with existing technologies, the present invention provides a method for acquiring performance data of AI chips, which has the following beneficial effects: This invention achieves time-series alignment and state encoding by collaboratively collecting multi-source monitoring data during AI chip operation and combining historical operation sequences and DVFS state transition trajectories. This allows raw performance data to be structurally expressed under a unified state semantics, thereby improving the comparability and consistency of data at different operation stages. Furthermore, by introducing state feature information and state confidence, sensitive features are extracted from multiple dimensions such as computing power execution, memory access, and power scheduling. State-aware constraints are constructed based on the characteristics of DVFS switching stages, ensuring that the generated verification load matches the actual operating state of the chip. This enhances the load's coverage and relevance to real-world operating scenarios. Simultaneously, by embedding a lightweight verification load into the chip's execution cycle and integrating it with real-time performance data... The sampling process is time-aligned and scheduled to achieve synchronous observation of verification disturbances and natural operation processes, effectively improving the ability to capture transient performance changes. By constructing dual-source performance observation data and introducing consistency constraints, the verification response is inverted and analyzed. The timing offset and state deviation are calculated by combining the feature mapping of the sampled data, thereby achieving refined identification of sampling errors and timing misalignment problems. By combining DVFS constraints, resource boundaries and performance coupling relationships, the conflict area is weighted and fused and time offset is compensated, so that data from different sources can be collaboratively corrected under a unified constraint framework. This significantly improves the accuracy, stability and timing consistency of AI chip performance data, thus providing a more reliable data foundation for subsequent performance evaluation, dynamic scheduling optimization and operation status analysis. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the method of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1: Please refer to Figure 1 An AI chip performance data acquisition method according to an embodiment of the present invention includes the following steps: S1: Collect multi-source monitoring data during the operation of the AI ​​chip, and combine it with historical operation sequences and DVFS state switching trajectories to perform time-series alignment and state encoding processing on the collected data to generate state feature information and corresponding state confidence.

[0019] The process of generating state feature information and corresponding state confidence in S1 is as follows: The AI ​​chip's computing power utilization, memory access bandwidth, power consumption, voltage, frequency, and temperature are synchronously collected through the on-chip performance monitoring unit and external monitoring interface to form a raw monitoring data stream. The on-chip performance monitoring unit continuously samples the internal operating indicators of the AI ​​chip during operation, while the external monitoring interface synchronously acquires the chip's system-level operating parameters. The on-chip performance monitoring unit is used to acquire internal chip status data such as computing power utilization, memory access bandwidth, power consumption, and operating frequency, while the external monitoring interface is used to collect external influencing parameters such as power supply voltage and ambient temperature. Each sampling channel is synchronously triggered according to a preset sampling period, and data from different sources are uniformly marked according to timestamps, thereby forming a raw monitoring data stream with a unified time base, ensuring the consistency of multi-source data in the time dimension. Based on a unified time reference, timestamp reconstruction and clock domain alignment are performed on the multi-source monitoring data stream. When performing timestamp reconstruction on the original monitoring data stream, the system master clock is used as the unified time reference to correct the sampling clock offset between the on-chip monitoring unit and the external monitoring interface. Data with different sampling frequencies are mapped to a unified time axis through interpolation alignment. Clock domain alignment is performed to resample and fuse data from different sampling domains according to a unified time granularity, so that each time slice corresponds to a unique set of state data, thereby eliminating the time misalignment problem caused by asynchronous sampling and forming a time-consistent multi-source aligned monitoring data stream. By combining the time location and duration information of DVFS state transitions in historical operation sequences, the monitoring data stream is segmented and marked to construct a state segmentation that includes a stable segment and a transition segment. By combining the DVFS state transition time points and their duration information recorded in historical operation sequences, the aligned monitoring data stream is further segmented and marked, with the DVFS state transition points serving as segment boundaries. The chip operation process is divided into different operation stages. Based on different DVFS state change trends such as frequency increase, frequency decrease, and stable operation, each time period is categorized and labeled to form a state segmentation that includes a stable operation segment and a transition adjustment segment. This enables the monitoring data under different operation states to be structurally divided in the time dimension. For state segmentation, segmented normalization and sliding window statistical methods are used to extract basic statistical features, and DVFS switching direction and switching rate are introduced as auxiliary coding variables. Within each state segment, a sliding window method is used to perform local statistical analysis on the monitoring data. The sliding window slides within the segment at a fixed time step to extract basic statistical features such as the average fluctuation of computing power utilization, the magnitude of memory access bandwidth change, and the slope of power consumption change. The DVFS state change direction is introduced as a directional identifier variable, and the frequency change rate is used as a dynamic auxiliary parameter to describe the adjustment intensity of the current stage. By combining the above statistical features with auxiliary variables, a basic feature description that can reflect the characteristics of different operating stages is formed. The extracted features are mapped to state representation vectors of a unified dimension. The corresponding state confidence coefficients are calculated by combining historical stability distributions with the current fluctuation amplitude, and the state feature information and state confidence are output. The extracted basic features are converted into state representation vectors of a fixed dimension through a unified feature mapping rule. The mapping process uses a normalization method to compress features of different dimensions into a unified numerical range, thereby ensuring the comparability between different indicators. Combining the stability distribution characteristics of the corresponding DVFS state in historical operating data, the deviation of the fluctuation amplitude of each feature in the current state from the historical stable range is calculated, and the state confidence coefficient is constructed based on the deviation. The state feature information containing the state representation vector and the corresponding confidence coefficient is output for the load construction and consistency analysis process.

[0020] S2: Based on state feature information and state confidence, extract sensitive features in the dimensions of computing power execution, memory access and power scheduling, combine them with the characteristics of DVFS switching phase to form state-aware constraints, determine the type and parameters of the verification load through the feature-load mapping rules, and generate a lightweight verification load task.

[0021] The process of extracting sensitive features from the dimensions of computing power execution, memory access, and power consumption scheduling in S2 is as follows: State feature information is reorganized into three dimensions: computing power execution, memory access, and power consumption scheduling to construct multi-dimensional features. When reorganizing state feature information into these three dimensions, various indicators in the state feature information are classified according to preset dimension division rules. Among them, computing power execution-related features include computing resource usage and execution efficiency indicators, memory access-related features include memory access behavior indicators, and power consumption scheduling-related features include energy consumption and voltage frequency change indicators. After classification, features within the same dimension are aggregated and reorganized according to a unified data structure to construct a multi-dimensional feature expression with clear semantic hierarchy, providing basic data structure support for dimension-level feature extraction. In the computing power execution dimension, the metrics of computing unit utilization, instruction throughput, and execution pause ratio are extracted, and abnormal fluctuations are amplified by combining state confidence. In the feature extraction process of the computing power execution dimension, three core metrics—computing unit utilization, instruction throughput, and execution pause ratio—are selected from the recombined multidimensional features. Among them, computing unit utilization is used to characterize the utilization level of chip computing resources, instruction throughput is used to reflect the computing execution capability per unit time, and execution pause ratio is used to describe the ineffective execution time of the computing pipeline. In actual computing, the above metrics are obtained through instruction execution logs and resource scheduling records within the statistical period, and abnormal fluctuation data are weighted and amplified by combining state confidence, so that performance fluctuations under higher confidence states have a higher impact weight, thereby enhancing the sensitivity to abnormal computing power states. In the memory access dimension, cache hit rate, bandwidth utilization, and access latency distribution are extracted, and a confidence gating mechanism is used to suppress low-reliability interval data. In the feature extraction process of the memory access dimension, cache hit rate, bandwidth utilization, and access latency distribution are extracted from the corresponding dimension data. Among them, cache hit rate is used to reflect data access efficiency, bandwidth utilization is used to characterize the storage channel usage, and access latency distribution is used to characterize the temporal stability of storage access. In actual implementation, the above indicators are obtained by statistical analysis of on-chip cache access logs and memory controller records, and a confidence gating mechanism is introduced to suppress low-reliability interval data. When the state confidence is lower than a preset threshold, the weight of the data in that interval is reduced, thereby reducing the interference of abnormal sampling on the overall feature expression. In the power consumption scheduling dimension, the power change gradient, voltage-frequency coordinated change trend, and energy efficiency ratio are extracted to form a power consumption dynamic feature vector. In the feature extraction process of the power consumption scheduling dimension, the power change gradient, voltage-frequency coordinated change trend, and energy efficiency ratio are extracted. The power change gradient is used to describe the speed characteristics of power consumption change over time, the voltage-frequency coordinated change trend is used to reflect the coupling relationship between voltage and frequency during DVFS regulation, and the energy efficiency ratio is used to measure the computational output efficiency per unit power consumption. In the specific implementation, the above indicators are calculated by jointly analyzing the power consumption data, voltage regulation records, and frequency change logs recorded by the power management unit, thereby forming a power consumption dynamic feature vector that can reflect the dynamic change law of chip energy consumption. A unified sensitive feature vector is constructed by concatenating and standardizing three types of features. Different weights are assigned to each dimension based on confidence level, and the sensitive features are output. When concatenating features from the three dimensions of computing power execution, memory access, and power scheduling, the features of each dimension are standardized to map indicators of different dimensions to a unified numerical range to eliminate the influence of differences in dimensions. Subsequently, the three standardized features are concatenated in dimensional order to construct a unified sensitive feature expression vector. Different weights are assigned to different dimension features based on state confidence level, with the weight of dimension features corresponding to high-confidence states increased to enhance their contribution to the overall feature expression. Finally, a sensitive feature result with weighted expression capability is output.

[0022] The process of generating lightweight verification workload tasks in S2 is as follows: The frequency rise phase, frequency fall phase, and stable operation phase are identified based on the DVFS state segmentation. Based on the DVFS state segmentation results, the frequency change characteristics corresponding to different DVFS states during the operation of the AI ​​chip are identified. The frequency rise phase corresponds to the acceleration process of the chip switching from low frequency to high frequency, the frequency fall phase corresponds to the deload process from high frequency to low frequency, and the stable operation phase corresponds to the operation state in which the frequency and voltage remain relatively constant. By performing time segmentation analysis on the frequency sampling sequence in the chip operation log and combining it with the DVFS control signal records, the start and end time points of each phase are determined, thereby completing the division of different operation phases. State-aware constraints are constructed based on the feature boundaries of each stage, including the computing power occupancy threshold range, memory access pressure range, and power consumption change rate limit. Based on each DVFS operation stage, feature boundary ranges are extracted according to the statistical results of historical operation data of the corresponding stage. The computing power occupancy threshold range is determined by statistically analyzing the average utilization rate of computing units under different frequency states, the memory access pressure range is determined by the distribution range of memory bandwidth occupancy rate, and the power consumption change rate limit is calculated by comprehensively calculating the historical maximum value of the power consumption change gradient per unit time and the stable threshold. By performing segmented statistical analysis on historical operation data and establishing a stage feature distribution model, state-aware constraints reflecting resource usage constraints under different DVFS states are constructed. A mapping rule between features and load behavior is established. Sensitive features are combined and mapped according to the dimensions of computing power execution, memory access, and power consumption scheduling to determine the corresponding compute-intensive, memory-intensive, or combined verification load types. When establishing the mapping rule between features and load behavior, sensitive features are categorized and combined according to three dimensions: computing power execution, memory access, and power consumption scheduling. The computing power execution dimension corresponds to feature combinations with high computing power ratio, the memory access dimension corresponds to feature combinations with high memory access, and the power consumption scheduling dimension corresponds to feature combinations related to energy consumption changes. A mapping rule library is constructed based on the correspondence between different feature combination modes and predefined load behavior templates. Compute-intensive loads correspond to high computing power feature combinations, memory-intensive loads correspond to feature combinations with high bandwidth and access frequency, and combined loads correspond to the balanced distribution of multi-dimensional features, thereby realizing the mapping determination from features to load types. Based on the current state characteristics and constraints, the corresponding load template is matched in the mapping rules; the similarity between the current state feature vector and the feature descriptions of each load template in the rule base is calculated. The similarity calculation is based on the weighted matching of the three-dimensional feature distance of computing power, memory access and power consumption. The load template that is closest to the current state characteristics is selected as the basic execution model. The applicable scope of the template is verified by combining the state-aware constraints, so as to determine the final matched lightweight verification load execution model. By combining the weight distribution of sensitive features, the parameters of load scale, execution duration, and trigger frequency are adjusted to generate a lightweight verification load task that meets the constraints and has minimal disturbance to chip operation. The load execution parameters are dynamically adjusted according to the weight distribution of sensitive features, where the resource consumption dimension corresponding to the feature with higher weight has higher priority. The computation scale parameter of the load is adjusted according to the computing power weight, the data access intensity parameter is adjusted according to the memory access weight, and the execution duration and trigger frequency parameter are adjusted according to the power consumption weight. By linearly scaling or piecewise adjusting the load parameters, the generated verification load maintains minimal disturbance to the normal operation of the chip while meeting the state-aware constraints, thus outputting a lightweight verification load task suitable for real-time verification scenarios.

[0023] S3: Embed lightweight verification workload tasks into the chip execution cycle and schedule them in time alignment with the real-time performance sampling process. Synchronously collect response characteristic data and monitoring sampling data of the verification workload to form dual-source performance observation data.

[0024] The time-aligned scheduling process for real-time performance sampling in S3 is as follows: In the chip scheduling control layer, low-priority execution channels are allocated to verification load tasks, and the insertion time window is determined based on the current task queue status. When scheduling verification load tasks in the chip scheduling control layer, the verification load tasks are marked as low-priority task types and connected to the chip's unified task scheduling queue. The scheduling controller manages the queuing according to the task priority strategy, and at the same time, it obtains the occupancy status of computing tasks, memory access tasks, and system maintenance tasks in the current task queue in real time. By scanning and analyzing the queue execution status, idle periods of computing resources or low-load execution gaps are identified, thereby determining the time window that can be used to insert verification load tasks. Based on the DVFS switching time node, the triggering time of the verification load is aligned to the critical time slices before and after the state transition. When aligning the triggering time based on the DVFS switching time node, the DVFS state change records output by the chip voltage and frequency control module are obtained, the time boundary points of frequency rise, fall or stabilization are extracted, and these are used as the critical time nodes of the state transition. The triggering time of the verification load task is remapped so that its triggering time is aligned to the critical time slice interval before and after the DVFS state change. This ensures that the execution process of the verification load can cover the transient change stage of the chip's dynamic frequency adjustment process and improves the ability to observe dynamic performance fluctuations. Within the insertable time window, the verification load execution cycle and the performance sampling cycle are jointly scheduled. When performing joint scheduling within the insertable time window, the verification load execution cycle and the performance sampling cycle are uniformly included in the management of the scheduling controller. By uniformly dividing the time granularity of the two types of cycles, they are mapped to the same time slice scheduling framework. Under this framework, the running rhythm of the verification load execution task and the performance sampling task are coordinated in an alternating or parallel manner, so that the verification load execution process can form a time overlap relationship with the sampling window, thereby realizing synchronous observation and data acquisition of the chip's operating status within the same time interval. The system dynamically adjusts its workload based on chip resource usage. When the system load exceeds a preset threshold, the execution scale of the verification load is delayed or reduced to complete the embedding and time-aligned scheduling of the verification load tasks within the chip execution cycle. By monitoring the chip's computing unit utilization, memory access bandwidth utilization, and power consumption in real time, the overall system load status is determined. When the system load is detected to exceed a preset resource threshold, the scheduling controller triggers a load protection mechanism to dynamically adjust the execution scale of the verification load tasks. The adjustment methods include reducing the number of concurrent executions, extending the task trigger interval, or reducing the computational load of a single execution, thereby reducing the impact of the verification load on system resource usage. Ultimately, while ensuring the normal operation and stability of the chip, the system achieves smooth embedding and time-aligned scheduling of the verification load tasks within the execution cycle.

[0025] The process of generating dual-source performance observation data in S3 is as follows: During the execution of the verification load, execution response data, including execution latency, throughput changes, and power consumption response curves, are collected through a dedicated monitoring channel. During the execution of the verification load, the running response of the verification load is collected in real time through a dedicated monitoring channel set up inside the chip. The dedicated monitoring channel is independent of the main performance sampling path to avoid sampling interference. The collected content includes task execution latency information, throughput changes per unit time, and power consumption response curve data over time. The latency data is obtained through the task scheduling receipt time difference, the throughput change is obtained through instruction completion rate statistics, and the power consumption response curve is generated by continuous sampling through the on-chip power consumption sensing module, thus forming response data that reflects the actual execution behavior of the verification load. Multi-source monitoring sampling data within the corresponding time window is obtained through the regular performance sampling channel. The sampling data includes computing power utilization, memory access bandwidth utilization, power consumption changes, and frequency status information. The sampling process adopts a fixed sampling period or a dynamic adaptive sampling period and is consistent with the execution time window of the verification load. The time window constraint mechanism ensures that the sampling data covers the entire process of the verification load execution, thereby obtaining system-level performance observation data corresponding to the verification execution environment. Both types of data are uniformly labeled with time tags and status identifiers, and time alignment processing is performed to form paired observation data units. The verification load execution response data and the regular performance sampling data are uniformly labeled with time tags. The two types of data are reconstructed with timestamps based on a unified clock source, and the chip's current operating status identifier is introduced for synchronization marking. The two types of data are matched through a time alignment algorithm to form a one-to-one correspondence between data within the same time slice, thereby constructing paired observation data units to ensure the comparability and consistency of verification response and system sampling in the time dimension. The paired observation data units are encapsulated in a structured manner to output dual-source performance observation data containing both the reference source and the observed source. The verification load execution response data is used as the reference observation data source, and the regular performance sampling data is used as the system observation data source. The data is organized uniformly according to the dimensions of time slice, status identifier, and performance index. By constructing a unified data structure, the two types of data are bound and stored according to their corresponding relationships, forming dual-source performance observation data containing both the reference source and the observed source. This provides a structured input basis for consistency analysis, deviation calculation, and performance correction.

[0026] S4: Based on dual-source performance observation data, establish a consistency constraint relationship between the sampled data and the verification response. Through the inversion calculation of the verification response and the feature mapping processing of the sampled data, calculate the time offset and state deviation between the two, and identify the conflict area of ​​performance observation.

[0027] The process of establishing consistency constraints between sampled data and verification responses in S4 is as follows: Based on dual-source performance observation data, combined with the known input characteristics and expected execution behavior of the verification load, a theoretical response curve is generated. Input characteristic parameters, including computational intensity setpoints, memory access modes, and power consumption constraints, are extracted from the verification load task definition. Combined with the historical execution records of the chip in a stable DVFS state, a correspondence between input parameters and output performance indicators is established. The expected execution behavior of the verification load in different operating states is segmented and extrapolated to generate a theoretical performance response curve that changes over time, which is used to characterize the performance evolution trend that the chip should exhibit under ideal consistency conditions. The actual verification response data is compared and matched with the theoretical response curve to obtain the reference response deviation range. The two types of data are uniformly mapped to the same time reference coordinate system, and a sliding time window method is used to compare them segment by segment. By calculating the deviation difference of the response values ​​within the same time slice, the degree of response deviation in each time interval is obtained. The degree of deviation is aggregated to form a continuous reference response deviation range, which is used to describe the deviation range of the actual execution process from the theoretical execution model. Based on the reference response deviation interval and state confidence, a correspondence between the sampled data and the verification response is constructed to form a mapping relationship. The state confidence is introduced as a data reliability weighting factor into the deviation analysis process, and the data at different confidence levels are weighted and adjusted. At the same time, with the reference response deviation interval as the constraint boundary, the performance indicators in the sampled data and the verification response data are correlated and matched within the same time slice, thereby establishing a mapping structure that reflects the consistency relationship between the two types of data, which is used to characterize the deviation mapping relationship between the sampled observation and the verification response. DVFS state parameters are introduced as constraint variables in the mapping relationship to limit the allowable deviation range under different states. The DVFS state identifiers of the corresponding time slices during chip operation are obtained, including frequency level, voltage level and state switching flag, and are embedded as constraint dimensions into the mapping relationship model. Based on the difference in the available range of chip resources under different DVFS states, the allowable deviation range is limited by state, so that different consistency tolerance ranges correspond to high frequency operation, low frequency operation and state transition stages, thereby avoiding the error amplification problem caused by dynamic frequency adjustment. Based on constraint variables, a consistency constraint relationship is established between sampled data and verification response. When establishing the consistency constraint relationship between sampled data and verification response based on DVFS constraint variables, the above mapping relationship and state constraint conditions are jointly constrained to ensure that the sampled data and verification response meet the deviation limit conditions of the corresponding state in dimensions such as computing power utilization, memory access bandwidth and power consumption changes. By calculating the intersection of the state constraint boundary and the mapping deviation range, a constraint relationship describing the consistency degree of the two types of data is finally formed, providing a basis for performance deviation identification and conflict area location.

[0028] The process of identifying conflicting regions in performance observations in S4 is as follows: Based on the input-output relationship of the verification load in the dual-source performance observation data, the verification response data is deduced in reverse to obtain the corresponding theoretical performance state. When deducing the verification response data in reverse based on the input-output relationship of the verification load in the dual-source performance observation data, we start from the input parameters of the verification load, including the scale of the computation task, the memory access mode and the power consumption constraint settings, and combine them with the historical operating characteristics of the chip in the corresponding DVFS state to reverse-engineer the performance output behavior that it may produce. By establishing the inverse mapping relationship between the input parameters and the performance output, we derive the theoretical performance state that the verification load should correspond to under ideal consistency conditions, which is used to characterize the standardized performance of the verification execution process. Align and match the theoretical performance state with the state features corresponding to the sampled data, calculate the optimal alignment position on the time axis, and obtain the time offset accordingly. Map both types of data to the same time reference coordinate system, and scan the state feature sequence segment by segment based on a sliding time window. By calculating the matching error of the two types of state sequences under different time offset assumptions, determine the time alignment position with the smallest error, thereby obtaining the optimal time axis alignment result. Based on this, calculate the time offset of the sampled data relative to the verification response data to reflect the degree of misalignment of the two types of data in the time dimension. Based on consistency constraints, the state deviation values ​​of the sampled data and the verification response in terms of computing power, memory access, and power consumption are calculated. The sampled data and the verification response data are compared dimension by dimension at the same time alignment position. The deviation is calculated based on the difference in computing unit utilization in the computing power dimension, the difference in memory access in the memory access dimension, and the difference in power consumption in the power consumption dimension. By weighting and integrating the deviations of each dimension, a comprehensive state deviation value is obtained, which is used to characterize the degree of consistency deviation between the two types of data in the multi-dimensional performance space. When the time offset or state deviation exceeds a preset threshold, the corresponding time segment is marked as a performance observation conflict area. The preset threshold is determined based on the system stability boundary under different DVFS states. By statistically analyzing the normal and abnormal intervals in historical operating data, a joint judgment condition of the time offset threshold and the state deviation threshold is set. When either indicator exceeds the corresponding threshold, it is considered that there is a consistency mismatch between the sampled data and the verification response within that time interval, thus marking that time segment as a performance observation conflict area, providing a basis for data correction and fusion.

[0029] S5: For performance observation conflict areas, combining DVFS constraints, resource boundaries and performance coupling relationships, the sampled data and verification response data are weighted and fused and time offset compensated to output AI chip performance data after dual-source consistency correction and time offset compensation.

[0030] The process of outputting AI chip performance data after dual-source consistency correction and time offset compensation in S5 is as follows: For the marked performance observation conflict areas, the weight allocation coefficients of the sampled data and the verification response data are determined by combining the current state of DVFS and the state confidence. The DVFS operating state corresponding to the conflict time segment is obtained, including frequency level, voltage level and state switching type. The reliability of the data in this state is quantitatively evaluated by combining the state confidence. According to the stability difference between the sampled data and the verification response data in different DVFS states, the two types of data are assigned basic weight coefficients respectively. The data with higher state stability corresponds to higher weight, and the data with larger state transition or fluctuation corresponds to lower weight, thus forming the weight allocation coefficients used for fusion calculation. By combining the upper limit of chip resource usage and the coupling relationship between various performance indicators, data that does not meet the resource boundary constraints are screened and corrected. Based on the upper limit of chip resource usage, constraint thresholds for computing power, memory access, and power consumption are set, and the sampled data and verification response data are compared and analyzed item by item. When a certain performance indicator is detected to exceed the resource boundary constraints, the data is marked as an anomaly, and interpolation correction or trend regression correction is performed in combination with the smoothed data of adjacent time slices to weaken the impact of transient anomalies on the overall performance characterization, thereby obtaining data that meets the resource constraint conditions. Based on the corrected data and weight allocation results, time axis compensation processing is performed on the sampled data according to the calculated time offset. The timestamps of the sampled data are shifted or segmented according to the time offset to realign them with the verification response data in the time dimension. By using the optimal alignment position as a reference, offset correction is performed on the sampled data in different time intervals to re-establish the consistency of the data correspondence in each time slice, thereby eliminating the time misalignment error caused by DVFS transient switching. After completing time axis compensation, the aligned sampled data and verification response data are weighted and fused based on the weight allocation coefficients to output AI chip performance data that has completed dual-source consistency correction and time offset compensation. The sampled data and verification response data are fused time-slice based on the weight allocation coefficients. The fusion process is weighted according to computing power, memory access and power consumption dimensions, and a comprehensive performance output value is generated under a unified time axis. By continuously splicing the fusion results of each time slice, the AI ​​chip performance data after dual-source consistency correction and time offset compensation is output for performance evaluation and scheduling analysis.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0032] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for acquiring performance data of an AI chip, characterized in that, Includes the following steps: Multi-source monitoring data is collected during the operation of the AI ​​chip, and combined with historical operation sequences and DVFS state switching trajectories, the collected data is processed for time alignment and state encoding to generate state feature information and corresponding state confidence. Based on state feature information and state confidence, sensitive features in the dimensions of computing power execution, memory access and power scheduling are extracted. Combined with the characteristics of DVFS switching phase, state-aware constraints are formed. The type and parameters of the verification load are determined by the feature-load mapping rules, and a lightweight verification load task is generated. Lightweight verification workload tasks are embedded into the chip execution cycle and time-aligned with the real-time performance sampling process. Response characteristic data and monitoring sampling data of the verification workload are collected synchronously to form dual-source performance observation data. Based on dual-source performance observation data, a consistency constraint relationship is established between the sampled data and the verification response. By inverting the verification response and processing the feature mapping of the sampled data, the time offset and state deviation between the two are calculated, and the conflict area of ​​performance observation is identified. For areas of performance observation conflict, the sampling data and verification response data are weighted, fused, and time-off compensated by combining DVFS constraints, resource boundaries, and performance coupling relationships. The resulting AI chip performance data is then output after dual-source consistency correction and time-off compensation.

2. The method for acquiring performance data of an AI chip according to claim 1, characterized in that, The process of generating state feature information and corresponding state confidence is as follows: The on-chip performance monitoring unit and external monitoring interface synchronously collect the computing power utilization, memory access bandwidth, power consumption, voltage, frequency and temperature of the AI ​​chip to form the raw monitoring data stream. Timestamp reconstruction and clock domain alignment are performed on multi-source monitoring data streams based on a unified time reference. By combining the time location and duration information of DVFS state transitions in historical operation sequences, the monitoring data stream is segmented and marked to construct a state segmentation that includes stable and transitional segments; For state segmentation, segmented normalization and sliding window statistical methods are used to extract basic statistical features, and DVFS switching direction and switching rate are introduced as auxiliary coding variables. The extracted features are mapped to a state representation vector of a unified dimension. The corresponding state confidence coefficient is calculated by combining the historical stability distribution and the current fluctuation amplitude, and the state feature information and state confidence are output.

3. The method for acquiring performance data of an AI chip according to claim 2, characterized in that, The process of extracting sensitive features from the dimensions of computing power execution, memory access, and power consumption scheduling is as follows: The state feature information is reorganized according to three dimensions: computing power execution, memory access, and power consumption scheduling to construct multi-dimensional features; In the computing power execution dimension, the indicators of computing unit utilization, instruction throughput and execution pause ratio are extracted, and abnormal fluctuations are amplified by combining state confidence. In the memory access dimension, cache hit rate, bandwidth utilization and access latency distribution are extracted, and low reliability interval data is suppressed through a confidence gating mechanism. In the power consumption scheduling dimension, the power change gradient, voltage-frequency coordinated change trend and energy efficiency ratio index are extracted to form a power consumption dynamic feature vector. A unified sensitive feature vector is constructed by concatenating and standardizing the three types of features. Different weights are assigned to each dimension according to the confidence level, and the sensitive features are output.

4. The performance data acquisition method for an AI chip according to claim 3, characterized in that, The process of generating a lightweight verification workload task is as follows: Based on the DVFS state segmentation, the frequency rise phase, frequency fall phase, and stable operation phase are identified. State-aware constraints are constructed based on the feature boundaries of each stage, including the computing power occupancy threshold range, memory access pressure range, and power consumption change rate limit. Establish mapping rules between features and load behavior, combine and map sensitive features according to the dimensions of computing power execution, memory access, and power consumption scheduling, and determine the corresponding compute-intensive, memory-intensive, or combined verification load types; Based on the current state characteristics and constraints, match the corresponding load template in the mapping rules; By combining the weight distribution of sensitive features, the parameters of load size, execution time and trigger frequency are adjusted to generate a lightweight verification load task that meets the constraints and has little disturbance to chip operation.

5. The performance data acquisition method for an AI chip according to claim 4, characterized in that, The process of time-aligned scheduling with the real-time performance sampling process is as follows: In the chip scheduling and control layer, a low-priority execution channel is allocated for the verification workload task, and the insertable time window is determined in combination with the current task queue status; Based on the DVFS switching time node, the triggering time of the verification load is aligned with the critical time slices before and after the state transition; Within the insertable time window, the execution cycle of the verification load and the performance sampling cycle are jointly scheduled; The system dynamically adjusts its workload based on chip resource usage. When the system load exceeds a preset threshold, the execution scale of the verification load is delayed or reduced, thus completing the embedding and time-aligned scheduling of the verification load task within the chip execution cycle.

6. The method for acquiring performance data of an AI chip according to claim 5, characterized in that, The process of generating dual-source performance observation data is as follows: During the verification load execution, execution response data, including execution latency, throughput changes, and power consumption response curves, are collected through a dedicated monitoring channel. Multi-source monitoring sampling data within the corresponding time window is obtained through the conventional performance sampling channel; Both types of data are uniformly labeled with time tags and status identifiers, and time alignment processing is performed to form paired observation data units; The paired observation data units are encapsulated in a structured manner to output dual-source performance observation data containing both the reference source and the observed source.

7. The performance data acquisition method for an AI chip according to claim 6, characterized in that, The process of establishing consistency constraints between sampled data and verification responses is as follows: Based on dual-source performance observation data, combined with the known input characteristics and expected execution behavior of the verification load, a theoretical response curve is generated. The actual verification response data is compared and matched with the theoretical response curve to obtain the reference response deviation range; Based on the reference response deviation range and state confidence, a correspondence between the sampled data and the verification response is constructed to form a mapping relationship; Introducing DVFS state parameters as constraint variables into the mapping relationship limits the allowable deviation range under different states; Based on constraint variables, establish consistency constraint relationships between sampled data and verification responses.

8. The method for acquiring performance data of an AI chip according to claim 7, characterized in that, The process of identifying conflict areas in performance observation is as follows: Based on the input-output relationship of the verification load in the dual-source performance observation data, the verification response data is reverse-derived to obtain the corresponding theoretical performance state; Align and match the theoretical performance state with the state features corresponding to the sampled data, calculate the optimal alignment position on the time axis, and obtain the time offset accordingly. Based on the aforementioned consistency constraint relationship, calculate the state deviation values ​​between the sampled data and the verification response in terms of computing power, memory access, and power consumption. When the time offset or state deviation exceeds a preset threshold, the corresponding time segment will be marked as a performance observation conflict area.

9. The performance data acquisition method for an AI chip according to claim 8, characterized in that, The process of outputting AI chip performance data after dual-source consistency correction and time offset compensation is as follows: For the marked performance observation conflict areas, the weight allocation coefficients of the sampled data and the verification response data are determined by combining the current state of DVFS and the state confidence. By combining the upper limit of chip resource usage and the coupling relationship between various performance indicators, data that does not meet the resource boundary constraints are filtered and corrected. Based on the corrected data and weight allocation results, time axis compensation processing is performed on the sampled data according to the calculated time offset. After completing time axis compensation, the aligned sampled data and verification response data are weighted and fused based on the weight allocation coefficients to output AI chip performance data that has completed dual-source consistency correction and time offset compensation.

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