A MIPI C-PHY high-speed receiver circuit integrated with automatic calibration function

Abstract

This invention discloses a high-speed MIPI C-PHY receiver circuit with integrated automatic calibration function, belonging to the field of integrated circuit technology. It includes a 3-wire termination circuit, an analog front-end receiving circuit, a clock data recovery circuit, and a decoder and serial-to-parallel conversion circuit. The clock data recovery circuit is the core innovation, comprising: a digitally controllable delay line (DCDL) for generating a delayed signal; an edge synthesis unit for generating a pulse signal (EDGE_CLK); and a clock generation unit for generating a recovered clock (RCLK). This invention effectively shields redundant switching points in the MIPI C-PHY multi-level signal through automatic calibration and can quickly lock onto a wide operating rate range, significantly improving the receiver's performance and reliability.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function. Background Technology

[0002] With the development of high-resolution displays, multi-camera modules, and technologies such as AI and 5G communication in smartphones, the bandwidth and power efficiency of chip interfaces also need to be improved accordingly. Unlike the simple source-synchronous scheme used in the D-PHY protocol, the C-PHY protocol proposed by MIPI (Mobile Industry Processor Interface) embeds the clock into the data channel through a unique encoding method, thus eliminating the need for a dedicated clock channel. The encoding technology and state mapping scheme used in C-PHY increase the data rate by 2.28 times, effectively reducing system power consumption while improving signal transmission rate and pin utilization efficiency.

[0003] The Symbol encoding rules defined by C-PHY ensure that a level flip occurs at each UI (unit interval) boundary, allowing the clock signal to be recovered from the bus for subsequent data sampling. While the clock recovery process of C-PHY is relatively simple, timing discrepancies can occur in the outputs of different receiver circuits when multiple input signals change simultaneously. This is mainly due to differences in the rise / fall times of the input signals and slight variations in the delay times of each receiver circuit depending on the input amplitude. This results in C-PHY's clock recovery circuit having inferior tracking capabilities compared to traditional high-speed clock recovery circuits.

[0004] Furthermore, as the signal rate increases, factors such as inter-symbol interference (ISI), reflection, and transmitter jitter will further degrade the performance of the receiving circuit, ultimately leading to data reception errors. Summary of the Invention

[0005] The purpose of this invention is to provide a MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function. This circuit effectively shields redundant flip-point signals caused by the influence of the transmitter signal and the external environment through automatic calibration. Moreover, the automatic calibration process has a fast locking capability, which improves the receiver performance and reduces the latency of the entire link, thus solving the problems mentioned in the background art.

[0006] The present invention aims to provide a MIPI C-PHY receiver circuit with integrated automatic calibration function and its clock data recovery method, so as to solve the problems of clock recovery failure due to redundant zero crossings and the inability of fixed delay schemes to adapt to a wide operating rate range in the prior art.

[0007] To achieve the above objectives, according to one aspect of the present invention, a MIPIC-PHY receiver circuit with integrated automatic calibration function is provided.

[0008] Preferably, the circuit includes a 3-wire termination circuit, an analog front-end receiving circuit, a clock data recovery circuit, and a decoder and serial-to-parallel conversion circuit; A 3-wire termination circuit is used to receive three linear signals A, B, and C from the transmitting end; An analog front-end receiving circuit, connected to the 3-wire termination circuit, includes three differential amplifiers for converting the three linear signals A, B, and C into three differential signals RX_AB, RX_BC, and RX_CA. A clock data recovery circuit, connected to the analog front-end receiving circuit, is used to recover the clock and sample data from the three differential signals RX_AB, RX_BC, and RX_CA; and The decoder and serial-to-parallel conversion circuit are connected to the clock data recovery circuit and are used to decode the sampled data and convert it into parallel data, which is then sent to the data logic domain to complete the final data processing. The clock data recovery circuit includes: A digitally controllable delay line, controlled by a first control signal PG_CODE, is used to delay the three differential signals respectively, generating three delayed signals AB_DLY, BC_DLY, and CA_DLY. The edge synthesis unit is used to perform an XOR operation on each differential signal and its corresponding delayed signal, and to perform an OR operation on the XOR result to generate the pulse signal EDGE_CLK. A clock generation unit is configured to generate an internal feedback clock signal RCLK_INT and a recovery clock RCLK based on the pulse signal EDGE_CLK; and An automatic calibration unit is used to adjust the second control signal CODE in a successive approximation manner according to the pulse signal and the internal feedback clock signal RCLK_INT, so as to adjust the delay of the digitally controllable delay line and thereby calibrate the duty cycle of the recovery clock RCLK to 50%.

[0009] Preferably, the clock generation unit includes: The trigger receives the pulse signal EDGE_CLK at its clock input and outputs the internal feedback clock signal RCLK_INT at its output. The AND gate takes the output signal "done" of the automatic calibration unit as its first input, the internal feedback clock signal "RCLK_INT" as its second input, and outputs the recovery clock "RCLK".

[0010] Preferably, the automatic calibration unit includes: A frequency counter is used to compare the frequency or duty cycle of the pulse signal EDGE_CLK with that of the internal feedback clock signal RCLK_INT. The digital logic control module is used to generate the second control signal CODE using a successive approximation algorithm based on the comparison result of the frequency meter, so as to control the delay step of the digitally controllable delay line.

[0011] Preferably, the clock data recovery circuit further includes a data sampling unit, which uses the recovery clock RCLK to sample the three delayed signals AB_DLY, BC_DLY, and CA_DLY to obtain the linear signal D_PRE<2:0>.

[0012] Preferably, the analog front-end receiving circuit also integrates a continuous-time linear equalizer to compensate for channel loss.

[0013] Preferably, the decoder and serial-to-parallel conversion circuit includes: The decoder circuit is used to convert the input linear signal D_PRE<2:0> into the signal D_POST<2:0> corresponding to the Symbol state; A serial-to-parallel conversion circuit is used to convert a single Symbol signal into low-rate L+1 bit Symbol data DATA_0. <l:0>、DATA_1 <l:0>and DATA_2 <l:0>The data is then sent to the digital logic unit for final data processing.

[0014] According to another aspect of the present invention, a clock data recovery method for a MIPI C-PHY receiver circuit is provided, the method comprising the following steps: receiving three differential signals; delaying the three differential signals through a digitally controllable delay line to generate three delayed signals; performing an XOR operation on each differential signal and its corresponding delayed signal, and performing an OR operation on the three XOR results to generate a pulse signal; generating a recovered clock based on the pulse signal; and performing an automatic calibration process: adjusting a control signal in a successive approximation manner according to the pulse signal and an internal feedback clock signal to adjust the delay amount of the digitally controllable delay line, thereby calibrating the duty cycle of the recovered clock to 50%.

[0015] Compared with the prior art, the beneficial effects of the present invention are: This invention integrates an automatic calibration function into a MIPI C-PHY high-speed receiver circuit, constructing a complete C-PHY receiver data reception link. It covers the front-end processing flow from port input to data recovery, specifically including a 3-wire termination circuit, an analog front-end circuit (AFE) with an integrated continuous-time linear equalizer, a clock data recovery circuit with automatic calibration, and a decoder and serial-to-parallel conversion circuit. By introducing the automatic calibration function, this invention can meet the C-PHY protocol's requirements for a wide operating rate range and low link latency, while effectively shielding redundant switching points caused by the transmitter signal and external environmental influences, significantly improving the C-PHY receiver circuit's tolerance to various non-ideal factors. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the MIPI C-PHY link system according to an embodiment of the present invention; Figure 2 This is an overall structural block diagram of the MIPI C-PHY receiver circuit described in an embodiment of the present invention; Figure 3 This is a failure timing diagram of an uncalibrated clock data recovery circuit in the prior art; Figure 4 This is a structural diagram of the clock data recovery circuit with integrated automatic calibration function described in an embodiment of the present invention; Figure 5 This is a timing diagram of the automatic calibration and data sampling of the clock data recovery circuit according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0018] like Figure 1 As shown, the C-PHY protocol uses a "triad" approach, meaning that data transmission is achieved through the combined action of three signal lines: A, B, and C. The entire MIPI C-PHY link mainly consists of three parts: the transmitting chip, the interconnect channel, and the receiving chip.

[0019] In the illustration, the transmitting chip is typically an image sensor used for data acquisition. This chip first converts the acquired data (DATA) into parallel Symbol data according to the mapping rules specified by the C-PHY. Then, a parallel-to-serial conversion circuit converts multiple parallel Symbol data into a single serial Symbol data. The encoder's role is to encode the input Symbol signal into a linear signal suitable for link transmission, i.e., a three-wire A, B, and C signal, which is finally transmitted to the interconnect channel via the driver circuit.

[0020] The interconnect channel between the transmitting and receiving ends carries the communication signals of the C-PHY and typically consists of multiple parts, such as PCB traces, connectors, and cables. With increasing transmission rates, the negative impacts of factors such as skin effect, dielectric loss, and impedance discontinuities will severely limit signal integrity.

[0021] The receiver chip is typically a System-on-a-Chip (SoC) for data processing. This chip receives signals through three differential amplifier circuits and sends the received signals to a clock data recovery circuit to recover the embedded clock and sample the data. Subsequently, the recovered clock is used to transmit the sampled linear data to the decoder to recover the Symbol data. A serial-to-parallel conversion circuit is responsible for converting individual Symbol data into parallel Symbol data, and finally converting it into the corresponding data (DATA) according to the mapping rules specified in the protocol, thus completing the data transmission of the entire link.

[0022] like Figure 2 As shown in the example, the high-speed receiver circuit for C-PHY proposed in this invention mainly consists of four parts: a 3-wire termination circuit, an analog front-end receiver circuit (AFE), a clock data recovery circuit (CDR), and a decoder and serial-to-parallel conversion circuit.

[0023] The 3-wire termination circuit is responsible for differential termination and impedance matching of signal reception, and is the first stage of signal reception circuitry. The analog front-end receiver (AFE) circuit mainly contains three differential amplifiers, whose outputs are used to determine the three-level signal state at the data transmission end. This AFE circuit integrates an optional continuous-time linear equalizer (CTLE) to compensate for channel loss. Subsequently, the three-level signal received by the AFE is sent to a clock data recovery circuit (CDR) with automatic calibration function to recover the embedded clock and mask redundant clock transition edges. At the same time, the CDR circuit synchronizes the sampled data to the recovered clock domain. Finally, the decoder circuit converts the linear signal into symbol data, and the serial-to-parallel conversion circuit converts a single symbol data into multiple symbol data, which are then sent to the data logic domain to complete the final data processing.

[0024] like Figure 3 As shown in the example, because the MIPI C-PHY protocol embeds the clock into the data, the receiving circuitry needs to extract the clock from the data. Although MIPI C-PHY generates corresponding transition edges at each line state switch, due to its multi-level signal transmission mechanism, the received differential signal will have multiple zero-crossing points. These redundant zero-crossing points will cause the clock recovery circuit to fail to extract the clock, resulting in data errors at the receiving end of the entire C-PHY system.

[0025] Figure 3 The diagram illustrates the timing of a clock recovery circuit failure when conventionally uncalibrated. As can be seen, two transition edges occur during the state transition. If the additional RCLK edge is not effectively masked, the clock extracted by the clock recovery circuit will contain redundant clock cycles, leading to data sampling errors.

[0026] Furthermore, MIPI C-PHY is a protocol covering a wide range of data rates. Taking the MIPI V2.1 protocol as an example, its minimum operating rate can reach 80 MSymbol / s, and its maximum rate can reach over 3.5 GSymbol / s. In this case, units using fixed shielding delay times can no longer meet the high-reliability clock recovery circuit requirements of C-PHY. Therefore, a clock recovery circuit capable of automatically calibrating according to the operating frequency is needed to achieve reliable clock extraction and data sampling.

[0027] like Figure 4 As shown, this invention proposes a clock data recovery circuit suitable for C-PHY with automatic calibration function. The input signals of this circuit are the outputs RX_AB, RX_BC, and RX_CA of the receiving differential amplifier, where the differential amplifier is located in the analog front-end receiver circuit (AFE), and its function is to convert the input signals A, B, and C into differential signal outputs, corresponding to RX_AB, RX_BC, and RX_CA, respectively.

[0028] In the clock data recovery circuit, signals RX_AB, RX_BC, and RX_CA, along with signals AB_DLY, BC_DLY, and CA_DLY (delayed by a digitally controlled delay line (DCDL)), are sent to the inputs of three XOR gates. After subsequent OR operations, the resulting pulse signal EDGE_CLK is used for clock recovery. The DCDL is controlled by an M+1-bit digital signal PG_CODE. <m:0>Control, used to adjust the width of the pulse signal.

[0029] Furthermore, the generated pulse signal EDGE_CLK is sent to a flip-flop, and after an AND operation, it generates the recovery clock RCLK, which maintains a corrected duty cycle of approximately 50% in the entire clock data recovery circuit. The recovery clock RCLK samples the signals AB_DLY, BC_DLY, and CA_DLY, which have been delayed by DCDL, thereby completing the data sampling of the linear signals, and simultaneously outputs the bus signal D_PRE<2:0>.

[0030] On the other hand, the generated pulse signal EDGE_CLK is triggered by a flip-flop. The coordinated operation of the Flop, CDR automatic calibration unit, and digitally controlled delay line (DCDL) completes the automatic calibration of the EDGE_CLK duty cycle, thereby ensuring that the recovery clock RCLK maintains approximately 50% duty cycle at different operating frequencies, effectively shielding redundant toggling points caused by the transmitter signal and external environmental influences. This CDR automatic calibration process generates a 50% duty cycle signal through set and reset triggers: RCLK_INT = "1" in the set state and RCLK_INT = "0" in the reset state. The pulse signal EDGE_CLK and the signal RCLK_INT sampled by the trigger are simultaneously sent to the CDR automatic calibration unit, compared by a frequency counter, and then the digital logic performs data judgment to determine the control signal code of the digitally controlled delay line (DCDL) circuit. <n:0>The value and whether a reset operation is performed. The Digital Controlled Delay Line (DCDL) is controlled by the N+1 bit code signal. <n:0>Controlled, and code <n:0>The adjustment adopts a successive approximation method to shorten the locking time during the CDR initialization phase, thereby reducing the latency of the entire link.

[0031] Figure 5 This is the timing diagram for the automatic calibration of the RCLK duty cycle and data sampling circuit of the clock data recovery circuit. When RX_AB, RX_BC, and RX_CA undergo state transitions, a corresponding pulse signal EDGE_CLK is generated. EDGE_CLK sets RCLK_INT high through a flip-flop. After a delay set by a digitally controlled delay line (DCDL), the internal digital logic of the automatic calibration unit determines whether to set RCLK_INT low via a clear signal. If the DCDL delay setting is too large or too small, the duty cycle deviation measured by the frequency meter will increase or decrease accordingly. In this case, it is necessary to adjust the code accordingly. <n:0>DCDL is adjusted to a suitable value. After several iterative calculations, the duty cycle of RCLK_INT is locked at approximately 50%. When the automatic calibration unit completes the calibration process, it pulls the done signal high, at which point RCLK enters a stable output state, maintaining a duty cycle of approximately 50%. Simultaneously, RCLK samples the signals AB_DLY, BC_DLY, and CA_DLY, which are delayed by DCDL, and outputs the bus signal D_PRE<2:0> to the subsequent decoder circuit.

[0032] The decoder circuit converts the input linear signals D_PRE<2:0> into the corresponding Symbol state signals D_POST<2:0>. Simultaneously, the serial-to-parallel conversion circuit converts a single Symbol signal into low-rate L+1 bit Symbol data DATA_0. <l:0>、DATA_1 <l:0>and DATA_2 <l:0>It is then sent to the digital logic unit for final data processing.

[0033] This invention constructs a complete C-PHY receiver data reception link, covering the front-end processing flow from port input to data recovery. Specifically, it includes a 3-wire termination circuit, an analog front-end circuit (AFE) with an integrated continuous-time linear equalizer, a clock data recovery circuit with automatic calibration, and a decoder and serial-to-parallel conversion circuit. By introducing automatic calibration, this invention can meet the C-PHY protocol's requirements for a wide operating rate range and low link latency, while effectively shielding redundant switching points caused by transmitter signals and external environmental influences, significantly improving the C-PHY receiver circuit's tolerance to various non-ideal factors.

[0034] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0035] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function, characterized in that, The circuit includes a 3-wire termination circuit, an analog front-end receiving circuit, a clock data recovery circuit, and a decoder and serial-to-parallel conversion circuit; The 3-wire termination circuit, as the first-stage circuit for signal reception, is used to receive three linear signals A, B, and C from the transmitting end. An analog front-end receiving circuit, connected to the three-wire termination circuit, includes three differential amplifiers for converting the three linear signals A, B, and C into three differential signals RX_AB, RX_BC, and RX_CA and outputting them. A clock data recovery circuit, connected to the analog front-end receiving circuit, is used to recover the clock and sample data from the three differential signals RX_AB, RX_BC, and RX_CA; and The decoder and serial-to-parallel conversion circuit are connected to the clock data recovery circuit and are used to decode the sampled data and convert it into parallel data, which is then sent to the data logic domain to complete the final data processing. The clock data recovery circuit includes: The digitally controllable delay line DCDL, controlled by the first control signal PG_CODE, is used to delay the three differential signals RX_AB, RX_BC, and RX_CA respectively, generating three delayed signals AB_DLY, BC_DLY, and CA_DLY. The edge synthesis unit is used to perform an XOR operation on each differential signal and its corresponding delayed signal, and to perform an OR operation on the XOR result to generate the pulse signal EDGE_CLK for clock recovery. A clock generation unit is configured to generate an internal feedback clock signal RCLK_INT and a recovery clock RCLK based on the pulse signal EDGE_CLK; and An automatic calibration unit is used to adjust the second control signal CODE in a successive approximation manner according to the pulse signal EDGE_CLK and the internal feedback clock signal RCLK_INT, so as to adjust the delay of the digitally controllable delay line DCDL, thereby calibrating the duty cycle of the recovery clock RCLK to 50%.

2. The MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function according to claim 1, characterized in that, The clock generation unit includes: The trigger receives the pulse signal EDGE_CLK at its clock input and outputs the internal feedback clock signal RCLK_INT at its output. The AND gate takes the output signal "done" of the automatic calibration unit as its first input, the internal feedback clock signal "RCLK_INT" as its second input, and outputs the recovery clock "RCLK".

3. The MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function according to claim 1 or 2, characterized in that, The automatic calibration unit includes: A frequency counter is used to compare the frequency or duty cycle of the pulse signal EDGE_CLK with that of the internal feedback clock signal RCLK_INT. The digital logic control module is used to generate the second control signal CODE based on the comparison result of the frequency meter using a successive approximation algorithm, so as to control the delay step of the digitally controllable delay line DCDL.

4. The MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function according to claim 1, characterized in that, The clock data recovery circuit also includes a data sampling unit, which uses the recovery clock RCLK to sample the three delayed signals AB_DLY, BC_DLY, and CA_DLY to obtain the linear signal D_PRE<2:0>.

5. The MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function according to claim 1, characterized in that, The analog front-end receiving circuit also integrates a continuous-time linear equalizer to compensate for channel loss.

6. The MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function according to claim 3, characterized in that, The first control signal PG_CODE is an M+1 bit digital signal PG_CODE <m:0>The second control signal CODE is an N+1 bit control signal code. <n:0> 。< / n:0> 7. The MIPI C-PHY high-speed receiver circuit with integrated automatic calibration function according to claim 4, characterized in that, The decoder and serial-to-parallel conversion circuit include: The decoder circuit is used to convert the input linear signal D_PRE<2:0> into the signal D_POST<2:0> corresponding to the Symbol state; A serial-to-parallel conversion circuit is used to convert a single Symbol signal into low-rate L+1 bit Symbol data DATA_0. <l:0>、DATA_1 <l:0>and DATA_2 <l:0> The data is then sent to the digital logic unit for final data processing.< / l:0>

Images