A voltage adaptation circuit, method and device

Abstract

This application discloses a voltage adaptation circuit, method, and apparatus in the field of computer technology. The voltage adaptation circuit provided by this application can adaptively adjust the operating voltage of the second interface of the PHY chip connected to the first interface based on the operating voltage of the first interface of the MAC controller, thereby enabling the PHY chip to automatically adapt to the operating voltage of the MAC controller. Regardless of how the operating voltage of the first interface of the MAC controller changes, the circuit provided by this solution can ensure that the operating voltage of the second interface of the PHY chip connected to the first interface is the same. Therefore, the voltage adaptation circuit provided by this application has good versatility and can reduce production and maintenance costs. Correspondingly, the voltage adaptation method and apparatus provided by this application also have the above-mentioned technical effects.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a voltage adaptation circuit, method, and device. Background Technology

[0002] Currently, different MAC (Media Access Control) controllers operate at different voltages, requiring the design of corresponding hardware boards to adapt the PHY (Physical) chip connected to the MAC controller to its operating voltage. This increases production and maintenance costs.

[0003] Therefore, how to make the PHY chip compatible with the operating voltage of different MAC controllers while reducing costs is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a voltage adaptation circuit, method, and apparatus to enable the PHY chip to adapt to the operating voltage of different MAC controllers while reducing costs. The specific solution is as follows:

[0005] In a first aspect, this application provides a voltage adapter circuit, including: a BMC, a PHY chip, and an adapter module;

[0006] The first interface of the MAC controller in the BMC is connected to the second interface of the PHY chip.

[0007] The PHY chip is connected to the adapter module through its own LDO0 and LDO1 pins;

[0008] The BMC connects to the adapter module via its own GPIO interface (General Purpose Input / Output).

[0009] The BMC is used to: after determining the operating voltage of the first interface, output an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface;

[0010] The adapter module is used to: control the level signals of the LDO0 pin and the LDO1 pin based on the electrical signal;

[0011] The PHY chip is used to: make the operating voltage of the second interface the same as the operating voltage of the first interface based on the level signals of the LDO0 pin and the LDO1 pin, and a preset configuration table.

[0012] Optionally, the BMC integrates multiple MAC controllers, and the first interface of different MAC controllers has a different operating voltage.

[0013] Optionally, the BMC connects to the PHY chip via its own MDIO (Management Data Input / Output) interface, and the BMC is also used to: perform configuration management of the PHY chip through the MDIO interface.

[0014] Optionally, the PHY chip is also connected to the server's network port and / or network card.

[0015] Optionally, the adapter module is also connected to a first indicator light and a second indicator light;

[0016] The first indicator light is turned on or off based on the level signal of the LDO0 pin. When it is on, it is used to indicate that the bandwidth of the server is gigabit.

[0017] The second indicator light is turned on or off based on the level signal of the LDO1 pin. When it is on, it is used to indicate that the bandwidth of the server is not gigabit.

[0018] Optionally, the first interface and the second interface have the same interface type, which is: RGMII (Reduced Gigabit Media Independent Interface), RMII (Reduced Media Independent Interface), or NCSI (Network Controller Sideband Interference).

[0019] Optionally, the BMC is specifically used to: when the operating voltage of the first interface is determined to be a first voltage value, output a low level to the adapter module through its own GPIO interface; the adapter module is specifically used to: control the LDO0 pin to a high level and control the LDO1 pin to a low level based on the low level; the PHY chip is specifically used to: look up the first voltage value in the preset configuration table based on the high level of the LDO0 pin and the low level of the LDO1 pin, and adjust the operating voltage of the second interface to the first voltage value.

[0020] Optionally, the BMC is specifically used to: when the operating voltage of the first interface is determined to be the second voltage value, output a high level to the adapter module through its own GPIO interface; the adapter module is specifically used to: control the LDO0 pin to be low level and control the LDO1 pin to be low level based on the high level; the PHY chip is specifically used to: look up the second voltage value in the preset configuration table based on the low level of the LDO0 pin and the low level of the LDO1 pin, and adjust the operating voltage of the second interface to the second voltage value.

[0021] Secondly, this application provides a voltage adaptation method, which is applied to the voltage adaptation circuit described in any of the above claims, wherein the voltage adaptation circuit includes a BMC, a PHY chip, and an adaptation module.

[0022] The method includes: after determining the operating voltage of the first interface of its own MAC controller, the BMC outputs an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface, so that the adapter module controls the level signals of the LDO0 and LDO1 pins of the PHY chip based on the electrical signal; the PHY chip, based on the level signals of the LDO0 and LDO1 pins and a preset configuration table, makes the operating voltage of its own second interface connected to the first interface the same as the operating voltage of the first interface.

[0023] Optionally, when the operating voltage of the first interface is a first voltage value, the BMC outputs a low level to the adapter module through its own GPIO interface, so that the adapter module controls the LDO0 pin to be high and the LDO1 pin to be low based on the low level; the PHY chip looks up the first voltage value in the preset configuration table based on the high level of the LDO0 pin and the low level of the LDO1 pin, and adjusts the operating voltage of the second interface to the first voltage value;

[0024] When the operating voltage of the first interface is the second voltage value, the BMC outputs a high level to the adapter module through its own GPIO interface, so that the adapter module controls the LDO0 pin to be low and the LDO1 pin to be low based on the high level; the PHY chip looks up the second voltage value in the preset configuration table based on the low level of the LDO0 pin and the low level of the LDO1 pin, and adjusts the operating voltage of the second interface to the second voltage value.

[0025] Thirdly, this application provides an electronic device, including: the voltage adaptation circuit described in any of the preceding claims.

[0026] Optionally, the electronic device is a server.

[0027] As can be seen from the above scheme, this application provides a voltage adaptation circuit, including: a BMC, a PHY chip, and an adaptation module; wherein, the first interface of the MAC controller in the BMC is connected to the second interface of the PHY chip; the PHY chip is connected to the adaptation module through its own LDO0 and LDO1 pins; the BMC is connected to the adaptation module through its own GPIO interface; wherein, the BMC is used to: after determining the operating voltage of the first interface, output an electrical signal corresponding to the operating voltage to the adaptation module through its own GPIO interface; the adaptation module is used to: control the level signals of the LDO0 and LDO1 pins based on the electrical signal; the PHY chip is used to: make the operating voltage of the second interface the same as the operating voltage of the first interface based on the level signals of the LDO0 and LDO1 pins and a preset configuration table.

[0028] As can be seen, the voltage adaptation circuit provided in this application includes a BMC, a PHY chip, and an adaptation module. After determining the operating voltage of the first interface of its MAC controller, the BMC outputs an electrical signal corresponding to the current operating voltage to the adaptation module through its own GPIO interface. This allows the adaptation module to control the level signals of the LDO0 and LDO1 pins of the PHY chip based on the current electrical signal. Then, the PHY chip, based on the level signals of its own LDO0 and LDO1 pins and a preset configuration table, can determine the operating voltage of the second interface connected to the first interface, thus making the operating voltages of the first and second interfaces the same. Therefore, this solution can adaptively adjust the operating voltage of the second interface connected to the first interface of the PHY chip based on the operating voltage of the first interface of the MAC controller, thereby automatically adapting the PHY chip to the operating voltage of the MAC controller. Regardless of how the operating voltage of the first interface of the MAC controller changes, the circuit provided in this solution can ensure that the operating voltage of the second interface connected to the first interface of the PHY chip is the same, eliminating the need to design different circuit structures for different MAC controllers. Therefore, the voltage adaptation circuit provided in this application has good versatility, eliminating the need to manufacture multiple hardware boards and reducing production and maintenance costs.

[0029] Correspondingly, the voltage adaptation method and device provided in this application also have the above-mentioned technical effects. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a voltage adapter circuit disclosed in this application;

[0032] Figure 2 This is a schematic diagram of another voltage adapter circuit disclosed in this application;

[0033] Figure 3 This is a flowchart of a voltage adaptation method disclosed in this application. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0035] Currently, different MAC controllers operate at different voltages, requiring the design of corresponding hardware boards to adapt the PHY chip connected to the MAC controller to its operating voltage. This increases production and maintenance costs. Therefore, this application provides a voltage adaptation circuit. Regardless of the operating voltage of the first interface of the MAC controller, this circuit ensures that the operating voltage of the second interface of the PHY chip connected to the first interface is the same. Thus, it reduces costs while enabling the PHY chip to adapt to the operating voltages of different MAC controllers.

[0036] See Figure 1 As shown in the figure, this application discloses a voltage adapter circuit, including: BMC, PHY chip and adapter module.

[0037] Specifically, the first interface of the MAC controller in the BMC is connected to the second interface of the PHY chip; the PHY chip is connected to the adapter module through its own LDO0 and LDO1 pins; and the BMC is connected to the adapter module through its own GPIO interface.

[0038] The BMC is used to: after determining the operating voltage of the first interface of the MAC controller in itself, output an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface.

[0039] The adapter module is used to control the level signals of the LDO0 pin and LDO1 pin of the PHY chip based on electrical signals.

[0040] The PHY chip is used to: make the operating voltage of the second interface the same as that of the first interface based on the level signal of the LDO0 pin, the level signal of the LDO1 pin, and a preset configuration table.

[0041] As can be seen in this embodiment, after determining the operating voltage of the first interface of a certain MAC controller in itself, the BMC can output an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface, so that the adapter module controls the level signals of the LDO0 and LDO1 pins of the PHY chip based on the current electrical signal; then the PHY chip can determine the operating voltage of the second interface connected to the first interface based on the level signals of the LDO0 and LDO1 pins and the preset configuration table, so that the operating voltages of the first interface and the second interface are the same.

[0042] In one specific implementation, the BMC integrates multiple MAC controllers, each with a different operating voltage for its first interface. Some MAC controllers operate at 1.8V for their first interface, while others operate at 3.3V. The first interface of any MAC controller can be an RGMII, RMII, or NCSI interface.

[0043] In one specific implementation, the BMC connects to the PHY chip via its own MDIO interface. The BMC is also used for configuring and managing the PHY chip through the MDIO interface. MDIO stands for Management Data Input / Output. Configuration management of the PHY chip includes managing the PHY address, speed, and network LED lighting mode.

[0044] In one specific implementation, the PHY chip is also connected to the server's network port and / or network interface card (NIC). The server's network port is, for example, an RJ45 connector. The server's NIC can be of any type.

[0045] In one specific implementation, the adapter module is also connected to a first indicator light and a second indicator light. The first indicator light illuminates or extinguishes based on the level signal of the LDO0 pin, indicating that the server's bandwidth is gigabit when illuminated. The second indicator light illuminates or extinguishes based on the level signal of the LDO1 pin, indicating that the server's bandwidth is non-gigabit when illuminated. That is, when the first indicator light is illuminated, it indicates that the server is using gigabit bandwidth for service operation. When the second indicator light is illuminated, it indicates that the server is using non-gigabit bandwidth for service operation. Non-gigabit bandwidth includes 10M, 100M, etc. It should be noted that the first and second indicator lights are different colors to facilitate differentiation of the bandwidth type used by the server. Generally, gigabit bandwidth is indicated by a green LED, and non-gigabit bandwidth by a yellow LED; therefore, the first indicator light illuminates green when illuminated, and the second indicator light illuminates yellow when illuminated.

[0046] In one specific implementation, the first interface and the second interface have the same interface type: RGMII, RMII, or NCSI. That is, when the first interface is an RGMII interface, the second interface is also an RGMII interface. When the first interface is an RMII interface, the second interface is also an RMII interface. When the first interface is an NCSI interface, the second interface is also an NCSI interface.

[0047] In one specific implementation, the process of adapting the PHY chip to the MAC controller's operating voltage can be described as follows. Specifically, the BMC is used to: when it determines that the operating voltage of the first interface of any MAC controller is a first voltage value (e.g., 1.8V), output a low level to the adapter module through its own GPIO interface; the adapter module is used to: control its LDO0 pin to a high level and its LDO1 pin to a low level based on the low level; the PHY chip is used to: look up the first voltage value in a preset configuration table based on the high level of the LDO0 pin and the low level of the LDO1 pin, and adjust the operating voltage of the second interface to the first voltage value. In this example, when the LDO0 pin is high and the LDO1 pin is low, it indicates that the MAC controller is operating at 1.8V.

[0048] In one specific implementation, the process of adapting the PHY chip to the MAC controller's operating voltage can be described as follows. Specifically, the BMC is used to: when it determines that the operating voltage of the first interface of any MAC controller is a second voltage value (e.g., 3.3V), output a high level to the adapter module through its own GPIO interface; the adapter module is used to: control the LDO0 pin to a low level and the LDO1 pin to a low level based on the high level; the PHY chip is used to: look up the second voltage value in a preset configuration table based on the low levels of the LDO0 and LDO1 pins, and adjust the operating voltage of the second interface to the second voltage value. In this example, when both the LDO0 and LDO1 pins are low, it indicates that the MAC controller is operating at 3.3V.

[0049] The default configuration table records the correspondence between the voltage levels of LDO0 and LDO1 and the operating voltage of the MAC controller. In one example, the default configuration table is shown in Table 1.

[0050] Table 1

[0051] LDO[0:1] Voltage of the first interface 00 3.3V 01 1.8V

[0052] As shown in Table 1, when both LDO0 and LDO1 are at a low level (0), the voltage of the first interface of the MAC controller is 3.3V. When LDO0 is at a low level (0) and LDO1 is at a high level (1), the voltage of the first interface of the MAC controller is 1.8V. Of course, the correspondence between the levels of LDO0 and LDO1 and the operating voltage of the MAC controller can be adjusted according to the actual situation.

[0053] As can be seen, this embodiment can adaptively adjust the operating voltage of the second interface in the PHY chip connected to the first interface based on the operating voltage of the first interface of the MAC controller, thereby enabling the PHY chip to automatically adapt to the operating voltage of the MAC controller. Regardless of how the operating voltage of the first interface of the MAC controller changes, the circuit provided by this solution can ensure that the operating voltage of the second interface in the PHY chip connected to the first interface is the same. Therefore, the voltage adaptation circuit provided in this application has good versatility and can reduce production and maintenance costs.

[0054] As described in the above embodiments, the MAC controller has two voltage options: 3.3V and 1.8V. This is to allow the BMC to support different types of PHY chips. If a 3.3V MAC controller is selected, the PHY voltage must also be set to 3.3V. If a 1.8V MAC controller is selected, the PHY voltage must also be set to 1.8V. The PHY chip controls the level of its RGMII interface through two strap pins, LDO0 and LDO1. LDO0 and LDO1 also control the on / off state of the Ethernet LEDs.

[0055] This embodiment uses the same adapter module to enable the PHY chip to adapt to both 1.8V and 3.3V voltages. For example... Figure 2 As shown, the four 1:2 MUX chips U1, U2, U3, and U4, along with other components, constitute the adapter module. Of course, the circuit configuration of the adapter module can also be designed based on logic circuits, etc.

[0056] The LDO0 / LDO1 pins of the PHY chip and the LED1 / LED2 pins, which control the network LEDs, are multiplexed pins. The LDO0 / LDO1 pins are strap pins, sampled when the PHY reset signal is high. If the LED pin is pulled up, the LED is active Low, meaning the PHY's internal logic controls this pin to light up the LED, and the actual voltage state of the LED pin is low. If the LED pin is pulled down, the LED is active High, meaning the PHY's internal logic controls this pin to light up the LED, and the actual voltage state of the LED pin is high. Based on this principle, a design can be performed... Figure 2 The circuit structure shown is shown.

[0057] exist Figure 2 In this configuration, the SEL signals of the four selectors are controlled by the GPIO interface of the BMC. When SEL is 0, the B0 of each selector is turned on, and the BMC controls the GPIO to output 0, making SEL 0. When SEL is 1, the B1 of each selector is turned on, and the BMC controls the GPIO to output 1, making SEL 1.

[0058] When the BMC controls the GPIO output to 0, the B0 pins of U1, U2, U3, and U4 are turned on, causing LDO1 to be pulled high by R1 and LDO0 to be pulled low by R6. According to Table 1, the PHY's RGMII interface voltage is configured to 1.8V. Since LDO1 is pulled up, LED2 is active low. A MOSFET is added between the B0 channels of U1 and U2 to act as an inverter. Since LDO0 is pulled down, LED1 is active high. LED1 pin indicates the link and active states of the 1000M network, and the corresponding LED color is green. LED2 pin indicates the link and active states of the 10M / 100M network, and the corresponding LED color is yellow. When the network is 10M / 100M, LED2 pin outputs 0, and becomes 1 after the MOSFET is inverted; LED1 pin outputs 0, and remains 0 after two MOSFET stages. Finally, the yellow LED lights up. When the network is 1000M, LED2 pin outputs 1, and becomes 0 after the MOSFET is inverted; LED1 pin outputs 1, and remains 1 after two MOSFET stages. Finally, the green light turned on.

[0059] When the BMC controls the GPIO output to 1, pin B1 of U1, U2, U3, and U4 is turned on, causing LDO1 to be pulled low by R3 and LDO0 to be pulled low by R6. According to Table 1, the PHY's RGMII level is configured to 3.3V. Since both LDO0 and LDO1 are pulled down, LED1 and LED2 are both active high. Specifically, when the network is 10M / 100M, LED2 pin outputs 1; LED1 pin outputs 0, and the yellow light illuminates. When the network is 1000M, LED1 pin outputs 1; LED2 pin outputs 0, and the green light illuminates.

[0060] like Figure 2 As shown, D1 and D2 are two LEDs connected end-to-end. D1 is yellow, used to indicate the link and active status of a 10M / 100M network. D2 is green, used to indicate the link and active status of a 1000M network. D1 and D2 work together through the PHY chip and adapter module to achieve the lighting behavior at different network speeds.

[0061] As can be seen, this embodiment utilizes both 1.8V and 3.3V voltage standards of the PHY chip. By setting up an adapter module and selecting the channel through the BMC GPIO interface, the PHY chip can adapt to both 1.8V and 3.3V voltage modes, and the network LED behavior is consistent in both modes. This embodiment automatically adapts the voltage through the BMC GPIO interface, avoiding the lengthy design process and increased costs associated with creating two separate hardware boards compared to traditional solutions.

[0062] The following describes a voltage adaptation method provided by an embodiment of this application. The voltage adaptation method described below and the voltage adaptation circuit described above can be referred to each other.

[0063] See Figure 3 As shown in the figure, this application discloses a voltage adaptation method, which is applied to the voltage adaptation circuit described in any of the above embodiments. The voltage adaptation circuit includes a BMC, a PHY chip, and an adaptation module.

[0064] The methods disclosed in the embodiments of this application include:

[0065] After determining the operating voltage of the first interface of the MAC controller in its own system, S301 and BMC output an electrical signal corresponding to the operating voltage to the adapter module through their own GPIO interface.

[0066] S302, the adapter module controls the level signals of the LDO0 and LDO1 pins of the PHY chip based on electrical signals.

[0067] The S303 PHY chip uses the level signals of the LDO0 and LDO1 pins and a preset configuration table to ensure that the operating voltage of the second interface connected to the first interface is the same as the operating voltage of the first interface.

[0068] The preset configuration table records the correspondence between the voltage levels of LDO0 and LDO1 and the operating voltage of the MAC controller. In one example, the preset configuration table is shown in Table 1. As shown in Table 1, when both LDO0 and LDO1 are low (0), the voltage of the first interface of the MAC controller is 3.3V; when LDO0 is low (0) and LDO1 is high (1), the voltage of the first interface of the MAC controller is 1.8V. Of course, the correspondence between the voltage levels of LDO0 and LDO1 and the operating voltage of the MAC controller can be adjusted according to actual conditions.

[0069] In this embodiment, the first interface of the MAC controller in the BMC is connected to the second interface of the PHY chip; the PHY chip is connected to the adapter module through its own LDO0 and LDO1 pins; and the BMC is connected to the adapter module through its own GPIO interface.

[0070] In this embodiment, after determining the operating voltage of the first interface of a certain MAC controller within itself, the BMC can output an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface. This allows the adapter module to control the level signals of the LDO0 and LDO1 pins of the PHY chip based on the current electrical signal. Then, the PHY chip can determine the operating voltage of the second interface connected to the first interface based on the level signals of the LDO0 and LDO1 pins and a preset configuration table, thereby making the operating voltages of the first and second interfaces the same.

[0071] In one specific implementation, the BMC integrates multiple MAC controllers, each with a different operating voltage for its first interface. Some MAC controllers operate at 1.8V for their first interface, while others operate at 3.3V. The first interface of any MAC controller can be an RGMII, RMII, or NCSI interface.

[0072] In one specific implementation, the BMC connects to the PHY chip through its own MDIO interface, and the BMC is also used to: configure and manage the PHY chip through the MDIO interface.

[0073] In one specific implementation, the PHY chip is also connected to the server's network port and / or network card.

[0074] In one specific implementation, the adapter module is also connected to a first indicator light and a second indicator light. The first indicator light illuminates or extinguishes based on the level signal of the LDO0 pin, indicating that the server's bandwidth is gigabit when illuminated. The second indicator light illuminates or extinguishes based on the level signal of the LDO1 pin, indicating that the server's bandwidth is non-gigabit when illuminated. That is, when the first indicator light is illuminated, it indicates that the server is using gigabit bandwidth for service operation. When the second indicator light is illuminated, it indicates that the server is using non-gigabit bandwidth for service operation. Non-gigabit bandwidth includes 10M, 100M, etc. It should be noted that the first and second indicator lights are different colors to facilitate differentiation of the bandwidth type used by the server. Generally, gigabit bandwidth is indicated by a green LED, and non-gigabit bandwidth by a yellow LED; therefore, the first indicator light illuminates green when illuminated, and the second indicator light illuminates yellow when illuminated.

[0075] In one specific implementation, the first interface and the second interface have the same interface type: RGMII, RMII, or NCSI. That is, when the first interface is an RGMII interface, the second interface is also an RGMII interface. When the first interface is an RMII interface, the second interface is also an RMII interface. When the first interface is an NCSI interface, the second interface is also an NCSI interface.

[0076] In one specific implementation, when the operating voltage of the first interface is the first voltage value, the BMC outputs a low level to the adapter module through its own GPIO interface, so that the adapter module controls the LDO0 pin to be high and the LDO1 pin to be low based on the low level; the PHY chip looks up the first voltage value in the preset configuration table based on the high level of the LDO0 pin and the low level of the LDO1 pin, and adjusts the operating voltage of the second interface to the first voltage value.

[0077] In one specific implementation, when the operating voltage of the first interface is the second voltage value, the BMC outputs a high level to the adapter module through its own GPIO interface, so that the adapter module controls the LDO0 pin to be low and the LDO1 pin to be low based on the high level; the PHY chip looks up the second voltage value in the preset configuration table based on the low level of the LDO0 pin and the low level of the LDO1 pin, and adjusts the operating voltage of the second interface to the second voltage value.

[0078] As can be seen, this embodiment provides a voltage adaptation method that can adaptively adjust the operating voltage of the second interface of the PHY chip connected to the first interface based on the operating voltage of the first interface of the MAC controller, thereby enabling the PHY chip to automatically adapt to the operating voltage of the MAC controller. Regardless of how the operating voltage of the first interface of the MAC controller changes, the circuit provided by this solution can ensure that the operating voltage of the second interface of the PHY chip connected to the first interface is the same. Therefore, the voltage adaptation circuit provided in this application has good versatility and can reduce production and maintenance costs.

[0079] The following describes an electronic device provided by an embodiment of this application. The electronic device described below and the voltage adaptation method described above can be referred to each other.

[0080] This application discloses an electronic device, including: the voltage adapter circuit described in any of the above embodiments.

[0081] In one specific implementation, the electronic device is a server.

[0082] In one specific implementation, the BMC integrates multiple MAC controllers, each with a different operating voltage for its first interface. Some MAC controllers operate at 1.8V for their first interface, while others operate at 3.3V. The first interface of any MAC controller can be an RGMII, RMII, or NCSI interface.

[0083] In one specific implementation, the BMC connects to the PHY chip through its own MDIO interface, and the BMC is also used to: configure and manage the PHY chip through the MDIO interface.

[0084] In one specific implementation, the PHY chip is also connected to the server's network port and / or network card.

[0085] In one specific implementation, the adapter module is also connected to a first indicator light and a second indicator light. The first indicator light illuminates or extinguishes based on the level signal of the LDO0 pin, indicating that the server's bandwidth is gigabit when illuminated. The second indicator light illuminates or extinguishes based on the level signal of the LDO1 pin, indicating that the server's bandwidth is non-gigabit when illuminated. That is, when the first indicator light is illuminated, it indicates that the server is using gigabit bandwidth for service operation. When the second indicator light is illuminated, it indicates that the server is using non-gigabit bandwidth for service operation. Non-gigabit bandwidth includes 10M, 100M, etc. It should be noted that the first and second indicator lights are different colors to facilitate differentiation of the bandwidth type used by the server. Generally, gigabit bandwidth is indicated by a green LED, and non-gigabit bandwidth by a yellow LED; therefore, the first indicator light illuminates green when illuminated, and the second indicator light illuminates yellow when illuminated.

[0086] In one specific implementation, the first interface and the second interface have the same interface type: RGMII, RMII, or NCSI. That is, when the first interface is an RGMII interface, the second interface is also an RGMII interface. When the first interface is an RMII interface, the second interface is also an RMII interface. When the first interface is an NCSI interface, the second interface is also an NCSI interface.

[0087] In one specific implementation, the BMC is specifically used to: when the operating voltage of the first interface is determined to be a first voltage value, output a low level to the adapter module through its own GPIO interface; the adapter module is specifically used to: control the LDO0 pin to be high level and control the LDO1 pin to be low level based on the low level; the PHY chip is specifically used to: look up the first voltage value in the preset configuration table based on the high level of the LDO0 pin and the low level of the LDO1 pin, and adjust the operating voltage of the second interface to the first voltage value.

[0088] In one specific implementation, the BMC is specifically used to: when the operating voltage of the first interface is determined to be the second voltage value, output a high level to the adapter module through its own GPIO interface; the adapter module is specifically used to: control the LDO0 pin to be low level and control the LDO1 pin to be low level based on the high level; the PHY chip is specifically used to: look up the second voltage value in the preset configuration table based on the low level of the LDO0 pin and the low level of the LDO1 pin, and adjust the operating voltage of the second interface to the second voltage value.

[0089] The preset configuration table records the correspondence between the voltage levels of LDO0 and LDO1 and the operating voltage of the MAC controller. In one example, the preset configuration table is shown in Table 1. As shown in Table 1, when both LDO0 and LDO1 are low (0), the voltage of the first interface of the MAC controller is 3.3V; when LDO0 is low (0) and LDO1 is high (1), the voltage of the first interface of the MAC controller is 1.8V. Of course, the correspondence between the voltage levels of LDO0 and LDO1 and the operating voltage of the MAC controller can be adjusted according to actual conditions.

[0090] As can be seen in this embodiment, after determining the operating voltage of the first interface of a certain MAC controller in itself, the BMC can output an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface, so that the adapter module controls the level signals of the LDO0 and LDO1 pins of the PHY chip based on the current electrical signal; then the PHY chip can determine the operating voltage of the second interface connected to the first interface based on the level signals of the LDO0 and LDO1 pins and the preset configuration table, so that the operating voltages of the first interface and the second interface are the same.

[0091] When the electronic device is a server, the server may specifically include: at least one processor, at least one memory, a power supply, a communication interface, an input / output interface, and a communication bus.

[0092] In this embodiment, the power supply is used to provide operating voltage for each hardware device on the server; the communication interface can create a data transmission channel between the server and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0093] In addition, the memory, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system, computer programs and data, etc., and the storage method can be temporary storage or permanent storage.

[0094] The operating system is used to manage and control the various hardware devices and computer programs on the server, enabling the processor to perform operations and processes on the data in the memory. It can be Windows Server, Netware, Unix, Linux, etc. In addition to computer programs capable of performing the voltage adaptation method disclosed in any of the foregoing embodiments, the computer programs may further include computer programs capable of performing other specific tasks. The data may include, in addition to data such as virtual machine data, data such as virtual machine developer information.

[0095] The processor in the server may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor can be implemented using at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor may also include a main processor and coprocessors. The main processor, also known as the CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which handles computational operations related to machine learning.

[0096] The memory in the server may include one or more computer-readable storage media, which may be non-transitory. The memory may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory is used to store at least the following computer program, which, after being loaded and executed by the processor, is capable of implementing the relevant steps in the voltage adaptation method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory may also include operating systems and data, and the storage method may be temporary or permanent storage. The operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, application update information.

[0097] As can be seen, this embodiment can adaptively adjust the operating voltage of the second interface in the PHY chip connected to the first interface based on the operating voltage of the first interface of the MAC controller, thereby enabling the PHY chip to automatically adapt to the operating voltage of the MAC controller. Regardless of how the operating voltage of the first interface of the MAC controller changes, the circuit provided by this solution can ensure that the operating voltage of the second interface in the PHY chip connected to the first interface is the same. Therefore, the voltage adaptation circuit provided in this application has good versatility and can reduce production and maintenance costs.

[0098] The terms “first,” “second,” “third,” “fourth,” etc., used in this application (if applicable) are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, or apparatus.

[0099] It should be noted that the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of those features. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0100] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0101] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of readable storage medium known in the art.

[0102] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A voltage adapter circuit, characterized in that, include: BMC, PHY chip and adapter module; The first interface of the MAC controller in the BMC is connected to the second interface of the PHY chip; the BMC integrates multiple MAC controllers, and the first interface of different MAC controllers has a different operating voltage. The PHY chip is connected to the adapter module through its own LDO0 and LDO1 pins; The BMC connects to the adapter module via its own GPIO interface; The BMC is used to: after determining the operating voltage of the first interface, output an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface; The adapter module is used to: control the level signals of the LDO0 pin and the LDO1 pin based on the electrical signal; The PHY chip is used to: make the operating voltage of the second interface the same as the operating voltage of the first interface based on the level signals of the LDO0 pin and the LDO1 pin, and a preset configuration table; Specifically, after determining the operating voltage of the first interface of its MAC controller, the BMC outputs an electrical signal corresponding to the operating voltage to the adapter module through its GPIO interface. This allows the adapter module to control the level signals of the LDO0 and LDO1 pins of the PHY chip based on the electrical signal. The PHY chip, based on the level signals of the LDO0 and LDO1 pins and a preset configuration table, ensures that the operating voltage of its second interface, which is connected to the first interface, is the same as the operating voltage of the first interface. The BMC connects to the PHY chip via its own MDIO interface. The BMC is also used to: perform configuration management of the PHY chip through the MDIO interface; the configuration management includes: management of PHY address, speed, network, and LED lighting mode.

2. The voltage adapter circuit according to claim 1, characterized in that, The PHY chip is also connected to the server's network port and / or network card.

3. The voltage adapter circuit according to claim 2, characterized in that, The adapter module is also connected to a first indicator light and a second indicator light; The first indicator light is turned on or off based on the level signal of the LDO0 pin. When it is on, it is used to indicate that the bandwidth of the server is gigabit. The second indicator light is turned on or off based on the level signal of the LDO1 pin. When it is on, it is used to indicate that the bandwidth of the server is not gigabit.

4. The voltage adapter circuit according to any one of claims 1 to 3, characterized in that, The first interface and the second interface have the same interface type, which is RGMII, RMII or NCSI.

5. A voltage adaptation method, characterized in that, This method is applied to the voltage adapter circuit according to any one of claims 1 to 4, wherein the voltage adapter circuit includes a BMC, a PHY chip, and an adapter module; The method includes: after determining the operating voltage of the first interface of its own MAC controller, the BMC outputs an electrical signal corresponding to the operating voltage to the adapter module through its own GPIO interface, so that the adapter module controls the level signals of the LDO0 and LDO1 pins of the PHY chip based on the electrical signal; the PHY chip, based on the level signals of the LDO0 and LDO1 pins and a preset configuration table, makes the operating voltage of its own second interface connected to the first interface the same as the operating voltage of the first interface.

6. The method according to claim 5, characterized in that, When the operating voltage of the first interface is the first voltage value, the BMC outputs a low level to the adapter module through its own GPIO interface, so that the adapter module controls the LDO0 pin to be high and the LDO1 pin to be low based on the low level; the PHY chip looks up the first voltage value in the preset configuration table based on the high level of the LDO0 pin and the low level of the LDO1 pin, and adjusts the operating voltage of the second interface to the first voltage value; When the operating voltage of the first interface is the second voltage value, the BMC outputs a high level to the adapter module through its own GPIO interface, so that the adapter module controls the LDO0 pin to be low and the LDO1 pin to be low based on the high level; the PHY chip looks up the second voltage value in the preset configuration table based on the low level of the LDO0 pin and the low level of the LDO1 pin, and adjusts the operating voltage of the second interface to the second voltage value.

7. An electronic device, characterized in that, include: The voltage adapter circuit according to any one of claims 1 to 4.

8. The electronic device according to claim 7, characterized in that, The electronic device is a server.

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