Packaging structure and method for realizing vertical stacking and interconnection of chips by electroless plating

Abstract

The application relates to the technical field of semiconductor packaging, in particular to a packaging structure and method for realizing vertical stacking and interconnection of chips through chemical plating. The packaging structure for realizing vertical stacking and interconnection of chips through chemical plating comprises chips, characterized in that: a plurality of chip units are vertically and alignedly stacked on a substrate from bottom to top, and the plurality of chip units are interconnected through chemical plating metal on pads; the chip unit comprises a wafer, a wafer pad and a copper layer; the top of the wafer is connected with the wafer pad; the surfaces of the wafer and the wafer pad are coated with a buffer protection layer, and the buffer protection layer is provided with the copper layer; and the two adjacent chip units are bonded through a DAF film. Compared with the prior art, the packaging structure and method for realizing vertical stacking and interconnection of chips through chemical plating realize the connection between the upper and lower chips and the chips, and the chips are alignedly interconnected and stacked.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, specifically a packaging structure and method for achieving vertical stacking and interconnection of chips through chemical plating. Background Technology

[0002] With the ever-increasing demands for data storage capacity and access speed from consumer electronics, data centers, and mobile devices, achieving higher storage density flash memory devices within limited physical space has become a core requirement for industry development. Current methods in the packaging field to increase storage density involve integrating multiple chips vertically, thereby significantly improving storage capacity and integration without substantially increasing the planar area of ​​the package.

[0003] In stacked interconnect solutions, wire bonding has long been one of the mainstream technologies for realizing multi-layer flash memory chip stacking due to its advantages such as mature technology, low cost, wide process adaptability, and compatibility with existing packaging infrastructure. The basic process of this technology is as follows: First, multiple qualified flash memory chips are stacked layer by layer using an adhesive and a lead frame or substrate as a carrier; then, using a high-precision wire bonding machine, through the combined action of heat, pressure, and ultrasonic energy, one end of a fine metal wire (usually gold or copper wire) is bonded to the chip's pad, and the other end is bonded to the corresponding pin on the substrate or lead frame, thus forming an electrical interconnect path from the chip to the external world, such as... Figure 1 As shown.

[0004] Although wire bonding technology is widely used, its inherent technical limitations are becoming increasingly apparent when it comes to flash memory stacking applications with higher layer counts, smaller pitches, and higher speeds. These limitations are mainly reflected in the following aspects:

[0005] 1. There are limitations on the number of stackable layers and the "staircase" structure. To expose all chip pads, stacked chips typically need to be designed in a "pyramid" or "staircase" shape, meaning the upper chip must be smaller than the lower chip to expose the pad area of ​​the lower chip. This structure not only limits the maximum number of stackable chip layers but also increases the overall package height and complexity.

[0006] 2. Bottlenecks exist in interconnect length and electrical performance. The metal leads formed by wire bonding inherently possess high inductance and resistance. As the number of stacked layers increases, the lead length leading to the top-layer chip increases significantly, leading to signal transmission delay, increased resistance loss, and stronger parasitic inductance and capacitance effects. This severely restricts the operating performance of flash memory devices at high frequencies and increases the design difficulty of signal integrity.

[0007] 3. Challenges in I / O density and pad spacing. As chip functions become more complex, the number of I / Os continues to increase, while the miniaturization of chip size requires a continuous reduction in pad spacing. Wire bonding technology has a physical limit; when the pad spacing is too small, short circuits or interference between leads are very likely to occur, limiting the realization of high-density interconnects.

[0008] Therefore, there is an urgent need in the field for a new stacked interconnect solution that can overcome or mitigate the defects of the above-mentioned wire bonding technology, in order to further improve the electrical performance, reliability and production efficiency of flash memory devices while maintaining high integration. Summary of the Invention

[0009] To overcome the shortcomings of the prior art, this invention provides a packaging structure and method for vertically stacking and interconnecting chips through chemical plating, thereby achieving connection between upper and lower chips and between chips, and aligning and stacking chips together.

[0010] To achieve the above objectives, a packaging structure is designed to achieve vertical stacking and interconnection of chips through chemical plating. The structure includes chips, characterized in that: a plurality of chip units are stacked vertically and aligned sequentially from bottom to top on a substrate; the plurality of chip units are interconnected to pads via chemical plating of metal; each chip unit includes a wafer, wafer pads, and a copper layer; the top of the wafer is connected to the wafer pads; a buffer protective layer is coated on the surface of the wafer and the wafer pads; a copper layer is provided on the buffer protective layer; adjacent chip units are bonded together via a DAF thin film.

[0011] The substrate has several substrate pads and conductive metal material inside. Several chip units and chemically plated metal on the substrate are encapsulated by a molding compound. Balls are planted at the bottom of the substrate.

[0012] The outer sides of the aforementioned chip units are encapsulated with filler glue.

[0013] The buffer protective layer is made of polyimide.

[0014] A packaging method for achieving vertical stacking and interconnection of chips through chemical plating, characterized in that the packaging method includes Method 1 and Method 2.

[0015] The specific process of method one is as follows:

[0016] S1-1, Wafer arrival, cleaning and other preparation work: drawing pads on the wafer surface;

[0017] S1-2, Draw grooves in the scribe line near the wafer pads;

[0018] S1-3, Polyimide is coated on the surface of the wafer where the circuit has been fabricated as a buffer protective layer, and then the pad openings are precisely etched out by standard photolithography process.

[0019] S1-4, Electroplated copper layer: Connecting the solder pads to the dicing groove;

[0020] S1-5, thinning the back side of the wafer; or first thinning to a certain distance from the polyimide layer, and then continuing to thin it until the polyimide layer is exposed by etching or dry plasma etching.

[0021] S1-6, Dicing: Retaining the copper layer in the dicing groove to form a chip unit structure with a copper layer on one side;

[0022] S1-7, Fabricate carrier wafer, place substrate on carrier, substrate pads and conductive metal material inside substrate for connection with wafer pads.

[0023] S1-8, Several chip units are stacked vertically and aligned sequentially on the substrate;

[0024] S1-9, the outer side of several chip units is filled with filler glue;

[0025] S1-10 uses a laser to create holes in the dicing groove for subsequent metal interconnect formation; the holes can be small or large.

[0026] S1-11, through chemical plating, interconnections between chip units and between chip units and the bottom substrate are established in the through-hole;

[0027] S1-12, plastic sealed;

[0028] S1-13, Remove the carrier plate from the substrate bottom plate;

[0029] S1-14, after ball placement, is cut into individual chip units to complete the entire packaging structure.

[0030] The specific process of method two is as follows:

[0031] S2-1, Wafer arrival, cleaning and other preparation work: drawing pads on the wafer surface;

[0032] S2-2, Draw grooves in the scribe line near the wafer pads;

[0033] S2-3, Polyimide is coated on the surface of the wafer with the completed circuit fabrication as a buffer protective layer, and then the pad openings are precisely etched out by standard photolithography process.

[0034] S2-4, Electroplated copper layer: Connecting the pads to the dicing groove;

[0035] S2-5, thinning the back side of the wafer; or first thinning to a certain distance from the polyimide layer, and then continuing to thin it until the polyimide layer is exposed by etching or dry plasma etching.

[0036] S2-6, Fabricating a carrier wafer, placing a substrate on the carrier, the substrate contains substrate pads and conductive metal material for connection with the wafer pads;

[0037] S2-7, Several chip units are stacked vertically and aligned sequentially on the substrate;

[0038] S2-8, holes are made at the dicing groove using a laser method for subsequent metal interconnect formation;

[0039] S2-9, through chemical plating, interconnections between chip units and between chip units and the bottom substrate are established within the through-hole;

[0040] S2-10, fill the voids in the chemically plated metal with molding compound or filler adhesive;

[0041] S2-11, Remove the carrier plate from the substrate bottom plate;

[0042] S2-12, after ball placement, is diced and cut into individual chip units to complete the entire packaging structure.

[0043] In steps S1-2 and S2-2, a groove is formed in the dicing track adjacent to the wafer pad by laser ablation or blade cutting, which is used for subsequent rewiring processes to form a structure in which copper interconnects climb within the groove.

[0044] The specific procedures for steps S1-4 and S2-4 are as follows:

[0045] S41, on a wafer that has already formed a polyimide layer and pad openings, an adhesion layer and a copper seed layer are sequentially deposited by physical vapor deposition.

[0046] S42, Subsequently, a patterned photoresist mask is formed in the area to be electroplated using a photolithography process, exposing the predetermined electroplating path to be connected to the pads and the dicing groove.

[0047] S43, Next, the copper electroplating operation is performed: the wafer is used as the cathode and immersed in an electrolyte containing copper ions. Under the action of an external electric field, copper ions are reduced and deposited on the surface of the copper seed layer. Its growth is strictly limited to the photoresist opening area.

[0048] S44, the electroplated copper layer starts from the pad, extends along the preset path and finally fills the groove in the dicing channel, thereby forming a metal connection structure.

[0049] In steps S1-6, before dicing, a DAF film is attached to the back of the wafer for subsequent chip stacking and bonding.

[0050] In steps S2-7, before stacking, a DAF film is attached to the back of the wafer for subsequent chip stacking and bonding.

[0051] Compared with the prior art, the present invention provides a packaging structure and method for achieving vertical stacking and interconnection of chips through chemical plating, realizing the connection between upper and lower chips and between chips, and aligning and stacking chips. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of a traditional chip packaging structure.

[0053] Figure 2 This is a schematic diagram of the chip packaging structure of Embodiment 1 of the present invention.

[0054] Figure 3 This is a schematic diagram of step one in the chip packaging method of Embodiment 1 of the present invention.

[0055] Figure 4 This is a schematic diagram of step two in the chip packaging method of Embodiment 1 of the present invention.

[0056] Figure 5 This is a schematic diagram of step three in the chip packaging method of Embodiment 1 of the present invention.

[0057] Figure 6 This is a schematic diagram of step four in the chip packaging method of Embodiment 1 of the present invention.

[0058] Figure 7 This is a schematic diagram of step five in the chip packaging method of Embodiment 1 of the present invention.

[0059] Figure 8 This is a schematic diagram of step six in the chip packaging method of Embodiment 1 of the present invention.

[0060] Figure 9 This is a schematic diagram of step seven in the chip packaging method of Embodiment 1 of the present invention.

[0061] Figure 10 This is a schematic diagram of step eight in the chip packaging method of Embodiment 1 of the present invention.

[0062] Figure 11 This is a schematic diagram of step nine in the chip packaging method of Embodiment 1 of the present invention.

[0063] Figure 12 This is a schematic diagram of step ten in the chip packaging method of Embodiment 1 of the present invention.

[0064] Figure 13This is a top view of the small hole and the large hole in step ten of the chip packaging method in Embodiment 1 of the present invention.

[0065] Figure 14 This is a schematic diagram of step eleven in the chip packaging method of Embodiment 1 of the present invention.

[0066] Figure 15 This is a schematic diagram of step 12 in the chip packaging method of Embodiment 1 of the present invention.

[0067] Figure 16 This is a schematic diagram of step thirteen in the chip packaging method of Embodiment 1 of the present invention.

[0068] Figure 17 This is a schematic diagram of step fourteen in the chip packaging method of Embodiment 1 of the present invention.

[0069] Figure 18 This is a schematic diagram of the chip packaging structure of Embodiment 2 of the present invention.

[0070] Figure 19 This is a schematic diagram of step one in the chip packaging method of Embodiment 2 of the present invention.

[0071] Figure 20 This is a schematic diagram of step two in the chip packaging method of Embodiment 2 of the present invention.

[0072] Figure 21 This is a schematic diagram of step three in the chip packaging method of Embodiment 2 of the present invention.

[0073] Figure 22 This is a schematic diagram of step four in the chip packaging method of Embodiment 2 of the present invention.

[0074] Figure 23 This is a schematic diagram of step five in the chip packaging method of Embodiment 2 of the present invention.

[0075] Figure 24 This is a schematic diagram of step six in the chip packaging method of Embodiment 2 of the present invention.

[0076] Figure 25 This is a schematic diagram of step seven in the chip packaging method of Embodiment 2 of the present invention.

[0077] Figure 26 This is a schematic diagram of step eight in the chip packaging method of Embodiment 2 of the present invention.

[0078] Figure 27 This is a schematic diagram of step nine in the chip packaging method of Embodiment 2 of the present invention.

[0079] Figure 28 This is a schematic diagram of step ten in the chip packaging method of Embodiment 2 of the present invention.

[0080] Figure 29This is a schematic diagram of step eleven in the chip packaging method of Embodiment 2 of the present invention.

[0081] Figure 30 This is a schematic diagram of step 12 in the chip packaging method of Embodiment 2 of the present invention.

[0082] Figure 31 The through-hole is a closed structure top view.

[0083] Figure 32 The top view shows a non-closed structure with through holes.

[0084] Figure 33 This is a schematic diagram showing the increase in area at the end of the metal rewiring hole for the case of electroless plating through-holes.

[0085] Figure 34 This is a schematic diagram of a through hole cut into a non-closed ring shape.

[0086] Figure 35 This is a schematic diagram of the stacked structure of the chip-DAF-chip of the present invention.

[0087] See Figure 2 1 is the molding compound, 2 is the electroless metal plating, 3 is the copper layer, 4 is the buffer protective layer, 5 is the solder pad, 6 is the wafer, 7 is the substrate, 8 is the DAF film, 9 is the substrate solder pad, 10 is the conductive metal material, and 11 is the filler adhesive. Detailed Implementation

[0088] The present invention will now be further described with reference to the accompanying drawings.

[0089] like Figure 2 As shown, the packaging structure of Embodiment 1 of the present invention includes a chip. A plurality of chip units are stacked vertically and aligned from bottom to top on a substrate 7. The chip units are interconnected by chemically plated metal 2 onto pads. Each chip unit includes a wafer, wafer pads, and a copper layer. The top of the wafer 6 is connected to pads 5. A buffer protective layer 4 is coated on the surfaces of the wafer 6 and pads 5, and a copper layer 3 is disposed on the buffer protective layer 4. Adjacent chip units are bonded together by a DAF film 8. The outer sides of the chip units are encapsulated with filler adhesive 11.

[0090] The substrate 7 has several substrate pads 9 and metal conductive material 10. Several chip units and chemically plated metal 2 on the substrate 7 are encapsulated by plastic encapsulation material 1. Balls are planted at the bottom of the substrate 7.

[0091] The buffer protective layer 4 is made of polyimide.

[0092] In Example 1, the pads of the stacked chips are connected using a chemical plating method. The chip units are stacked vertically and aligned, a significant difference from traditional wire bonding: the chips are stacked vertically and aligned, without any staggered exposed pads, thus avoiding the limitation on the number of stacked chip layers. Because of the vertical stacking, the stacked area is comparable to the chip area, reducing the planar area and shortening the signal line length.

[0093] A groove structure is created within the dicing channel, and rewiring is fabricated to form a structure with a metal layer on the side, which facilitates subsequent chemical plating to form an interconnect structure.

[0094] This structure can be stacked on wafers, chemically plated, and then diced to separate the wafers.

[0095] The packaging process flow of Example 1 is as follows:

[0096] like Figure 3 As shown, Step 1: Wafers arrive, and preparation work such as cleaning is carried out.

[0097] Two pads are drawn on the wafer surface. This is understandable, as there is a chip array on the wafer surface. There are more than just two pads drawn; it means there is a pad array corresponding to many chips.

[0098] like Figure 4 As shown, step 2: A groove is scribed within the scribe line near the wafer pads. A groove is formed within the scribe line adjacent to the wafer pads using laser ablation or blade cutting. This groove is used in subsequent redistribution processes to create the structure for copper interconnects to climb within the groove, facilitating the connection between the subsequently 3D-printed metal connectors and the chip. A standalone copper redistribution layer is often less than 5µm thick, resulting in a small contact area when connecting to the 3D-printed metal connectors. Forming metal interconnects within the groove effectively increases the contact area between the copper redistribution layer and the printed metal connectors.

[0099] like Figure 5 As shown, step 3: Coat the surface of the wafer with the completed circuit fabrication with polyimide (PI) as a buffer protective layer, and then precisely etch the pad openings using standard photolithography processes (including exposure and development).

[0100] like Figure 6As shown, step 4: Copper electroplating, connecting the pads to the dicing groove. On the wafer with the polyimide layer and pad openings already formed, an adhesion layer (such as titanium / titanium nitride) and a copper seed layer are sequentially deposited using a physical vapor deposition (PVD) process, such as sputtering. Subsequently, a patterned photoresist mask is formed in the area to be electroplated using a photolithography process, exposing the predetermined electroplating path to connect the pads to the dicing groove. Next, the copper electroplating operation is performed: the wafer is immersed as the cathode in an electrolyte containing copper ions. Under the action of an applied electric field, copper ions are reduced and deposited on the surface of the copper seed layer, and its growth is strictly limited to the photoresist opening area. The electroplated copper layer starts from the pads, extends along the predetermined path, and finally fills the grooves in the dicing groove, thereby forming a metal connection structure.

[0101] like Figure 7 As shown, step 5: Thinning the back of the chip can be done by thinning the polyimide layer. Alternatively, it can be thinned to a certain distance from the polyimide layer, such as 10µm, and then further thinned to expose the polyimide layer by etching or dry plasma etching.

[0102] like Figure 8 As shown, step 6: dicing, retaining the copper layer in the dicing groove to form a chip unit structure with a copper layer on one side.

[0103] like Figure 9 As shown, step 7: Fabricate the carrier wafer. A substrate is placed on the carrier. The substrate contains substrate pads and conductive metal material for connection with the wafer pads.

[0104] like Figure 10 As shown, step 8: Stack several chip units vertically and aligned on the substrate in sequence.

[0105] like Figure 11 As shown, step 9: fill the outside of several chip cells with underfill adhesive.

[0106] like Figure 12 As shown, step 10: Using methods such as lasers, holes are drilled in the dicing grooves for subsequent metal interconnect formation.

[0107] like Figure 13 As shown, there are two methods: the left view is a top view of the small hole structure, and the right view is a top view of the large hole structure.

[0108] like Figure 14 As shown, step 11: establish interconnects between chips and between chips and the bottom substrate wafer using chemical plating.

[0109] like Figure 15 As shown, step 12: sealing.

[0110] like Figure 16 As shown, step 13: Remove the carrier plate.

[0111] like Figure 17 As shown, step 14: After the balls are planted, they are cut open to form independent single-cell encapsulation structures, completing the encapsulation process.

[0112] like Figure 18 As shown, the packaging structure of Embodiment 2 of the present invention includes a chip. A plurality of chip units are stacked vertically and aligned from bottom to top on a substrate 7. The plurality of chip units are interconnected with pads by chemically plated metal 2. The chip unit includes a wafer, wafer pads, and a copper layer. The top of the wafer 6 is connected to the pads 5. The surfaces of the wafer 6 and the pads 5 are coated with a buffer protective layer 4. A copper layer 3 is provided on the buffer protective layer 4. Adjacent chip units are bonded together by a DAF film 8.

[0113] The substrate 7 has several substrate pads 9 and metal conductive material 10. Several chip units and chemically plated metal 2 on the substrate 7 are encapsulated by plastic encapsulation material 1. Balls are planted at the bottom of the substrate 7.

[0114] The buffer protective layer 4 is made of polyimide.

[0115] In Example 2, the pads of the stacked chips are connected using chemical plating. The chip units are stacked vertically and aligned, a significant difference from traditional wire bonding: the chips are stacked vertically and aligned, without any staggered exposed pads, thus avoiding the limitation on the number of stacked chip layers. Because of the vertical stacking, the stacked area is comparable to the chip area, reducing the planar area and shortening the signal line length.

[0116] A groove structure is created within the dicing channel, and rewiring is fabricated to form a structure with a metal layer on the side, which facilitates subsequent chemical plating to form an interconnect structure.

[0117] This structure can be stacked on wafers, chemically plated, and then diced to separate the wafers.

[0118] The packaging process flow of Example 2 is as follows:

[0119] like Figure 19 As shown, Step 1: Wafers arrive, and preparation work such as cleaning is carried out.

[0120] Two pads are drawn on the wafer surface. This is understandable, as there is a chip array on the wafer surface. There are more than just two pads drawn; it means there is a pad array corresponding to many chips.

[0121] like Figure 20As shown, step 2: A groove is scribed within the scribe line near the wafer pads. A groove is formed within the scribe line adjacent to the wafer pads using laser ablation or blade cutting. This groove is used in subsequent redistribution processes to create the structure for copper interconnects to climb within the groove, facilitating the connection between the subsequently 3D-printed metal connectors and the chip. A standalone copper redistribution layer is often less than 5µm thick, resulting in a small contact area when connecting to the 3D-printed metal connectors. Forming metal interconnects within the groove effectively increases the contact area between the copper redistribution layer and the printed metal connectors.

[0122] like Figure 21 As shown, step 3: Coat the surface of the wafer with the completed circuit fabrication with polyimide (PI) as a buffer protective layer, and then precisely etch the pad openings using standard photolithography processes (including exposure and development).

[0123] like Figure 22 As shown, step 4: Copper electroplating, connecting the pads to the dicing groove. On the wafer with the polyimide layer and pad openings already formed, an adhesion layer (such as titanium / titanium nitride) and a copper seed layer are sequentially deposited using a physical vapor deposition (PVD) process, such as sputtering. Subsequently, a patterned photoresist mask is formed in the area to be electroplated using a photolithography process, exposing the predetermined electroplating path to connect the pads to the dicing groove. Next, the copper electroplating operation is performed: the wafer is immersed as the cathode in an electrolyte containing copper ions. Under the action of an applied electric field, copper ions are reduced and deposited on the surface of the copper seed layer, and its growth is strictly limited to the photoresist opening area. The electroplated copper layer starts from the pads, extends along the predetermined path, and finally fills the grooves in the dicing groove, thereby forming a metal connection structure.

[0124] like Figure 23 As shown, step 5: Thinning the back of the chip can be done by thinning the polyimide layer. Alternatively, it can be thinned to a certain distance from the polyimide layer, such as 10µm, and then further thinned to expose the polyimide layer by etching or dry plasma etching.

[0125] like Figure 24 As shown, step 6: Fabricate the carrier wafer. A substrate is placed on the carrier. The substrate contains substrate pads and conductive metal material for connection with the wafer pads.

[0126] like Figure 25 As shown, step 7: Stack several chip units vertically and aligned on the substrate in sequence.

[0127] like Figure 26 As shown, step 8: Using methods such as lasers, holes are drilled at the dicing grooves for subsequent metal interconnect formation.

[0128] like Figure 27As shown, step 9: establish interconnections between chips and between chips and the bottom substrate wafer using chemical plating.

[0129] like Figure 28 As shown, step 10: fill the voids in the electroless plated metal with molding material or underfill.

[0130] like Figure 29 As shown, step 11: Remove the carrier plate.

[0131] like Figure 30 As shown, step 12: ball placement and dicing to form an independent single-chip encapsulation structure.

[0132] like Figure 31 , Figure 32 As shown, for electroless plated vias, the via area can be formed at the end of the metal redistribution to increase the contact area of ​​the via, which is beneficial for forming good metal interconnects. At the same time, the via is finally cut into a closed or open ring shape, which facilitates subsequent organic filling.

[0133] like Figure 33 As shown, in the case of electroless plated through-holes, the area of ​​the through-hole can be formed at the end of the metal redistribution to increase the contact area of ​​the through-hole, which is conducive to forming a good metal interconnect.

[0134] like Figure 34 As shown, the through-hole is ultimately cut into a non-closed ring shape, which facilitates subsequent filling with organic matter.

[0135] The stacked structure of the chip-DAF-chip of this invention, and the via morphology as follows: Figure 35 As shown.

Claims

1. A packaging structure for vertically stacking and interconnecting chips via chemical plating, comprising chips, characterized in that: Several chip units are stacked vertically and aligned from bottom to top on a substrate (7). Several chip units are interconnected by chemically plated metal (2) to the pads. The chip unit includes a wafer, a wafer pad, and a copper layer. The top of the wafer (6) is connected to the wafer pad (5). The surfaces of the wafer (6) and the wafer pad (5) are coated with a buffer protective layer (4). A copper layer (3) is provided on the buffer protective layer (4). Adjacent chip units are bonded together by a DAF film (8).

2. The packaging structure for vertical chip stacking and interconnection via chemical plating as described in claim 1, characterized in that: The substrate (7) is provided with several substrate pads (9) and metal conductive material (10). Several chip units and chemically plated metal (2) on the substrate (7) are encapsulated by plastic encapsulation material (1). Balls are planted at the bottom of the substrate (7).

3. The packaging structure for vertical chip stacking and interconnection via chemical plating as described in claim 1, characterized in that: The outer side of the aforementioned chip units is encapsulated with filler glue (11).

4. The packaging structure for vertical chip stacking and interconnection via chemical plating according to claim 1, characterized in that: The buffer protective layer (4) is polyimide.

5. A packaging method for achieving vertical chip stacking and interconnection packaging structures through chemical plating, characterized in that: The encapsulation methods include Method 1 and Method 2.

6. The packaging method for achieving vertical chip stacking and interconnection packaging structure by chemical plating according to claim 5, characterized in that: The specific process of method one is as follows: S1-1, Wafer arrival, cleaning and other preparation work: drawing pads on the wafer surface; S1-2, Draw grooves in the scribe line near the wafer pads; S1-3, Polyimide is coated on the surface of the wafer where the circuit has been fabricated as a buffer protective layer, and then the pad openings are precisely etched out by standard photolithography process. S1-4, Electroplated copper layer: Connecting the solder pads to the dicing groove; S1-5, thinning the back side of the wafer; or first thinning to a certain distance from the polyimide layer, and then continuing to thin it until the polyimide layer is exposed by etching or dry plasma etching. S1-6, Dicing: Retaining the copper layer in the dicing groove to form a chip unit structure with a copper layer on one side; S1-7, Fabricate carrier wafer, place substrate on carrier, substrate pads and conductive metal material inside substrate for connection with wafer pads. S1-8, Several chip units are stacked vertically and aligned sequentially on the substrate; S1-9, the outer side of several chip units is filled with filler glue; S1-10 uses a laser to create holes in the dicing groove for subsequent metal interconnect formation; the holes can be small or large. S1-11, through chemical plating, interconnections between chip units and between chip units and the bottom substrate are established in the through-hole; S1-12, plastic sealed; S1-13, Remove the carrier plate from the substrate bottom plate; S1-14, after ball placement, is cut into individual chip units to complete the entire packaging structure.

7. The packaging method for achieving vertical chip stacking and interconnection packaging structure by chemical plating according to claim 5, characterized in that: The specific process of method two is as follows: S2-1, Wafer arrival, cleaning and other preparation work: drawing pads on the wafer surface; S2-2, Draw grooves in the scribe line near the wafer pads; S2-3, Polyimide is coated on the surface of the wafer with the completed circuit fabrication as a buffer protective layer, and then the pad openings are precisely etched out by standard photolithography process. S2-4, Electroplated copper layer: Connecting the pads to the dicing groove; S2-5, thinning the back side of the wafer; or first thinning to a certain distance from the polyimide layer, and then continuing to thin it until the polyimide layer is exposed by etching or dry plasma etching. S2-6, Fabricating a carrier wafer, placing a substrate on the carrier, the substrate contains substrate pads and conductive metal material for connection with the wafer pads; S2-7, Several chip units are stacked vertically and aligned sequentially on the substrate; S2-8, holes are made at the dicing groove using a laser method for subsequent metal interconnect formation; S2-9, through chemical plating, interconnections between chip units and between chip units and the bottom substrate are established within the through-hole; S2-10, fills the voids in the chemically plated metal with molding compound or filler adhesive; S2-11, Remove the carrier plate from the substrate bottom plate; S2-12, after ball placement, is diced and cut into individual chip units to complete the entire packaging structure.

8. The packaging method for achieving a vertically stacked and interconnected chip packaging structure through chemical plating according to claim 6 or 7, characterized in that: In steps S1-2 and S2-2, a groove is formed in the dicing track adjacent to the wafer pad by laser ablation or blade cutting, which is used for subsequent rewiring processes to form a structure in which copper interconnects climb within the groove.

9. The packaging method for achieving a vertically stacked and interconnected chip packaging structure through chemical plating according to claim 6 or 7, characterized in that: The specific procedures for steps S1-4 and S2-4 are as follows: S41, on a wafer that has already formed a polyimide layer and pad openings, an adhesion layer and a copper seed layer are sequentially deposited by physical vapor deposition. S42, Subsequently, a patterned photoresist mask is formed in the area to be electroplated using a photolithography process, exposing the predetermined electroplating path to be connected to the pads and the dicing groove. S43, Next, the copper electroplating operation is performed: the wafer is used as the cathode and immersed in an electrolyte containing copper ions. Under the action of an external electric field, copper ions are reduced and deposited on the surface of the copper seed layer. Its growth is strictly limited to the photoresist opening area. S44, the electroplated copper layer starts from the pad, extends along the preset path and finally fills the groove in the dicing channel, thereby forming a metal connection structure.

10. The packaging method for achieving vertical chip stacking and interconnection packaging structure by chemical plating according to claim 6, characterized in that: In steps S1-6, before dicing, a DAF film is attached to the back of the wafer for subsequent chip stacking and bonding.

11. The packaging method for achieving vertical chip stacking and interconnection packaging structure by chemical plating according to claim 7, characterized in that: In steps S2-7, before stacking, a DAF film is attached to the back of the wafer for subsequent chip stacking and bonding.

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