An implantable multi-modal brain-computer interface sensing device and a preparation method thereof

Abstract

The application discloses an implantable multi-modal brain-computer interface sensing device and a preparation method thereof. The implantable multi-modal brain-computer interface sensing device comprises, in sequence, a biological fluid barrier layer, a silicon thin film active transistor array layer, a gate dielectric layer, an epitaxial gate metal array layer, a first metal circuit pattern layer, an insulating isolation layer, a second metal circuit pattern layer and a packaging layer. Each epitaxial gate metal unit in the epitaxial gate metal array layer and each silicon thin film active transistor unit in the silicon thin film active transistor array layer are arranged in one-to-one correspondence. Each silicon thin film active transistor is used as an electric sensor, an optical sensor and an ion pH sensor to detect the electric signal, the optical signal and the ion pH signal of the measured biological fluid attached to the biological fluid barrier layer. In the application, various physiological signal detections can be considered, the device structure is simple and easy to realize, the transistor does not need to directly contact the measured biological fluid, and the service life of the sensing device is prolonged.

Description

Technical Field

[0001] This invention relates to the field of sensors, and in particular to an implantable multimodal brain-computer interface sensing device and its fabrication method. Background Technology

[0002] Neurophysiological monitoring plays an irreplaceable role in the diagnosis and treatment of neurological diseases. For example, neuroelectrorecording can provide real-time prevention or early warning of the pathological state of chronic diseases such as epilepsy, thus helping to avoid missing the optimal treatment window. Utilizing neurophysiological signals to aid diagnosis often requires monitoring multiple different physiological signals. For instance, diseases such as tumors are often accompanied by abnormal cortical electrical activity, some diseases require optogenetic intervention, and most brain diseases cause abnormal ion concentrations. However, simultaneously monitoring multiple different physiological signals often presents challenges due to the complexity of the devices used and the difficulty in coupling them. Summary of the Invention

[0003] The purpose of this invention is to provide an implantable multimodal brain-computer interface sensing device and its preparation method, which can detect three different physiological signals, has a simple and easy-to-implement structure, and a long service life.

[0004] To solve the above-mentioned technical problems, the present invention provides an implantable multimodal brain-computer interface sensing device, comprising a biofluid barrier layer, a silicon thin film active transistor array layer, a gate dielectric layer, an epitaxial gate metal array layer, a first metal circuit pattern layer, an insulating isolation layer, a second metal circuit pattern layer and an encapsulation layer stacked sequentially.

[0005] In this configuration, each epitaxial gate metal unit in the epitaxial gate metal array layer and each silicon thin-film active transistor unit in the silicon thin-film active transistor array layer are arranged in a one-to-one correspondence; the first metal line pattern layer and the source of each silicon thin-film active transistor unit are electrically connected; the second metal line pattern layer and the drain of each silicon thin-film active transistor unit are electrically connected.

[0006] Each of the aforementioned silicon thin-film active transistors is used as an electrical sensor, optical sensor, and ionic pH sensor to detect the electrical, optical, and ionic pH signals of the biofluid being tested that is attached to the biofluid barrier layer.

[0007] In one optional embodiment of this application, the biofluid barrier layer is a thermal silica layer with a thickness of 0.3µm to 2µm.

[0008] In one optional embodiment of this application, the silicon thin-film active transistor unit is a MOSFET active transistor; the channel length of the silicon thin-film active transistor is 8µm to 25µm, and the width is 60µm to 150µm.

[0009] In one optional embodiment of this application, the gate dielectric layer includes a silicon dioxide layer and an aluminum oxide layer; wherein the thickness of the gate dielectric layer is not greater than 100 nm.

[0010] In one optional embodiment of this application, the epitaxial gate metal unit is any one of a square metal layer, a triangular metal layer, or a circular metal layer with a aperture size of 150µm to 300µm.

[0011] In one optional embodiment of this application, the thickness of the first metal circuit pattern layer is 50nm~200nm;

[0012] The thickness of the second metal circuit pattern layer is 200nm~500nm;

[0013] The insulating layer is a polyimide layer with a thickness of 0.5µm to 2µm.

[0014] In one optional embodiment of this application, the encapsulation layer is a polyimide layer.

[0015] Alternatively, the encapsulation layer may be a multilayer polyimide film layer bonded together by a polydimethylsiloxane layer or a silicone adhesive layer.

[0016] In one optional embodiment of this application, the thickness of the encapsulation layer is 4µm to 20µm.

[0017] A method for fabricating an implantable multimodal brain-computer interface sensing device includes:

[0018] A biofluid barrier layer is formed on the first surface of the silicon thin film;

[0019] Mask diffusion is performed on the second surface of the silicon thin film to fabricate silicon thin film active transistor units that form an array distribution;

[0020] A gate dielectric layer is deposited on the second surface of the silicon thin film, and vias are formed at the source and drain positions of each silicon thin film active transistor unit.

[0021] An epitaxial gate metal unit corresponding to each of the thin-film active transistor units is etched on the gate dielectric layer, and a first metal line pattern layer is formed that is electrically connected to the source of each of the silicon thin-film active transistor units through the via.

[0022] An insulating isolation layer covering the epitaxial gate metal unit and the first metal line pattern layer is sequentially formed on the gate dielectric layer, a second metal line pattern layer electrically connected to the drain of each silicon thin film active transistor unit through the via, and an encapsulation layer covering the second metal line pattern layer.

[0023] In one optional embodiment of this application, a biofluid barrier layer is formed on a first surface of the silicon thin film, comprising:

[0024] A thermal silicon dioxide layer is grown on the first surface of the silicon thin film to serve as the biofluid barrier layer.

[0025] This invention provides an implantable multimodal brain-computer interface sensing device and its fabrication method. The implantable multimodal brain-computer interface sensing device includes a biofluid barrier layer, a silicon thin-film active transistor array layer, a gate dielectric layer, an epitaxial gate metal array layer, a first metal circuit pattern layer, an insulating isolation layer, a second metal circuit pattern layer, and an encapsulation layer, which are stacked sequentially. Each epitaxial gate metal unit in the epitaxial gate metal array layer corresponds one-to-one with each silicon thin-film active transistor unit in the silicon thin-film active transistor array layer. The first metal circuit pattern layer is electrically connected to the source of each silicon thin-film active transistor unit; the second metal circuit pattern layer is electrically connected to the drain of each silicon thin-film active transistor unit. Each silicon thin-film active transistor is used as an electrical sensor, an optical sensor, and an ion pH sensor to detect the electrical signal, optical signal, and ion pH signal of the biofluid being tested attached to the biofluid barrier layer.

[0026] The brain-computer interface sensing device of this application uses silicon thin-film active transistors as sensor units to realize neurophysiological signals. Each silicon thin-film active transistor is a sensing unit that integrates three sensing functions: electrical sensor, optical sensor, and ion pH sensor. It can simultaneously monitor multiple different physiological signals, and the entire sensing device has a simple structure that is easy to implement. In addition, each silicon thin-film active transistor does not need to directly contact the biological fluid being measured, which helps to extend the service life of the sensing device. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 An exploded structural diagram of the implantable multimodal brain-computer interface sensing device provided in the embodiments of this application;

[0029] Figure 2 A schematic diagram of a partial exploded structure of a silicon thin-film active transistor unit in an implantable multimodal brain-computer interface sensing device provided in an embodiment of this application;

[0030] Figure 3A schematic diagram of the equivalent circuit of the silicon thin-film active crystal unit as an electrical sensor provided in the embodiments of this application;

[0031] Figure 4 for Figure 3 A schematic diagram of the input and output voltages changing over time in a circuit diagram;

[0032] Figure 5 A schematic diagram of the equivalent circuit of the silicon thin-film active crystal unit as a photosensitive element provided in the embodiments of this application;

[0033] Figure 6 for Figure 5 In the circuit diagram, I under different source-drain voltages DS A coordinate diagram showing the variation of incident blue LED intensity;

[0034] Figure 7 A schematic diagram of the equivalent circuit of the silicon thin-film active crystal unit as an ion pH sensor provided in the embodiments of this application;

[0035] Figure 8 for Figure 7 V in the circuit diagram REF A graph showing the relationship between pH value and coordinates.

[0036] Figure 9 for Figure 7 In the circuit diagram, V under different source-drain voltages REF A graph showing the relationship between pH value and coordinates.

[0037] Figure 10 A schematic flowchart illustrating the fabrication method of the implantable multimodal brain-computer interface sensing device provided in this application embodiment;

[0038] In the attached figure: 1 is the biological fluid barrier layer, 2 is the silicon thin film active transistor unit, 3 is the gate dielectric layer, 4 is the epitaxial gate metal unit, 5 is the first metal circuit pattern layer, 6 is the insulating isolation layer, 7 is the second metal circuit pattern layer, 8 is the encapsulation layer, and 9 is the reference electrode. Detailed Implementation

[0039] The core of this invention is to provide an implantable multimodal brain-computer interface sensing device and its preparation method, which can simplify the structure of the sensing device and extend its service life while simultaneously monitoring multiple different physiological signals.

[0040] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] Figure 1 This is an exploded structural diagram of the implantable multimodal brain-computer interface sensing device provided in the embodiments of this application.

[0042] like Figure 1 As shown, an implantable multimodal brain-computer interface sensing device provided in a specific embodiment of this application may include:

[0043] The following layers are stacked sequentially: a biological fluid barrier layer 1, a silicon thin film active transistor array layer, a gate dielectric layer 3, an epitaxial gate metal array layer, a first metal line pattern layer 5, an insulating isolation layer 6, a second metal line pattern layer 7, and an encapsulation layer 8.

[0044] In this configuration, each epitaxial gate metal unit 4 in the epitaxial gate metal array layer and each silicon thin film active transistor unit 2 in the silicon thin film active transistor array layer are arranged in a one-to-one correspondence; the first metal line pattern layer 5 is electrically connected to the source of each silicon thin film active transistor unit 2; and the second metal line pattern layer 7 is electrically connected to the drain of each silicon thin film active transistor unit 2.

[0045] Each silicon thin-film active transistor unit 2 is used as an electrical sensor, optical sensor and ion pH sensor to detect the electrical signal, optical signal and ion pH signal of the biological fluid being tested attached to the biological fluid barrier layer 1.

[0046] The implantable multimodal brain-computer interface sensing device in this application consists of a membrane-like structure formed by stacking multiple layers in sequence, which allows for better adhesion to the surface of the object being tested in practical applications.

[0047] like Figure 1As shown, in this embodiment, the part of the brain-computer interface that directly contacts the tested biological fluid is the biofluid barrier layer 1. This biofluid barrier layer 1 can isolate the tested biological fluid from direct contact with the transistor device, thereby preventing the transistor device from being corroded and damaged, thus affecting the lifespan of the entire sensing device. The biofluid barrier layer 1 is a light-transmitting structural layer and can also serve as a dielectric layer for capacitors. It is also a flexible structural layer, allowing for better adhesion to the surface of the tested object. In this embodiment, the biofluid barrier layer 1 can be a thermally heated silicon dioxide layer. A thicker thermally heated silicon dioxide layer results in a longer device lifespan, but relatively speaking, the capacitive coupling effect and mechanical flexibility are worse. In practical applications, the thickness of the biofluid barrier layer 1 can be 0.3µm to 2µm.

[0048] The silicon thin-film active transistor array layer is directly bonded to the biological fluid barrier layer 1. It is the main device for signal detection. The silicon thin-film active transistor array layer is a number of silicon thin-film active transistor units 2 arranged in an array, which are prepared by means of mask diffusion, etching, deposition and other methods on the same silicon thin film (refer to the conventional transistor preparation process).

[0049] Each silicon thin-film active transistor unit 2 in this embodiment is also a transistor device with signal detection function, such as... Figure 2 As shown, the silicon thin-film active transistor unit 2 can specifically be a MOSFET active transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, also known as a metal-oxide-semiconductor field-effect transistor); each silicon thin-film active transistor unit 2 is a transistor device that integrates three sensing functions: an electrical signal sensor for detecting the electrical signal of the analyte, a photosensitive sensor for detecting the optical signal of the analyte, and an ion pH sensor for detecting the ion pH signal of the analyte.

[0050] like Figure 1 As shown, each silicon thin-film active transistor unit 2 can be arranged in a 4×4 array or in a larger number of rows, depending on the actual measurement needs, and this application does not impose specific limitations on this. Furthermore, each silicon thin-film active transistor unit 2 can be either an N-channel transistor or a P-channel transistor.

[0051] like Figure 2As shown, when the silicon thin-film active transistor unit 2 works as a photosensor, the channel size of the silicon thin-film active transistor unit 2 directly determines the strength of the light signal that can be detected. The shorter the channel length (the distance between the source and drain), the stronger the current corresponding to the detected light signal; the wider the channel width (the dimension perpendicular to the line connecting the drain and source), the stronger the current. Therefore, combined with the transistor size and survival rate requirements, the channel length can be in the range of 8μm-25μm, the channel width can be in the range of 60μm-150μm, and the thickness can use the standard SOI of 220nm or other similar thickness.

[0052] like Figure 2 As shown, for each silicon thin-film active transistor unit 2, the source ( Figure 2 S and drain (in the middle) Figure 2 D) should be located on the side of the silicon thin-film active transistor unit 2 away from the biological fluid barrier layer 1. In addition, a gate dielectric layer 3 is further attached and covered on the surface of the silicon thin-film active transistor unit 2 away from the biological fluid barrier layer 1. The gate dielectric layer 3 may consist of only a silicon dioxide layer or may consist of two layers: a silicon dioxide layer and an aluminum oxide layer. However, regardless of whether the gate dielectric layer 3 is a single-layer dielectric layer structure or a double-layer dielectric layer structure, its thickness should not exceed 100 nm, for example, it can be 50 nm.

[0053] On the side of the gate dielectric layer 3 facing away from the silicon thin-film active transistor unit 2, an epitaxial gate metal unit 4 is further provided. The epitaxial gate metal unit 4 should be arranged in an array attached to the gate dielectric layer 3, and each epitaxial gate metal unit 4 and each silicon thin-film active transistor unit 2 should be arranged in a one-to-one correspondence. Of course, each epitaxial gate metal unit 4 includes a metal block facing the channel region of the silicon thin-film active transistor unit 2, and also includes a metal block extending beyond the region of the silicon thin-film active transistor unit 2. This part of the metal block can be regarded as a metal plate. When the silicon thin-film active transistor unit 2 works as an ion pH sensor or an electrical sensor, it can form a capacitor together with the separately configured reference electrode 9. The gate dielectric layer 3 and the thermal silicon dioxide layer attached to the metal plate are also the capacitance medium between the metal plate and the reference electrode 9, thereby realizing the detection of the ion pH signal of the measured fluid. Each epitaxial gate metal unit 4 can be any one of a square metal layer, a triangular metal layer, or a circular metal layer. The larger the area of ​​the epitaxial gate metal, the better the capacitive coupling effect for AC current, but the lower the spatial resolution. In practical applications, its aperture size can be 150µm to 300µm. That is, if it is a square metal layer, its diagonal size can be 150µm to 300µm; if it is a circular metal layer, its diameter size can be 150µm to 300µm. Of course, the epitaxial gate metal unit 4 in this application is not limited to a centrally symmetrical structure. For example, it can also be a rectangular metal layer with each side length being 150µm to 300µm, or an elliptical metal layer with both the major and minor axes being 150µm to 300µm, etc., which does not affect the implementation of the technical solution of this application.

[0054] Based on this, in addition to the epitaxial gate metal unit 4, a first metal line pattern layer 5 is also provided on the side of the gate dielectric layer 3 away from the silicon thin film active transistor unit 2. The first metal line pattern layer 5 and the epitaxial gate metal unit 4 can be provided on the same layer as the first metal line pattern layer 5 or on two adjacent layers, as long as they are insulated from each other and do not contact each other.

[0055] Furthermore, an insulating isolation layer 6 is further provided on the side of the first metal circuit pattern layer 5 away from the gate dielectric layer 3, and a second metal circuit pattern layer 7 is provided on the side of the insulating isolation layer 6 away from the first metal circuit pattern layer 5. That is to say, the first metal circuit pattern layer 5 and the second metal circuit pattern layer 7 are mutually insulated and isolated. The first metal circuit pattern layer 5 and the second metal circuit pattern layer 7 are used to realize the electrical connection between the source and drain of each silicon thin film active transistor unit 2 and the external circuit.

[0056] Therefore, in practical applications, the first metal circuit pattern layer 5 is electrically connected to the source of each silicon thin film active transistor unit 2 through the first via formed on the gate dielectric layer 3, while the second metal circuit pattern layer 7 is electrically connected to the drain of each silicon thin film active transistor unit 2 through the second via formed on the gate dielectric layer 3 and the insulating isolation layer 6. At this time, each first via can be formed at the position directly opposite the source of each silicon thin film active transistor unit 2, and the second via can be formed at the position directly opposite the drain of each silicon thin film active transistor unit 2.

[0057] In practical applications, the first metal circuit pattern layer 5 can be electrically connected to the drain of each silicon thin-film active transistor unit 2 through a first via on the gate dielectric layer 3, while the second metal circuit pattern layer 7 can be electrically connected to the source of each silicon thin-film active transistor unit 2 through a second via on the gate dielectric layer 3 and the insulating isolation layer 6. In this case, each first via can be opened at the drain position of each silicon thin-film active transistor unit 2, and the second via can be opened at the source position of each silicon thin-film active transistor unit 2.

[0058] Of course, the first and second vias are not necessarily directly opposite the source and drain of each silicon thin-film active transistor unit 2. They can also be at a certain distance from the source and drain, and the source and gate can be electrically connected to the two metal circuit patterns through some conductive leads. In short, as long as the first and second vias are staggered to avoid short circuits between the first metal circuit pattern layer 5 and the second metal circuit pattern layer 7, and also to avoid short circuits between the drain and the source, it is acceptable.

[0059] Based on this, taking the source electrical connection between the first metal line pattern layer 5 and each silicon thin-film active transistor unit 2 as an example, in the first metal line pattern layer 5, a metal line can be independently set for the source of each silicon thin-film active transistor unit 2 and electrically connected to the external circuit. Alternatively, the metal lines corresponding to the sources of each silicon thin-film active transistor unit 2 can be connected in series and then connected to the external circuit through a main lead. Similarly, a similar layout can be adopted for the lines in the second metal line pattern layer 7 that connect to the drain of each silicon thin-film active transistor unit 2, which will not be described in detail in this embodiment.

[0060] Furthermore, the thickness of the first metal circuit pattern layer 5 can be 50nm~200nm, and the thickness of the second metal circuit pattern layer 7 can be 200nm~500nm; while the insulating isolation layer 6 disposed between the first metal circuit pattern layer 5 and the second metal circuit pattern layer 7 can be a polyimide layer with a thickness of 0.5µm~2µm.

[0061] Based on the above discussion, an encapsulation layer 8 can be further provided on the side of the second metal circuit pattern layer 7 away from the insulating isolation layer 6. The encapsulation layer 8 and the biofluid barrier layer 1 can jointly encapsulate the silicon thin film active transistor array layer, the epitaxial gate metal unit 4, the first metal circuit pattern layer 5 and the second metal circuit pattern layer 7, thereby avoiding direct contact between the above crystal devices and the tested biofluid, thus extending the service life of the devices.

[0062] In this embodiment, the encapsulation layer 8 can be a flexible polyimide layer or a multilayer polyimide film layer bonded together sequentially by a polydimethylsiloxane layer or a silicone adhesive layer. Regardless of whether the encapsulation layer 8 is a single-layer polyimide layer or a multilayer film structure, its total thickness can be set to 4µm~20µm.

[0063] Based on the above discussion, and referring to... Figure 1 In an optional embodiment of this application, the implantable multimodal brain-computer interface sensing device may include:

[0064] The first layer is a thermal SiO2 layer with a thickness of 0.3μm-2μm, which serves as both a biological fluid barrier and a dielectric layer for capacitive coupling.

[0065] The second layer is a silicon thin-film active transistor array layer, which is composed of silicon thin-film active transistor units 2 arranged in a 4×4 array. The thickness can be 220nm. It is a transistor device with key structural layers (such as a silicon thin-film structure with p+, np+, n+, pn+ and other structural layers). Each silicon thin-film active transistor unit 2 is a MOSFET.

[0066] The third layer is the gate dielectric layer 3, which includes a 50nm SiO2 layer and a 15nm Al2O3 layer. The overall thickness can be appropriately increased or decreased, but not exceeding 100nm. It is the insulating structure of the MOSFET, which allows almost no current to flow through the gate of the MOSFET.

[0067] The fourth layer consists of an epitaxial gate metal array layer 4 and a first metal line patterning layer 5. The epitaxial gate metal array layer includes 16 epitaxial gate metal units 4 arranged in an array. The first metal patterning layer 5 includes 4 column-direction common leads (common source or common drain), with a thickness ranging from 50nm to 200nm.

[0068] The fifth layer is an electrical insulation barrier layer between the two metal wiring layers. A thinner PI (polyimide) material can be selected, with a thickness ranging from 0.5μm to 2μm.

[0069] The sixth layer is the second metal circuit pattern layer 7, with a thickness ranging from 200nm to 500nm, involving four row-direction common leads in the array.

[0070] The seventh layer is the encapsulation layer 8, with a thickness of 4μm-20μm, which provides electrical encapsulation and waterproofing.

[0071] like Figure 1 As shown, the implantable multimodal brain-computer interface sensing device in this embodiment adopts a common source and common drain lead design. The silicon thin film MOSFET acts as an electrical sensor, as well as a light sensor and an ion pH sensor. The number of its arrays is not limited to 4×4 and can be increased or decreased arbitrarily according to the size of the sensing device. The spatial resolution can also be arbitrarily adjusted according to the transistor size and lead method, which can realize large-area, high-density monitoring.

[0072] Based on the above embodiments, the working modes of each silicon thin-film active transistor unit 2 in the implantable multimodal brain-computer interface sensing device as an electrical sensor, an optical sensor, and an ion pH sensor will be described below.

[0073] Taking silicon thin-film active transistor unit 2 as a P-type MOSFET as an example, when silicon thin-film active transistor unit 2 works as an electrical sensor, the source follower circuit based on the P-type MOSFET is as follows: Figure 3 As shown, based on Figure 3 The circuit structure in, such as Figure 4 As shown, the output AC signal V of this P-type MOSFET OUT (Drain output) and input signal V IN (Reference electrode 9 input) The amplitude and frequency are almost consistent, which means that the signal of this P-type MOSFET has high fidelity.

[0074] When the silicon thin-film active transistor unit 2 operates as a light sensor, such as Figure 5 and Figure 6 As shown, Figure 5 The diagram shows the equivalent circuit of silicon thin-film active transistor unit 2 as a photosensor, illustrating the similarity in sensing principle between the photosensor based on silicon thin-film active transistor unit 2 and the photosensor based on silicon photodiode, both based on the photoelectric effect at single-crystal silicon and its PN junction; in this case, the silicon thin-film active transistor operates with no gate voltage; as shown... Figure 6 As shown, Figure 6 The diagram shows two drain-source voltages V at -0.2V and -1.0V. DS Below, the corresponding drain-source current and the incident blue LED intensity both show a highly linear relationship, based on Figure 6 The photometric sensitivity of the silicon thin-film active transistor unit 2 can reach up to approximately 0.57 nA / (mW / cm²).

[0075] When the silicon thin-film active transistor unit 2 operates as an ion pH sensor, its circuit diagram is as follows: Figure 7As shown, when used in an ion pH sensor, a capacitance is formed between the epitaxial gate metal layer as the working electrode and the reference electrode 9. RE and WE represent the reference electrode 9 and the working electrode (epitaxy gate metal unit 4), respectively. The capacitance is utilized using the reference voltage V. REF (The voltage value connected to the reference electrode 9) adjusts the transfer characteristics of the silicon thin-film active transistor unit 2 to the linear region. At this time, the number of ions attached to the gate sensitive layer (working electrode, i.e., the epitaxial gate metal unit 4) of the silicon thin-film active transistor unit 2 increases (i.e., the ion concentration increases), which will effectively apply a charge bias voltage to the epitaxial gate metal unit 4 of the silicon thin-film active transistor unit 2, causing the transistor threshold voltage V T Offset, and the same reference voltage V REF Under the action of the channel current I D Significantly improved or decreased.

[0076] like Figure 8 and Figure 9 As shown, Figure 8 The reference voltage V based on the transfer characteristic curve is shown in the figure. REF The sensitivity, relating to ionic pH, reaches approximately 46.9 mV / pH. Figure 9 The middle section shows the current I based on the output characteristic curve. DS The sensitivity to pH is approximately 0.65 μA / pH, and it increases with the drain-source voltage V. DS It increases as it grows.

[0077] Based on the above discussion, each silicon thin-film active transistor unit 2 in this application can utilize the three sensing principles mentioned above to achieve a three-in-one sensing mode, that is, to detect three different signals: electrical, optical, and ionic pH. This allows the silicon thin-film array transistor layer to serve as a highly integrated three-purpose array layer. Specifically, the specific sensing locations for electrical sensing, optical sensing, and ionic pH sensing are the epitaxial gate metal unit 4, the transistor channel, and the epitaxial gate metal unit 4, respectively. Unlike electrical sensing, ionic pH sensing requires an additional reference electrode 9, which is typically an Ag layer or an AgCl layer.

[0078] In summary, the brain-computer interface sensor in this application uses silicon thin-film active transistors as the sensor unit to realize neurophysiological signals. Each silicon thin-film active transistor is a sensing unit that integrates three sensing functions: electrical sensor, optical sensor, and ion pH sensor. It can simultaneously monitor multiple different physiological signals, and the entire sensing device has a simple structure that is easy to implement. In addition, each silicon thin-film active transistor does not need to directly contact the biological fluid being measured, which helps to extend the service life of the sensing device.

[0079] Based on the above discussion, a corresponding fabrication method is further provided for the aforementioned implantable multimodal brain-computer interface sensing device. The fabrication method for the implantable multimodal brain-computer interface sensing device provided in this application may include:

[0080] S1: A biofluid barrier layer 1 is formed on the first surface of the silicon thin film;

[0081] S2: Mask diffusion is performed on the second surface of the silicon thin film to fabricate silicon thin film active transistor units 2 that form an array distribution;

[0082] S3: A gate dielectric layer 3 is deposited on the second surface of the silicon thin film, and through holes are opened at the source and drain positions of each silicon thin film active transistor unit 2.

[0083] S4: Etch an epitaxial gate metal unit 4 on the gate dielectric layer 3 to form an epitaxial gate metal unit 4 corresponding to each thin film active transistor unit 2, and form a first metal line pattern layer 5 that is electrically connected to the source of each silicon thin film active transistor unit 2 through a via.

[0084] S5: An insulating isolation layer 6 covering the epitaxial gate metal unit 4 and the first metal line pattern layer 5, a second metal line pattern layer 7 electrically connected to the drain of each silicon thin film active transistor unit 2 through vias, and an encapsulation layer 8 covering the second metal line pattern layer 7 are sequentially formed on the gate dielectric layer 3.

[0085] Optionally, the biofluid barrier layer 1 in this embodiment can specifically be a thermally grown silicon dioxide layer on a silicon thin film. Furthermore, mask diffusion is performed on the second surface of the silicon thin film to form the drain and gate of each silicon thin film active transistor, thus realizing the fabrication process of each silicon thin film active transistor. Then, the gate dielectric layer, epitaxial gate metal unit 4, first metal circuit pattern layer 5, insulating isolation layer 6, second metal circuit pattern layer 7, and encapsulation layer 8 are sequentially fabricated layer by layer, ultimately obtaining an implantable multimodal brain-computer interface sensing device.

[0086] In one optional embodiment, the method for fabricating the implantable multimodal brain-computer interface sensing device may include:

[0087] (1) Preparation of silicon-on-insulator substrate: An N-type SOI wafer is obtained, which consists of a 220nm single crystal silicon layer (used to form the active region of MOSFET, i.e., silicon thin film), a 300nm Box layer (buried oxide layer, i.e. thermal oxide layer), and a 500μm bottom silicon layer. The bottom silicon layer is removed by mechanical polishing to expose the Box layer, and the thermal oxide layer can be obtained directly.

[0088] (2) Doping and isolation: A 600 nm thick SiO2 layer was deposited on a single crystal silicon layer at 300 °C using plasma-enhanced chemical vapor deposition (PECVD) as a diffusion mask; in order to obtain silicon thin film units with p+ and np+ structures arranged in an array, the doping window was defined by photolithography and first etched by reactive ion etching, and the deeper oxide layer was removed by buffer oxide etchant; boron pre-deposition was carried out in a tube furnace at 960 °C for 15 minutes, and then in a tube furnace at 1100 °C for 35 minutes to form a P-type region; patterned etching was carried out by photolithography to pattern the single crystal silicon layer between each silicon thin film unit to form 16 silicon thin film active transistor units 2 arranged in an array, that is, to form 16 mutually isolated measurement channels;

[0089] (3) Gate oxide deposition and opening: A 50 nm SiO2 layer is formed by PECVD deposition at 350 °C, and a 15 nm Al2O3 layer is obtained by atomic layer deposition at 250 °C, thereby forming a double gate dielectric layer; then, through holes are opened in the regions facing the source and drain of each silicon thin film active transistor unit 2 by photolithography.

[0090] (4) First metal patterning and isolation layer: A chromium metal layer (thickness of 5nm) and a gold metal layer (thickness of 50nm) are deposited by magnetron sputtering. The gate metal of the array of 16 channels and 4 column-direction common leads (common source leads or common drain leads) are formed by photolithography and wet etching. Then, a thin polyimide layer (thickness of 1μm) is spin-coated as an insulating isolation layer 6. On the insulating isolation layer 6, through holes facing the source or drain are defined by photolithography and RIE to prepare for subsequent connection with the second metal wiring layer.

[0091] (5) Second layer metal patterning: A chromium metal layer (10 nm thick) and a gold metal layer (300 nm thick) are deposited by magnetron sputtering. Photolithography defines and wet etching forms an array of four row-direction common leads. The row-direction common leads are connected to the source or drain through the via formed on the insulating isolation layer in (4).

[0092] (6) Packaging: A polyimide layer (6 μm thick) is spin-coated as the packaging layer. Polydimethylsiloxane (PDMS) or silicone adhesive is used as a soft adhesive to attach the polyimide film to the glass substrate. PDMS is cured at 110°C for 60 minutes. Another layer of PDMS is spin-coated on the polyimide film to bond the polyimide layer to the polyimide film. Pressure is applied and the film is fixed with a fixture and cured at 110°C for 60 minutes. The bottom silicon (glass substrate) is removed by inductively coupled plasma reactive ion etching (SF6 and O2 flow ratio of 30:6). The remaining bulk silicon is then etched using a highly selective xenon difluoride etching system to achieve flexibility. Finally, the opening area of ​​the contact leads is defined by photolithography, bias (CF4 and O2 flow ratio of 40:1) and BOE.

[0093] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the elements inherent in a process, method, article, or apparatus that includes a list of elements are included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Additionally, portions of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of corresponding technical solutions in the prior art have not been described in detail to avoid excessive elaboration.

[0094] This article uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. An implantable multimodal brain-computer interface sensing device, characterized in that, It includes a biological fluid barrier layer, a silicon thin film active transistor array layer, a gate dielectric layer, an epitaxial gate metal array layer, a first metal line pattern layer, an insulating isolation layer, a second metal line pattern layer and an encapsulation layer stacked sequentially. In this configuration, each epitaxial gate metal unit in the epitaxial gate metal array layer and each silicon thin-film active transistor unit in the silicon thin-film active transistor array layer are arranged in a one-to-one correspondence; the first metal line pattern layer and the source of each silicon thin-film active transistor unit are electrically connected; the second metal line pattern layer and the drain of each silicon thin-film active transistor unit are electrically connected. Each of the aforementioned silicon thin-film active transistors is used as an electrical sensor, optical sensor, and ionic pH sensor to detect the electrical, optical, and ionic pH signals of the biofluid being tested that is attached to the biofluid barrier layer.

2. The implantable multimodal brain-computer interface sensing device as described in claim 1, characterized in that, The biofluid barrier layer is a thermal silica layer with a thickness of 0.3µm to 2µm.

3. The implantable multimodal brain-computer interface sensing device as described in claim 1, characterized in that, The silicon thin-film active transistor unit is a MOSFET active transistor; the channel length of the silicon thin-film active transistor is 8µm~25µm, and the width is 60µm~150µm.

4. The implantable multimodal brain-computer interface sensing device as described in claim 1, characterized in that, The gate dielectric layer comprises a silicon dioxide layer and an aluminum oxide layer; wherein the thickness of the gate dielectric layer is not greater than 100 nm.

5. The implantable multimodal brain-computer interface sensing device as described in claim 1, characterized in that, The epitaxial gate metal unit is any one of the following metal layers: square metal layer, triangular metal layer, and circular metal layer with a aperture size of 150µm to 300µm.

6. The implantable multimodal brain-computer interface sensing device as described in claim 1, characterized in that, The thickness of the first metal circuit pattern layer is 50nm~200nm; The thickness of the second metal circuit pattern layer is 200nm~500nm; The insulating layer is a polyimide layer with a thickness of 0.5µm to 2µm.

7. The implantable multimodal brain-computer interface sensing device as described in claim 1, characterized in that, The encapsulation layer is a polyimide layer; Alternatively, the encapsulation layer may be a multilayer polyimide film layer bonded together by a polydimethylsiloxane layer or a silicone adhesive layer.

8. The implantable multimodal brain-computer interface sensing device as described in claim 7, characterized in that, The thickness of the encapsulation layer is 4µm to 20µm.

9. A method for fabricating an implantable multimodal brain-computer interface sensing device, characterized in that, include: A biofluid barrier layer is formed on the first surface of the silicon thin film; Mask diffusion is performed on the second surface of the silicon thin film to fabricate silicon thin film active transistor units that form an array distribution; A gate dielectric layer is deposited on the second surface of the silicon thin film, and vias are formed at the source and drain positions of each silicon thin film active transistor unit. An epitaxial gate metal unit corresponding to each of the thin-film active transistor units is etched on the gate dielectric layer, and a first metal line pattern layer is formed that is electrically connected to the source of each of the silicon thin-film active transistor units through the via. An insulating isolation layer covering the epitaxial gate metal unit and the first metal line pattern layer is sequentially formed on the gate dielectric layer, a second metal line pattern layer electrically connected to the drain of each silicon thin film active transistor unit through the via, and an encapsulation layer covering the second metal line pattern layer.

10. The method for fabricating the implantable multimodal brain-computer interface sensing device as described in claim 9, characterized in that, A biofluid barrier layer is formed on the first surface of the silicon thin film, including: A thermal silicon dioxide layer is grown on the first surface of the silicon thin film to serve as the biofluid barrier layer.

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