A method of generating a test waveform and a digital board card

Abstract

The application relates to a test waveform generation method and a digital board card. The method is applied to a digital board card of an integrated circuit test device, and the digital board card comprises a first encoding module and a second encoding module. The method comprises the following steps: the first encoding module encodes the waveform format of an original test stream based on waveform format information of the original test stream, and first encoding data of each period is obtained; the second encoding module updates the first encoding data of each channel of each period based on a mask enable signal corresponding to each channel, and second encoding data is obtained; the second encoding data is respectively subjected to differential encoding and cumulative flip integral processing, and third encoding data is obtained; and the third encoding data of each channel is subjected to delay control and serial XOR processing, and test waveforms of the entire test process are obtained. The method can solve the problem that the existing test waveform generation mode has low precision due to dependence on manual operation.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and in particular to a method for generating test waveforms and a digital board. Background Technology

[0002] With the rapid development of semiconductor technology, the integration level and operating frequency of chips have been continuously improved. As chip integration level and operating frequency continue to increase, verifying and testing the timing characteristics and functions of chips is particularly important to ensure the performance and quality of integrated circuits. During the testing of chips using integrated circuit testing equipment, the accuracy of the test waveform directly affects the reliability of the test results.

[0003] Existing methods for generating test waveforms typically employ customized application-specific integrated circuits (ASICs) as the core for timing shaping. These chips integrate high-precision analog delay chains, digital phase-locked loops, and dedicated phase synthesis circuits, enabling picosecond-level edge positioning accuracy. However, in this approach, the functional architecture of the dedicated chip is fixed after tape-out, making it impossible to flexibly adjust according to the evolution of test protocols or changes in test requirements. When support for new rate standards or waveform formats is needed, hardware redesign is required, resulting in high equipment upgrade costs.

[0004] To address the above issues, a waveform synthesis method based on a large-scale lookup table (LUT) is proposed. Within an FPGA (Field Programmable Gate Array), a truth table containing all possible cases is pre-defined. Then, based on the test requirements, the pre-defined truth table is indexed and looked up to output formatted waveform data. However, this method relies on manual enumeration and filling of the pre-defined truth table, which can lead to low accuracy due to logical omissions or errors during manual operation.

[0005] The existing methods for generating test waveforms suffer from low accuracy due to reliance on manual operation, and no effective solution has yet been proposed. Summary of the Invention

[0006] Therefore, it is necessary to provide a method for generating test waveforms and a digital board to address the aforementioned technical problems.

[0007] Firstly, this application provides a method for generating test waveforms. A digital board used in integrated circuit testing equipment, the digital board including a first encoding module and a second encoding module, the method comprising:

[0008] The first encoding module encodes the received original test stream based on the waveform format information of the original test stream to obtain the first encoded data for each cycle, and sends the first encoded data for each cycle to the second encoding module; each cycle includes N channels, where N is greater than or equal to 1;

[0009] The second encoding module updates the first encoded data of each path in each cycle based on the mask enable signal corresponding to each path to obtain the second encoded data of each cycle; performs differential encoding and cumulative inversion integral processing on the second encoded data of each path in each cycle to obtain the third encoded data of each cycle; and performs delay control and serial XOR processing on the third encoded data of each path in each cycle to obtain the test waveform of the entire test process.

[0010] In one embodiment, the second encoding module updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path, to obtain the second encoded data of each period, including:

[0011] The second encoding module updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path and the preset path mask mode signal, so as to obtain the second encoded data of each period.

[0012] In one embodiment, the second encoding module updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path and a preset path mask mode signal to obtain the second encoded data of each period, including:

[0013] The second encoding module, for each path in each cycle of the entire test process, if the current path is not the first path of the current cycle, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, the first encoded data of the previous path is used as the second encoded data of the current path; if the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, the first encoded data of the last path of the previous cycle is used as the second encoded data of the current path.

[0014] If the current path is the first path in the current cycle and the current cycle is the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, then 0 is used as the second encoded data of the current path.

[0015] If the mask enable signal corresponding to the current path is invalid and the preset path mask mode signal indicates that the current path mask is invalid, then the first encoded data of the current path will be used as the second encoded data of the current path.

[0016] In one embodiment, each of the said pathways includes multiple edges,

[0017] The step of using the first encoded data of the previous path as the second encoded data of the current path includes:

[0018] For each edge of the current path, if the current edge is the first edge of the current path, then the last edge data of the first encoded data of the previous path is determined as the edge data of the current edge of the second encoded data; if the current edge is not the first edge of the current path, then the edge data of the previous edge of the second encoded data is determined as the edge data of the current edge of the second encoded data.

[0019] The step of using the first encoded data of the last path in the previous cycle as the second encoded data of the current path includes:

[0020] For each edge of the current path, if the current edge is the first edge of the current path, then the last edge data of the first encoded data of the last path of the previous cycle is determined as the edge data of the current edge of the second encoded data; if the current edge is not the first edge of the current path, then the edge data of the previous edge of the second encoded data is determined as the edge data of the current edge of the second encoded data.

[0021] The step of using 0 as the second encoded data of the current path includes:

[0022] 0 is defined as the edge data of each edge of the second encoded data of the current path;

[0023] The step of using the first encoded data of the current path as the second encoded data of the current path includes:

[0024] The edge data of each edge of the first encoded data of the current path is determined as the edge data of each edge of the second encoded data of the current path.

[0025] In one embodiment, the second encoding module performs differential encoding and cumulative inversion integral processing on the second encoded data of each path in each period to obtain the third encoded data of each period, including:

[0026] The second encoding module performs differential encoding on the second encoded data of each path in each period to obtain the differentially encoded second encoded data of each period.

[0027] The second encoded data after differential encoding of each path in each period is subjected to cumulative inversion integral processing to obtain the third encoded data of each period.

[0028] In one embodiment, the second encoding module performs differential encoding on the second encoded data of each path in each period to obtain differentially encoded second encoded data for each period, including:

[0029] The second encoding module, for each path in each cycle of the entire test process, performs an XOR operation between the level value of the second encoded data of the current path and the reference level of the current path to obtain the flip signal of the current path; wherein, if the current path is not the first path of the current cycle, the level value of the second encoded data of the previous path is used as the reference level of the current path; if the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, the level value of the second encoded data of the last path of the previous cycle is used as the reference level of the current path; if the current path is the first path of the current cycle and the current cycle is the first cycle of the entire test process, zero is used as the reference level of the current path;

[0030] The flip signals of each path in each cycle are used as the second encoded data after differential encoding of each path in each cycle, thus obtaining the second encoded data after differential encoding of each cycle.

[0031] In one embodiment, each of the paths includes multiple edges, and the step of XORing the level value of the second encoded data of the current path with the reference level of the current path to obtain the flip signal of the current path includes:

[0032] For each edge of each path, the level value of the current edge of the second encoded data is XORed with the reference level of the current edge to obtain the toggle signal of the current edge. Specifically, if the current edge is not the first edge of the current path, the level value of the previous edge of the second encoded data of the current path is used as the reference level of the current edge. If the current edge is the first edge of the current path, but the current path is not the first path of the current cycle, the level value of the last edge of the second encoded data of the previous path is used as the reference level of the current edge. If the current edge is the first edge of the current path, the current path is the first path of the current cycle, but the current cycle is not the first cycle of the entire test process, the level value of the last edge of the second encoded data of the last path of the previous cycle is used as the reference level of the current edge. If the current edge is the first edge of the current path, the current path is the first path of the current cycle, and the current cycle is the first cycle of the entire test process, then zero level is used as the reference level of the current edge.

[0033] The flip signal of each path is determined based on the flip signal of each edge of each path.

[0034] In one embodiment, the second encoding module performs cumulative inversion integral processing on the differentially encoded second encoded data of each path in each period to obtain the third encoded data of each period, including:

[0035] The second encoding module, for each cycle of the entire test process, if the current cycle is not the first cycle of the entire test process, performs a bitwise XOR operation on the second encoded data of the differentially encoded current path and the second encoded data of the differentially encoded current path of all cycles before the current cycle for each path in the current cycle, and uses the result of the operation as the third encoded data of the current path in the current cycle.

[0036] If the current period is the first period of the entire testing process, then for each path in the current period, the second encoded data after differential encoding of the current path is used as the third encoded data of the current path in the current period.

[0037] In one embodiment, each of the said pathways includes multiple edges,

[0038] If the current period is not the first period of the entire test process, for each edge of each path in the current period, the flip signal of the current edge of the current path is XORed bit by bit with the flip signals of the current edge of the current path in all periods before the current period, and the result is used as the third encoded data of the current edge of the current path in the current period.

[0039] If the current cycle is the first cycle of the entire test process, then for each edge of each path in the current cycle, the flip signal of the current edge of the current path is used as the third encoded data of the current edge of the current path in the current cycle.

[0040] In one embodiment, the second encoding module performs delay control and serial XOR processing on the third encoded data of each path in each cycle to obtain the test waveform of the entire test process, including:

[0041] The second encoding module performs delay control on the third encoded data of each path in each cycle based on the delay information corresponding to the original test data of each path in each cycle, and obtains the third encoded data of each path in each cycle after delay control.

[0042] The third encoded data after delay control of each path in each cycle is XORed and serialized to obtain the test waveform of the entire test process.

[0043] In one embodiment, the second encoding module performs XOR serial processing on the third encoded data after delay control of each path in each cycle to obtain the test waveform of the entire test process, including:

[0044] The second encoding module, for each cycle of the entire test process, if the current cycle is not the first cycle of the entire test process, performs serial XOR processing on the third encoded data after delay control of N consecutive paths starting from the current path and moving backward, for each path of the current cycle, to obtain the test value of the current path of the current cycle.

[0045] If the current cycle is the first cycle of the entire test process, then for each path in the current cycle, the third encoded data after all delay control from the first path in the current cycle to the current path is serially XORed to obtain the test value of the current path in the current cycle.

[0046] The test values ​​of each path in each cycle are output serially to obtain the test waveform of the entire test process.

[0047] Secondly, this application also provides a digital board. Applied to integrated circuit testing equipment, the digital board includes: a first encoding module and a second encoding module, wherein...

[0048] The first encoding module is used to encode the received original test stream based on the waveform format information of the original test stream to obtain the first encoded data of each cycle, and send the first encoded data of each cycle to the second encoding module; each cycle includes N channels, where N is greater than or equal to 1;

[0049] The second encoding module is used to update the first encoded data of each path in each cycle based on the mask enable signal corresponding to each path, so as to obtain the second encoded data of each cycle; to perform differential encoding and cumulative inversion integral processing on the second encoded data of each path in each cycle, so as to obtain the third encoded data of each cycle; and to perform delay control and serial XOR processing on the third encoded data of each path in each cycle, so as to obtain the test waveform of the entire test process.

[0050] In one embodiment, the digital board further includes a graphics generation module, a cache module, and a timing control module;

[0051] The graphics generation module is connected to the cache module and is used to generate an original test stream based on user requirements and store the original test stream in the cache module.

[0052] The caching module, connected to the first encoding module and the timing control module, is used to periodically read the original test data in the original test stream in a first-in-first-out order, and send the original test data of each cycle to the first encoding module; the caching module is also used to send the configuration information of the original test stream to the timing control module; the configuration information includes the mask enable signal corresponding to each original test data and the delay information corresponding to each original test data;

[0053] The timing control module is also connected to the second encoding module, and is used to send the mask enable signal corresponding to the original test data in the received configuration information and the delay information corresponding to each original test data to the second encoding module.

[0054] The aforementioned method for generating test waveforms and a digital board utilizes a first encoding module on the digital board to encode the received original test stream based on its waveform format information, obtaining first-encoded data for each cycle. A second encoding module then updates the first-encoded data for each path in each cycle based on the mask enable signal corresponding to each path, obtaining second-encoded data for each cycle. Differential encoding and cumulative inversion integral processing are then performed on the second-encoded data for each path in each cycle to obtain third-encoded data for each cycle. Finally, delay control and serial XOR processing are applied to the third-encoded data for each path in each cycle to obtain the test waveform for the entire test process. The entire encoding process does not rely on a pre-generated large-scale lookup table; it is entirely completed automatically by logical operations, eliminating the need for manual enumeration and truth table filling, thus avoiding human error and ensuring the accuracy of waveform generation. This solves the problem of low accuracy caused by reliance on manual operation in existing test waveform generation methods.

[0055] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0056] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0057] Figure 1 A flowchart illustrating a method for generating test waveforms according to an embodiment of this application;

[0058] Figure 2 This is a first structural schematic diagram of a digital board card provided in an embodiment of this application;

[0059] Figure 3 This is a first structural schematic diagram of a second encoding module provided in an embodiment of this application;

[0060] Figure 4 A schematic diagram of the structure of the update unit of the second encoding module provided in an embodiment of this application;

[0061] Figure 5 This is a schematic diagram of the second structure of a second encoding module provided in an embodiment of this application;

[0062] Figure 6 A schematic diagram of the XOR gate structure of a differential coding unit provided in an embodiment of this application;

[0063] Figure 7 This is a schematic diagram of the XOR gate structure of the cumulative inverting integral unit provided in an embodiment of this application;

[0064] Figure 8 A schematic diagram of the third structure of the second encoding module provided in an embodiment of this application;

[0065] Figure 9 This is a second structural schematic diagram of a digital board provided in an embodiment of this application. Detailed Implementation

[0066] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0067] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0068] This embodiment provides a method for generating test waveforms, applied to a digital board of an integrated circuit testing equipment. The digital board includes a first encoding module and a second encoding module. Figure 1 This is a flowchart of the test waveform generation process in this embodiment, as shown below. Figure 1 As shown, the process includes the following steps:

[0069] Step S110: The first encoding module encodes the received original test stream based on the waveform format information of the original test stream to obtain the first encoded data of each cycle, and sends the first encoded data of each cycle to the second encoding module; each cycle includes N channels, where N is greater than or equal to 1.

[0070] The aforementioned original test stream can be a sequence of test vectors generated by the pattern generation module of the digital board. This test vector sequence can consist of multiple pattern data, each pattern data including N channels (i.e., pre-set test channels N WAY), where N is greater than or equal to 1. Each pattern data corresponds to the expected logic value of all channels in one test cycle (e.g., in the first cycle, channel 0 is drive 1, channel 1 is drive 0, and channel 2 is high impedance; in the second cycle, channel 0 is sampling, channel 1 is drive 1, and channel 2 is drive 1). Each expected logic value represents the expected logic state, not the actual voltage value. Each channel corresponds to one or more bits. The specific number of bits in each channel can be configured according to specific needs and application scenarios. This embodiment does not impose specific limitations here. Generally, the number of bits in each channel is less than or equal to the number of pins under test in the chip under test. Each channel can also include one or more edges. It should be noted that although the above Pattern data, while each path corresponds to a desired logic value, is essentially an abstract, unformatted test requirement, lacking timing details (such as edge position, pulse width, etc.). The raw test stream composed of Pattern data can serve as the raw input data for the entire test waveform generation process, characterizing the basic logic state of each path that the user wants to apply to the pins of the Device Under Test (DUT). Only after performing waveform format encoding, subsequent updates, differential encoding, cumulative inversion integration, delay control, and serial XOR processing on each path of the raw test stream can the accurate test waveform that meets the customer's requirements for the entire test process be obtained. The aforementioned first encoded data can be the encoded data used to characterize the timing and level state of the corresponding waveform after mapping and converting the desired logic values ​​of each path in each test cycle of the raw test stream according to the pre-configured waveform format encoding rules.

[0071] The waveform format information mentioned above can be user-defined and sent to the digital board via the underlying software. This information is used to determine the waveform format of the original test stream and to encode the logic values ​​of each path in the original test stream based on that waveform format. The waveform format can be one or more of a preset set of 16 waveforms. The 16 preset waveforms mentioned above can include NRZB (Non-Return-to-Zero Binary), DNRZ (Differential Non-Return-to-Zero), RZ (Return to Zero), RZZ (Return-to-Zero Zigzag), AMI (Alternate Mark Inversion), HDB3 (High Density Bipolar of Order 3), CMI (Coded Mark Inversion), MC (Manchester Code), DMC (Differential Manchester Code), Biphase-M (Biphase Mark Code), Biphase-S (Biphase Space Code), MC (Miller Code), PAM4 (4-Pulse Amplitude Modulation), and 2B1Q (2 Binary 1 Quaternary (double binary to quad level code), NRZ-L (Non-Return-to-Zero Level), and NRZ-M (Non-Return-to-Zero Mark). It should be noted that different waveform formats define different logic levels, whether the data returns to zero in the middle, whether the edges flip, the duty cycle, and the start or end level for the logic values ​​corresponding to each path of the pattern data. The specific waveform format information of the original test stream can be set according to specific test requirements; this embodiment does not impose specific limitations here.

[0072] Specifically, the first encoding module described above performs waveform format encoding on the received original test stream based on the waveform format information of the original test stream to obtain the first encoded data for each cycle. This can be achieved by the first encoding module periodically performing waveform format encoding on each Pattern data in the received original test stream based on the waveform format information of the original test stream, mapping the original logic 0 or 1 of each path in each cycle to first encoded data with waveform timing or level rules, thereby obtaining the first encoded data for each path in each cycle.

[0073] In one example, if one cycle corresponds to two paths, path 0 and path 1, the sequence of pattern data for the first two cycles of the original test stream is: 1, 0, 0, 1. That is, in the first cycle, the logic value of path 0 is 1, and the logic value of path 1 is 0; in the second cycle, the logic value of path 0 is 0, and the logic value of path 1 is 1. If the waveform format information of the original test stream indicates that the waveform of the original test stream is NRZB code (the characteristic of this waveform is that logic 1 represents the entire cycle (it should be noted that this cycle is the cycle corresponding to the current path, that is, the time window corresponding to the current path) remaining high), logic... If logic 0 indicates that the entire cycle remains low (without intermediate zeroing or transitions), then based on the waveform format information, the waveform format encoding is performed on each path of the Pattern data in the first two cycles of the received raw test stream. The logic value 1 of the path is converted to remain high, and the logic value 0 of the path is converted to remain low. Finally, the first encoded data corresponding to path 0 in the first cycle is a high-level encoded value, and the first encoded data corresponding to path 1 is a low-level encoded value. In the second cycle, the first encoded data corresponding to path 0 is a low-level encoded value, and the first encoded data corresponding to path 1 is a high-level encoded value.

[0074] Similarly, if one cycle corresponds to one path, path 0, the sequence of pattern data in the first two cycles of the original test stream is: 1, 0. That is, in the first cycle, the logic value of path 0 is 1, and in the second cycle, the logic value of path 0 is 0. If the waveform format information of the original test stream indicates that the waveform of the original test stream is NRZB code, then based on the waveform format information, waveform format encoding is performed on each path of the pattern data in the first two cycles of the received original test stream. Finally, the first encoded data corresponding to path 0 in the first cycle is a high-level encoded value, and the first encoded data corresponding to path 0 in the second cycle is a low-level encoded value.

[0075] Step S120: The second encoding module updates the first encoded data of each path in each cycle based on the mask enable signal corresponding to each path to obtain the second encoded data of each cycle; performs differential encoding and cumulative inversion integral processing on the second encoded data of each path in each cycle to obtain the third encoded data of each cycle; performs delay control and serial XOR processing on the third encoded data of each path in each cycle to obtain the test waveform of the entire test process.

[0076] Before updating the first encoded data of each path in each cycle in the second encoding module based on the mask enable signals corresponding to each path, it is necessary to determine the mask enable signals corresponding to each path in each cycle. This determination of the mask enable signals corresponding to each path in each cycle can be achieved by the second encoding module based on the mask enable signals corresponding to each path in each cycle of the original test data received from the timing control module. For example, the mask enable signal corresponding to the first path in the first cycle of the original test data received by the second encoding module is set to 1. Alternatively, the determination of the mask enable signals corresponding to each path can also be achieved by the first encoding module based on the mask information corresponding to each path in each cycle of the original test data received from the timing control module, determining the mask enable signals corresponding to each path in each cycle of the original test data, and sending these mask enable signals to the second encoding module. The mask enable signals corresponding to each of the aforementioned paths are used by the second encoding module to control the data updates of each path in each cycle based on the mask enable signals. Based on the different states of the mask enable signals, the module determines whether the current path in the current cycle should retain the data from the previous state (the previous path) or retain the data of the current path. The state information of the mask enable signals can be represented by 0 or 1. For example, if the mask enable signal is 0, it means the mask enable signal is invalid; if the mask enable signal is 1, it means the mask enable signal is valid.

[0077] Based on the mask enable signal corresponding to each path, the first encoded data of each path in each cycle is updated to obtain the second encoded data of each cycle. Taking one path per cycle as an example, if the entire test process is in single-path mode, only the mask enable signal corresponding to each path is used to update the first encoded data of each path in each cycle. Specifically, the second encoding module updates the first encoded data of each path in each cycle based on the mask enable signal corresponding to each path to obtain the second encoded data of each cycle. This can be done by the second encoding module for each path in each cycle of the entire test process. If the current path is not the first path of the current cycle, then the current path... When the corresponding mask enable signal is valid, the first coded data of the previous path is used as the second coded data of the current path. If the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid, the first coded data of the last path of the previous cycle is used as the second coded data of the current path. If the current path is the first path of the current cycle and the current cycle is the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid, 0 is used as the second coded data of the current path. If the mask enable signal corresponding to the current path is invalid, then the first coded data of the current path is used as the second coded data of the current path. This single-path mode allows for a single physical path (i.e., one test path) throughout the entire test process. There is no data multiplexing between paths, nor are there differences in direction or enable between different paths; data updates depend only on the mask enable signal.

[0078] Similarly, when the entire testing process is in multi-path mode, one cycle corresponds to multiple paths. The first encoded data of each path in each cycle can also be updated based on the mask enable signal corresponding to each path, which will not be elaborated here.

[0079] Steps S110 to S120 above involve the first encoding module of the digital board encoding the received original test stream based on its waveform format information to obtain first-encoded data for each cycle. Then, using the second encoding module, based on the mask enable signal corresponding to each path, the first-encoded data for each path in each cycle is updated to obtain second-encoded data for each cycle. Differential encoding and cumulative inversion integral processing are then performed on the second-encoded data for each path in each cycle to obtain third-encoded data for each cycle. Finally, delay control and serial XOR processing are applied to the third-encoded data for each path in each cycle to obtain the test waveform for the entire test process. This entire encoding process does not rely on a pre-generated large-scale lookup table; it is entirely completed automatically by logical operations, eliminating the need for manual enumeration and truth table filling, thus avoiding human error and ensuring the accuracy of waveform generation. This solves the problem of low accuracy caused by reliance on manual operation in existing test waveform generation methods.

[0080] In one embodiment, a digital board card for use in integrated circuit testing equipment is provided. Figure 2 This is a first structural schematic diagram of a digital board provided in an embodiment of this application, as shown below. Figure 2 As shown, the digital board 100 includes a first encoding module 110 and a second encoding module 120, wherein the first encoding module 110 is connected to the second encoding module 120. The first encoding module 110 encodes the received original test stream based on the waveform format information of the original test stream to obtain first encoded data for each cycle, and sends the first encoded data for each cycle to the second encoding module 120. Each cycle includes N channels, where N is greater than or equal to 1. The second encoding module 120 updates the first encoded data for each channel in each cycle based on the mask enable signal corresponding to each channel to obtain second encoded data for each cycle. Differential encoding and cumulative inversion integral processing are performed on the second encoded data for each channel in each cycle to obtain third encoded data for each cycle. Delay control and serial XOR processing are performed on the third encoded data for each channel in each cycle to obtain the test waveform of the entire test process.

[0081] In one embodiment, step S120 involves the second encoding module 120 updating the first encoded data of each path in each period based on the mask enable signal corresponding to each path, to obtain the second encoded data for each period, including:

[0082] In step S121, the second encoding module 120 updates the first encoded data of each path in each cycle based on the mask enable signal corresponding to each path and the preset path mask mode signal, so as to obtain the second encoded data of each cycle.

[0083] In the multi-path mode, with multiple paths corresponding to each cycle, the path selection of each path in each cycle is performed by a preset path mask mode signal to realize the multiplexing of multiple paths (for example, some paths are blocked in a specific cycle, or some paths are forced to inherit data from other paths).

[0084] The aforementioned preset path mask mode signal can be obtained based on user-preset configuration information or directly configured through the graphics generation module. The preset path mask mode signal is used to determine the current path's operating mode in the current cycle and whether the current path's mask is valid in the current cycle. According to the configuration information, if the path mask mode signal is 0, it indicates that the current path mask is invalid, and the path's operating mode is a valid path. If the path mask mode signal is 1, it indicates that the current path mask is valid, and the path's operating mode is an invalid path. For example, in a multi-path mode, if there are 8 paths in one cycle, including paths 1 to 8, according to the configuration information, the path mask mode signals for paths 1 to 4 are all 0, and the valid paths are paths 1, 2, 3, and 4. The remaining paths 5 to 8 need to be masked, so the path mask mode signals for paths 1 to 4 are all 0. The path mask mode signals for paths 5 to 8 are all 1, meaning the remaining paths 5 to 8 are invalid paths, and their corresponding path masks are valid. Paths 5 to 8 all need to be masked, and the data path mask mode signals of other paths must be forcibly inherited. Of course, for multi-path mode, if there are 8 channels in one cycle, including channels 1 to 8, and if the channel mask mode signal of channel 1 is 0 and the channel mask mode signals of channels 2 to 8 are all 1 according to the configuration information, then only one channel is effective and the remaining channels are all masked, which can achieve the single-channel conduction effect.

[0085] In this embodiment, a preset path mask mode signal and a path-specific mask enable signal are used together to determine whether the data of each path needs to be updated. Specifically, if the current path's mask enable signal is valid and / or the preset path mask mode signal indicates that the current path mask is valid, the first encoded data of the current path needs to be updated. If the current path is not the first path in the current cycle, the first encoded data of the previous path in the current cycle is used as the second encoded data of the current path. If the current path is the first path in the current cycle and the current cycle is not the first cycle of the entire test process, the first encoded data of the last path in the previous cycle is used as the second encoded data of the current path. If the current path is the first path in the current cycle and the current cycle is the first cycle of the entire test process, 0 is used as the second encoded data of the current path. Only when the current path's mask enable signal is invalid and the preset path mask mode signal indicates that the current path mask is invalid, is the first encoded data of the current path used as the second encoded data of the current path.

[0086] Figure 3 This is a first structural schematic diagram of the second encoding module 120 provided in an embodiment of this application, as shown below. Figure 3 As shown, the second encoding module 120 includes an update unit 121. The update unit 121 is connected to the first encoding module 110 and receives the first encoded data sent by the first encoding module 110. The update unit 121 updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path and the preset path mask mode signal to obtain the second encoded data of each path in each period, and outputs the second encoded data of each period.

[0087] Specifically, in one embodiment, in step S121, the second encoding module 120 updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path and the preset path mask mode signal, to obtain the second encoded data of each period, including:

[0088] In step S1212, the second encoding module 120, for each path in each cycle of the entire test process, if the current path is not the first path of the current cycle, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, the first encoded data of the previous path is used as the second encoded data of the current path; if the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, the first encoded data of the last path of the previous cycle is used as the second encoded data of the current path; if the current path is the first path of the current cycle and the current cycle is the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, 0 is used as the second encoded data of the current path.

[0089] Step S1214: If the mask enable signal corresponding to the current path is invalid and the preset path mask mode signal indicates that the current path mask is invalid, then the first encoded data of the current path is used as the second encoded data of the current path.

[0090] For example, a cycle has 3 channels (P0, P1, and P2). The first encoded data for the first two cycles are as follows: First cycle, P0=1, P1=0, P2=1; Second cycle, P0=1, P1=1, P2=0. The mask enable signal and channel mask mode signal are configured as follows: 1 indicates valid, 0 indicates invalid. The mask enable signals for each channel in the first two cycles are: 1 0 1 0 1 0. The preset channel mask mode signal indicates the mask validity of each channel in the first two cycles as: 1 1 1 0 0 0. The process of obtaining the second encoded data for the first two cycles can be shown in Table 1.

[0091] Table 1

[0092]

[0093] In steps S1212 to S1214 above, the second encoding module 120 updates the first encoded data of each path in each cycle by combining the mask enable signal and the path mask mode signal in a logical OR manner, thereby obtaining the second encoded data of each cycle.

[0094] In one embodiment, step S1212, using the first encoded data of the previous path as the second encoded data of the current path, includes the following steps:

[0095] Step S1: For each edge of the current path, if the current edge is the first edge of the current path, then the last edge data of the first encoded data of the previous path is determined as the edge data of the current edge of the second encoded data; if the current edge is not the first edge of the current path, then the edge data of the previous edge of the second encoded data is determined as the edge data of the current edge of the second encoded data.

[0096] Further, step S1212, using the first encoded data of the last path of the previous cycle as the second encoded data of the current path, includes the following steps:

[0097] Step S2: For each edge of the current path, if the current edge is the first edge of the current path, then the last edge data of the first encoded data of the last path of the previous cycle is determined as the edge data of the current edge of the second encoded data; if the current edge is not the first edge of the current path, then the edge data of the previous edge of the second encoded data is determined as the edge data of the current edge of the second encoded data.

[0098] Step S1212, using 0 as the second encoded data for the current path, includes the following steps:

[0099] Step S3: 0 is determined as the edge data of each edge of the second encoded data of the current path.

[0100] Step S1214, using the first encoded data of the current path as the second encoded data of the current path, includes the following steps:

[0101] Step S4: Determine the edge data of each edge of the first encoded data of the current path as the edge data of each edge of the second encoded data of the current path.

[0102] Figure 4 This is a schematic diagram of the structure of the update unit 121 of the second encoding module 120 provided in the embodiments of this application, as shown below. Figure 4 As shown, the update unit 121 includes multiple selectors, namely Mux[n], Mux[n-1], ..., Mux[0]. Each cycle includes N channels, and the first encoded data of each channel are data n, data n-1, ..., data 0, respectively. Each channel corresponds to a selector. The input of each selector is the first encoded data of its corresponding channel, the first encoded data of the previous channel (if there is no previous channel, the first encoded data of the previous channel is defaulted to 0), the mask enable signal corresponding to its corresponding channel, and the preset channel mask mode signal. The output of each selector is the second encoded data of its corresponding channel. Among them, A[n], A[n-1], ..., A[0] are the second encoded data of each channel.

[0103] In another embodiment, step S120, the second encoding module 120, performs differential encoding and cumulative inversion integral processing on the second encoded data of each path in each period to obtain the third encoded data of each period, including:

[0104] In step S122, the second encoding module 120 performs differential encoding on the second encoded data of each path in each period to obtain the differentially encoded second encoded data of each period.

[0105] The differential encoding described above can convert the second coded data in level form into a flip signal. This flip signal indicates whether the coded data of the current path has flipped relative to the coded data of the previous path. The purpose of converting the second coded data in level form into a flip signal is to prepare for subsequent cumulative flip integration.

[0106] The second encoding module 120 performs differential encoding on the second encoded data of each path in each period, and the calculation process for obtaining the differentially encoded second encoded data of each period is as follows:

[0107] The flip signal of the current path = the second encoded data of the current path XOR the reference level;

[0108] The aforementioned reference level can be the level value corresponding to the encoded data of the previous path. If the current path is the first path in the entire test process, i.e., the current path does not have a previous path, then the value 0 is used as the reference level of the current path. XOR stands for Exclusive OR, representing XOR logic. XOR logic can be implemented using XOR gates, or by combining AND, OR, and NOT gates, or by using XOR gate chips. To simplify the logic circuit, the XOR structure involved in the embodiments of this application is generally implemented using XOR gates. It should be noted that the XOR structure in the embodiments of this application can also be implemented in other ways based on requirements, and no specific limitation is made here.

[0109] Specifically, the second encoding module 120, for each path in each cycle of the entire test process, if the current path is not the first path of the current cycle, performs an XOR operation on the level value of the second encoded data of the current path and the level value of the second encoded data of the previous path to obtain the flip signal of the current path; if the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, performs an XOR operation on the level value of the second encoded data of the current path and the level value of the second encoded data of the last path of the previous cycle to obtain the flip signal of the current path; if the current path is the first path of the current cycle and the current cycle is the first cycle of the entire test process, performs an XOR operation on the level value of the second encoded data of the current path and zero to obtain the flip signal of the current path; the flip signals of each path in each cycle are used as the differentially encoded second encoded data of each path in each cycle to obtain the differentially encoded second encoded data of each cycle.

[0110] For example, there are four paths in each cycle. The current cycle is not the first cycle of the entire test process. The parallel data consisting of the second encoded data corresponding to the four paths is A[3:0]. The second encoded data corresponding to each path is represented from front to back as: A[3], A[2], A[1], A[0]. The parallel data consisting of the second encoded data after differential encoding in the current cycle is B[3:0]. The second encoded data after differential encoding corresponding to each path is represented from front to back as: B[3], B[2], B[1], B[0].

[0111] The calculation process for the second encoded data after differential encoding in the current period is as follows:

[0112] ;

[0113] ;

[0114] ;

[0115] ;

[0116] Among them, A -1 [0] is the level value of the second encoded data of the last path in the previous cycle of the current cycle.

[0117] Step S123: Perform cumulative inversion integral processing on the differentially encoded second encoded data of each path in each period to obtain the third encoded data of each period.

[0118] The above-described logic process for accumulating and inverting the integral of the differentially encoded second-coded data of each path in each cycle is as follows: If the current cycle is the first cycle of the entire test process, then for each path in the current cycle, the differentially encoded second-coded data of the current path is used as the third-coded data of the current path in the current cycle; for each cycle of the entire test process, if the current cycle is not the first cycle of the entire test process, then for each path in the current cycle, the differentially encoded second-coded data of the current path is XORed bit by bit with the differentially encoded second-coded data of the current path in all cycles before the current cycle, and the result is used as the third-coded data of the current path in the current cycle. The specific process is as follows:

[0119] If the current period is the first period of the entire testing process, the calculation process for the third encoded data of each path in the current period is as follows:

[0120] ;

[0121] Where n is the path label, C 1 [n] represents the third encoded data of the first periodic path with path number n, B 1 [n] represents the second encoded data after differential encoding of the path labeled n in the first period.

[0122] For example, the first cycle of the entire testing process has 4 pathways, labeled 3, 2, 1, and 0.

[0123] Therefore, the calculation process for the third encoded data of the four paths is as follows:

[0124] ;

[0125] ;

[0126] ;

[0127] ;

[0128] If the current period is not the first period of the entire test process, the calculation process for the third encoded data of each path in the current period (the t-th period of the entire test process) is as follows:

[0129] C t [n] = B t [n] XOR C t-1 [n];

[0130] Among them, C t [n] represents the third encoded data of the path with path number n in the t-th period, C-1 [n] represents the third encoded data of the path with path number n in the (t-1)th cycle, B t [n] represents the second encoded data after differential encoding of the path labeled n in the t-th period.

[0131] Because the third encoded data of the first cycle path labeled n is equal to the second encoded data after differential encoding of the current path, according to the recursive formula, we can obtain:

[0132] ;

[0133] Therefore, if the current cycle is not the first cycle of the entire testing process, the second encoded data after differential encoding of the current path is XORed bit by bit with the second encoded data after differential encoding of the current path in all cycles preceding the current cycle. The result is used as the third encoded data of the current path in the current cycle. In the logic circuit design, the third encoded data output in the current cycle is simply used as the input signal for the next cycle, and XORed with the second encoded data after differential encoding of the next cycle to obtain the third encoded data for the next cycle.

[0134] In this embodiment, the above-mentioned cumulative inversion integral is the inverse process of differential encoding. As long as the initial value (0) is known, the cumulative inversion integral can be performed on each channel from the first cycle, and the absolute level or the third encoded data in the format of the encoded value of each channel in each cycle can be recovered without loss. This provides data directly related to the test waveform amplitude for subsequent delay control and serial XOR, and the whole process is simple to implement in hardware.

[0135] In steps S122 to S123 above, the second encoding module 120 performs differential encoding on the second encoded data of each path in each cycle, converting the level signal into a flip signal. Then, when an output waveform is needed, only one XOR device (one flip-flop and one XOR gate) is needed to perform cumulative flip-integration processing on the differentially encoded second encoded data of each path in each cycle to obtain the third encoded data of each cycle in level form. By obtaining the third encoded data of each path in each cycle, it is convenient to perform delay control and serial XOR processing on the third encoded data of each path in each cycle to obtain the test waveform of the entire test process.

[0136] In one example, if the second encoded data for the four channels in the first period are 1 0 0 1, and the second encoded data for the four channels in the second period are 1 0 0 1, then the process of differentially encoding each second encoded data to obtain the differentially encoded second encoded data for each channel is as follows:

[0137] First cycle:

[0138] First path: 1 XOR 0 = 1;

[0139] The second path: 0 XOR 1 = 1;

[0140] The third path: 0 XOR 0 = 0;

[0141] The fourth path: 1 XOR 0 = 1;

[0142] Second cycle:

[0143] First path: 1 XOR 1 = 0;

[0144] The second path: 0 XOR 1 = 1;

[0145] The third path: 0 XOR 0 = 0;

[0146] The fourth path: 1 XOR 0 = 1;

[0147] The second encoded data obtained after differential encoding of each path in the first period is: 1 1 0 1; the second encoded data obtained after differential encoding of each path in the second period is: 0 1 0 1;

[0148] The process of performing cumulative inversion integral processing on the differentially encoded second-coded data of each path in each period to obtain the third-coded data of each period is as follows:

[0149] First cycle:

[0150] First pathway: 1;

[0151] Second pathway: 1;

[0152] The third pathway: 0;

[0153] The fourth pathway: 1;

[0154] Second cycle:

[0155] First path: 0 XOR 1 = 1;

[0156] The second path: 1 XOR 1 = 0;

[0157] The third path: 0 XOR 0 = 0;

[0158] The fourth path: 1 XOR 1 = 0.

[0159] Figure 5 This is a schematic diagram of the second structure of the second encoding module 120 provided in the embodiments of this application, as shown below. Figure 5 As shown, the second encoding module 120 further includes a differential encoding unit 122 and an accumulator-flipper unit 123. The differential encoding unit 122 is connected to the update unit 121 and the accumulator-flipper unit 123 respectively. It is used to receive the second encoded data of each path in each period, perform differential encoding on the second encoded data of each path in each period to obtain the differentially encoded second encoded data of each period, and send the differentially encoded second encoded data of each period to the accumulator-flipper unit 123. The accumulator-flipper unit 123 is used to perform accumulator-flipper integration on the differentially encoded second encoded data of each path in each period to obtain the third encoded data of each period.

[0160] The differential coding unit 122 described above may include multiple XOR gates, each XOR gate corresponding to one path, that is, each XOR gate corresponding to a selector of the update unit 121. Figure 6 This is a schematic diagram of the XOR gate structure of the differential coding unit 122 provided in the embodiments of this application, as shown below. Figure 6 As shown, each XOR gate corresponds to a path. The second encoded data output by the update unit 121 corresponding to the path is obtained as one of the inputs. The other input of the XOR gate is a reference level. Generally, the reference level is the second encoded data output by the update unit 121 corresponding to the previous path (if there is no previous path, the first encoded data of the previous path is defaulted to 0). The XOR gate outputs the second encoded data after differential encoding of the path.

[0161] The aforementioned cumulative flip integration unit 123 may include multiple XOR gates, each XOR gate corresponding to one path, that is, each XOR gate corresponds to the XOR gate of a differential coding unit 122. Figure 7 This is a schematic diagram of the XOR gate structure of the cumulative inversion integration unit 123 provided in the embodiments of this application, as shown below. Figure 7 As shown, each XOR gate corresponds to a path. The differentially encoded second coded data output by the differential coding unit 122 corresponding to that path is used as one input. The other input of the XOR gate is the third coded data output from the previous cycle. The XOR gate outputs the third coded data of that path. The output of the third coded data of that path is also used as the input for the next cycle to update the third coded data for the next cycle.

[0162] In one embodiment, step S122, the second encoding module 120, performs differential encoding on the second encoded data of each path in each period to obtain the differentially encoded second encoded data of each period, including:

[0163] Step S1222: The second encoding module performs an XOR operation on the level value of the second encoded data of the current channel and the reference level of the current channel for each channel in each cycle of the entire test process to obtain the flip signal of the current channel. Wherein, if the current channel is not the first channel of the current cycle, the level value of the second encoded data of the previous channel is used as the reference level of the current channel; if the current channel is the first channel of the current cycle and the current cycle is not the first cycle of the entire test process, the level value of the second encoded data of the last channel of the previous cycle is used as the reference level of the current channel; if the current channel is the first channel of the current cycle and the current cycle is the first cycle of the entire test process, zero is used as the reference level of the current channel.

[0164] Step S1224: The flip signal of each path in each cycle is used as the second encoded data after differential encoding of each path in each cycle, so as to obtain the second encoded data after differential encoding of each cycle.

[0165] Specifically, in one embodiment, step S1222, the second encoding module, for each path in each cycle of the entire test process, performs an XOR operation between the level value of the second encoded data of the current path and the reference level of the current path to obtain the flip signal of the current path, including:

[0166] Step S4, the second encoding module 120, for each path in each cycle of the entire test process, if the current path is not the first path of the current cycle, performs an XOR operation on the level value of the second encoded data of the current path and the level value of the second encoded data of the previous path to obtain the flip signal of the current path.

[0167] Step S5: If the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, then perform an XOR operation between the level value of the second encoded data of the current path and the level value of the second encoded data of the last path of the previous cycle to obtain the flip signal of the current path.

[0168] Step S6: If the current path is the first path of the current cycle and the current cycle is the first cycle of the entire test process, then the level value of the second encoded data of the current path is XORed with the zero value to obtain the flip signal of the current path.

[0169] For example, there are four paths in each cycle. The current cycle is the first cycle of the entire test process. The parallel data consisting of the second encoded data corresponding to the four paths is A[3:0]. The second encoded data corresponding to each path is represented from front to back as: A[3], A[2], A[1], A[0]. The parallel data consisting of the second encoded data after differential encoding in the current cycle is B[3:0]. The second encoded data after differential encoding corresponding to each path is represented from front to back as: B[3], B[2], B[1], B[0].

[0170] The calculation process for the second encoded data after differential encoding in the current period is as follows:

[0171] ;

[0172] ;

[0173] ;

[0174] ;

[0175] Step S7: The flip signals of each path in each cycle are used as the second encoded data after differential encoding of each path in each cycle, thus obtaining the second encoded data after differential encoding of each cycle.

[0176] Steps S4 to S7 above involve XORing the level values ​​of the second encoded data of each path in each cycle with the reference level to obtain the flip signal of each path in each cycle. Calculating the flip signal of each path in each cycle facilitates subsequent cumulative flip integration.

[0177] In one embodiment, each path includes multiple edges. In step S1222, the second encoding module, for each path in each cycle of the entire test process, performs an XOR operation between the level value of the second encoded data of the current path and the reference level of the current path to obtain the flip signal of the current path. The module further includes:

[0178] Step S8: For each edge of each path, XOR the level value of the current edge of the second encoded data with the reference level of the current edge to obtain the flip signal of the current edge; wherein, if the current edge is not the first edge of the current path, the level value of the previous edge of the second encoded data of the current path is used as the reference level of the current edge; if the current edge is the first edge of the current path, but the current path is not the first path of the current cycle, the level value of the last edge of the second encoded data of the previous path is used as the reference level of the current edge; if the current edge is the first edge of the current path, the current path is the first path of the current cycle, but the current cycle is not the first cycle of the entire test process, the level value of the last edge of the second encoded data of the last path of the previous cycle is used as the reference level of the current edge; if the current edge is the first edge of the current path, the current path is the first path of the current cycle, and the current cycle is the first cycle of the entire test process, then zero level is used as the reference level of the current edge;

[0179] Step S9: Determine the flip signal of each path based on the flip signal of each edge of each path.

[0180] Each of the aforementioned paths includes multiple edge data. The level value of the second coded data of the current path is XORed with the level value of the second coded data of the previous path to obtain the flip signal of the current path. Specifically, this includes the following steps:

[0181] For each edge of the current path, if the current edge is the first edge of the current path, the level value of the last edge of the second encoded data of the previous path is XORed with the level value of the first edge of the second encoded data of the current path to determine the first edge toggling signal of the current path; if the current edge is not the first edge of the current path, the level value of the previous edge of the second encoded data of the current path is XORed with the level value of the current edge to determine the current edge toggling signal of the current path.

[0182] The level value of the second coded data of the current path is XORed with the level value of the second coded data of the last path in the previous cycle to obtain the flip signal of the current path, including:

[0183] For each edge of the current path, if the current edge is the first edge of the current path, the level value of the last edge of the last path of the previous cycle is XORed with the level value of the first edge of the second encoded data of the current path to determine the first edge toggling signal of the current path; if the current edge is not the first edge of the current path, the level value of the previous edge of the second encoded data of the current path is XORed with the level value of the current edge to determine the current edge toggling signal of the current path.

[0184] If the current path is the first path in the current cycle and the current cycle is the first cycle of the entire test process, then the level value of the second encoded data of the current path is XORed with zero to obtain the flip signal of the current path, including:

[0185] For each edge of the current path, if the current edge is the first edge of the current path, the first edge level value of the second encoded data of the current path is XORed with 0 to determine the first edge toggling signal of the current path; if the current edge is not the first edge of the current path, the previous edge level value of the second encoded data of the current path is XORed with the current edge level value to determine the current edge toggling signal of the current path.

[0186] The edge-flipping signals within each path are combined to form the second encoded data after differential encoding of each path.

[0187] In one example, if the first period includes two paths, each path including a leading edge and a trailing edge, and the corresponding second-coded data are 1 1 0 1; and the second period also includes two paths, each path including a leading edge and a trailing edge, and the corresponding second-coded data are 1 1 0 1, then the process of differentially encoding each second-coded data to obtain the differentially encoded second-coded data for each path is as follows:

[0188] First cycle:

[0189] First path front: 1 XOR 0 = 1;

[0190] Trailing edge of the first path: 1 XOR 1 = 0;

[0191] Second path front: 0 XOR 1 = 1;

[0192] Second path trailing edge: 1 XOR 0 = 1;

[0193] Second cycle:

[0194] First path front: 1 XOR 1 = 0;

[0195] Second path trailing edge: 1 XOR 1 = 0;

[0196] The third path front: 0 XOR 1 = 1;

[0197] Fourth path trailing edge: 1 XOR 0 = 1;

[0198] The edge flip signals of each path in the first cycle are: 1 0 1 1; the edge flip signals of each path in the second cycle are: 0 0 11.

[0199] The process of accumulating and integrating the edge-flipping signals of each path in each cycle to obtain the third encoded data for each cycle is as follows:

[0200] First cycle:

[0201] First pathway frontier: 1;

[0202] Trailing edge of the first path: 0;

[0203] Second pathway frontier: 1;

[0204] Second path trailing edge: 1;

[0205] Second cycle:

[0206] First path front: 0 XOR 1 = 1;

[0207] Trailing edge of the first path: 0 XOR 0 = 0;

[0208] Second path front: 1 XOR 1 = 0;

[0209] Second path trailing edge: 1 XOR 1 = 0.

[0210] In another embodiment, step S123, the second encoding module 120, performs cumulative inversion integration processing on the differentially encoded second encoded data of each path in each period to obtain the third encoded data of each period, including:

[0211] Step S1232, the second encoding module 120, for each cycle of the entire test process, if the current cycle is not the first cycle of the entire test process, then for each path of the current cycle, performs a bitwise XOR operation on the second encoded data after differential encoding of the current path and the second encoded data after differential encoding of the current path in all cycles before the current cycle, and uses the result of the operation as the third encoded data of the current path in the current cycle.

[0212] Step S1234: If the current period is the first period of the entire testing process, then for each path in the current period, the second encoded data after differential encoding of the current path is used as the third encoded data of the current path in the current period.

[0213] In steps S1232 to S1234 above, the second encoding module 120 performs a bitwise XOR operation on the differentially encoded second encoded data of the current path with the differentially encoded second encoded data of the current path in all previous cycles for each cycle of the entire test process. The result is used as the third encoded data of the current path in the current cycle. If the current cycle is the first cycle of the entire test process, the differentially encoded second encoded data of the current path is used as the third encoded data of the current path in the current cycle for each path. This allows for independent XOR operations on the differential encoding result of the current cycle with the differential encoding results of all previous cycles for each path, thereby restoring the absolute level value of each path and facilitating subsequent delay control and serial XOR processing.

[0214] In one embodiment, each path includes multiple edges. The second encoding module performs cumulative inversion integration processing on the differentially encoded second encoded data of each path in each period to obtain the third encoded data of each period as follows:

[0215] If the current period is not the first period of the entire test process, for each edge in each path of the current period, the current edge flip signal of the current path is XORed with the current edge flip signals of the current path of all periods before the current period, and the result is used as the third encoded data of the current edge of the current path of the current period.

[0216] If the current period is the first period of the entire test process, then for each edge in each path of the current period, the current edge flip signal of the current path is used as the third encoded data of the current edge of the current path in the current period.

[0217] Further, in one embodiment, step S120, the second encoding module 120, performs delay control and serial XOR processing on the third encoded data of each path in each cycle to obtain the test waveform of the entire test process, including:

[0218] In step S124, the second encoding module 120 performs delay control on the third encoded data of each path in each cycle based on the delay information corresponding to the original test data of each path in each cycle, and obtains the third encoded data of each path in each cycle after delay control.

[0219] During the generation of the raw test stream by the graphics generation module, the raw test stream is also equipped with configuration information, including delay information corresponding to each raw test data, that is, delay information corresponding to the raw test data of each path in each cycle. The aforementioned delay information includes at least one of the following: rising edge delay, falling edge delay, high impedance delay, comparison window, etc. This embodiment uses the delay information corresponding to the raw test data of each path in each cycle to perform delay control on the third encoded data of each path in each cycle, thereby determining the specific time when the physical waveform transition of the third encoded data of each path occurs. The second encoding module 120 described above, based on the delay information corresponding to the original test data of each path in each cycle, performs delay control on the third encoded data of each path in each cycle, obtaining the third encoded data of each path after delay control in each cycle. This allows for comparison of the third encoded data of the current path in the current cycle with the third encoded data of the previous path to determine whether a transition type such as 0→1, 1→0, or 0→Hi-Z has occurred. Furthermore, based on the transition type and the delay information corresponding to that path, the delay value corresponding to the required transition position is obtained. Finally, the ideal edge position of the waveform of each path (path cycle start point + delay value) is obtained and appended to the third encoded data, resulting in the third encoded data of each path in each cycle after delay control. Therefore, the third encoded data after delay control is a collection of data structures containing information such as the path's level value, edge type, and delay offset. It should be noted that the third encoded data after delay control contains specific timing information and can be directly used to drive physical pins.

[0220] Of course, delay control is applied to the third encoded data of each path in each cycle to obtain the third encoded data of each path in each cycle after delay control. If each path includes multiple edges, then delay control is applied to the third encoded data corresponding to each edge of each path.

[0221] This embodiment uses independent delay information for each cycle and each path to convert the ideal level transition in the third encoded data into actual time offset, generating waveform description data with precise edge positions. This satisfies the timing requirements of the chip under test and compensates for hardware channel differences, laying the timing foundation for the final serial waveform output.

[0222] Step S125: Perform XOR serial processing on the third encoded data after delay control of each path in each cycle to obtain the test waveform of the entire test process.

[0223] The above-mentioned XOR serial processing of the third encoded data after delay control for each path in each cycle yields the test waveform of the entire test process. Specifically, for each cycle of the entire test process, if the current cycle is not the first cycle, then for each path in the current cycle, the third encoded data after delay control for the N consecutive paths starting from the current path is serially XORed to obtain the test value of the current path in the current cycle; if the current cycle is the first cycle of the entire test process, then for each path in the current cycle, the third encoded data after delay control for the entire path from the first path in the current cycle to the current path is serially XORed to obtain the test value of the current path in the current cycle. The test values ​​of each path in each cycle are then serially output to obtain the test waveform of the entire test process.

[0224] Specifically, each cycle contains N pathways. The third encoded data after delay control in the t-th (t≥1) cycle forms a sequence of length N: C t [N-1], C t [N-2], ..., C t [0] (each C) t [i] represents the level or waveform information of the path labeled i.

[0225] For each path in each cycle, if the current cycle is the first cycle of the entire test process, the calculation process for the output value of each path in the current cycle is as follows:

[0226] ;

[0227] Among them, Out 1 [k] represents the output value of the path labeled k.

[0228] If the current period is not the first period, the calculation process for the output values ​​of each channel in the t-th period is as follows:

[0229] Out t [k] = C t [k] XOR... XOR C t [N-1] XOR C t-1 [0] XOR ... XOR C t-1 [Nk-1];

[0230] In steps S124 to S125 above, the second encoding module 120 performs delay control on the third encoded data of each path in each cycle based on the delay information corresponding to the original test data of each path in each cycle, and obtains the third encoded data after delay control of each path in each cycle. Then, the third encoded data after delay control of each path in each cycle is XORed and serialized to obtain the test waveform of the entire test process. The final test waveform output with high timing accuracy, low storage overhead, flexible waveform generation and easy pipeline is achieved with extremely low hardware cost (a small number of registers and combinational logic).

[0231] Figure 8 This is a schematic diagram of the third structure of the second encoding module 120 provided in the embodiments of this application, as shown below. Figure 8 As shown, the second encoding module 120 further includes a delay unit 124 and a serial processing unit 125. The delay unit 124 is connected to the cumulative inversion integration unit 123 and the serial processing unit 125, respectively. It is used to perform delay control on the third encoded data of each path in each cycle based on the delay information corresponding to the original test data of each path in each cycle, to obtain the third encoded data after delay control of each path in each cycle, and send the third encoded data after delay control of each path to the serial processing unit 125. The serial processing unit 125 is used to perform XOR serial processing on the third encoded data after delay control of each path in each cycle to obtain the test waveform of the entire test process.

[0232] In one embodiment, step S125 involves the second encoding module 120 performing XOR serial processing on the third encoded data after delay control of each path in each cycle to obtain the test waveform of the entire test process, including:

[0233] Step S1252, the second encoding module 120, for each cycle of the entire test process, if the current cycle is not the first cycle of the entire test process, then for each path of the current cycle, the third encoded data after delay control of N consecutive paths starting from the current path is serially XORed to obtain the test value of the current path of the current cycle; where N is the number of paths included in the current cycle.

[0234] Step S1254: If the current cycle is the first cycle of the entire test process, then for each path in the current cycle, perform serial XOR processing on all the third encoded data after delay control from the first path in the current cycle to the current path to obtain the test value of the current path in the current cycle.

[0235] Step S1256: Serially output the test values ​​of each channel in each cycle to obtain the test waveform of the entire test process.

[0236] For example, each cycle has four paths, and the third encoded data after delay control in the first cycle is C. 1 [3], C 1 [2], C 1 [1], C 1 [0], the third encoded data after the delay control of the second cycle are C 2 [3], C 2 [2], C 2 [1], C 2 [0].

[0237] Therefore, the output value of the first path in the first cycle is:

[0238] ;

[0239] The output value of the second path in the first cycle is:

[0240] ;

[0241] The output value of the third path in the first cycle is:

[0242] ;

[0243] The output value of the fourth path in the first cycle is:

[0244] ;

[0245] The output value of the first path in the second cycle is:

[0246] ;

[0247] The output value of the second path in the second cycle is:

[0248] ;

[0249] The output value of the third path in the second cycle is:

[0250] ;

[0251] The output value of the fourth path in the second cycle is:

[0252] ;

[0253] Steps S1252 to S1256 above convert the delayed, multi-channel, third-encoded data into a serial binary waveform stream by using a sliding window XOR operation with a length of N (the number of channels in one cycle). This method achieves data compression and waveform diversification with simple hardware, and the final output can directly drive physical test pins to generate the entire test waveform.

[0254] Figure 9 This is a schematic diagram of the second structure of a digital board 100 provided in an embodiment of this application, as shown below. Figure 9 As shown, the digital board 100 also includes a graphics generation module 130, a cache module 140, and a timing control module 150. The graphics generation module 130, connected to the cache module 140, is used to generate an original test stream based on user requirements and store the original test stream in the cache module 140. The cache module 140, connected to the first encoding module and the timing control module 150, is used to periodically read the original test data in the original test stream in a first-in-first-out order and send the original test data of each cycle to the first encoding module 110. The cache module 140 is also used to send the configuration information of the original test stream to the timing control module 150. The configuration information includes the mask enable signal corresponding to each original test data and the delay information corresponding to each original test data. The timing control module 150 is also connected to the second encoding module 120 and is used to send the mask enable signal corresponding to the original test data and the delay information corresponding to each original test data in the received configuration information to the second encoding module 120. The above configuration information can be sent directly from the host computer, or it can be sent to the graphics generation module 130, or it can be configured and sent to the timing control module 150.

[0255] The original test data mentioned above can be pattern data.

[0256] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0257] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0258] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0259] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for generating test waveforms, applied to the digital board of an integrated circuit test equipment, characterized in that, The digital board includes a first encoding module and a second encoding module, and the method includes: The first encoding module encodes the received original test stream based on the waveform format information of the original test stream to obtain the first encoded data for each cycle, and sends the first encoded data for each cycle to the second encoding module; each cycle includes N channels, where N is greater than or equal to 1; The second encoding module updates the first encoded data of each path in each cycle based on the mask enable signal corresponding to each path to obtain the second encoded data of each cycle; performs differential encoding and cumulative inversion integral processing on the second encoded data of each path in each cycle to obtain the third encoded data of each cycle; and performs delay control and serial XOR processing on the third encoded data of each path in each cycle to obtain the test waveform of the entire test process.

2. The method for generating test waveforms according to claim 1, characterized in that, The second encoding module updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path, to obtain the second encoded data of each period, including: The second encoding module updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path and the preset path mask mode signal, so as to obtain the second encoded data of each period.

3. The method for generating test waveforms according to claim 2, characterized in that, The second encoding module updates the first encoded data of each path in each period based on the mask enable signal corresponding to each path and the preset path mask mode signal, to obtain the second encoded data of each period, including: The second encoding module, for each path in each cycle of the entire test process, if the current path is not the first path of the current cycle, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, the first encoded data of the previous path is used as the second encoded data of the current path; if the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, the first encoded data of the last path of the previous cycle is used as the second encoded data of the current path. If the current path is the first path in the current cycle and the current cycle is the first cycle of the entire test process, then when the mask enable signal corresponding to the current path is valid and / or the preset path mask mode signal indicates that the current path mask is valid, then 0 is used as the second encoded data of the current path. If the mask enable signal corresponding to the current path is invalid and the preset path mask mode signal indicates that the current path mask is invalid, then the first encoded data of the current path will be used as the second encoded data of the current path.

4. The method for generating test waveforms according to claim 3, wherein each of the paths includes multiple edges, characterized in that, The step of using the first encoded data of the previous path as the second encoded data of the current path includes: For each edge of the current path, if the current edge is the first edge of the current path, then the last edge data of the first encoded data of the previous path is determined as the edge data of the current edge of the second encoded data; if the current edge is not the first edge of the current path, then the edge data of the previous edge of the second encoded data is determined as the edge data of the current edge of the second encoded data. The step of using the first encoded data of the last path in the previous cycle as the second encoded data of the current path includes: For each edge of the current path, if the current edge is the first edge of the current path, then the last edge data of the first encoded data of the last path of the previous cycle is determined as the edge data of the current edge of the second encoded data; if the current edge is not the first edge of the current path, then the edge data of the previous edge of the second encoded data is determined as the edge data of the current edge of the second encoded data. The step of using 0 as the second encoded data of the current path includes: 0 is defined as the edge data of each edge of the second encoded data of the current path; The step of using the first encoded data of the current path as the second encoded data of the current path includes: The edge data of each edge of the first encoded data of the current path is determined as the edge data of each edge of the second encoded data of the current path.

5. The method for generating test waveforms according to claim 1, characterized in that, The second encoding module performs differential encoding and cumulative inversion integral processing on the second encoded data of each path in each period to obtain the third encoded data of each period, including: The second encoding module performs differential encoding on the second encoded data of each path in each period to obtain the differentially encoded second encoded data of each period. The second encoded data after differential encoding of each path in each period is subjected to cumulative inversion integral processing to obtain the third encoded data of each period.

6. The method for generating test waveforms according to claim 5, characterized in that, The second encoding module performs differential encoding on the second encoded data of each path in each period to obtain the differentially encoded second encoded data for each period, including: The second encoding module, for each path in each cycle of the entire test process, performs an XOR operation between the level value of the second encoded data of the current path and the reference level of the current path to obtain the flip signal of the current path; wherein, if the current path is not the first path of the current cycle, the level value of the second encoded data of the previous path is used as the reference level of the current path; if the current path is the first path of the current cycle and the current cycle is not the first cycle of the entire test process, the level value of the second encoded data of the last path of the previous cycle is used as the reference level of the current path; if the current path is the first path of the current cycle and the current cycle is the first cycle of the entire test process, zero is used as the reference level of the current path; The flip signals of each path in each cycle are used as the second encoded data after differential encoding of each path in each cycle, thus obtaining the second encoded data after differential encoding of each cycle.

7. The method for generating test waveforms according to claim 6, wherein each of the paths includes multiple edges, characterized in that, The step of performing an XOR operation between the level value of the second encoded data of the current path and the reference level of the current path to obtain the flip signal of the current path includes: For each edge of each path, the level value of the current edge of the second encoded data is XORed with the reference level of the current edge to obtain the toggle signal of the current edge. Specifically, if the current edge is not the first edge of the current path, the level value of the previous edge of the second encoded data of the current path is used as the reference level of the current edge. If the current edge is the first edge of the current path, but the current path is not the first path of the current cycle, the level value of the last edge of the second encoded data of the previous path is used as the reference level of the current edge. If the current edge is the first edge of the current path, the current path is the first path of the current cycle, but the current cycle is not the first cycle of the entire test process, the level value of the last edge of the second encoded data of the last path of the previous cycle is used as the reference level of the current edge. If the current edge is the first edge of the current path, the current path is the first path of the current cycle, and the current cycle is the first cycle of the entire test process, then zero level is used as the reference level of the current edge. The flip signal of each path is determined based on the flip signal of each edge of each path.

8. The method for generating test waveforms according to claim 5, characterized in that, The second encoding module performs cumulative inversion integral processing on the differentially encoded second encoded data of each path in each period to obtain the third encoded data of each period, including: The second encoding module, for each cycle of the entire test process, if the current cycle is not the first cycle of the entire test process, performs a bitwise XOR operation on the second encoded data of the differentially encoded current path and the second encoded data of the differentially encoded current path of all cycles before the current cycle for each path in the current cycle, and uses the result of the operation as the third encoded data of the current path in the current cycle. If the current period is the first period of the entire testing process, then for each path in the current period, the second encoded data after differential encoding of the current path is used as the third encoded data of the current path in the current period.

9. The method for generating test waveforms according to claim 8, wherein each of the paths includes multiple edges, characterized in that, If the current period is not the first period of the entire test process, for each edge of each path in the current period, the flip signal of the current edge of the current path is XORed bit by bit with the flip signals of the current edge of the current path in all periods before the current period, and the result is used as the third encoded data of the current edge of the current path in the current period. If the current cycle is the first cycle of the entire test process, then for each edge of each path in the current cycle, the flip signal of the current edge of the current path is used as the third encoded data of the current edge of the current path in the current cycle.

10. The method for generating test waveforms according to claim 1, characterized in that, The second encoding module performs delay control and serial XOR processing on the third encoded data of each path in each cycle to obtain the test waveform of the entire test process, including: The second encoding module performs delay control on the third encoded data of each path in each cycle based on the delay information corresponding to the original test data of each path in each cycle, and obtains the third encoded data of each path in each cycle after delay control. The third encoded data after delay control of each path in each cycle is XORed and serialized to obtain the test waveform of the entire test process.

11. The method for generating test waveforms according to claim 10, characterized in that, The second encoding module performs XOR serial processing on the third encoded data after delay control of each path in each cycle to obtain the test waveform of the entire test process, including: The second encoding module, for each cycle of the entire test process, if the current cycle is not the first cycle of the entire test process, performs serial XOR processing on the third encoded data after delay control of N consecutive paths starting from the current path and moving backward, for each path of the current cycle, to obtain the test value of the current path of the current cycle. If the current cycle is the first cycle of the entire test process, then for each path in the current cycle, the third encoded data after all delay control from the first path in the current cycle to the current path is serially XORed to obtain the test value of the current path in the current cycle. The test values ​​of each path in each cycle are output serially to obtain the test waveform of the entire test process.

12. A digital board, used in integrated circuit testing equipment, characterized in that, The digital board includes: a first encoding module and a second encoding module, wherein... The first encoding module is used to encode the received original test stream based on the waveform format information of the original test stream to obtain the first encoded data of each cycle, and send the first encoded data of each cycle to the second encoding module; each cycle includes N channels, where N is greater than or equal to 1; The second encoding module is used to update the first encoded data of each path in each cycle based on the mask enable signal corresponding to each path, so as to obtain the second encoded data of each cycle; to perform differential encoding and cumulative inversion integral processing on the second encoded data of each path in each cycle, so as to obtain the third encoded data of each cycle; and to perform delay control and serial XOR processing on the third encoded data of each path in each cycle, so as to obtain the test waveform of the entire test process.

13. The digital board according to claim 12, characterized in that, The digital board also includes a graphics generation module, a cache module, and a timing control module; The graphics generation module is connected to the cache module and is used to generate an original test stream based on user requirements and store the original test stream in the cache module. The caching module, connected to the first encoding module and the timing control module, periodically reads the raw test data from the raw test stream and sends the raw test data for each cycle to the first encoding module; the caching module is also used to send the configuration information of the raw test stream to the timing control module; the configuration information includes the mask enable signal corresponding to each raw test data and the delay information corresponding to each raw test data. The timing control module is also connected to the second encoding module, and is used to send the mask enable signal corresponding to the original test data in the received configuration information and the delay information corresponding to each original test data to the second encoding module.

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