A high linearity low noise amplifier based on improved derivative superposition technique

Abstract

The application discloses a high linearity low noise amplifier based on an improved derivative superposition technology and belongs to the technical field of radio frequency integrated circuit design. The high linearity low noise amplifier comprises a first-stage amplification circuit, a second-stage amplification circuit and a linearization auxiliary circuit. The first-stage amplification circuit performs low noise pre-amplification on a radio frequency input signal; the second-stage amplification circuit adopts a common source and common gate structure and provides main gain, a common source tube gate of the second-stage amplification circuit is connected to a first-stage output, and a common gate tube provides an output; the linearization auxiliary circuit comprises an auxiliary transistor, a gate of the auxiliary transistor is connected to a source of a second-stage common source tube through a fourth capacitor, a drain of the auxiliary transistor is connected to an internal node between a common source tube drain and a common gate tube source in the common source and common gate structure, the gate of the auxiliary transistor is independently biased and powered, and the source of the auxiliary transistor is suspended. According to the application, the sampling point of the auxiliary circuit is moved to the common source tube source, and the compensation current is injected into the internal node of the common source and common gate, and the independent biasing is matched, so that the linearity can be improved, and the influence on input matching and noise performance can be reduced.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit design technology, and specifically to a high linearity, low noise amplifier based on improved derivative superposition technology. Background Technology

[0002] As a key module in the RF receiver front-end, the noise figure of the low-noise amplifier directly affects the receiver sensitivity, while its linearity determines the receiver's anti-blocking capability in environments with strong interference. In advanced wireless communication systems, low-noise amplifiers often need to possess both low noise and high linearity characteristics, and there are often design trade-offs between the two.

[0003] To improve linearity, the industry has proposed derivative superposition technology, which involves connecting an auxiliary transistor biased in the weak inversion region in parallel with the main amplifier. The auxiliary transistor's third-order transconductance with opposite polarity is used to cancel the third-order nonlinear current of the main transistor. However, in conventional derivative superposition structures, the auxiliary transistor is usually directly connected in parallel to the gate input of the main amplifier. This connection method can have some adverse effects in high-frequency applications: the parasitic capacitance and noise current of the auxiliary transistor are directly applied to the input, easily causing the input matching characteristics to deviate from the predetermined design value and potentially worsening the overall noise figure; simultaneously, the interaction of second-order and third-order intermodulation products caused by parasitic effects at high frequencies can also limit the linearity improvement effect to some extent.

[0004] Therefore, a low-noise amplifier structure is needed to alleviate the mutual constraints between linearity improvement and noise and input matching. Summary of the Invention

[0005] The purpose of this invention is to provide a high linearity, low noise amplifier based on an improved derivative superposition technique. By moving the sampling point of the auxiliary circuit to the source of the common source transistor and injecting the compensation current into the internal node of the common source cascode transistor, combined with independent bias, the linearity can be improved while reducing the impact on input matching and noise performance.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A high-linearity, low-noise amplifier based on an improved derivative superposition technique includes: a first-stage amplifier circuit, a second-stage amplifier circuit, and a linearization auxiliary circuit, wherein the first-stage amplifier circuit is connected to the second-stage amplifier circuit, and the second-stage amplifier circuit is connected to the linearization auxiliary circuit. The first-stage amplifier circuit adopts a common-source amplifier structure to perform low-noise pre-amplification of the radio frequency input signal; The second-stage amplifier circuit adopts a common-source, common-gate structure, including a second transistor and a third transistor. The second transistor is a common-source transistor, and the third transistor is a common-gate transistor. The first-stage amplifier circuit connects the gate of the second transistor and the drain of the third transistor. The gate of the third transistor is connected to a third power supply component. The drain of the third transistor is connected to one end of a third capacitor. The other end of the third capacitor is the output terminal. The substrate of the third transistor is grounded. The source of the third transistor is connected to the drain of the second transistor. The source of the second transistor is grounded. The sources of the second transistor and the third transistor are connected to the linearization auxiliary circuit. The linearization auxiliary circuit includes an auxiliary transistor, the source of the third transistor is connected to the drain of the auxiliary transistor, the source of the second transistor is connected to one end of a fourth capacitor, a fourth power supply component and the fourth capacitor are connected to the gate of the auxiliary transistor, the substrate of the auxiliary transistor is grounded, and the source of the auxiliary transistor is left floating.

[0007] Furthermore, the first stage amplifier circuit is a first transistor, which is a common-source transistor. Its input terminal is connected to one end of a first capacitor, and the other end of the first capacitor is connected to a seventh inductor and a first inductor. The first inductor is connected to the positive terminal of a first DC power supply, and the seventh inductor is connected to the gate of the first transistor. The source of the first transistor is connected to a second inductor, which is grounded. The drain of the first transistor is connected to a second capacitor and a third inductor. The second capacitor is connected to the gate of the second transistor, and the third inductor is connected to a fifth inductor. The fifth inductor is connected to the drain of the third transistor.

[0008] Furthermore, the high linearity low noise amplifier also includes a second DC power supply, the positive terminal of which is connected to the drain of the third transistor via the fifth inductor.

[0009] Furthermore, the positive terminal of the first DC power supply is also connected to a fourth inductor, which is connected to the gate of the second transistor.

[0010] Furthermore, the third power supply component is a third DC power supply, the positive terminal of the third DC power supply is connected to a first resistor, the first resistor is connected to the gate of the third transistor and a fifth capacitor, and the fifth capacitor is grounded.

[0011] Furthermore, the fourth power supply component is a fourth DC power supply, and the positive terminal of the fourth DC power supply is connected to a sixth inductor, which is connected to the gate of the auxiliary transistor.

[0012] In summary, the present invention has at least one of the following beneficial technical effects: First, by setting the signal sampling point of the linearization auxiliary circuit at the source of the second-stage common-source transistor, rather than the traditional gate input, the low impedance characteristics of the source node can be utilized to reduce the interference of the auxiliary circuit on the input impedance characteristics and help suppress the injection of auxiliary transistor noise into the main signal path. This improves linearity while maintaining the amplifier's input matching performance and noise performance.

[0013] Second, by connecting the drain of the auxiliary transistor to the internal node between the second and third transistors in the cascode structure, the nonlinear compensation current is drawn in and canceled at the location where the distortion occurs, which helps to improve the compensation accuracy and reduce the possibility of additional distortion introduced by active devices in the compensation path.

[0014] Third, the auxiliary transistor uses an independent DC bias power supply, which can be flexibly adjusted to the subthreshold operating region to generate the required nonlinear transconductance. In addition, the bias current of the auxiliary transistor is low, which has a small impact on the increase in overall power consumption.

[0015] Fourth, the first-stage amplifier circuit adopts a common-source structure with a source-degraded inductor, which helps to optimize noise matching and impedance matching at the input end, providing a low-noise pre-amplified signal for the subsequent stage, thus making the linearization improvement of the second stage have less impact on the front-end performance. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the circuit structure of the present invention; Figure 2 This is a schematic diagram showing the simulation comparison results of the signal S-parameters; Figure 3 This is a schematic diagram showing the comparison results of the noise figure NF simulation. Figure 4 A schematic diagram of the simulation results of the third-order transconductance of the main amplifier and the auxiliary amplifier; Figure 5 This is a schematic diagram showing the simulation comparison results of the performance IIP3. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0018] like Figure 1As shown, the present invention provides a high linearity low noise amplifier based on an improved derivative superposition technique, comprising: a first-stage amplifier circuit, a second-stage amplifier circuit, and a linearization auxiliary circuit, wherein the first-stage amplifier circuit is connected to the second-stage amplifier circuit, and the second-stage amplifier circuit is connected to the linearization auxiliary circuit; The following is a detailed explanation of each circuit: The first-stage amplifier circuit employs a common-source amplifier structure for low-noise pre-amplification of the RF input signal. Specifically, the first-stage amplifier circuit is a first transistor M1, which is a common-source transistor. The RF input signal is input via an input terminal connected to one end of a first capacitor C1. The other end of the first capacitor C1 is simultaneously connected to the first end of a seventh inductor L7 and the first end of the first inductor L1. The second end of the first inductor L1 is connected to the positive terminal of a first DC power supply DC1. The second end of the seventh inductor L7 is connected to the gate of the first transistor M1. The source of the first transistor M1 is connected to the first end of a second inductor L2, and the second end of the second inductor L2 is grounded. The drain of the first transistor M1 is simultaneously connected to the first end of a second capacitor C2 and the first end of a third inductor L3. The second end of the second capacitor C2 is connected to the gate of the second transistor M2 in the subsequent second-stage amplifier circuit. The second end of the third inductor L3 is connected to the first end of a fifth inductor L5, and the second end of the fifth inductor L5 is connected to the drain of the third transistor M3.

[0019] The second-stage amplifier circuit adopts a common-source, common-gate structure, including a second transistor M2 and a third transistor M3. The second transistor M2 is a common-source transistor, and the third transistor M3 is a common-gate transistor. The first-stage amplifier circuit connects the gate of the second transistor M2 and the drain of the third transistor M3. Specifically, as described above, the first-stage amplifier circuit couples the pre-amplified signal to the gate of the second transistor M2 through the second capacitor C2; simultaneously, the third inductor L3 in the first-stage amplifier circuit is connected to the drain of the third transistor M3 via the fifth inductor L5 to provide power. The gate of the third transistor M3 is connected to a third power supply component. In this embodiment, the third power supply component is a third DC power supply DC3. The positive terminal of the third DC power supply DC3 is connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to both the gate of the third transistor M3 and the first terminal of the fifth capacitor C5. The second terminal of the fifth capacitor C5 is grounded. The drain of the third transistor M3 is also connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 serves as the output terminal of the entire amplifier, providing the final radio frequency signal. The substrate of the third transistor M3 is grounded. The source of the third transistor M3 is connected to the drain of the second transistor M2. The source of the second transistor M2 is grounded. It should be noted that the sources of both the second transistor M2 and the third transistor M3 are connected to the linearization auxiliary circuit.

[0020] The linearization auxiliary circuit includes an auxiliary transistor M4. The source of the third transistor M3 (i.e., the connection node between the drain of M2 and the source of M3) is connected to the drain of the auxiliary transistor M4. The source of the second transistor M2 is connected to the first terminal of the fourth capacitor C4. The fourth power supply component and the second terminal of the fourth capacitor C4 are connected to the gate of the auxiliary transistor M4. In this embodiment, the fourth power supply component is a fourth DC power supply DC4, the positive terminal of which is connected to the first terminal of the sixth inductor L6, and the second terminal of the sixth inductor L6 is connected to the gate of the auxiliary transistor M4. The substrate of the auxiliary transistor M4 is grounded. The source of the auxiliary transistor M4 is floating.

[0021] Regarding the bias power supply, the high-linearity low-noise amplifier also includes a second DC power supply DC2. The positive terminal of the second DC power supply DC2 is connected to the drain of the third transistor M3 through a fifth inductor L5. Simultaneously, the positive terminal of the first DC power supply DC1 is also connected to the first terminal of a fourth inductor L4, and the second terminal of the fourth inductor L4 is connected to the gate of the second transistor M2, thereby providing DC bias for the second transistor M2.

[0022] The working process and principle of the present invention will be explained below.

[0023] The RF input signal is transmitted to the gate of the first transistor M1 via the first capacitor C1 and the seventh inductor L7. The common-source amplifier stage, consisting of the first transistor M1 and the source second inductor L2, performs low-noise pre-amplification of the signal, while simultaneously optimizing input impedance matching and noise matching through the second inductor L2. The pre-amplified signal is output from the drain of the first transistor M1, and then transmitted to the gate of the second transistor M2 in the second-stage amplifier circuit via the interstage coupling second capacitor C2.

[0024] The second-stage amplifier circuit employs a common-source, common-gate (CSG) structure. The second transistor M2 acts as a common-source transistor, providing the main gain, while the third transistor M3 acts as a common-gate transistor, providing high output impedance and reverse isolation. The gate of the third transistor M3 is AC grounded through the fifth capacitor C5, and a stable DC bias is provided by the third DC power supply DC3 via the first resistor R1. The final amplified signal is taken from the drain of the third transistor M3, DC-blocked by the third capacitor C3, and then output.

[0025] Regarding linearization, the second transistor M2 has a parasitic inductance or a small degenerate inductance introduced by the design on its source-to-ground path during operation. When the RF signal current flows through this inductance, a weak voltage swing related to the signal is induced at the source of the second transistor M2. This voltage signal is coupled to the gate of the auxiliary transistor M4 via the fourth capacitor C4. The auxiliary transistor M4 is independently biased by the fourth DC power supply DC4 through the sixth inductor L6 and can be adjusted to operate in the subthreshold region, thereby generating a third-order transconductance that is inversely phase to the second transistor M2. The drain of the auxiliary transistor M4 is directly connected to the common-source cascode internal node between the source of the third transistor M3 and the drain of the second transistor M2 to inject nonlinear compensation current at this node. By appropriately adjusting the voltage value of the fourth DC power supply DC4, the third-order nonlinear current generated by the auxiliary transistor M4 can be made to have equal amplitude and opposite phase to the third-order nonlinear current generated by the second transistor M2 at this internal node, thereby canceling each other out, effectively suppressing third-order intermodulation distortion, and significantly improving the linearity of the amplifier.

[0026] In this invention, the source of the auxiliary transistor M4 is left floating, and its substrate is grounded. This design allows the auxiliary transistor M4 to provide the required third-order transconductance characteristics in a specific operating state. The first transistor M1, the second transistor M2, the third transistor M3, and the auxiliary transistor M4 can all be implemented using N-type MOS field-effect transistors.

[0027] In summary, this invention significantly improves the linearity performance of an amplifier by setting the sampling point of the linearization auxiliary circuit at the source of the second-stage common-source transistor and injecting compensation current into the internal nodes of the common-source and common-gate transistors, in conjunction with the independent subthreshold bias of the auxiliary transistors, while maintaining low noise and good input matching.

[0028] This invention employs a low-noise amplifier designed using the TSMC65 process. By utilizing derivative superposition technology, an auxiliary transistor is added at the common-source transistor of the second stage to cancel the third-order transconductance of the main transistors (referring to the first transistor M1, the second transistor M2, and the third transistor M3), thereby enabling the low-noise amplifier to achieve better linearity performance.

[0029] Next Figures 2 to 5 Please provide a detailed explanation.

[0030] Figure 2 This is a schematic diagram showing the comparison results of the signal S-parameter simulation, as shown below. Figure 2 As shown, Figure 2Simulation curves of the input reflection coefficient S11 (DS), forward transmission gain S21 (DS), and output reflection coefficient S22 (DS) of the circuit of the present invention in the 20GHz to 27GHz frequency band are shown, as well as simulation curves of the input reflection coefficient S11, forward transmission gain S21, and output reflection coefficient S22 of the conventional structure circuit without linearization auxiliary circuit in the 20GHz to 27GHz frequency band. The simulation curves of the circuit of the present invention and the conventional structure circuit are compared.

[0031] Within a wide frequency band of 20 GHz to 27 GHz, the forward transmission gain S21 (DS) of the circuit of this invention remains between 14 dB and 17 dB, almost perfectly overlapping with the curve of the forward transmission gain S21 of the conventional circuit structure, with only minimal fluctuations. This indicates that the addition of the auxiliary transistor M4 did not impair the core gain performance of the circuit. Throughout the target frequency band, the input reflection coefficient S11 (DS) of both the circuit of this invention and the conventional circuit structure is below -13 dB, demonstrating excellent input impedance matching. More importantly, the two curves are highly consistent across the entire frequency band, strongly proving that moving the signal sampling point from the conventional input gate to the source of the second-stage common-source transistor M2 successfully avoids the loading effect of the auxiliary transistor's parasitic capacitance on the input, thus perfectly maintaining the amplifier's front-end input matching characteristics. The output reflection coefficient S22 (DS) of the circuit of this invention exhibits a deep matching notch (below -20 dB) near 23.5 GHz to 24.5 GHz, meeting the high-efficiency power transfer requirements of the RF front-end.

[0032] Figure 3 This is a schematic diagram showing the comparison results of the noise figure NF simulation, as shown below. Figure 3 As shown, Figure 3 Simulated noise figure (NF) comparison curves of the amplifier in the 19GHz to 28GHz frequency band are shown. Within the central operating frequency band of 21GHz to 24GHz, the noise figure of the circuit of this invention is controlled at an extremely low level of 2.82dB to 2.85dB. By comparing the solid line NF(DS) representing the structure of this invention with the dashed line NF representing the conventional structure, it can be found that the overall noise figure degradation is extremely small (less than 0.02dB) after introducing the improved derivative superposition auxiliary circuit. This result shows that by injecting the streamer of the auxiliary transistor M4 into the internal node of the cascode and implementing independent subthreshold bias, the injection of noise current from the auxiliary transistor itself into the main signal path can be effectively suppressed, breaking the constraint in traditional derivative superposition technology that "linearity improvement must come at the cost of noise figure degradation."

[0033] Figure 4 A schematic diagram of the simulation results of the third-order transconductance of the main amplifier and the auxiliary amplifier, as shown below. Figure 4 As shown, Figure 4The curves showing the third-order transconductance (g3) of the main amplification path transistor and the linearization auxiliary transistor as a function of the gate-source voltage (Vgs) are presented to illustrate the nonlinearity cancellation mechanism of this invention. The nonlinear distortion of the transistor (especially the third-order intermodulation distortion IMD3) is mainly determined by its third-order transconductance g3. Figure 4 As shown by solid line g3 (main), when the first DC power supply DC1 sets the bias voltage of the main transistor to 0.6V, the third transconductance g3 of the main transistor near the operating point is positive (approximately +0.3A / V3). At this time, by adjusting the fourth DC power supply DC4, the auxiliary transistor M4 is independently biased in the subthreshold region (weak inversion region). Figure 4 As shown by the dashed line g3 (auxiliary), the auxiliary transistor M4 generates a negative third-order transconductance (approximately -0.2A / V3) with a similar peak value but opposite sign within the corresponding voltage swing region. When the RF voltage swing at the source of the second-stage common-source transistor M2 is coupled to the gate of M4 through the fourth capacitor C4, M4 injects a compensation current at the internal node of the common-source cascode (between the drain of M2 and the source of M3). Since the signs of g3 of the two transistors are opposite and their amplitudes are similar, the third-order nonlinear currents of the two transistors are vector-superimposed and cancel each other out at the internal node (i.e., the sum of g3 of the main path and g3 of the auxiliary transistor is approximately equal to 0), thereby suppressing the generation of third-order intermodulation products at the source.

[0034] Figure 5 This is a schematic diagram showing the comparison results of the IIP3 simulation. Figure 5 As shown, Figure 5 Simulation results comparing the input third-order cutoff point (IIP3) of the circuit of this invention with that of a conventional circuit in the 22GHz to 25GHz frequency band are presented. This is a core indicator for evaluating the high linearity and anti-interference capability of an amplifier. The conventional low-noise amplifier without an auxiliary transistor (the curve marked with a dotted line in the figure) exhibits a poor IIP3 across the entire frequency band, averaging only around -5dBm. The low-noise amplifier using the improved derivative superposition technique of this invention (the curve marked with a square in the figure, IIP3(DS)) shows a significant improvement in IIP3 to +6.5dBm to +8.5dBm in the 22GHz to 25GHz frequency band. Experimental data show that the IIP3 of the circuit of this invention is improved by approximately 11.5dB to 13.5dB compared to the conventional structure. Simultaneously, because the auxiliary transistor M4 operates in the subthreshold region, its DC bias current is only at the microamplitude (µA) level, and its increase in overall circuit power consumption is almost negligible. This significant leap in linearity directly confirms the efficiency and practicality of the linearization improvement scheme of this invention.

[0035] like Figure 4As shown, at DC1=0.6V, the third-order transconductance g3 of the main and auxiliary transistors essentially cancels each other out. However, the auxiliary transistor and the main transistor cannot share the same bias. After determining the bias voltage of the main transistor, an auxiliary transistor of suitable size and bias voltage is selected based on its simulated third-order transconductance to cancel the third-order transconductance of the main transistor. This bias voltage is generally in the subthreshold region, and the bias current is only in the μA range, so it will not significantly increase the overall power consumption of the circuit. A high linearity performance of IIP3=5dBm was achieved at a supply voltage of 1.8V. Figure 5 As shown, this represents an improvement of approximately 10 dBm compared to IIP3 without the auxiliary transistor. Figure 2 and Figure 3 As shown, the impact on S-parameters and NF is relatively small.

[0036] Embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0037] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0038] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0039] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0040] Contents not described in detail in this specification are prior art known to those skilled in the art. It is hereby indicated that the above description is intended to help those skilled in the art understand this invention, but does not limit the scope of protection of this invention. Any equivalent substitutions, modifications, improvements, or simplifications of the above descriptions that do not depart from the essential content of this invention fall within the scope of protection of this invention.

Claims

1. A high-linearity, low-noise amplifier based on an improved derivative superposition technique, characterized in that, include: The system comprises a first-stage amplifier circuit, a second-stage amplifier circuit, and a linearization auxiliary circuit, wherein the first-stage amplifier circuit is connected to the second-stage amplifier circuit, and the second-stage amplifier circuit is connected to the linearization auxiliary circuit. The first-stage amplifier circuit adopts a common-source amplifier structure to perform low-noise pre-amplification of the radio frequency input signal; The second-stage amplifier circuit adopts a common-source, common-gate structure, including a second transistor and a third transistor. The second transistor is a common-source transistor, and the third transistor is a common-gate transistor. The first-stage amplifier circuit connects the gate of the second transistor and the drain of the third transistor. The gate of the third transistor is connected to a third power supply component. The drain of the third transistor is connected to one end of a third capacitor. The other end of the third capacitor is the output terminal. The substrate of the third transistor is grounded. The source of the third transistor is connected to the drain of the second transistor. The source of the second transistor is grounded. The sources of the second transistor and the third transistor are connected to the linearization auxiliary circuit. The linearization auxiliary circuit includes an auxiliary transistor, the source of the third transistor is connected to the drain of the auxiliary transistor, the source of the second transistor is connected to one end of a fourth capacitor, a fourth power supply component and the fourth capacitor are connected to the gate of the auxiliary transistor, the substrate of the auxiliary transistor is grounded, and the source of the auxiliary transistor is left floating.

2. The high linearity, low noise amplifier based on improved derivative superposition technology according to claim 1, characterized in that, The first stage amplifier circuit is a first transistor, which is a common-source transistor. Its input terminal is connected to one end of a first capacitor, and the other end of the first capacitor is connected to a seventh inductor and a first inductor. The first inductor is connected to the positive terminal of a first DC power supply, and the seventh inductor is connected to the gate of the first transistor. The source of the first transistor is connected to a second inductor, which is grounded. The drain of the first transistor is connected to a second capacitor and a third inductor. The second capacitor is connected to the gate of the second transistor. The third inductor is connected to a fifth inductor, and the fifth inductor is connected to the drain of the third transistor.

3. A high-linearity, low-noise amplifier based on improved derivative superposition technology according to claim 2, characterized in that, The high linearity low noise amplifier also includes a second DC power supply, the positive terminal of which is connected to the drain of the third transistor via the fifth inductor.

4. A high-linearity, low-noise amplifier based on improved derivative superposition technology according to claim 2, characterized in that, The positive terminal of the first DC power supply is also connected to a fourth inductor, which is connected to the gate of the second transistor.

5. A high-linearity, low-noise amplifier based on improved derivative superposition technology according to claim 1, characterized in that, The third power supply component is a third DC power supply. The positive terminal of the third DC power supply is connected to a first resistor. The first resistor is connected to the gate of the third transistor and a fifth capacitor. The fifth capacitor is grounded.

6. A high-linearity, low-noise amplifier based on improved derivative superposition technology according to claim 1, characterized in that, The fourth power supply component is a fourth DC power supply, and the positive terminal of the fourth DC power supply is connected to a sixth inductor, which is connected to the gate of the auxiliary transistor.

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