A clock taming method and apparatus

Abstract

This invention provides a clock discipline method and apparatus, relating to the field of time synchronization technology. The method first calculates the original time difference sequence, then filters it, then calculates the frequency increment based on the filtered time difference sequence, and finally performs calibration based on the frequency increment. This ensures that the frequency deviation information on which calibration depends is no longer affected by the random jitter of the BeiDou clock second pulse signal, thereby suppressing frequent oscillations in the calibration command. At the same time, because the time difference sequence on which calibration is based has become smooth and stable, the calibration process converges faster, avoiding phase disturbances introduced by repeated trial and error. Thus, without sacrificing the inherent short-term stability of the local crystal oscillator, it achieves continuous and stable correction of its long-term frequency drift, taking into account both the short-term stability and long-term frequency accuracy of the output clock.

Description

Technical Field

[0001] This invention relates to the field of time synchronization technology, and in particular to a clock discipline method and apparatus. Background Technology

[0002] In existing BeiDou clock discipline technologies, satellite signals are affected by various factors such as atmospheric delay, multipath effects, satellite ephemeris errors, and electromagnetic interference. This results in significant random jitter and short-term instability in the second pulse signal (i.e., the 1PPS signal). While local crystal oscillators offer excellent short-term stability, they suffer from aging drift and frequency drift, leading to poor long-term stability. Therefore, directly calibrating the frequency based on the time difference between BeiDou 1PPS and the local 1PPS results in frequent oscillations in the calibration command, slow convergence, and the introduction of additional phase noise, making it difficult to simultaneously achieve both short-term stability and long-term frequency accuracy. Summary of the Invention

[0003] The purpose of this invention is to provide a clock discipline method and apparatus to alleviate the technical problem in the prior art that it is difficult to simultaneously ensure the short-term stability of the local crystal oscillator and the long-term frequency accuracy of the BeiDou clock.

[0004] In a first aspect, the present invention provides a clock discipline method, comprising: calculating the rising edge time difference between the first-second pulse signal of a BeiDou clock and the second-second pulse signal of a clock to be disciplined, to obtain an original time difference sequence; filtering the original time difference sequence to obtain a smoothed time difference sequence; calculating the frequency increment sequence of the clock to be disciplined based on the smoothed time difference sequence; and continuously calibrating the oscillation frequency of the clock to be disciplined based on the frequency increment sequence to obtain a disciplined second pulse signal.

[0005] In an optional implementation, the time difference between the rising edges of the first-second pulse signal of the BeiDou clock and the second-second pulse signal of the clock to be disciplined is calculated to obtain the original time difference sequence. This includes: connecting the first-second pulse signal and the second-second pulse signal to the start input of the carry chain inside the CPLD, respectively; synchronously starting the delay propagation of the two carry chains under the trigger of a preset high-frequency clock; sampling the level state of each carry chain tap in parallel during each sampling period to determine the position index of the rising edge of the first-second pulse signal and the rising edge of the second-second pulse signal on their respective delay chains; and calculating the original time difference sequence between the first-second pulse signal and the second-second pulse signal based on the position index, the clock period of the preset high-frequency clock, and the pre-calibrated mapping relationship between the position index and the delay.

[0006] In an optional implementation, the original time difference sequence is filtered to obtain a smoothed time difference sequence, including: initializing the initial time difference and initial covariance between the first-second pulse signal and the second-second pulse signal; iteratively calculating the correction coefficients corresponding to each time difference in the time difference sequence based on the initial covariance to obtain a correction coefficient sequence; and correcting each time difference in the original time difference sequence based on the correction coefficient sequence and the initial time difference to obtain a smoothed time difference sequence.

[0007] In an optional implementation, if the second-second pulse signal is a signal generated by a voltage-controlled crystal oscillator, then based on the smoothed time difference sequence, the frequency increment sequence of the clock to be disciplined is calculated, including: segmenting the smoothed time difference sequence according to a preset adjustment period, and calculating the average time difference within each segment to obtain an average time difference sequence; based on the average time difference sequence, calculating the time change between adjacent average time differences; using an incremental PID algorithm to process the time change corresponding to the most recent three adjustment periods to obtain the control voltage increment corresponding to the current adjustment period; and based on the control voltage increment corresponding to each adjustment period, determining the frequency increment sequence of the clock to be disciplined.

[0008] In an optional implementation, the preset adjustment period includes: a first adjustment period and a second adjustment period; the first adjustment period is less than the second adjustment period; when the time change is greater than or equal to a first threshold, the preset adjustment period adopts the first adjustment period; when the time change is less than the first threshold, the preset adjustment period adopts the second adjustment period.

[0009] In an optional implementation, after obtaining the tamed second pulse signal, the method further includes: acquiring each frequency increment and corresponding adjustment time in the frequency increment sequence within a preset historical time period before the current moment; and fitting a functional relationship between the frequency increment and time based on each frequency increment and corresponding adjustment time.

[0010] In an optional implementation, after obtaining the tamed second pulse signal, the method further includes: if it is determined that the first second pulse signal is lost, substituting the current time into the functional relationship between frequency increment and time to obtain the estimated frequency increment corresponding to the current moment; and compensating the current oscillation frequency of the clock to be tamed based on the estimated frequency increment to obtain the frequency-compensated second pulse signal.

[0011] Secondly, the present invention provides a clock discipline device, comprising: a first calculation module for calculating the rising edge time difference between the first-second pulse signal of a BeiDou clock and the second-second pulse signal of a clock to be disciplined, to obtain an original time difference sequence; a filtering module for filtering the original time difference sequence to obtain a smoothed time difference sequence; a second calculation module for calculating the frequency increment sequence of the clock to be disciplined based on the smoothed time difference sequence; and a calibration module for continuously calibrating the oscillation frequency of the clock to be disciplined based on the frequency increment sequence to obtain a disciplined second pulse signal.

[0012] Thirdly, the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the computer program to implement the clock discipline method described in any of the foregoing embodiments.

[0013] Fourthly, the present invention provides a computer-readable storage medium storing computer instructions that, when executed by a processor, implement the clock discipline method described in any of the foregoing embodiments.

[0014] This invention first calculates the original time difference sequence, then filters it, then calculates the frequency increment based on the filtered time difference sequence, and finally performs calibration based on the frequency increment. This ensures that the frequency deviation information on which calibration depends is no longer affected by the random jitter of the BeiDou clock second pulse signal, thereby suppressing frequent oscillations in the calibration command. At the same time, because the time difference sequence on which calibration is based has become smooth and stable, the calibration process converges faster, avoiding phase disturbances introduced by repeated trial and error. Thus, without sacrificing the inherent short-term stability of the local crystal oscillator, it achieves continuous and stable correction of its long-term frequency drift, taking into account both the short-term stability and long-term frequency accuracy of the output clock. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 A flowchart of a clock discipline method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a carry chain tap timing provided in an embodiment of the present invention; Figure 3 A schematic diagram of a time difference measurement principle provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the time difference sequence before and after filtering provided in an embodiment of the present invention; Figure 5 A flowchart of another clock discipline method provided in an embodiment of the present invention; Figure 6 A schematic diagram of BeiDou second pulse jitter provided in an embodiment of the present invention; Figure 7 A schematic diagram of the aging process of a free crystal oscillator provided in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the clock frequency change after clock discipline is performed using the method provided in this embodiment of the invention. Figure 9 A functional block diagram of a clock discipline device provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0018] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0019] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0020] Example 1 Figure 1 A flowchart of a clock discipline method provided in an embodiment of the present invention is shown below. Figure 1 As shown, the method specifically includes the following steps: Step S102: Calculate the rising edge time difference between the first second pulse signal of the Beidou clock and the second second pulse signal of the clock to be tamed to obtain the original time difference sequence.

[0021] In this embodiment of the invention, the first-second pulse signal of the BeiDou clock, i.e., the second pulse signal output by the BeiDou satellite navigation system, is an ideal long-term time reference source due to its wide coverage, high timing accuracy, and long-term stability reaching the nanosecond level. Therefore, this embodiment uses it as an external reference clock. The second-second pulse signal of the clock to be tamed is the second pulse signal generated by the local oscillator (such as a voltage-controlled crystal oscillator) after frequency division. The time difference between the rising edges of the first-second pulse signal and the second-second pulse signal essentially reflects the instantaneous phase shift of the local clock relative to the BeiDou standard time. By constructing a time measurement path with high resolution at the hardware level, the relative positions of the two pulse edges within each sampling period are digitally captured, thereby forming the original time difference sequence that evolves over time.

[0022] Step S104: Filter the original time difference sequence to obtain a smoothed time difference sequence.

[0023] Because the first-second pulse signal is subject to various interferences during transmission (such as channel disturbances, multipath effects, and receiver internal noise), it exhibits jitter. This results in random jitter and anomalous jumps in the original time difference sequence, which, if directly used for frequency control, will lead to feedback oscillations or miscalibration. Therefore, this embodiment of the invention requires filtering the original time difference sequence to effectively suppress jitter while preserving the true evolution trend of the time difference. Optionally, the filtering process does not rely on fixed-window averaging or simple low-pass filtering. Instead, it is based on modeling the dynamic characteristics of time difference changes. By fusing system model predictions and real-time observation data, it outputs a smooth time difference sequence with higher confidence and better statistical consistency, providing a stable and robust state input for subsequent frequency estimation.

[0024] Step S106: Calculate the frequency increment sequence of the clock to be tamed based on the smoothed time difference sequence.

[0025] Specifically, the rate of change of time reflected in the time difference sequence essentially characterizes the instantaneous frequency deviation between the local clock frequency and the BeiDou standard frequency. Therefore, by calculating the rate of change of time difference on the smoothed time difference sequence, the serialized increment information reflecting the dynamic characteristics of frequency offset can be determined. This step is not simply a two-point difference operation, but rather combines time scale characteristics to extract physically meaningful frequency changes at a reasonable time granularity, so that the obtained frequency increment sequence can balance clock adjustment speed and clock stability. This sequence is the quantitative basis for frequency correction commands in the disciplined closed loop and serves as an intermediate variable connecting time difference measurement and frequency control.

[0026] Step S108: The oscillation frequency of the clock to be tamed is continuously calibrated based on the frequency increment sequence to obtain the tamed second pulse signal.

[0027] Based on the frequency adjustment direction and amplitude indicated by the frequency increment sequence, an adjustment quantity adapted to the physical characteristics of the oscillator to be tamed (used to generate the clock to be tamed) can be generated and converted into a controllable physical excitation (such as voltage-controlled voltage, digital tuning word, or temperature compensation parameter) to dynamically adjust the oscillator's output frequency. This calibration process is continuous and adaptive: on the one hand, it is not a one-time correction, but rather a periodic update of the control quantity according to a predetermined rhythm to cope with slowly changing factors such as crystal aging and temperature drift; on the other hand, its adjustment intensity and response speed can be strategically adjusted according to the current system state (such as the magnitude of frequency deviation and the degree of convergence) to ensure rapid approach to the target during the locking phase and low-disturbance operation during the steady-state phase. When multiple consecutive frequency increments are less than a preset frequency threshold, the clock taming stable state is determined to have been reached. The final output second pulse signal is a high-performance time source optimized for the short-term characteristics of the local oscillator under the constraints of the BeiDou long-term reference.

[0028] This invention first calculates the original time difference sequence, then filters it, then calculates the frequency increment based on the filtered time difference sequence, and finally performs calibration based on the frequency increment. This ensures that the frequency deviation information on which calibration depends is no longer affected by the random jitter of the BeiDou clock second pulse signal, thereby suppressing frequent oscillations in the calibration command. At the same time, because the time difference sequence on which calibration is based has become smooth and stable, the calibration process converges faster, avoiding phase disturbances introduced by repeated trial and error. Thus, without sacrificing the inherent short-term stability of the local crystal oscillator, it achieves continuous and stable correction of its long-term frequency drift, taking into account both the short-term stability and long-term frequency accuracy of the output clock.

[0029] In an optional implementation, step S102 above, which calculates the rising edge time difference between the first-second pulse signal of the BeiDou clock and the second-second pulse signal of the clock to be tamed, to obtain the original time difference sequence, specifically includes the following steps: Step S1021: Connect the first second pulse signal and the second second pulse signal to the start input terminal of the carry chain inside the CPLD, respectively.

[0030] The first-second pulse signal and the second-second pulse signal are both digital level signals with distinct rising edge characteristics. They are independently and isolatedly introduced into the starting points of two structurally identical and electrically matched carry chains within the CPLD chip. The carry chain is a special logic device within the CPLD, composed of dedicated fast carry logic units, each with an extremely small propagation delay (approximately tens of picoseconds under typical process technology). These units are connected in series to form a delay line. The input of each unit is the carry output of the previous stage, and the output is the carry output of the current stage.

[0031] Step S1022: Under the trigger of a preset high-frequency clock, the delayed propagation of the two carry chains is started synchronously.

[0032] A preset high-frequency clock serves as the global sampling cycle for the entire time measurement module, and its rising edge is used as a unified "sampling gate signal." Optionally, a local 1PPS (i.e., the second-second pulse signal) signal is generated based on a local crystal oscillator, and a 200MHz (exemplary value) high-frequency clock is generated through the CPLD's internal phase-locked loop (PLL). The time difference between the local 1PPS and the BeiDou 1PPS (i.e., the first-second pulse signal) is measured using this 200MHz high-frequency clock and the CPLD's internal carry chain.

[0033] When the high-frequency clock edge arrives, the CPLD's internal logic circuitry simultaneously sends enable commands to both carry chains, driving the pulse signals at their respective inputs to propagate sequentially along the delay chains. Because the carry chain units have extremely small and relatively stable inherent propagation delays (typically on the order of tens of picoseconds), this synchronous startup mechanism ensures that the two signals experience completely consistent timing reference starting points in their respective delay chains, thereby eliminating systematic deviations introduced by asynchronous triggering. This design transforms two asynchronous pulses that were originally difficult to directly compare into measurable physical quantities that map time offsets to spatial positions within the same time coordinate system.

[0034] Step S1023: In each sampling period, the level state of each carry chain tap is sampled in parallel to determine the position index of the rising edge of the first second pulse signal and the rising edge of the second second pulse signal on their respective delay chains.

[0035] Figure 2 This invention provides a schematic diagram of carry chain tap timing. Each carry chain has a dedicated tap at the output of each carry unit. These taps are arranged in a fixed order, forming a discrete "time scale". At the end of each high-frequency clock cycle (i.e., within one sampling period), the CPLD internal register array synchronously latches the current level state of all taps. Since the pulse signal propagates at a finite speed in the delay chain, its rising edge must be between two taps at a certain sampling moment. By identifying the low-to-high transition boundary on the tap (i.e., the first tap number to present a high level), the position index of the pulse rising edge on this delay chain can be uniquely determined.

[0036] Step S1024: Based on the position index, the clock period of the preset high-frequency clock, and the pre-calibrated mapping relationship between the position index and the delay, calculate the original time difference sequence between the first-second pulse signal and the second-second pulse signal.

[0037] Due to manufacturing variations, the delay of each carry logic unit is not exactly equal, so the time cannot be calculated simply by multiplying the position index by the nominal unit delay (e.g., 70 ps). Therefore, before the device leaves the factory or during the initialization phase, the entire carry chain needs to be calibrated using a test signal with a known time interval (e.g., an atomic clock 1 PPS or a high-stability signal generator) to establish a mapping table between tap positions and delay times (i.e., the mapping relationship between position indices and delays) to ensure measurement accuracy.

[0038] Next, after determining the position indices of the rising edges of the first-second pulse signal and the second-second pulse signal on their respective delay chains, the interval between the rising edges of each pulse and the subsequent sampling time can be obtained by looking up the tables. Figure 3 This invention provides a schematic diagram for time difference measurement. Let T1 be the interval between the rising edge of the BeiDou 1PPS signal and its subsequent sampling time, T2 be the interval between the rising edge of the local 1PPS signal and its subsequent sampling time, T0 be the clock period of a preset high-frequency clock, and n be the number of times the high-frequency clock samples between the rising edges of the first and second second pulse signals. Then, the time difference between the rising edges of the first and second second pulse signals is: This calculation is repeated in each sampling period to form the original time difference sequence.

[0039] In an optional embodiment, step S104 above, which filters the original time difference sequence to obtain a smoothed time difference sequence, specifically includes the following steps: Step S1041: Initialize the initial time difference and initial covariance between the first-second pulse signal and the second-second pulse signal.

[0040] In this embodiment of the invention, the initial time difference x(0) represents the system startup or relocking time, and is a priori estimate of the phase relationship between the BeiDou 1PPS and the local 1PPS. Its value can be derived from power-on self-test, inheritance of historical convergence values, or a rough measurement mean. The purpose is to provide reasonable initial state values ​​for subsequent recursion and avoid severe oscillations in the initial output of the filter. Initial covariance The initial value is used to quantify the degree of uncertainty. Its value can be randomly selected from the confidence interval obtained from the statistics of historical operating data. The initial time difference and initial covariance only affect the convergence time of the filter.

[0041] Step S1042: Based on the initial covariance, iteratively calculate the correction coefficients corresponding to each time difference in the time difference sequence to obtain the correction coefficient sequence.

[0042] Step S1043: Based on the correction coefficient sequence and the initial time difference, correct each time difference in the original time difference sequence to obtain a smoothed time difference sequence.

[0043] Optionally, embodiments of the present invention use a Kalman filter to process the measured values. The Kalman filter is an optimal state estimation algorithm, particularly suitable for noisy dynamic systems. It recursively fuses system model predictions with noisy observations to provide an optimal estimate of the system state. It assumes the system is a linear Gaussian process and can minimize the mean square error of the estimation. Its core recursion consists of two steps: Step 1: Based on the preset initial time difference x(0) and initial covariance... Process noise Noise measurement Calculate the covariance for each filtering step. And the correction factor b(k).

[0044] Step 2: Using the previous output x(k-1) of the filter and the correction coefficient b(k) used in this filtering, filter the current input y(k) of the filter to obtain the current output x(k) of the filter. The input of the filter is the time difference in the original time difference sequence, and the output of the filter is the smoothed time difference.

[0045] In this embodiment of the invention, covariance The recursive formula is: The recursive formula for the correction coefficient calculated based on covariance is as follows: The recursive formula for the smoothed time difference is: x(k) = x(k-1) + b(k)[y(k) - x(k-1)].

[0046] Where x(k) is the current output of the filter, x(k-1) is the previous output of the filter, y(k) is the current input of the filter, and x(0), , , All are constants, and appropriate values ​​are selected according to the actual situation to balance the debouncing and tracking capabilities of the filter. k represents the sequence number; after the device starts working, each measured data is numbered starting from 0; x(0), These are just initial values ​​and generally only affect the convergence time of the filter; For process noise, the smaller the noise, the easier the system converges, the higher the confidence in the model's predicted values, and the final result is that the filter output will be more stable and less jittery. For measuring noise, this value affects the confidence level of the measured value. The larger the value, the lower the confidence level and the worse the filter's tracking ability. The smaller the value, the faster the system converges, but too small a value can also easily cause oscillations.

[0047] According to the recursive formula for covariance, it is known that... , In the case of k=0, we can calculate b(0); according to the recursive formula of the correction coefficient, we know that... , , In the case of k=1, we can calculate b(1); next, we can substitute b(1) into the recursive formula for covariance to obtain Then Substituting into the recursive formula for the correction coefficient, we can obtain b(2); and so on, we can obtain the sequence of correction coefficients {b(k)}.

[0048] Next, according to the formula for the smoothed time difference, when k=1, x(1)=x(0)+b(1)[y(1)-x(0)]. According to the measurement order, by substituting the corresponding correction coefficients into the correction coefficient sequence, the time differences in the original time difference sequence can be corrected to obtain the smoothed time difference sequence. The above operation does not change the time series structure of the original data, but generates a new sequence with lower variance, smaller abnormal fluctuations, and accurate reflection of the true phase drift trend while maintaining temporal consistency.

[0049] Figure 4 This is a schematic diagram of the time difference sequence before and after filtering provided in an embodiment of the present invention. The blue and red graphs represent the data before and after filtering, respectively. (Refer to...) Figure 4 It can be seen that the filtering method used in the embodiments of the present invention can significantly reduce jitter while retaining sufficient fast following ability, and is suitable for clock discipline scenarios.

[0050] In an optional implementation, if the second-second pulse signal is a signal generated by a voltage-controlled crystal oscillator, then step S106 above, based on the smoothed time difference sequence, calculates the frequency increment sequence of the clock to be disciplined, specifically including the following steps: Step S1061: Divide the smoothed time difference sequence into segments according to the preset adjustment period, and calculate the average time difference in each segment to obtain the average time difference sequence.

[0051] Specifically, although the smoothed time difference sequence has filtered out high-frequency jitter, it may still contain low-amplitude fluctuations caused by measurement residual errors, environmental disturbances, or short-term fluctuations in the crystal oscillator. Directly differentiating it point by point can easily amplify noise and lead to frequency estimation distortion. Therefore, this embodiment of the invention introduces a preset adjustment period (i.e., the smallest time granularity of the control action), dividing the continuous time difference sequence into several equal-length time intervals, and calculating the arithmetic mean within each time interval to obtain the average time difference sequence. Clearly, the longer the preset adjustment period, the stronger the noise resistance, but the more sluggish the dynamic response; the shorter the period, the more sensitive it is to reflecting real-time deviations, but the noise suppression is insufficient.

[0052] Step S1062: Based on the average time difference sequence, calculate the time change between adjacent average time differences. That is, ΔT = T n T n-1 T n T represents the average time difference within the nth segment. n-1 This represents the average time difference within the (n-1)th segment.

[0053] To control the frequency of the local clock, it is necessary to know the frequency difference between the local clock and the BeiDou satellite system clock. Given Δf = ΔT / τ, where Δf = f - f0, f is the local clock frequency, f0 is the reference frequency (i.e., the BeiDou satellite system frequency), τ is the sampling period (1 second in this embodiment), and ΔT is the difference between the two time difference data (i.e., the change in time difference). The rate of change of the time difference ΔT / τ is equal to the frequency difference between the two signals. Therefore, by measuring the two time difference data, the difference between the current local clock frequency and the reference frequency can be calculated. This explains why frequency calibration can be performed by measuring the time difference.

[0054] Step S1063: Use the incremental PID algorithm to process the time changes corresponding to the three most recent adjustment cycles to obtain the control voltage increment corresponding to the current adjustment cycle.

[0055] If the second-second pulse signal is generated by a voltage-controlled crystal oscillator (VCO), and it is known that the VCO frequency needs to be controlled by a control voltage, this embodiment of the invention uses an incremental PID algorithm to control the voltage. The formula for the control voltage increment corresponding to the current adjustment period is expressed as: ;in, , , , , , These represent the changes in time difference between the current, previous, and previous time periods, respectively. Indicates the preset adjustment period. , , All of these represent constant parameters, while A, B, and C represent intermediate parameters.

[0056] Step S1064: Determine the frequency increment sequence of the clock to be disciplined based on the control voltage increment corresponding to each adjustment cycle.

[0057] After determining the control voltage increment for each adjustment cycle, the control voltage increment is superimposed on the control voltage of the previous adjustment cycle to obtain the control voltage for the current adjustment cycle. Next, based on the voltage-frequency characteristics of the voltage-controlled crystal oscillator, the oscillation frequency for the current adjustment cycle can be obtained. Subtracting the oscillation frequency of the previous adjustment cycle from the current adjustment cycle's oscillation frequency yields the frequency increment for the current adjustment cycle. This frequency increment sequence characterizes the active correction amount applied to the crystal oscillator frequency by the system in each adjustment cycle.

[0058] To balance adjustment speed and clock stability, in one optional implementation, the preset adjustment period includes: a first adjustment period and a second adjustment period; the first adjustment period is shorter than the second adjustment period.

[0059] Specifically, this invention constructs an adaptive time-scale control mechanism that enables the frequency calibration process to achieve an optimal balance between response speed and operational stability based on the current dynamic deviation state of the system.

[0060] Crystal oscillators exhibit significantly different dynamic characteristics at different operating stages: after initial unlocking or experiencing significant environmental disturbances, their frequency deviation is often large and changes rapidly. Using an excessively long adjustment period at this time will lead to calibration lag, continuous accumulation of phase errors, and even periodic oscillations. Conversely, when the system is close to a locked steady state, the frequency deviation is small and changes smoothly. Maintaining short-cycle high-frequency adjustment not only wastes hardware resources but also easily degrades short-term stability due to the small jitter of the control input combined with the crystal oscillator's own noise. Therefore, this invention abandons the static control paradigm with a fixed period and instead uses real-time observable time changes as state variables to drive the autonomous evolution of the adjustment rhythm.

[0061] Therefore, when the time change is greater than or equal to the first threshold, the preset adjustment period adopts the first adjustment period; when the time change is less than the first threshold, the preset adjustment period adopts the second adjustment period.

[0062] Among them, the first threshold serves as the sole quantitative criterion for the adjustment cycle switching decision. Its physical meaning is the boundary marker for the local clock frequency deviation to enter the steady-state region. Its value can be set based on experience. When the calculated time change is greater than or equal to the threshold, it indicates that the current frequency deviation is still in a significant change range. The system determines that a higher frequency calibration rhythm needs to be enabled to enhance the dynamic tracking capability. Once the change is consistently lower than the threshold for several consecutive cycles, the system automatically switches to low-frequency fine-tuning mode, shifting the control focus from rapid approximation to fine maintenance.

[0063] Optionally, the first adjustment period is set to a shorter time interval (e.g., 30 seconds) for the rapid convergence phase of the system. Its design goal is to improve the tracking bandwidth for large deviations, shorten the discipline setup time, and ensure that the system can quickly approach the target frequency after the initial frequency deviation of the crystal oscillator is large or after sudden disturbances. The second adjustment period is set to a relatively longer time interval (e.g., 60 seconds or longer) for the precise and stable operation phase of the system. Its design goal is to reduce the frequency of control actions and reduce the step disturbances introduced by frequency adjustment, thereby maximizing the preservation of the inherent low phase noise advantage of the local crystal oscillator.

[0064] As described above, the time change is positively correlated with the frequency deviation. Therefore, the frequency deviation can also be used as the switching condition for the adjustment period. For example, when the frequency difference between the first-second pulse signal and the second-second pulse signal is greater than or equal to 0.01Hz, the first adjustment period is used; when the frequency difference between the first-second pulse signal and the second-second pulse signal is less than 0.01Hz, the second adjustment period is used.

[0065] In one optional embodiment, after obtaining the tamed second pulse signal, the present invention further includes the following steps: Step S201: Obtain the frequency increments and corresponding adjustment times in the frequency increment sequence within the preset historical time period before the current time.

[0066] Step S202: Based on each frequency increment and the corresponding adjustment time, fit the functional relationship between frequency increment and time.

[0067] To ensure the local crystal oscillator continues to function normally for a period of time after the loss of BeiDou satellite signals, thus maintaining frequency accuracy, it's crucial to address the issue of frequency aging. Since normal training cannot proceed after the loss of satellite signals, the crystal oscillator frequency will gradually shift over time. This aging phenomenon necessitates compensation for the crystal oscillator. Maintaining frequency accuracy presupposes that the local crystal oscillator has been trained and stabilized for a certain period. After training, aging causes the crystal oscillator frequency to monotonically increase or decrease. Therefore, the overall trend of frequency increment during the training process will either increase or decrease.

[0068] Optionally, in this embodiment of the invention, the frequency increment sequence of the past 1440 minutes (i.e., the number of minutes in a day) is stored in RAM, that is, the preset historical time period is the past 24 hours. The data pairs (frequency increment, corresponding adjustment time) obtained from the frequency increment sequence are used to form a set of discrete time series samples, and then the least squares method is used to fit the functional relationship between frequency increment and time based on the discrete time series sample set.

[0069] In one optional embodiment, after obtaining the tamed second pulse signal, the present invention further includes the following: If the first second pulse signal is lost, substitute the current time into the function relationship between frequency increment and time to obtain the estimated frequency increment corresponding to the current moment; based on the estimated frequency increment, compensate for the current oscillation frequency of the clock to be disciplined to obtain the frequency-compensated second pulse signal.

[0070] After the satellite signal is lost, the aging frequency of the crystal oscillator is basically linearly related to time in the short term. Therefore, after constructing the functional relationship between frequency increment and time, the current time can be substituted into the above relationship as an input variable to calculate the frequency correction amount to be applied at this moment (that is, the estimated frequency increment). Then, the frequency correction amount is used to compensate the current oscillation frequency of the clock to be disciplined to obtain the frequency-compensated second pulse signal.

[0071] If the second-second pulse signal is generated by a voltage-controlled crystal oscillator (VCO), the estimated frequency increment is not directly applied to the crystal oscillator. Instead, the CPLD's internal digital control module, combined with the VCO's calibration response characteristics (such as the voltage adjustment corresponding to a unit frequency increment), converts it into an equivalent control voltage increment, which is then superimposed on the current holding voltage reference to form a new control voltage command. This command is applied to the crystal oscillator's voltage control terminal via digital-to-analog conversion, thereby dynamically offsetting frequency shifts caused by factors such as material aging and gradual temperature changes.

[0072] Taking a local crystal oscillator as a voltage-controlled crystal oscillator as an example, Figure 5 The flowchart of another clock discipline method provided by the embodiments of the present invention provides a clearer understanding of the complete operation steps of clock discipline. Figure 6 This is a schematic diagram of BeiDou second pulse jitter provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of the aging process of a free crystal oscillator provided in an embodiment of the present invention. Figure 8 This is a schematic diagram illustrating the clock frequency change after clock discipline is performed using the method provided in the embodiments of the present invention.

[0073] In summary, the embodiments of this invention aim to combine the advantages of BeiDou second pulses and local crystal oscillators, fully utilizing the high long-term stability of BeiDou second pulses to effectively filter out random jitter of BeiDou second pulses, achieving high-precision discipline of the local crystal oscillator, and outputting a clock signal with high short-term stability, high frequency accuracy, and high long-term stability. Its advantages are as follows: 1. Filter out random jitter in the second pulse and improve discipline robustness: Through digital filtering and dynamic processing mechanism based on CPLD design, the random jitter and abnormal jumps in the 1PPS signal output by the Beidou receiver are effectively suppressed, avoiding discipline errors caused by the deterioration of the second pulse quality and enhancing the system's working stability in complex environments.

[0074] 2. Achieve high-precision frequency discipline and improve frequency accuracy: Utilize the optimized 1PPS signal as a long-term frequency reference, and combine high-resolution time measurement and digital frequency control technology to precisely calibrate the oscillation frequency of the local crystal oscillator, so that its output frequency is locked precisely to the clock frequency of the BeiDou satellite system for a long time, achieving high frequency accuracy.

[0075] 3. Maintain high short-term stability of the local crystal oscillator: During the taming process, fully preserve the excellent short-term stability and low phase noise characteristics of the local crystal oscillator, avoid introducing additional frequency disturbances due to excessively frequent or coarse feedback control, and ensure that the system output clock has extremely high stability within the short-term observation window.

[0076] 4. Improve system integration and reduce costs: All core synchronization algorithms and control logic are implemented based on CPLD. By utilizing the parallel processing, hardware programmability and high-precision timing capabilities of CPLD, key functions such as second pulse jitter suppression, phase measurement, digital filtering and frequency control word generation are completed within a single chip, reducing system complexity and effectively reducing hardware costs.

[0077] 5. Ensure the continuity and reliability of the output clock: When the BeiDou signal is briefly lost or abnormal, the local crystal oscillator can continue to output a high-precision and high-stability clock signal within a specified time by using historical discipline data and the hold mode algorithm inside the CPLD, so as to achieve seamless switching from the locked state to the hold state, thereby improving the system's time holding capability and overall reliability.

[0078] Example 2 This invention also provides a clock taming device, which is mainly used to execute the clock taming method provided in Embodiment 1 above. The clock taming device provided in this invention will be described in detail below.

[0079] Figure 9 A functional block diagram of a clock discipline device provided in an embodiment of the present invention is shown below. Figure 9 As shown, the device mainly includes: a first calculation module 10, a filtering module 20, a second calculation module 30, and a calibration module 40, wherein: The first calculation module 10 is used to calculate the rising edge time difference between the first second pulse signal of the Beidou clock and the second second pulse signal of the clock to be tamed, so as to obtain the original time difference sequence.

[0080] The filtering module 20 is used to filter the original time difference sequence to obtain a smoothed time difference sequence.

[0081] The second calculation module 30 is used to calculate the frequency increment sequence of the clock to be tamed based on the smoothed time difference sequence.

[0082] The calibration module 40 is used to continuously calibrate the oscillation frequency of the clock to be tamed based on the frequency increment sequence to obtain the tamed second pulse signal.

[0083] This invention first calculates the original time difference sequence, then filters it, then calculates the frequency increment based on the filtered time difference sequence, and finally performs calibration based on the frequency increment. This ensures that the frequency deviation information on which calibration depends is no longer affected by the random jitter of the BeiDou clock second pulse signal, thereby suppressing frequent oscillations in the calibration command. At the same time, because the time difference sequence on which calibration is based has become smooth and stable, the calibration process converges faster, avoiding phase disturbances introduced by repeated trial and error. Thus, without sacrificing the inherent short-term stability of the local crystal oscillator, it achieves continuous and stable correction of its long-term frequency drift, taking into account both the short-term stability and long-term frequency accuracy of the output clock.

[0084] Optionally, the first computing module 10 is specifically used for: Connect the first-second pulse signal and the second-second pulse signal to the start input terminal of the carry chain inside the CPLD, respectively.

[0085] Triggered by a preset high-frequency clock, the delayed propagation of the two carry chains is started synchronously.

[0086] Within each sampling period, the level state of each carry chain tap is sampled in parallel to determine the position index of the rising edge of the first second pulse signal and the rising edge of the second second pulse signal on their respective delay chains.

[0087] Based on the position index, the clock period of the preset high-frequency clock, and the pre-calibrated mapping relationship between the position index and the delay, the original time difference sequence between the first-second pulse signal and the second-second pulse signal is calculated.

[0088] Optionally, the filtering module 20 is specifically used for: Initialize the initial time difference and initial covariance between the first-second pulse signal and the second-second pulse signal; Based on the initial covariance, the correction coefficients corresponding to each time difference in the time difference sequence are calculated iteratively to obtain the correction coefficient sequence. Based on the correction coefficient sequence and the initial time difference, each time difference in the original time difference sequence is corrected to obtain a smoothed time difference sequence.

[0089] Optionally, if the second-second pulse signal is a signal generated by a voltage-controlled crystal oscillator, then the second calculation module 30 is specifically used for: The smoothed time difference sequence is segmented according to a preset adjustment period, and the average time difference within each segment is calculated to obtain the average time difference sequence.

[0090] Based on the average time difference series, calculate the time change between adjacent average time differences.

[0091] The incremental PID algorithm is used to process the time changes corresponding to the most recent three adjustment cycles to obtain the control voltage increment corresponding to the current adjustment cycle.

[0092] Based on the control voltage increment corresponding to each adjustment cycle, the frequency increment sequence of the clock to be disciplined is determined.

[0093] Optionally, the preset adjustment period includes: a first adjustment period and a second adjustment period; the first adjustment period is shorter than the second adjustment period.

[0094] When the change in time is greater than or equal to the first threshold, the preset adjustment period adopts the first adjustment period.

[0095] When the change in time is less than the first threshold, the preset adjustment period adopts the second adjustment period.

[0096] Optionally, after obtaining the tamed second pulse signal, the device is also used for: Obtain the frequency increments and corresponding adjustment times in the frequency increment sequence within a preset historical time period prior to the current moment.

[0097] Based on each frequency increment and the corresponding adjustment time, a functional relationship between the frequency increment and time is fitted.

[0098] Optionally, after obtaining the tamed second pulse signal, the device is also used for: If the first-second pulse signal is lost, substitute the current time into the function relating frequency increment and time to obtain the estimated frequency increment corresponding to the current moment.

[0099] The current oscillation frequency of the clock to be disciplined is compensated based on the estimated frequency increment to obtain the frequency-compensated second pulse signal.

[0100] Example 3 See Figure 10 This invention provides an electronic device, which includes a processor 60, a memory 61, a bus 62, and a communication interface 63. The processor 60, the communication interface 63, and the memory 61 are connected via the bus 62. The processor 60 is used to execute executable modules, such as computer programs, stored in the memory 61.

[0101] The memory 61 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 63 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc.

[0102] Bus 62 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 10 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0103] The memory 61 is used to store programs. After receiving an execution instruction, the processor 60 executes the program. The method executed by the apparatus defined by the process disclosed in any of the foregoing embodiments of the present invention can be applied to the processor 60 or implemented by the processor 60.

[0104] Processor 60 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 60 or by instructions in software form. Processor 60 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 61. Processor 60 reads the information in memory 61 and, in conjunction with its hardware, completes the steps of the above method.

[0105] The computer program product of the clock discipline method and apparatus provided in the embodiments of the present invention includes a computer-readable storage medium storing non-volatile program code executable by a processor. The instructions included in the program code can be used to execute the methods described in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0106] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0107] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0108] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0109] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0110] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0111] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock disciplining method, characterized by, include: The rising edge time difference between the first second pulse signal of the Beidou clock and the second second pulse signal of the clock to be tamed is calculated to obtain the original time difference sequence; The original time difference sequence is filtered to obtain a smoothed time difference sequence; Based on the smoothed time difference sequence, calculate the frequency increment sequence of the clock to be tamed; The oscillation frequency of the clock to be tamed is continuously calibrated based on the frequency increment sequence to obtain the tamed second pulse signal.

2. The clock doming method of claim 1, wherein, The rising edge time difference between the first-second pulse signal of the BeiDou clock and the second-second pulse signal of the clock to be tamed is calculated to obtain the original time difference sequence, including: Connect the first second pulse signal and the second second pulse signal to the start input terminal of the carry chain inside the CPLD, respectively; Triggered by a preset high-frequency clock, the delayed propagation of the two carry chains is started synchronously. Within each sampling period, the level state of each carry chain tap is sampled in parallel to determine the position index of the rising edge of the first second pulse signal and the rising edge of the second second pulse signal on their respective delay chains. Based on the position index, the clock period of the preset high-frequency clock, and the pre-calibrated mapping relationship between the position index and the delay, the original time difference sequence between the first second pulse signal and the second second pulse signal is calculated.

3. The clock doming method of claim 1, wherein, The original time difference sequence is filtered to obtain a smoothed time difference sequence, including: Initialize the initial time difference and initial covariance between the first-second pulse signal and the second-second pulse signal; Based on the initial covariance, the correction coefficients corresponding to each time difference in the time difference sequence are iteratively calculated to obtain the correction coefficient sequence. Based on the correction coefficient sequence and the initial time difference, each time difference in the original time difference sequence is corrected to obtain the smoothed time difference sequence.

4. The clock doming method of claim 1, wherein, If the second second pulse signal is a signal generated by a voltage-controlled crystal oscillator, then based on the smoothed time difference sequence, the frequency increment sequence of the clock to be disciplined is calculated, including: The smoothed time difference sequence is segmented according to a preset adjustment period, and the average time difference within each segment is calculated to obtain the average time difference sequence. Based on the average time difference sequence, calculate the time change between adjacent average time differences; The incremental PID algorithm is used to process the time changes corresponding to the three most recent adjustment cycles to obtain the control voltage increment corresponding to the current adjustment cycle. Based on the control voltage increment corresponding to each adjustment cycle, the frequency increment sequence of the clock to be disciplined is determined.

5. The clock doming method of claim 4, wherein, The preset adjustment period includes: a first adjustment period and a second adjustment period; the first adjustment period is shorter than the second adjustment period. When the time change is greater than or equal to the first threshold, the preset adjustment period adopts the first adjustment period; When the time change is less than the first threshold, the preset adjustment period adopts the second adjustment period.

6. The clock doming method of claim 1, wherein, After obtaining the tamed second pulse signal, the process also includes: Obtain each frequency increment and its corresponding adjustment time in the frequency increment sequence within a preset historical time period prior to the current moment; Based on each frequency increment and the corresponding adjustment time, a functional relationship between the frequency increment and time is fitted.

7. The clock doming method of claim 6, wherein, After obtaining the tamed second pulse signal, the process also includes: If it is determined that the first second pulse signal is lost, substitute the current time into the functional relationship between the frequency increment and time to obtain the estimated frequency increment corresponding to the current moment; The current oscillation frequency of the clock to be disciplined is compensated based on the estimated frequency increment to obtain a frequency-compensated second pulse signal.

8. A clock training apparatus, characterized by comprising: include: The first calculation module is used to calculate the rising edge time difference between the first second pulse signal of the Beidou clock and the second second pulse signal of the clock to be tamed, so as to obtain the original time difference sequence. A filtering module is used to filter the original time difference sequence to obtain a smoothed time difference sequence. The second calculation module is used to calculate the frequency increment sequence of the clock to be tamed based on the smoothed time difference sequence. The calibration module is used to continuously calibrate the oscillation frequency of the clock to be tamed based on the frequency increment sequence, so as to obtain the tamed second pulse signal.

9. An electronic device comprising a memory, a processor, the memory having stored thereon a computer program executable on the processor, characterized in that, When the processor executes the computer program, it implements the clock discipline method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the clock discipline method of any one of claims 1 to 7.

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