A method for optimal ripple clamped modulation for two parallel converters

Abstract

This invention proposes a ripple-optimal clamping modulation method for two parallel converters. Based on the equivalent voltage vector plane of the two parallel converters, the method divides the vector plane into multiple equilateral triangular regions according to the principle of near-three-vector synthesis. Within each equilateral triangular region, by controlling the total number of conducting switches in each of the three-phase parallel branches to vary in an increasing or decreasing manner, a set of optimal ripple vector sequences is constructed. A switching sequence is generated based on this vector sequence, and the final optimal switching sequence is determined with the goal of minimizing the peak value of single-phase circulating current. Furthermore, a carrier modulation scheme based on a combination of increasing and decreasing sawtooth carriers is constructed. According to the symmetry of the switching sequence, the configuration of the carrier and modulation wave is selected. Simultaneously, the carrier polarity is alternately configured within adjacent carrier periods to achieve symmetry of adjacent carrier periods of the switching signal. This method can effectively reduce output current ripple and suppress parallel branch circulating current, while simultaneously reducing switching losses and improving system performance.

Description

Technical Field

[0001] This invention relates to a modulation implementation algorithm for ripple optimization, specifically to a ripple-optimal clamping modulation method for two parallel converters. Background Technology

[0002] Output current ripple, switching losses, and circulating current are key indicators for the reliable operation of converters. Excessive current ripple can cause significant torque pulsation in the motor drive system, leading to mechanical vibration and noise. High switching losses reduce the energy utilization of the converter. Circulating current causes additional energy loss, and the peak value of the circulating current will affect the design of the filter inductor. Existing modulation strategies optimized for these high-frequency indicators are difficult to simultaneously achieve all three key indicators. For example, the ripple minimization modulation algorithm (reference [Z. Zeng, Z. Li, and S. Goetz, "Line current ripple minimization PWM strategy with reduced zero-sequence circulating current for two parallel interleaved three-phase converters," IEEE Trans. Power Electron., vol. 35, no. 7, pp. 6931–6943, Jul. 2020.]) achieves optimal ripple, but its switching losses are relatively large. The discontinuous pulse width modulation algorithm based on interleaved carriers (reference [G. Gohiletal., "Modified discontinuous PWM for size reduction of While the circulating current filter in parallel-interleaved converters (IEEE Trans. Power Electron., vol. 30, no. 7, pp. 3457–3470, Jul. 2015.) reduces switching losses, its circulating current peak is relatively large. The three-level pulse width modulation algorithm (Z. Quan and Y.W. Li, “A three-level space vector modulation scheme for parallel-interleaved converter storeduce circulating current and common-mode voltage,” IEEE Trans. Power Electron., vol. 32, no. 1, pp. 703–714, Jan. 2017.) reduces the circulating current peak, but its ripple is poor. Therefore, there is an urgent need to design a modulation method that can simultaneously optimize these three key performance indicators. Summary of the Invention

[0003] The purpose of this invention is to provide a ripple-optimal clamping modulation method for two parallel converters, which solves the problem that existing modulation methods cannot simultaneously optimize output current ripple and switching losses. This method can effectively reduce output current ripple and suppress circulating current in parallel branches, while also reducing switching losses and improving system performance.

[0004] The technical solution to achieve the purpose of this invention is as follows:

[0005] A ripple-optimal clamping modulation method for two parallel converters includes:

[0006] Based on the equivalent voltage vector plane of two parallel converters, the equivalent voltage vector plane is divided into multiple equilateral triangular regions of equal area according to the principle of near three-vector synthesis. The vertices of each equilateral triangle are composed of the basic voltage vector and its redundant voltage vector.

[0007] Within each equilateral triangle region, the basic voltage vector or its redundant voltage vector corresponding to any vertex is used as the starting vector. By controlling the total number of conducting devices in each parallel branch of the three phases to change in an increasing or decreasing manner, the voltage vectors of the other two vertices are switched sequentially, and the starting vector is returned in the reverse order of the switching path to construct a 5-segment symmetrical vector sequence.

[0008] Based on the 5-segment symmetrical vector sequence, with its last vector as the starting vector of a new round, the same switching path is repeated once. The two generated symmetrical vector sequences are then sequentially spliced ​​together to form a 9-segment clamping vector sequence with optimal ripple, thereby constructing a set of clamping vector sequences with optimal output current ripple. Each segment of the 9-segment clamping complete vector sequence with optimal ripple corresponds to a voltage vector.

[0009] Based on the clamping vector sequence set, the corresponding switch combination is determined to generate the switch sequence. Switch sequences that cause unidirectional growth of the circulating current in the three-phase parallel branch are eliminated, and the optimal switch sequence is determined with the minimum peak value of the single-phase circulating current as the optimization objective.

[0010] The optimal switching sequence is used to generate a modulation wave and construct a carrier modulation scheme. By alternately configuring the carrier polarity in adjacent carrier cycles, the switching signals of the same bridge arm are symmetrically distributed in two consecutive carrier cycles.

[0011] Furthermore, the step of dividing the equivalent voltage vector plane into multiple equilateral triangular regions of equal area according to the principle of near-three-vector synthesis specifically involves: the voltage vector plane is initially divided into 6 basic sectors, each basic sector is further divided into 4 equilateral triangles of equal area, and finally the voltage vector plane is divided into 24 equilateral triangular regions of equal area, wherein the vertices of each equilateral triangle are the basic vectors and their redundant vectors on the vector plane.

[0012] Furthermore, the construction of the 5-segment symmetrical vector sequence is specifically as follows: within each equilateral triangle region, the basic voltage vector or its redundant voltage vector corresponding to any vertex is used as the starting vector. By controlling the total number of conducting switches in each parallel branch of the three phases to change in an increasing or decreasing manner, the voltage vectors at the vertices of the equilateral triangle are switched sequentially, so that each of the three vertex voltage vectors is visited once. Then, with the last visited vertex voltage vector as the center of symmetry, the starting vector is returned in reverse order of the switching path to construct the 5-segment symmetrical vector sequence.

[0013] Furthermore, the construction of the clamping vector sequence set with optimal output current ripple specifically involves: selecting any vertex vector as the starting vector, changing the way the total number of conducting switching devices in each parallel branch of the three phases increases or decreases, and constructing two different vector sequences; since the three vertex vectors of an equilateral triangle can all be used as starting vectors, a total of 6 vector sequences are constructed in each basic sector, and there are a total of 36 clamping vector sequences with optimal ripple in the entire vector plane, thus obtaining the clamping vector sequence set.

[0014] Furthermore, the method for generating the switching sequence includes: mapping the clamping vector sequence to a changing sequence of the total number of conducting switches in each phase parallel branch, and, under the condition of satisfying the constraint of the total number of conducting switches, converting the changing sequence into a corresponding switching state sequence to generate a candidate switching sequence.

[0015] Furthermore, determining the optimal switching sequence specifically includes: first, removing switching sequences from the candidate switching sequences that cause unidirectional growth of the circulating current; second, within each equilateral triangle region, based on the real-time position of the reference voltage vector, comparing the single-phase circulating current peak values ​​of the switching sequences, and selecting the switching sequence with the smallest peak value as the optimal switching sequence corresponding to the position of the reference voltage; finally, according to the distribution law of the selected optimal switching sequences with the position of the reference voltage vector, refining each basic sector into 6 sub-sectors, each sub-sector corresponding to a unique optimal switching sequence.

[0016] Furthermore, the carrier wave is a sawtooth wave, including an incrementing carrier and a decrementing carrier. The incrementing carrier uses an incrementing counting method, which resets to zero after reaching a set period value and enters the next period. The decrementing carrier uses a decrementing counting method, which decrements from the set period value to zero, then reassigns the period value and enters the next period.

[0017] Furthermore, generating a modulated wave and constructing a carrier modulation scheme based on the optimal switching sequence specifically includes:

[0018] The carrier modulation scheme is constructed as follows: the configuration of the carrier modulation scheme is determined according to the symmetry of the switching sequence within the carrier period. When the switching sequence is asymmetrical, a comparison between multiple modulated waves and a single carrier is used; when the switching sequence is symmetrical, a comparison between a single modulated wave and multiple carriers is used.

[0019] The modulation wave is generated as follows: based on the action time of each vector in the optimal switching sequence, the duty cycle of each parallel bridge arm switch is calculated; and according to the carrier modulation scheme, the modulation wave expression corresponding to each optimal switching sequence is calculated.

[0020] Furthermore, the comparison method between the multi-modulated wave and the single carrier is as follows: when comparing the single carrier with two modulated waves, the switching state is determined based on the comparison relationship between the modulated wave and the carrier, including:

[0021] If modulation wave 1 is greater than or equal to the incremental carrier wave, or modulation wave 2 is less than or equal to the incremental carrier wave, then a high level is output to turn on the corresponding phase switch transistor.

[0022] If modulation wave 1 is less than or equal to the decrementing carrier wave, or modulation wave 2 is greater than or equal to the decrementing carrier wave, then a high level is output to turn on the corresponding phase switch.

[0023] If modulation wave 1 is less than or equal to the incrementing carrier wave and modulation wave 2 is greater than or equal to the incrementing carrier wave, then output a high level to turn on the corresponding phase switch transistor;

[0024] If modulation wave 1 is less than or equal to the decrementing carrier wave and modulation wave 2 is greater than or equal to the decrementing carrier wave, then output a high level to turn on the corresponding phase switch transistor;

[0025] Among them, modulation wave 2 is greater than modulation wave 1;

[0026] The method of comparing a single modulated wave with multiple carriers is as follows: when comparing a single modulated wave with two carriers, the switching state is determined based on the comparison relationship between the modulated wave and the carriers, including:

[0027] If the modulated wave is greater than both the incrementing and decrementing carrier waves, a high level is output to turn on the corresponding phase switch.

[0028] Furthermore, the alternating configuration of carrier polarity within adjacent carrier periods specifically refers to:

[0029] For a switching sequence that is asymmetric within a unit carrier period, incremental sawtooth carriers and decremental sawtooth carriers are alternately used in adjacent carrier periods, so that the switching sequences of two adjacent carrier periods are symmetrical about the two carrier periods.

[0030] Compared with the prior art, the beneficial effects of the present invention are: (1) The modulation method proposed in the present invention can reduce switching losses while achieving optimal output current ripple; (2) The parallel branch low-frequency circulating current suppression method proposed in the present invention effectively avoids the risk of inductor core saturation and improves the reliability of converter operation. Attached Figure Description

[0031] Figure 1 This is a topology diagram of two parallel converters.

[0032] Figure 2 (a) is the equivalent vector plane diagram of two parallel converters; Figure 2 (b) is the equivalent vector plane diagram of the two parallel converters after the unified characterization of each equivalent voltage vector.

[0033] Figure 3 (a) A vector plane diagram showing the initial sector division of the proposed modulation algorithm; Figure 3 (b) is the optimal sector partitioning vector plane diagram of the proposed modulation algorithm.

[0034] Figure 4 The diagram shows the five switching transistor logic output modes of the proposed modulation algorithm. Figure 4 (a) shows the logic output diagram of the switching transistors for operation modes 1 to 4. Figure 4 (b) shows the logic output diagram of the 5th operating mode switch.

[0035] Figure 5 The optimal switching sequence and circulating waveform of the proposed modulation algorithm in sub-sector 1 of the first basic sector are shown, as well as the switching sequence and circulating waveform after suppressing the inherent low-frequency circulating current of the sequence using a two-carrier-period symmetrical method.

[0036] Figure 6 (a) shows the three-phase parallel current diagram of the proposed modulation algorithm. Figure 6 (b) shows the single-phase circulation diagram of phase A of the proposed modulation algorithm. Figure 6 (c) shows the zero-sequence circulating waveform of the proposed modulation algorithm.

[0037] Figure 7 (a) shows the three-phase parallel current after suppressing the inherent low-frequency circulating current of the sequence using the method proposed in this invention. Figure 7 (b) is a single-phase circulation diagram of phase A after suppressing the inherent low-frequency circulation of the sequence using the method proposed in this invention. Figure 7(c) is a zero-sequence circulation waveform after suppressing the inherent low-frequency circulation of the sequence using the method proposed in this invention.

[0038] Figure 8 In the middle (a), the circulating current spectrum of phase A of the two parallel converters is shown in the frequency range of 0Hz to 700Hz. Figure 8 (b) is the A-phase circulating current spectrum of two parallel converters at a frequency of 0Hz to 700Hz after suppressing the inherent low-frequency circulating current of the sequence using the method proposed in this invention; Figure 8 (c) shows the zero-sequence circulating current spectrum of two parallel converters in the frequency range of 0Hz to 700Hz. Figure 8 (d) is the zero-sequence circulating current spectrum of two parallel converters at frequencies from 0Hz to 700Hz after suppressing the inherent low-frequency circulating current of the sequence using the method proposed in this invention. Detailed Implementation

[0039] The technical methods in the embodiments of this aspect will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] To address the problems in the background technology, this invention proposes a modulation algorithm that can simultaneously optimize three key performance indicators: output current ripple, switching loss, and circulating current. First, the magnitude of the output current ripple directly reflects the instantaneous error between the reference voltage and the actual output voltage. Since the current ripple is proportional to the integral of the voltage error vector with respect to time, selecting the near-three voltage vector method to synthesize the reference voltage vector can maximize ripple optimization. Second, switching loss mainly depends on the number of times the switching transistors switch within a carrier cycle. To optimize switching loss, the switching state of a certain phase must be clamped within a single carrier cycle, meaning the total number of conducting switching devices in each parallel branch of a certain phase must remain constant. Finally, due to the difference in the instantaneous switching states between the two parallel converters within each carrier cycle, circulating currents are generated between the converters. These circulating currents can be divided into single-phase circulating currents and zero-sequence circulating currents, typically exhibiting high-frequency characteristics. The peak value of the circulating current will affect the design of the filter inductor. Based on the above constraints on ripple and switching loss, the optimal sequence can be selected according to the peak value of the circulating current. In summary, this invention proposes a modulation algorithm for the coordinated optimization of current ripple, switching loss, and parallel branch circulating current.

[0041] However, it should be noted that the modulation algorithm proposed in this invention, due to the non-symmetric nature of the switching sequence about half the switching period, leads to the problem of low-frequency circulating current. The presence of low-frequency circulating current easily causes inductor core saturation, thereby weakening its ability to suppress high-frequency current and affecting the reliable operation of the converter. To address this problem, this invention also proposes a method to achieve equivalent symmetry of the switching sequence within two carrier cycles to suppress low-frequency circulating current. Specifically, this invention proposes a method for ripple-optimal clamping modulation for two parallel converters, comprising:

[0042] (1) Based on the equivalent voltage vector plane of two parallel converters, the voltage vector plane is divided into multiple equilateral triangular regions of equal area according to the principle of near-three-vector synthesis. The vertices of each equilateral triangle are composed of the basic voltage vector and its redundant voltage vector. Specifically, this includes:

[0043] Based on the mathematical model of the two parallel converters, the topology of the two parallel converters is as follows: Figure 1 As shown, L1, R1 and L2, R2 are the filter inductors and parasitic resistances on the two converters, respectively, i = [i a i b i c ] T For the three-phase parallel output current on the AC side, i1=[i a1 i b1 i c1 ] T For the three-phase output current on the first converter, i2=[i a2 i b2 i c2 ] T V represents the three-phase output current on the second converter. DC S is the DC-side bus voltage. 11 ~S 16 and S 21 ~S 26 These are the power switching transistors for the two converters. The inductance and parasitic resistance on the bridge arm side generally satisfy L1=L2 and R1=R2.

[0044] Based on Kirchhoff's laws, the expression for the equivalent output voltage of two parallel converters in a two-phase stationary coordinate system can be derived:

[0045] (1)

[0046] Among them, u α u β These are the components of the equivalent output voltage in the two-phase stationary coordinate system, S. a1 S b1 S c1 S a2 Sb2 S c2 These represent the switching states of the switching transistors on the first and second converters, respectively, and can take values ​​of 0 and 1. x1 =1 indicates that the upper tube of phase x of the first converter is turned on, S x1 =0 indicates that the upper tube of phase x of the first converter is turned off, S x2 =1 indicates that the upper tube of phase x of the second converter is on, S x2 =0 indicates that the upper tube of phase x of the second converter is turned off.

[0047] Based on the different switching states of the switching transistors, a total of 64 switching combinations are obtained for the two parallel converters. Substituting these 64 switching combinations into equation (1), 19 equivalent voltage output vectors can be summarized. Table 1 details the correspondence between the equivalent output voltage vectors and the switching combinations. Simultaneously, based on the positions of these equivalent voltage output vectors in the two-phase stationary coordinate system, an equivalent vector plane diagram is drawn, as shown below. Figure 2 As shown.

[0048] Table 1. Relationship between equivalent voltage vector and switching state combination of two parallel converters.

[0049]

[0050] Based on the above equivalent voltage vector plane, the vector plane is divided into 6 basic sectors, each 60° apart. The angle ranges corresponding to each sector are as follows: basic sector I is 0°~60°, basic sector II is 60°~120°, basic sector III is 120°~180°, basic sector IV is 180°~240°, basic sector V is 240°~300°, and basic sector VI is 300°~360°.

[0051] Following the principle of near-three-vector synthesis, each basic sector is initially divided into four equilateral triangular regions of equal area. The vertices of each equilateral triangle are formed by the three equivalent voltage vectors closest to the reference voltage vector, such as... Figure 3 As shown in (a). In each basic sector, the four equilateral triangular regions correspond to sub-sectors 1 through 4 respectively. For example, in basic sector 1, the vector set {V0, V...}... 13 V 14 The equilateral triangle formed by} corresponds to sub-sector 1, which is composed of the vector set {V7, V... 13 V 14 The equilateral triangle formed by} corresponds to sub-sector 2, which is composed of the vector set {V7, V... 13 The equilateral triangle formed by {V1} corresponds to sub-sector 3, which is determined by the vector set {V7, V...}. 14 The equilateral triangle formed by , V2} corresponds to sub-sector 4.

[0052] The vertex vector sets constituting each sub-sector in the entire vector plane are summarized as follows: The three vertex vector sets constituting each sub-sector in basic sector I are {V0, V...} 13 V 14}、{V7,V 13 V 14}、{V7,V 13 ,V1}、{V7,V 14 In basic sector II, the three vertex vector sets constituting each sub-sector are {V0, V2}; 15 V 14}、{V8,V 15 V 14}、{V8,V 14 {V2}, {V8, V} 15 In basic sector III, the three vertex vector sets constituting the sub-sectors are {V0, V3}; 15 V 16}、{V9,V 15 V 16}、{V9,V 15 ,V3}、{V9,V 16 The three vertex vector sets constituting each sub-sector in the basic sector IV are {V0, V4}; 16 V 17}、{V 10 V 17 V 16}、{V 10 V 16 and V4}、{V 10 V 17 The three vertex vector sets constituting each sub-sector in the basic sector V are {V0, V5}; 18 V 17}、{V 11 V 17 V 18},{V 11 V 17 ,V5}、{V 11 V 18 The three vertex vector sets constituting each sub-sector in the basic sector VI are {V0, V6}; 18 V 13},{V 12 V 13 V 18},{V 12 V 18 ,V6}、{V 12 V 13 ,V1}.

[0053] Ultimately, the entire vector plane was initially divided into 24 sub-sectors.

[0054] (2) Based on the equilateral triangular region defined above, by controlling the total number of conducting switches in each parallel branch of the three phases to change in an increasing or decreasing manner, a clamping vector sequence set with optimal output current ripple is constructed. Specifically, it includes:

[0055] First, define S max S mid and S min The three core parameters correspond to the total number of switching devices connected to the positive terminal of the DC bus in each parallel branch belonging to the maximum, intermediate, and minimum value phases, respectively. Based on this definition, any voltage vector in the vector plane can be uniformly characterized by the above parameters. With voltage vector V 14 For example, its corresponding switch combination is V 110 / V 111 V 110 / V 000 Within basic sector II, the magnitude relationship of the three-phase reference voltages satisfies u b >u a >u c Therefore, S max =S b S mid =S a S min =S c Then the voltage vector can be uniformly represented as V 221 or V 110 Following the above representation method, the switch combinations corresponding to each vector in Table 1 are uniformly organized and remapped to the equivalent vector plane diagram, as shown below. Figure 2 As shown in (b).

[0056] Secondly, the construction method of the optimal clamping vector sequence for output current ripple is as follows: Within each of the aforementioned equilateral triangular regions, the basic voltage vector or its redundant voltage vector corresponding to any vertex is used as the starting vector. By controlling the total number of conducting devices in each parallel branch of the three phases to change in an increasing or decreasing manner, the system sequentially switches to the voltage vectors of the other two vertices, ensuring that all vertex voltage vectors are visited once. Using the last visited vertex voltage vector as the center of symmetry, the system returns to the starting vector in reverse order of the vector switching path, thus constructing a 5-segment symmetrical vector sequence. Based on this, the process is repeated once along the same switching path, allowing the 5-segment symmetrical vector sequence to be sequentially spliced ​​together to further form a 9-segment optimal clamping vector sequence for output current ripple, consisting of three vertex voltage vectors, where each segment corresponds to one voltage vector. This vector sequence construction method achieves optimal ripple while ensuring that one phase switch state is always clamped within a single carrier cycle, thereby achieving a balance between optimizing output current ripple and switching losses.

[0057] Finally, this vector sequence construction method is applied to the entire vector plane to obtain the set of vector sequences with optimal ripple: by selecting any vertex vector as the starting vector and changing the way the total number of conducting switches in each parallel branch of the three phases increases or decreases, two different vector sequences can be constructed; since the three vertex vectors of an equilateral triangle can all be used as starting vectors, a total of 6 vector sequences are constructed in each basic sector. Therefore, there are a total of 36 clamping vector sequences with optimal ripple in the entire vector plane.

[0058] The following uses basic sector I to illustrate the method for constructing a ripple-optimal clamped vector sequence:

[0059] In sub-sector 1, the three vertex vectors of the equilateral triangle are V0, V... 13 and V 14 , respectively corresponding to V 000 / V 111 / V 222 V 100 / V 211 V 110 / V 221 If one of the vertex vectors V0 is selected as the starting vector, since the total number of conducting switches in each parallel branch of the three phases can change in an increasing or decreasing manner, there are two vector switching paths.

[0060] One type is an incremental vector switching path: First, using one of the redundant vectors V0, V... 000 As the starting vector, the total number of controlled switching devices that are turned on increases sequentially from phase A to phase B, so that the voltage vectors at all three vertices are visited once to generate the basic vector sequence: Next, following the reverse order of this switching path, the total number of controlled switching devices decreases sequentially from phase B to phase A, thus returning to the starting vector, thereby constructing a 5-segment symmetrical vector sequence: Finally, using the last vector of the above symmetrical vector sequence as the starting vector of a new round, the process is repeated once along the same switching path. The two generated symmetrical vector sequences are then concatenated in sequence to form a complete 9-segment vector sequence: V 000 →V 100 →V 110 →V 100 →V 000 →V 100 →V 110 →V 100 →V 000 .

[0061] Another approach is a decreasing vector switching path: First, the total number of control switches is turned on decreases sequentially from phase C to phase B, generating a basic vector sequence. Next, following the reverse order of this switching path, the total number of controlled switching devices is increased sequentially from phase B to phase C, thereby constructing a 5-segment symmetrical vector sequence: Finally, repeat the process along the same switching path once more, concatenating the two generated symmetrical vector sequences in order to form a complete 9-segment vector sequence: V 222 →V 221 →V 211 →V 221 →V 222 →V 221 →V 211 →V 221 →V 222 .

[0062] Similarly, the optimal clamping vector sequences for all possible ripples in the four sub-sectors within the basic sector I are summarized in Table 2.

[0063] Table 2. All possible ripple-optimal clamping vector sequences within basic sector I.

[0064]

[0065] In summary, there are a total of 6 optimal ripple clamping vector sequences within the basic sector I. Based on the magnitude of the three-phase reference voltage, the vector sequences of this sector are extended to the entire vector plane, resulting in the vector sequence arrangement patterns in the full vector plane, as shown in Table 3.

[0066] Table 3 shows the arrangement pattern of all vector sequences in the entire vector plane.

[0067]

[0068] In Table 3, the starting vectors used vary depending on the basic sector. V0 can be used as the starting vector for any basic sector; V1 can be used as the starting vector for basic sector I and basic sector VI; V3 can be used as the starting vector for basic sector II and basic sector III; V5 can be used as the starting vector for basic sector IV and basic sector V; V2 can be used as the starting vector for basic sector I and basic sector II; V4 can be used as the starting vector for basic sector III and basic sector IV; V6 can be used as the starting vector for basic sector V and basic sector VI; and V7, V8, V9, and V... 10 V 11 and V 12 These can be used as the starting vectors for their respective basic sectors; the direction and order of the total number of conducting phases are arranged according to the magnitude relationship of the three-phase reference voltages in the vector plane. For example, in basic sector I, the largest phase is phase A, the middle phase is phase B, and the smallest phase is phase C. Therefore, S max =S a S mid =S b S min =S c N represents the basic sector number (N=1~6), and the numbers 1~4 correspond to sub-sectors 1~4 respectively. Since the complete vector sequence is obtained by repeating the 5-segment symmetrical vector sequence twice, that is, the complete vector sequence is symmetrical about 1 / 2 of the switching cycle, only the vector sequence of the first half of the cycle is listed in Table 3.

[0069] (3) Based on the above vector sequence, determine the corresponding switch combinations to generate the switch sequence, and determine the final optimal switch sequence with the minimum peak value of the single-phase circulating current as the optimization objective. Specifically, this includes:

[0070] First, the vector sequence obtained in step (2) is mapped to a changing sequence of the total number of conducting switches in each parallel branch. Then, under the constraint of satisfying the total number of conducting switches, the changing sequence is converted into the corresponding switch state sequence to generate candidate switch sequences. The specific method is as follows:

[0071] The following uses one of the vector sequences V from sub-sector 3 in basic sector I. 200 →V 210 →V 211 →V 210 →V 200 →V 210 →V 211 →V 210 →V 200 For example, let's explain in detail how to construct a switch sequence:

[0072] Define s x1-m and s x2-m These are the x phases of the first and second converters, respectively. The on-state of the upper transistor of the power switch can be either 0 or 1, forming an x-phase switching sequence; define s x-m The sum of the number of power switches that are turned on in the parallel branch of phase x is the total number of power switches that are turned on. It can take the value of 0, 1 or 2, and can form a vector sequence of phase x. Here, m (=1~9) represents the segment number that forms a complete 9-segment vector sequence.

[0073] Based on the above definition, the x-phase vector sequence can be represented as a 1×9 dimensional row vector matrix [S x ]:

[0074] (2)

[0075] The x-phase switching sequence can be represented as a 2×9 dimensional matrix. :

[0076] (3)

[0077] In the formula, S x1 S x2 These are the 1×9 dimensional switch sequence row vectors for the x phases of the two converters, respectively.

[0078] The switching sequence must satisfy the constraints of the corresponding phase vector sequence:

[0079] (4)

[0080] The vector sequence V 200 →V 210 →V 211 →V 210 →V 200 →V 210 →V 211 →V 210 →V 200 The mapping is represented by the sequence of changes in the total number of conducting switches in each phase and parallel branch, resulting in:

[0081] The sequence of changes in the number of conducting devices in the parallel branch of phase A is as follows:

[0082] (5)

[0083] The sequence of changes in the number of conducting devices in the parallel branch of phase B is as follows:

[0084] (6)

[0085] The sequence of changes in the number of conducting devices in the parallel branch of phase C is as follows:

[0086] (7)

[0087] Under the constraint of the total number of conducting phases satisfying equations (5), (6), and (7), the phase change sequence is converted into the corresponding switching state sequence. Among them, one change sequence may correspond to multiple switching state sequences.

[0088] The A-phase change sequence has only one switching state sequence that satisfies the constraint conditions:

[0089] (8)

[0090] The B-phase change sequence contains multiple switching state sequences that satisfy the constraints, including but not limited to:

[0091] (9)

[0092] The C-phase change sequence contains multiple switching state sequences that satisfy the constraints, including but not limited to:

[0093] (10)

[0094] Therefore, the corresponding switching sequence under this vector sequence can be obtained by arbitrarily combining the possible switching state sequences of each phase obtained above, including but not limited to:

[0095] (11)

[0096] Next, switch sequences that cause unidirectional growth of the circulating current are removed from the candidate switch sequences. The specific method is as follows:

[0097] Taking the two candidate switching sequences listed in equation (11) as examples, this paper illustrates the method of eliminating switching sequences based on the rate of change of circulation. Based on Kirchhoff's laws, the expression for the rate of change of zero-sequence circulation can be derived as follows:

[0098] (12)

[0099] The rate of change of zero-sequence circulation is expressed as V DC Using / (2L1) as the base value and normalizing it, we can obtain the zero-sequence circulating current change rate of switch sequence 1 listed in equation (11): 0→1→2→1→0→1→2→1→0, and the zero-sequence circulating current change rate of switch sequence 2: 0→1→0→1→0→-1→0→-1→0. Since the circulating current change rate of switch sequence 1 is maintained at a positive value, it will lead to unidirectional growth of the circulating current. Therefore, this sequence is removed from the candidate switch sequences. Since the total circulating current change of switch sequence 2 is zero, it will not lead to unidirectional growth of the circulating current. Therefore, this sequence is retained as the screening object for the subsequent optimal switch sequence.

[0100] Based on the same switch sequence construction method described above, there are 20 switch sequences that satisfy the constraints in each basic sector. Therefore, there are a total of 120 switch sequences that satisfy the constraints in the entire vector plane.

[0101] Finally, since the 120 selected switching sequences all have redundancy within each sub-sector, the optimization objective is to minimize the peak value of the single-phase circulating current. Therefore, each basic sector is further subdivided into 6 sub-sectors, and the optimal switching sequence is determined. The specific method is as follows:

[0102] According to Kirchhoff's laws, the expression for the rate of change of a single-phase circulation is:

[0103] (13)

[0104] Based on the single-phase circulating current change rate expression (13), the time-domain expression of the single-phase circulating current of each phase under each switching sequence can be obtained. Taking switching sequence 2 in equation (11) as an example, the time-domain expression of the single-phase circulating current of each phase in the first 1 / 2 carrier period is as follows:

[0105] (14)

[0106] Among them, t1, t7, t 13 Corresponding basic voltage vectors V1, V7, V 13 In the synthesized reference voltage vector V ref The duration of each action, calculated using the volt-second balance principle, is expressed as follows:

[0107] (15)

[0108] Among them, V 1α and V 1β This represents the components of the basic voltage vector V1 in a two-phase stationary coordinate system; V 7α and V 7β Represents the basic voltage vector V 13 Components in a two-phase stationary coordinate system; V 13α and V 13β Represents the basic voltage vector V 13 The component V in the two-phase stationary coordinate system rα and V rβ Represents the reference voltage vector V ref The components in a two-phase stationary coordinate system; M represents the modulation degree, M=2|V ref | / V DC ,|V ref | represents the magnitude of the reference voltage vector; θ represents the angle of the reference voltage vector.

[0109] Substituting equation (15) into equation (14), we can obtain the expression for the single-phase circulating current peak value of the above switching sequence 2 as follows:

[0110] (16)

[0111] Based on the same calculation method described above, the single-phase circulating current expressions for the remaining switching sequences can be obtained. The calculation results show that for different switching sequences with the same vector sequence, their single-phase circulating current peak values ​​are the same. Therefore, the single-phase circulating current expressions for each switching sequence within basic sector I can be classified and summarized according to the vector sequence as follows:

[0112] Vector sequence: V0-V 13 -V 14 The expression for the peak value of a single-phase circulating current is:

[0113] (17)

[0114] Vector sequence: V0-V 14 -V 13 The expression for the peak value of a single-phase circulating current is:

[0115] (18)

[0116] Vector sequence: V7-V 13 -V 14 The expression for the peak value of a single-phase circulating current is:

[0117] (19)

[0118] Vector sequence: V7-V 14 -V 13 The expression for the peak value of a single-phase circulating current is:

[0119] (20)

[0120] Vector sequence: V1-V7-V 13 The expression for the peak value of a single-phase circulating current is:

[0121] (twenty one)

[0122] Vector sequence: V2-V7-V 14 The expression for the peak value of a single-phase circulating current is:

[0123] (twenty two)

[0124] Based on the calculated single-phase circulating current peak values ​​for each vector sequence, the circulating current peak values ​​of each switching sequence are analyzed and compared. According to the real-time position of the reference voltage vector, the optimal switching sequence at that position that minimizes the circulating current peak value is determined. Finally, the modulation region within basic sector I that optimizes the single-phase circulating current peak value is obtained, such as... Figure 3As shown in (b), the basic sector I is further subdivided into 6 sub-sectors, and the range expression for each sub-sector is as follows:

[0125] (twenty three)

[0126] in, These are the per-unit values ​​of the three-phase reference voltage vectors, with a per-unit reference value of V. DC .

[0127] Based on the magnitude relationship of the three-phase reference voltage in each basic sector, the expression can be extended to the entire vector plane. The expressions for each sub-sector range are summarized as follows:

[0128] (twenty four)

[0129] in, .

[0130] Table 4 lists the optimal switching sequences determined in each sub-sector with the objective of minimizing the peak value of the single-phase circulating current. The values ​​in parentheses in the table represent the zero-sequence circulating current rate of change via V. DC The result after normalization using / (2L1) as the base value. It should be noted that swapping the switching sequences of the two converters yields another equivalent optimal sequence. These two sequences are opposite only in the polarity (sign) of the circulating current, while remaining identical in key performance indicators such as output current ripple characteristics and circulating current peak value. Therefore, either one can be chosen in practical applications; Table 4 only shows one optimal switching sequence.

[0131] Table 4 Optimal Switching Sequence within Basic Sector I

[0132]

[0133] (4) Based on the optimal switching sequence obtained above, a carrier modulation scheme based on a combination of increasing and decreasing sawtooth carriers is constructed, and the configuration of the carrier and modulation wave is selected according to the symmetry of the switching sequence. Specifically, this includes:

[0134] First, to generate the target optimal sequence, the comparison method between the modulated wave and the carrier wave needs to be configured. This configuration method is mainly determined based on the symmetry of the optimal switching sequence within the carrier period.

[0135] When the switching sequence is asymmetrical, a comparison method between multiple modulated waves and a single carrier is used, and the switching state is determined based on the comparison relationship between the modulated waves and the carrier. Specifically, the four logic output modes of the switching transistors are defined as operation modes 1 to 4, such as... Figure 4 As shown in (a):

[0136] Operation mode 1: If modulation wave 1 is greater than or equal to the incremental carrier wave or modulation wave 2 is less than or equal to the incremental carrier wave, then output a high level to turn on the corresponding phase switch transistor;

[0137] Operation mode 2: If modulation wave 1 is greater than or equal to the incremental carrier wave or modulation wave 2 is less than or equal to the incremental carrier wave, then output a high level to turn on the corresponding phase switch transistor;

[0138] Operation mode 3: If modulation wave 1 is less than or equal to the incrementing carrier and modulation wave 2 is greater than or equal to the incrementing carrier, then output a high level to turn on the corresponding phase switch transistor;

[0139] Operation mode 4: If modulation wave 1 is less than or equal to the decrementing carrier and modulation wave 2 is greater than or equal to the decrementing carrier, then output a high level to turn on the corresponding phase switch transistor;

[0140] Among them, modulation wave 2 is greater than modulation wave 1.

[0141] When the switching sequence is symmetrical, a comparison method between a single modulated wave and multiple carriers is used, and the switching state is determined based on the comparison relationship between the modulated wave and the carriers. Specifically, the logic output mode of the switching transistor is defined as action mode 5, such as... Figure 4 As shown in (b):

[0142] Operation mode 5: If the modulated wave is greater than both the incrementing carrier and the decrementing carrier, a high level is output to turn on the corresponding phase switch.

[0143] Next, based on the above carrier and modulation wave configuration, the modulation wave expression corresponding to each optimal switching sequence is calculated. Taking the optimal switching sequence SQ1 in basic sector I as an example, its modulation wave expression and the corresponding switching transistor logic output mode for each phase and parallel branch can be calculated:

[0144] (25)

[0145] Among them, u m-a1 and u m-a2 Corresponding to the two modulated waves on phase A, u m-b1 and u m-b2 The two modulated waves corresponding to phase B; u m-c1 and u m-c2 The two modulated waves corresponding to phase C; u* a u* b and u* c They represent V respectively DC The three-phase voltage per unit value is used as the reference; Operation mode 1, Operation mode 2, and Operation mode 5 indicate the logic output mode of the switching transistor; d0, d 13 and d 14 Representing vectors V0 and V 13 and V 14The duty cycle of the action can be obtained from the volt-second balance principle:

[0146] (26)

[0147] Similarly, the modulation waveform expressions for the switching sequences of the remaining sub-sectors within basic sector I and the corresponding switching transistor logic output methods for each phase and parallel branch can be derived as follows:

[0148] (27)

[0149] (28)

[0150] (29)

[0151] Finally, based on the same calculation method described above, the modulation wave expressions for each switching sequence in the other five basic sectors and the corresponding switching transistor logic output methods for each phase and parallel branch can be derived. Finally, based on the magnitude relationship of the reference voltage in each basic sector, the results are extended to the entire vector plane and summarized as follows:

[0152] (30)

[0153] (31)

[0154] (32)

[0155] Among them, u* max u* mid and u* min They represent V respectively DC The per-unit values ​​of the maximum, intermediate, and minimum phase three-phase reference voltages; u m-max1 u m-max2 These correspond to the two modulation waves of the phase with the largest per-unit value of the three-phase reference voltage; u m-mid1 u m-mid2 The two modulation waves correspond to the per-unit values ​​of the intermediate phases of the three-phase reference voltage, respectively; u m-min1 u m-min2 These are two modulation waves corresponding to the minimum phase per unit value of the three-phase reference voltage; Operation modes 1 to 5 represent the logic output mode of the switching transistor.

[0156] (5) Based on the above optimal switching sequence, the carrier polarity is alternately configured within adjacent carrier cycles so that the switching signals of the same bridge arm form a symmetrical distribution within two consecutive carrier cycles. Specifically, this includes:

[0157] For a switching sequence that is asymmetric within a unit carrier period, alternating incrementing and decrementing sawtooth carriers within adjacent carrier periods ensures that the switching sequences of two adjacent carrier periods are symmetrical about the center of the two carrier periods. Taking the switching sequence SQ1 within basic sector I as an example, the specific implementation of the method for achieving symmetry of the switching sequence over two carrier periods proposed in this invention is as follows:

[0158] like Figure 5 As shown, the switching sequences of phases B and C in the switching sequence SQ1 are asymmetrical within a single carrier cycle, resulting in the inability of the positive and negative areas of the single-phase circulating current in phases B and C to cancel each other out within a carrier cycle. This causes the average value of the circulating current to be non-zero. Furthermore, this non-zero average value persists throughout the entire fundamental cycle, inevitably introducing a low-frequency single-phase circulating current component, leading to inductor core saturation and affecting system stability. Combining the definition of the single-phase circulating current rate of change and the expressions for the duty cycles of each vector, the expression for the average value of the single-phase circulating current under this sequence is further calculated [Equation (33)]. This formula further confirms theoretically that the asymmetry of the switching sequence introduces a low-frequency single-phase circulating current.

[0159] (33)

[0160] To address the aforementioned issues and suppress the inherent low-frequency single-phase circulating current caused by asymmetric switching sequences, the original switching sequence SQ1 remains unchanged during the k-th carrier cycle. The first converter uses an increasing sawtooth carrier, corresponding to the logic output mode of the A-phase switch being operation mode 5, and the logic output modes of the B-phase and C-phase switches being operation mode 1. The second converter uses a decreasing sawtooth carrier, corresponding to the logic output mode of the A-phase switch being operation mode 5, and the logic output modes of the B-phase and C-phase switches being operation mode 2. During the (k+1)-th carrier cycle, after alternating the carrier polarity configuration, the first converter... To use a decreasing sawtooth carrier, the logic output mode of the A-phase switch is set to operation mode 5, while the logic output modes of the B-phase and C-phase switches are both changed to operation mode 2. The second converter is then changed to use an increasing sawtooth carrier, with the logic output mode of the A-phase switch set to operation mode 5, and the logic output modes of the B-phase and C-phase switches set to operation mode 1. Using the end vector of the original sequence SQ1 as the mirror center, the original sequence is mirrored and reversed; that is, the end vector of the original sequence becomes the start vector of the reversed sequence, and vice versa. The reversed switching sequence is V0 (V... 111 / V 111 -V 14 (V) 110 / V 111 -V 13 (V) 110 / V 101 V 14 (V) 110 / V 111-V0(V 111 / V 111 -V 14 (V) 111 / V 110 -V 13 (V) 101 / V 110 -V 14 (V) 111 / V 110 -V0(V 111 / V 111 The above method achieves an equivalent symmetrical distribution of the switching signals of each phase in adjacent carrier cycles by alternately configuring the carrier polarity. The positive and negative areas of the circulating current cancel each other out, and the average value is zero, thus ultimately suppressing the low-frequency single-phase circulating current.

[0161] Other switching sequences also use the above method to suppress low-frequency single-phase circulating current. The method is summarized as follows: Taking two adjacent carrier cycles as an adjustment period, in the k-th carrier cycle, the first converter uses an increasing sawtooth carrier and the second converter uses a decreasing sawtooth carrier, generating switching signals based on the preset switching transistor logic output mode; in the k+1-th carrier cycle, the carrier polarity used by the two converters is alternately configured, that is, the first converter uses a decreasing sawtooth carrier and the second converter uses an increasing sawtooth carrier, while the switching transistor logic output mode of the corresponding phases of the two converters is exchanged, so that the switching signals of the same bridge arm form a symmetrical distribution in two consecutive carrier cycles, and finally achieve the suppression of the inherent low-frequency single-phase circulating current of the proposed switching sequence in two carrier cycles.

[0162] Finally, the effectiveness of the proposed ripple-optimal clamping modulation method and its inherent low-frequency single-phase circulating current suppression scheme is verified through simulation. The simulation parameters are shown in the table below.

[0163] Table 5 Simulation Parameters

[0164]

[0165] The simulation mainly demonstrates the modulation algorithm proposed in this invention and the simulation results after suppressing the inherent low-frequency circulation of the sequence using the method proposed in this invention. Figures 6-8 The proposed modulation method is obtained by using the proposed modulation algorithm at a modulation depth of 0.8, and the simulation results are shown after using the proposed method to suppress the inherent low-frequency circulation of the sequence. Figure 6 In the middle (a), the three-phase parallel currents of the proposed modulation algorithm are shown. Figure 6 (b) shows the single-phase circulating current of phase A in the proposed modulation algorithm. Figure 6 (c) shows the zero-sequence circulating waveform of the proposed modulation algorithm; Figure 7(a) shows the three-phase parallel current after suppressing the inherent low-frequency circulating current of the sequence using the method proposed in this invention. Figure 7 (b) shows the single-phase circulation of phase A after suppressing the inherent low-frequency circulation of the sequence using the method proposed in this invention. Figure 7 (c) shows the zero-sequence circulation waveform after suppressing the inherent low-frequency circulation of the sequence using the method proposed in this invention; Figure 8 In the middle (a), the circulating current spectrum of phase A of the two parallel converters is shown in the frequency range of 0Hz to 700Hz. Figure 8 (b) shows the A-phase circulating current spectrum of the two parallel converters at a frequency of 0Hz to 700Hz after suppressing the inherent low-frequency circulating current of the sequence using the method proposed in this invention; Figure 8 (c) shows the zero-sequence circulating current spectrum of the two parallel converters in the frequency range of 0Hz to 700Hz. Figure 8 (d) shows the zero-sequence circulating current spectrum of two parallel converters at frequencies from 0 Hz to 700 Hz after suppressing the inherent low-frequency circulating current of the sequence using the method proposed in this invention.

[0166] As can be seen from the simulation results, the total harmonic distortion (THD) of the output current ripple of the modulation algorithm proposed in this invention is as low as 0.91%, and the peak value of the parallel branch circulating current is within ±2A, achieving synergistic optimization of ripple, switching loss and parallel branch circulating current.

[0167] After further introducing a low-frequency circulating current suppression strategy, the spectrum of single-phase / zero-sequence circulating current shows that the low-frequency components of both single-phase and zero-sequence circulating currents are effectively suppressed to near zero. Simultaneously, the output current ripple THD increases slightly to 0.92%, and the peak value of the parallel branch circulating current remains within ±2A. Therefore, the proposed control method effectively suppresses low-frequency circulating currents while preserving the original high-frequency performance indicators.

[0168] In summary, the modulation strategy proposed in this invention can effectively reduce output current ripple and suppress parallel branch circulating current, while simultaneously reducing switching losses and improving system performance.

[0169] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the protection scope of the present invention.

Claims

1. A ripple-optimal clamping modulation method for two parallel converters, characterized in that: include: Based on the equivalent voltage vector plane of two parallel converters, the equivalent voltage vector plane is divided into multiple equilateral triangular regions of equal area according to the principle of near three-vector synthesis. The vertices of each equilateral triangle are composed of the basic voltage vector and its redundant voltage vector. Within each equilateral triangle region, the basic voltage vector or its redundant voltage vector corresponding to any vertex is used as the starting vector. By controlling the total number of conducting devices in each parallel branch of the three phases to change in an increasing or decreasing manner, the voltage vectors of the other two vertices are switched sequentially, and the starting vector is returned in the reverse order of the switching path to construct a 5-segment symmetrical vector sequence. Based on the 5-segment symmetrical vector sequence, with its last vector as the starting vector of a new round, the same switching path is repeated once. The two generated symmetrical vector sequences are then sequentially spliced ​​together to form a 9-segment clamping vector sequence with optimal ripple, thereby constructing a set of clamping vector sequences with optimal output current ripple. Each segment of the 9-segment clamping complete vector sequence with optimal ripple corresponds to a voltage vector. Based on the clamping vector sequence set, the corresponding switch combination is determined to generate the switch sequence. Switch sequences that cause unidirectional growth of the circulating current in the three-phase parallel branch are eliminated, and the optimal switch sequence is determined with the minimum peak value of the single-phase circulating current as the optimization objective. The optimal switching sequence is used to generate a modulation wave and construct a carrier modulation scheme. By alternately configuring the carrier polarity in adjacent carrier cycles, the switching signals of the same bridge arm are symmetrically distributed in two consecutive carrier cycles.

2. The ripple-optimal clamping modulation method for two parallel converters according to claim 1, characterized in that: The process of dividing the equivalent voltage vector plane into multiple equilateral triangular regions of equal area according to the principle of near-three-vector synthesis is as follows: the voltage vector plane is initially divided into 6 basic sectors, each basic sector is further divided into 4 equilateral triangles of equal area, and finally the voltage vector plane is divided into 24 equilateral triangular regions of equal area, wherein the vertices of each equilateral triangle are the basic vectors and their redundant vectors on the vector plane.

3. The ripple-optimal clamping modulation method for two parallel converters according to claim 1, characterized in that: The construction of the 5-segment symmetrical vector sequence is as follows: Within each equilateral triangle region, the basic voltage vector or its redundant voltage vector corresponding to any vertex is used as the starting vector. By controlling the total number of conducting switches in each parallel branch of the three phases to change in an increasing or decreasing manner, the voltage vectors at the vertices of the equilateral triangle are switched sequentially, so that each of the three vertex voltage vectors is visited once. Then, with the last visited vertex voltage vector as the center of symmetry, the starting vector is returned in reverse order of the switching path to construct the 5-segment symmetrical vector sequence.

4. The ripple-optimal clamping modulation method for two parallel converters according to claim 1, characterized in that: The specific steps for constructing the clamping vector sequence set with optimal output current ripple are as follows: select any vertex vector as the starting vector, change the way the total number of conducting switches in each parallel branch of the three phases increases or decreases, and construct two different vector sequences; since the three vertex vectors of an equilateral triangle can all be used as starting vectors, a total of 6 vector sequences are constructed in each basic sector, and there are a total of 36 clamping vector sequences with optimal ripple in the entire vector plane, thus obtaining the clamping vector sequence set.

5. The ripple-optimal clamping modulation method for two parallel converters according to claim 1, characterized in that: The method for generating a switch sequence includes: mapping a clamping vector sequence to a changing sequence of the total number of conducting switches in each parallel branch of the phase, and converting the changing sequence into a corresponding switch state sequence under the condition of satisfying the constraint of the total number of conducting switches, thereby generating a candidate switch sequence.

6. The ripple-optimal clamping modulation method for two parallel converters according to claim 5, characterized in that: The determination of the optimal switching sequence specifically includes: First, removing switching sequences from the candidate switching sequences that cause unidirectional growth of circulating current; Second, within each equilateral triangle region, based on the real-time position of the reference voltage vector, comparing the single-phase circulating current peak values ​​of the switching sequences, and selecting the switching sequence with the smallest peak value as the optimal switching sequence corresponding to the position of the reference voltage; Finally, according to the distribution law of the selected optimal switching sequences with the position of the reference voltage vector, each basic sector is refined into 6 sub-sectors, and each sub-sector corresponds to a unique optimal switching sequence.

7. The ripple-optimal clamping modulation method for two parallel converters according to claim 1, characterized in that: The carrier wave is a sawtooth wave, including an incrementing carrier and a decrementing carrier. The incrementing carrier uses an incrementing counting method, which resets to zero after reaching a set period value and enters the next period. The decrementing carrier uses a decrementing counting method, which decrements from the set period value to zero, then reassigns the period value and enters the next period.

8. The ripple-optimal clamping modulation method for two parallel converters according to claim 1, characterized in that: Generating a modulation wave and constructing a carrier modulation scheme based on the optimal switching sequence specifically includes: The carrier modulation scheme is constructed as follows: the configuration of the carrier modulation scheme is determined according to the symmetry of the switching sequence within the carrier period. When the switching sequence is asymmetrical, a comparison between multiple modulated waves and a single carrier is used; when the switching sequence is symmetrical, a comparison between a single modulated wave and multiple carriers is used. The modulation wave generation method is as follows: based on the action time of each vector in the optimal switching sequence, the duty cycle of each parallel bridge arm switch is calculated; and according to the carrier modulation scheme, the modulation wave expression corresponding to each optimal switching sequence is calculated.

9. The ripple-optimal clamping modulation method for two parallel converters according to claim 8, characterized in that: The comparison method between the multi-modulated wave and the single carrier is as follows: when comparing two modulated waves with a single carrier, the switching state is determined based on the comparison relationship between the modulated wave and the carrier, including: If modulation wave 1 is greater than or equal to the incremental carrier wave, or modulation wave 2 is less than or equal to the incremental carrier wave, then a high level is output to turn on the corresponding phase switch transistor. If modulation wave 1 is less than or equal to the decrementing carrier wave, or modulation wave 2 is greater than or equal to the decrementing carrier wave, then a high level is output to turn on the corresponding phase switch. If modulation wave 1 is less than or equal to the incrementing carrier wave and modulation wave 2 is greater than or equal to the incrementing carrier wave, then output a high level to turn on the corresponding phase switch transistor; If modulation wave 1 is less than or equal to the decrementing carrier wave and modulation wave 2 is greater than or equal to the decrementing carrier wave, then output a high level to turn on the corresponding phase switch transistor; Among them, modulation wave 2 is greater than modulation wave 1; The method of comparing a single modulated wave with multiple carriers is as follows: when comparing a single modulated wave with two carriers, the switching state is determined based on the comparison relationship between the modulated wave and the carriers, including: If the modulated wave is greater than both the incrementing and decrementing carrier waves, a high level is output to turn on the corresponding phase switch.

10. The ripple-optimal clamping modulation method for two parallel converters according to claim 1, characterized in that: The alternating configuration of carrier polarity within adjacent carrier periods specifically refers to: For a switching sequence that is asymmetric within a unit carrier period, incremental sawtooth carriers and decremental sawtooth carriers are alternately used in adjacent carrier periods, so that the switching sequences of two adjacent carrier periods are symmetrical about the two carrier periods.

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