Cross-module atpg test method, device, system, chip, equipment and medium

Abstract

The embodiment of the application discloses a cross-module ATPG test method, device, system, chip, equipment and medium, and belongs to the technical field of integrated circuit testing. The method comprises the following steps: sequentially writing ATPG test vectors provided by a single EDT module into a first logic module group and a second logic module group through a first scan chain, a first buffer chain and a second scan chain; and returning ATPG test responses read out sequentially through a fourth scan chain, a second buffer chain and a third scan chain to the EDT module. The first logic module group and the second logic module group are arranged on the two sides of an untestable hard core module, the first scan chain and the third scan chain are opposite in the direction of displacement in the first logic module group, the second scan chain and the fourth scan chain are opposite in the direction of displacement in the second logic module group, and the first buffer chain and the second buffer chain are arranged in the hard core module and are opposite in direction. Only a single EDT module is needed to realize ATPG test across the hard core module.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit testing technology, and in particular to a cross-module Automatic Test Pattern Generation (ATPG) testing method, apparatus, system, chip, electronic device and computer-readable storage medium. Background Technology

[0002] As semiconductor processes advance to advanced nodes, large-scale system-on-chips (SoCs) typically employ modular design methodologies, with multiple teams developing different functional modules in parallel. In Design for Test (DFT) of chips, ATPG (Automatic Test-Testing Group) is a key method for verifying chip manufacturing quality. Embedded Deterministic Test (EDT), as a test data compression technique, can significantly reduce the amount of scanned test data and test time.

[0003] In large-scale SoC chips, multiple logic modules are typically located on either side of an untestable hard IP module, and these modules have functional interaction requirements, necessitating unified ATPG testing. Since the hard IP module's internal structure is a black box, external scan signals are prohibited from penetrating it. Existing methods make it difficult to ensure that scan signals can safely cross the hard IP module using only a single EDT module. Using multiple EDT modules or additional wiring increases chip area, power consumption, or layout and routing complexity, and also makes it impossible to directly pass through the hard IP using a single scan chain.

[0004] Therefore, an ATPG testing solution is needed that can reuse a single set of EDT resources and safely cross untestable hard core modules. Summary of the Invention

[0005] The present invention proposes a cross-module ATPG testing method, apparatus, system, chip, device and medium, which realizes ATPG testing of scan signals across untestable hard core modules without increasing additional hardware overhead.

[0006] A cross-module ATPG testing method, comprising:

[0007] The ATPG test vector provided by a single EDT module is sequentially written into the first logic module group and the second logic module group via the first scan chain, the first buffer chain and the second scan chain.

[0008] The ATPG test response read from the second logic module group and the first logic module group is returned to the EDT module via the fourth scan chain, the second buffer chain and the third scan chain in sequence.

[0009] The first logic module group is located on the first side of the unmeasurable hard core module, the second logic module group is located on the second side of the hard core module, the first scan chain and the third scan chain shift in opposite directions within the first logic module group, the second scan chain and the fourth scan chain shift in opposite directions within the second logic module group, and the first buffer chain and the second buffer chain are disposed in the hard core module.

[0010] In one implementation, the first buffer chain and the second buffer chain are two independent channels formed by reusing the buffer chain used for functional signal interaction in the hard core module.

[0011] In one implementation, it further includes:

[0012] In response to receiving a valid test mode selection signal, the input of the first buffer chain is switched from the function signal corresponding to the first buffer chain to the ATPG test vector, and the input of the second buffer chain is switched from the function signal corresponding to the second buffer chain to the ATPG test response.

[0013] In one embodiment, the first scan chain includes a first group of registers in the first logic module group, wherein each register in the first group of registers is connected in series; the third scan chain includes a second group of registers in the first logic module group, wherein each register in the second group of registers is connected in series; the second scan chain includes a third group of registers in the second logic module group, wherein each register in the third group of registers is connected in series; and the fourth scan chain includes a fourth group of registers in the second logic module group, wherein each register in the fourth group of registers is connected in series.

[0014] In one embodiment, the first logic module group includes multiple logic modules, and the scan sub-chains of each of the multiple logic modules are connected in series to form the first scan chain and the third scan chain; the second logic module group includes multiple logic modules, and the scan sub-chains of each of the multiple logic modules are connected in series to form the second scan chain and the fourth scan chain.

[0015] In one implementation, the scan subchain of the logic module directly adjacent to the hard core module includes registers that are manually connected in series.

[0016] In the scan subchain of logic modules that are not directly adjacent to the hard core module, there are registers that are automatically concatenated using EDA tools.

[0017] In one implementation, it further includes:

[0018] Based on the number of registers in the second logic module group that need to be tested for ATPG, the ATPG test vector and the bit width of the ATPG test response are statically determined.

[0019] A cross-module ATPG testing device, comprising:

[0020] The write module is used to write the ATPG test vector provided by a single EDT module into the first logic module group and the second logic module group in sequence through the first scan chain, the first buffer chain and the second scan chain.

[0021] The readout module is used to return the ATPG test response read from the second logic module group and the first logic module group sequentially via the fourth scan chain, the second buffer chain and the third scan chain to the EDT module;

[0022] The first logic module group is located on the first side of the unmeasurable hard core module, the second logic module group is located on the second side of the hard core module, the first scan chain and the third scan chain shift in opposite directions within the first logic module group, the second scan chain and the fourth scan chain shift in opposite directions within the second logic module group, and the first buffer chain and the second buffer chain are disposed in the hard core module.

[0023] A cross-module ATPG testing system, comprising:

[0024] A single EDT module is used to provide ATPG test vectors and receive ATPG test responses;

[0025] The first logic module group is located on the first side of the unmeasurable hard core module. The first logic module group includes a first scan chain and a third scan chain. The first scan chain and the third scan chain have opposite shifting directions within the first logic module group.

[0026] The second logic module group is located on the second side of the hard core module. The second logic module group includes a second scan chain and a fourth scan chain. The second scan chain and the fourth scan chain have opposite shift directions within the second logic module group.

[0027] The first and second buffer chains are configured in the hard core module;

[0028] The output of the EDT module, the first scan chain, the first buffer chain, and the second scan chain are connected in sequence to form the write path of the ATPG test vector; the fourth scan chain, the second buffer chain, the third scan chain, and the input of the EDT module are connected in sequence to form the read path of the ATPG test response.

[0029] In one implementation, the first buffer chain and the second buffer chain are two independent channels formed by reusing the buffer chain used for functional signal interaction in the hard core module.

[0030] In one embodiment, a test mode selection signal input terminal is also included for receiving a test mode selection signal;

[0031] The test mode selection signal is used to switch the functional signal corresponding to the first buffer chain to the ATPG test vector when it is active, and to switch the input of the second buffer chain from the functional signal corresponding to the second buffer chain to the ATPG test response.

[0032] In one embodiment, the first scan chain includes a first group of registers in the first logic module group, wherein each register in the first group of registers is connected in series; the third scan chain includes a second group of registers in the first logic module group, wherein each register in the second group of registers is connected in series; the second scan chain includes a third group of registers in the second logic module group, wherein each register in the third group of registers is connected in series; and the fourth scan chain includes a fourth group of registers in the second logic module group, wherein each register in the fourth group of registers is connected in series.

[0033] A chip comprising the cross-module ATPG test system described above.

[0034] An electronic device, comprising:

[0035] processor;

[0036] The memory stores a computer program executable by the processor for causing the processor to perform the cross-module ATPG test method as described above.

[0037] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the cross-module ATPG testing method as described above.

[0038] As can be seen from the above technical solution, in the embodiments of the present invention, only a single EDT module is needed to complete the ATPG test of the logic modules on both sides of the hard core. Compared with the existing solution that deploys independent EDT modules on both sides of the hard core, the chip area and power consumption are effectively controlled, and the test control logic is also simpler. Compared with the existing solution that bypasses the hard core with additional wiring, there is no need to modify the existing physical layout, avoiding wiring congestion and timing convergence problems. Compared with the existing single-chain solution that penetrates the hard core, the scan signal does not need to enter the sensitive area inside the hard core, does not violate the hard core design rules, and does not affect the normal function of the hard core. In addition, test vector loading and test response readout can be performed simultaneously, and the test time is shortened.

[0039] Furthermore, the first and second buffer chains reuse the buffer chain structure originally used for functional signal interaction in the hard core module. In functional mode, they serve functional signal transmission, and in test mode, they seamlessly switch to test signal channels. The same hardware resource performs different functions in the two modes, eliminating the need for an additional dedicated scan channel for testing purposes and avoiding physical conflicts between functional and test signals within the hard core. Moreover, the write and read directions use different register groups, which are physically independent and do not share resources. Furthermore, modules directly adjacent to the hard core use a manual chaining method, allowing precise control of register connection order and port positions to ensure accurate signal connection with the hard core buffer chain ports; external modules use EDA tools for automatic chaining, reducing manual intervention and design complexity, while the tools can be optimized based on timing and load. Attached Figure Description

[0040] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which will make the above and other features and advantages of the present invention more apparent to those skilled in the art. In the drawings:

[0041] Figure 1 This is an exemplary flowchart of a cross-module ATPG testing method according to an embodiment of the present invention.

[0042] Figure 2 This is a schematic diagram of a cross-module ATPG testing system according to an embodiment of the present invention.

[0043] Figure 3 This is a schematic diagram of the module layout and signal flow of an application example of the cross-module ATPG testing method according to an embodiment of the present invention.

[0044] Figure 4 This is an exemplary structural diagram of a cross-module ATPG testing apparatus according to an embodiment of the present invention.

[0045] Figure 5 This is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the following embodiments are provided to further illustrate the invention in detail. The nouns and pronouns referring to "person" in this patent application are not limited to specific genders.

[0047] For the sake of brevity and intuitiveness, the following description uses several representative embodiments to illustrate the solution of the present invention. Numerous details in the embodiments are only used to aid in understanding the solution of the present invention. However, it is obvious that the technical solution of the present invention can be implemented without being limited to these details. To avoid unnecessarily obscuring the solution of the present invention, some embodiments are not described in detail, but only a framework is given. In the following text, "comprising" means "including but not limited to," and "according to..." means "at least according to..., but not limited to only according to...". Due to Chinese language habits, unless the quantity of a component is specifically indicated below, it means that the component can be one or more, or can be understood as at least one.

[0048] In chip design-for-testability, ATPG testing requires that scan signals be able to be transmitted completely between test modules. For multiple logic modules that are physically separated by hard core modules, the cross-module transmission of scan signals faces challenges: the internal structure of a hard core module is a black box, and its design rules explicitly prohibit external scan signals from penetrating internal registers.

[0049] To address this constraint, existing technologies have developed several solutions, including:

[0050] (a) Single EDT direct connection solution

[0051] Logically, this scheme treats the modules distributed on both sides of the hard core as a complete scan chain, controlled by a single EDT module. The scan chains of all modules are connected end-to-end, with scan signals passing through each module sequentially. However, since the hard core module is physically located between the modules on both sides, the scan chain must inevitably pass through the hard core. The hard core module typically contains independent clock domains, phase-locked loops, or sensitive analog circuits. When the scan signal passes through, it may cause timing disturbances or functional conflicts, leading to malfunctions in the hard core. Therefore, this scheme is not permitted in practical engineering.

[0052] (ii) Multiple EDT Independent Scheme

[0053] This solution deploys independent EDT modules on both sides of the hard core. The left EDT controls the testing of the left module, and the right EDT controls the testing of the right module. Testing on both sides is performed independently, eliminating the need for scanning signals to cross the hard core. However, multiple EDT modules mean the chip requires additional compression and decompression logic, independent test ports, and more complex test clock management, significantly increasing chip area and power consumption. Furthermore, the collaborative generation of test vectors on both sides and the unified management of test responses also increase the testing time of the Automated Test Equipment (ATE).

[0054] (iii) Additional cabling solutions

[0055] This approach involves routing around the hard core to physically connect the scan chains on both sides, preventing scan signals from entering the hard core. However, since the chip's physical layout is already complete, this routing requires additional metal layers, increasing the complexity and risk of the physical design.

[0056] (iv) Hierarchical ATPG regimen

[0057] Hierarchical ATPG achieves test isolation by inserting wrapper chains around submodules. In this approach, each submodule has an independent scan chain, and signal isolation and transmission between modules are achieved through wrapper cells in test mode. This approach eliminates the need for scan signals to traverse other modules, but it requires inserting additional wrapper cells at the boundaries of each submodule, increasing design complexity and area overhead. Furthermore, the wrapper cells themselves must be included in the test coverage, further increasing the number of test vectors and test time.

[0058] The aforementioned solutions, addressing logical connectivity, physical partitioning, spatial bypassing, and hierarchical isolation respectively, all failed to achieve a balance between not increasing hardware overhead and not violating hard-core rules. The fundamental reason is that these solutions all treat the hard-core module as an obstacle to be bypassed or avoided, failing to utilize the existing structural resources of the hard-core module itself.

[0059] To address the aforementioned issues, this invention proposes a reverse approach: instead of viewing the hard core module as an obstacle to bypass, it utilizes the existing buffer chain (BUF Chain) within the hard core module for functional signal interaction as a transmission channel for the scan signal, allowing the scan signal to traverse the hard core module via the buffer chain channel within the hard core module.

[0060] Specifically, in normal functional mode, the hard core module needs to interact with the logic modules on both sides. To drive long-distance signal transmission, the hard core typically has two sets of buffer chains with opposite directions: one set for signal transmission from left to right, and the other set for signal transmission from right to left. These buffer chains transmit functional data in functional mode, and can be reused as transmission channels for scan signals in test mode. Based on this reuse concept, the embodiment of this invention constructs two physically independent, oppositely oriented complete scan paths:

[0061] (1) Write path: The ATPG test vector output by the EDT module is written to the logic modules on both sides of the hard core in sequence through the first side scan chain, the first buffer chain in the hard core, and the second side scan chain.

[0062] (2) Readout path: The test response passes through the second side scan chain, the second buffer chain in the hard core, and the first side scan chain, and returns to the EDT module.

[0063] The write path and read path can operate simultaneously, enabling parallel loading of test vectors and reading of test responses. By reusing the existing buffer chain of the hard core, this embodiment of the invention can achieve ATPG testing across untestable hard cores using only a single EDT module, without adding extra hardware or changing the internal structure of the hard core, while supporting independent development and testing of modules on both sides of the hard core.

[0064] The above disclosure details the technical defects existing in the relevant technology, the causes of these defects, and the thought process and analysis involved in overcoming them. In fact, the understanding of these technical defects is not common knowledge in the field, but rather a novel discovery made by the inventors during their research. Furthermore, the tracing of the causes of these defects and the thought process and analysis involved in overcoming them are also the results of the inventors' gradual analysis during the actual research process, and are not common knowledge in the field.

[0065] Figure 1 This is an exemplary flowchart of a cross-module ATPG testing method according to an embodiment of the present invention. Figure 1 As shown, the method includes:

[0066] Step 101: Write the ATPG test vector provided by a single EDT module into the first logic module group and the second logic module group in sequence through the first scan chain, the first buffer chain and the second scan chain.

[0067] In this implementation, a single EDT module provides the ATPG test vector. Here, "single" means that only one EDT module is used in the entire test architecture, unlike existing technologies that instantiate independent EDT modules on both sides of the hard core. By using only a single EDT module, the increased chip area and power consumption issues associated with multiple EDT solutions are avoided.

[0068] The ATPG test vector refers to the serial test data stream obtained by the EDT module after decompressing the compressed test data input from the ATE device. This data stream is used to load into the registers of each scan chain inside the chip to apply preset logic stimuli.

[0069] The first and second logic module groups are collections of logic modules that need to be tested, located on either side of the untestable hard core module (i.e., the hard core module does not participate in ATPG testing). Specifically, the first logic module group is located on the first side of the hard core module, and the second logic module group is located on the second side of the hard core module (the first and second sides are opposite to each other; such as left-right, up-down, etc.). The hard core module is physically located between the first and second logic module groups. The first scan chain is formed by concatenating the registers to be tested in the first logic module group, and is used to provide a serial shift channel in the test vector write direction. The second scan chain is formed by concatenating the registers to be tested in the second logic module group, and is used to receive the test vector transmitted through the first buffer chain and write it into the second logic module group. The first buffer chain is set in the hard core module to provide a channel for transmitting signals from the first side to the second side of the hard core module.

[0070] Specifically, after the ATPG test vector is output in parallel from the output of the EDT module, it first enters the input of the first scan chain, passing through each register in the first scan chain sequentially, thus being written into the first logic module group. Subsequently, the test vector is output from the output of the first scan chain, enters the input of the first buffer chain, passes through the hard core module, and is output from the output of the first buffer chain. Next, the test vector enters the input of the second scan chain, passing through each register in the second scan chain sequentially, thus being written into the second logic module group. During this process, the test vector is sequentially written to all target registers of the logic modules on both sides of the hard core module in a serial shift manner, completing the loading of the test vector.

[0071] Step 102: The ATPG test response read from the second logic module group and the first logic module group in sequence via the fourth scan chain, the second buffer chain and the third scan chain is returned to the EDT module; wherein the first logic module group is located on the first side of the unmeasurable hard core module, the second logic module group is located on the second side of the hard core module, the first scan chain and the third scan chain shift in opposite directions within the first logic module group, the second scan chain and the fourth scan chain shift in opposite directions within the second logic module group, and the first buffer chain and the second buffer chain are set in the hard core module.

[0072] In this embodiment, the ATPG test response refers to the logic result data generated and captured in the scan chain registers by the combinational logic within the first and second logic module groups based on the loaded test vectors under the capture clock. This data is shifted out of the scan chain in a serial data stream manner and used to compare with the expected results to determine whether there are manufacturing defects in the chip. The shift direction refers to the direction in which the scan data flows in the scan chain, that is, the direction from the input end to the output end of the scan chain.

[0073] The first scan chain shifts from the first side to the second side of the hard core module. The third scan chain consists of the registers to be tested in the first logic module group connected in series, and its shift direction is opposite to that of the first scan chain, i.e., from the second side to the first side. The second scan chain also shifts from the first side to the second side of the hard core module. The fourth scan chain consists of the registers to be tested in the second logic module group connected in series, and its shift direction is opposite to that of the second scan chain, i.e., from the second side to the first side. The first buffer chain and the second buffer chain are respectively set in the hard core module, wherein the first buffer chain is used to provide a channel for transmitting signals from the first side to the second side of the hard core module, and the second buffer chain is used to provide a channel for transmitting signals from the second side to the first side of the hard core module.

[0074] Specifically, after clock acquisition, the ATPG test responses in the second and first logic module groups are sequentially moved out along their respective scan chains. First, the ATPG test response enters the fourth scan chain from the second logic module group, flows through each register in the fourth scan chain, and is output from the output of the fourth scan chain. Then, the ATPG test response enters the input of the second buffer chain, passes through the hard core module, and is output from the output of the second buffer chain. Next, the ATPG test response enters the input of the third scan chain, flows through each register in the third scan chain, and is output from the output of the third scan chain. Finally, the ATPG test response returns to the input of the EDT module.

[0075] visible, Figure 1 The illustrated process enables the writing of ATPG test vectors and the reading of ATPG test responses from the logic modules on both sides of the hard core module, allowing ATPG testing across untestable hard core modules using only a single EDT module. The write and read paths described above can operate simultaneously to achieve parallel loading of test vectors and reading of test responses. Figure 1 The process shown can be executed by the chip under test (DUT). For example, it can be executed collaboratively by the DUT's internal EDT module, scan chain, and buffer chain under the control of the ATE device.

[0076] In one embodiment, the method further includes: in response to receiving a valid test mode selection signal, switching the input of the first buffer chain from a function signal corresponding to the first buffer chain to an ATPG test vector, and switching the input of the second buffer chain from a function signal corresponding to the second buffer chain to an ATPG test response.

[0077] Specifically, the first and second buffer chains embedded in the hard core module are used to transmit functional signals during normal chip operation. These include control signals, data signals, or handshake signals sent from the first-side logic module to the second-side logic module. When ATPG testing is required, the chip enters test mode, at which point the test mode selection signal is set to an active level (e.g., active high or active low, depending on the chip design). In response to this active test mode selection signal, the input sources of the first and second buffer chains switch: the input to the first buffer chain changes from the functional signal corresponding to the first buffer chain to the ATPG test vector, and the input to the second buffer chain changes from the functional signal corresponding to the second buffer chain to the ATPG test response. After the switch, the two buffer chains no longer transmit functional signals but are instead used for the transmission of test vectors from the first side to the second side, and for the transmission of test responses from the second side to the first side, respectively.

[0078] For example, in a specific instance, when the chip is operating normally, the first buffer chain transmits functional data from the left SRC module to the right RS_L1 module, and the second buffer chain transmits functional data from the right RS_L1 module to the left SRC module. When the test mode selection signal is valid, the input of the first buffer chain switches to the ATPG test vector output by the EDT module, and the input of the second buffer chain switches to the ATPG test response from the right RS_L1 module. These two buffer chains serve the write path of the test vector and the read path of the test response, respectively.

[0079] Through the aforementioned switching mechanism, the first and second buffer chains achieve time-division multiplexing between functional mode and test mode. When the chip is operating normally, the two buffer chains serve the interaction of functional signals; when the chip is performing ATPG testing, the two buffer chains seamlessly switch to become transmission channels for test signals. The same hardware resource undertakes different functions in the two modes, avoiding the need for additional dedicated scan channels for testing purposes and preventing physical conflicts between functional signals and test signals within the hard core. Furthermore, the switching process does not affect the internal structure and function of the hard core module.

[0080] In one implementation, the first scan chain includes a first group of registers in the first logic module group, and the registers in the first group of registers are connected in series; the third scan chain includes a second group of registers in the first logic module group, and the registers in the second group of registers are connected in series; the second scan chain includes a third group of registers in the second logic module group, and the registers in the third group of registers are connected in series; the fourth scan chain includes a fourth group of registers in the second logic module group, and the registers in the fourth group of registers are connected in series.

[0081] Specifically, the first logic module group contains two independent sets of registers: a first set of registers and a second set of registers. The registers in the first set are connected in series (i.e., the output of one register is connected to the input of the next register), forming a first scan chain used to test the write direction of the vector (from the first side to the second side of the hard core module). The registers in the second set are connected in series, forming a third scan chain used to test the read direction of the response (from the second side to the first side of the hard core module). Similarly, the second logic module group also contains two independent sets of registers: a third set of registers and a fourth set of registers, forming the second and fourth scan chains respectively. The third set of registers is used to test the write direction of the vector (from the first side to the second side of the hard core module), and the fourth set of registers is used to test the read direction of the response (from the second side to the first side of the hard core module). The first and second sets of registers are physically independent, each with its own input and output terminals, and they do not share terminals. The third and fourth sets of registers are also physically independent, each with its own input and output terminals, and they do not share terminals.

[0082] For example, in a logic module, its internal registers are divided into two groups: a write group and a read group, which are physically independent. The registers in the write group are connected end-to-end to form a left-to-right shift path for receiving test vectors; the registers in the read group are connected end-to-end to form a right-to-left shift path for forwarding test responses. The write group and the read group can operate simultaneously without interfering with each other.

[0083] As can be seen, because the write path and read path use different register groups, test vector loading and test response reading can be performed simultaneously without interference, thus improving test efficiency. Response data generated during the capture phase is stored in the read group registers and will not be overwritten by subsequent test vector shift operations, ensuring the integrity and accuracy of the test data. The two sets of registers within each logic module group use independent connection paths, further avoiding signal conflicts and electrical races, improving test stability and reliability.

[0084] In one implementation, the first logic module group includes multiple logic modules, and the scan sub-chains of each of the multiple logic modules are connected in series to form a first scan chain and a third scan chain; the second logic module group includes multiple logic modules, and the scan sub-chains of each of the multiple logic modules are connected in series to form a second scan chain and a fourth scan chain.

[0085] Specifically, when the first or second logic module group contains multiple logic modules, each logic module independently contains two sets of registers. One set is used for the write direction (part of the first or second scan chain), and the other set is used for the read direction (part of the third or fourth scan chain). The write group registers within each logic module are concatenated to form the write scan sub-chain of that module; the read group registers are concatenated to form the read scan sub-chain of that module. Within the module group, the write scan sub-chains of each logic module are concatenated sequentially, with the output of the write scan sub-chain of the previous logic module connected to the input of the write scan sub-chain of the next logic module, thus forming a complete write direction scan chain; similarly, the read scan sub-chains of each logic module are also concatenated sequentially to form a complete read direction scan chain.

[0086] For example, the first logic module group contains two logic modules, A and B. The write group registers within logic module A are cascaded to form a write sub-chain, and the read group registers are cascaded to form a read sub-chain. Similarly, logic module B forms both a write sub-chain and a read sub-chain. The output of the write sub-chain of logic module A is connected to the input of the write sub-chain of logic module B, and the two are cascaded to form a complete first scan chain. The input of the read sub-chain of logic module A is connected to the output of the read sub-chain of logic module B, and the two are cascaded to form a complete third scan chain. The same logic applies to the multiple logic modules in the second logic module group.

[0087] As can be seen, the scan sub-chains of each logic module are connected in series within the module group to form a complete scan chain. Each module group on both sides of the hard core only needs to connect through two buffer chains within the hard core to complete the cross-hard core connection. Even if the number of modules on both sides of the hard core differs or their internal logic is complex, simply connecting the scan sub-chains of modules on the same side sequentially allows for flexible adaptation to chip layouts of different sizes, resulting in a clear connection structure and good scalability. Simultaneously, write and read operations within each logic module can still be performed independently and in parallel, and testing efficiency is not reduced due to module concatenation. The overall testing solution exhibits good scalability and adaptability.

[0088] In one implementation, the scan subchain of logic modules directly adjacent to the hard core module includes registers that are manually connected in series; the scan subchain of logic modules not directly adjacent to the hard core module includes registers that are automatically connected in series using EDA tools.

[0089] Specifically, for logic modules located on either side of and directly adjacent to the hard core module, the registers in their scan subchains are manually connected. This means the designer specifies the connection order of each register based on the physical layout and port location, ensuring precise alignment between the input / output terminals of the scan subchain and the ports of the buffer chain in the hard core module. For logic modules not directly adjacent to the hard core module (i.e., located outside the directly adjacent module), the registers in their scan subchains are automatically connected using EDA tools. This means the synthesis or DFT tools automatically complete the register scan connection and optimization based on the netlist.

[0090] For example, the first logic module group includes module A and module B. Module B is directly adjacent to the hard core module, while module A is located outside module B (not directly adjacent to the hard core). The registers in the scan subchain of module B are manually connected by the designer to ensure that their ports precisely match the ports of the hard core buffer chain; the registers in the scan subchain of module A are automatically connected by an EDA tool. The second logic module group is similar: modules directly adjacent to the hard core are manually connected, while outer modules are automatically connected by the tool.

[0091] As can be seen, manually connecting the scan subchains of directly adjacent modules allows for precise control of register connection order and port positions, ensuring accurate signal interface with the buffer chain ports in the hard core module and avoiding signal mismatch issues caused by port offsets or connection errors. Modules not directly adjacent to the hard core are automatically connected using EDA tools, reducing manual intervention and design complexity. The tools can also optimize based on timing and load, guaranteeing signal quality and timing performance of the scan chain. This combination of manual and automatic methods balances connection accuracy and design efficiency, achieving a balance under the differentiated needs of different modules and reducing overall design difficulty and labor costs.

[0092] In one implementation, the method further includes: statically determining the ATPG test vector and the bit width of the ATPG test response based on the number of registers in the second logic module group that need to be tested for ATPG.

[0093] Specifically, bit width refers to the number of parallel scan chains. ATPG test vectors and test responses are transmitted simultaneously through each scan chain in parallel, and the bit width determines the length of each scan chain. Generally, a larger bit width results in higher parallelism, shorter scan chain lengths, and shorter test data loading and reading times. The bit width can be determined based on the total number of registers in the second logic module group that need to be tested using ATPG. For example, dividing the total number of registers by the number of registers expected to be accommodated in each scan chain yields the required bit width. Once the bit width is determined, the number of scan chains in the first logic module group is also synchronously adapted to the bit width. Static determination here refers to setting the bit width during the chip design phase, without needing to dynamically adjust it based on actual conditions during chip runtime.

[0094] For example, if the second logic module group contains multiple logic modules, and the total number of registers requiring ATPG testing within these logic modules is M, and if it is desired that the number of registers in each scan chain does not exceed N, then dividing M by N and rounding up determines the bit width W. Regardless of the total number of registers in the first logic module group, the number of scan chains is adapted to this bit width W. If the total number of registers requiring ATPG testing in the first logic module group is less than W multiplied by N, some scan chains may be shorter, but the bit width remains unchanged at W. After setting the bit width, the number of the second and fourth scan chains is W, and the number of the first and third scan chains is also synchronously adapted to W. The output and input terminals of the EDT module are also set to W bits respectively.

[0095] As can be seen, the bit width is determined solely by the number of registers in the second logic module group, while the number of scan chains in the first logic module group is adapted to the same bit width, automatically matching on both sides during buffer chain connection. Designers only need to focus on the testing requirements of the hard core side to complete the bit width setting. The EDT module only needs one set of input / output ports corresponding to the bit width to drive the entire scan chain, eliminating the need for additional adaptation circuits due to differences in the scale of modules on both sides of the hard core. Compared to the method of merging the total number of registers on both sides of the hard core to determine the bit width, this avoids uneven scan chain utilization caused by differences in the number of registers. Moreover, the bit width is fixed once determined in the design phase, requiring no adjustments in subsequent testing. The EDT module port configuration and scan chain physical connections can be determined in advance, reducing design complexity and verification workload.

[0096] The present invention also proposes a cross-module ATPG testing system. Figure 2 This is a schematic diagram of a cross-module ATPG testing system according to an embodiment of the present invention. Figure 2 As shown, the system includes: a single EDT module for providing ATPG test vectors and receiving ATPG test responses; a first logic module group located on the first side of the unmeasurable hard core module, the first logic module group containing a first scan chain and a third scan chain, the first scan chain and the third scan chain shifting in opposite directions within the first logic module group; a second logic module group located on the second side of the hard core module, the second logic module group containing a second scan chain and a fourth scan chain, the second scan chain and the fourth scan chain shifting in opposite directions within the second logic module group; a first buffer chain and a second buffer chain, disposed within the hard core module; wherein the output of the EDT module, the first scan chain, the first buffer chain, and the second scan chain are connected in sequence to form the write path of the ATPG test vector; the fourth scan chain, the second buffer chain, the third scan chain, and the input of the EDT module are connected in sequence to form the read path of the ATPG test response.

[0097] In one implementation, the first buffer chain and the second buffer chain are two independent channels formed by multiplexing the buffer chain used for functional signal interaction in the hard core module.

[0098] In one implementation, a test mode selection signal input terminal is also included ( Figure 2 (not shown in the image) is used to receive a test mode selection signal; wherein the test mode selection signal is used to switch the function signal corresponding to the first buffer chain to the ATPG test vector when it is active, and to switch the input of the second buffer chain from the function signal corresponding to the second buffer chain to the ATPG test response.

[0099] In one implementation, the first scan chain includes a first group of registers in the first logic module group, and the registers in the first group of registers are connected in series; the third scan chain includes a second group of registers in the first logic module group, and the registers in the second group of registers are connected in series; the second scan chain includes a third group of registers in the second logic module group, and the registers in the third group of registers are connected in series; the fourth scan chain includes a fourth group of registers in the second logic module group, and the registers in the fourth group of registers are connected in series.

[0100] This invention also proposes a chip comprising the cross-module ATPG test system described in any of the preceding embodiments. Specifically, the chip integrates an EDT module, logic module groups located on both sides of the hard core module, and two buffer chains with opposite directions pre-embedded in the hard core module, forming a complete cross-module ATPG test structure. In the chip's normal functional mode, the two buffer chains pre-embedded in the hard core module are used to transmit functional signals (e.g., interactive data and control signals between the logic modules on both sides of the hard core). After the chip enters test mode, the two buffer chains are multiplexed as transmission channels for ATPG test signals, used for writing ATPG test vectors and reading ATPG test responses, respectively.

[0101] During chip testing, the EDT module decompresses the compressed test data input from the ATE equipment to generate ATPG test vectors. These test vectors are sequentially written to the first and second logic module groups via the first scan chain, first buffer chain, and second scan chain. Under the capture clock, the combinational logic of each module within the chip generates ATPG test responses, which are returned to the EDT module via the fourth scan chain, second buffer chain, and third scan chain. Test vector loading and test response reading can occur simultaneously without interference. After compressing the test responses, the EDT module outputs them to the ATE equipment for comparison with expected results to determine if the chip has manufacturing defects.

[0102] As can be seen, the chip proposed in this embodiment of the invention does not require adding an extra EDT module or dedicated scan channel for ATPG testing. It can achieve ATPG testing across hard core modules simply by reusing the existing buffer chain structure in the hard core module. The chip area and power consumption will not increase significantly due to the introduction of the test structure, the test coverage is high, the physical layout does not need to be modified, and the back-end design complexity is low.

[0103] Figure 3 This is a schematic diagram of the module layout and signal flow of an application example of the cross-module ATPG testing method according to an embodiment of the present invention. The following is in conjunction with... Figure 3 This application example will be described in detail.

[0104] This example uses a large-scale SoC chip as an application scenario. For example... Figure 3 As shown, the SOC chip contains, from left to right, the SRC module, RS_L0 module, THR module, RS_L1 module, and DES module. The SRC and RS_L0 modules are located to the left of the THR module (first side), forming the first logic module group; the RS_L1 and DES modules are located to the right of the THR module (second side), forming the second logic module group. The THR module is an untestable hard-core module; its internal structure is a black box and it does not participate in ATPG testing.

[0105] The SRC module internally contains a left-to-right scan chain (part of the first scan chain) and a right-to-left scan chain (part of the third scan chain). The SRC module also integrates an EDT module. The ATPG test vector output by the EDT module is transmitted to the RS_L0 module via the left-to-right scan chain within the SRC module and then through the Scan_in[36:0] port. Additionally, the ATPG test response received from the RS_L0 module through the Scan_out[36:0] port reaches the EDT module via the right-to-left scan chain within the SRC module. Both the Scan_in[36:0] and Scan_out[36:0] ports have a bit width of 37.

[0106] The RS_L0 module internally contains two independent parallel scan chains. Each scan chain consists of multiple D flip-flops (dff) connected in series. The D flip-flops are the basic storage units of the scan chain, including the data input terminal D, the scan input terminal SI, and the output terminal Q. For simplicity, in... Figure 3 Only the first register of each scan chain is shown; a complete scan chain consists of multiple registers connected in series.

[0107] The parallel scan chains in the upper region of the RS_L0 module are q[0]~q

[36] (a total of 37, which are part of the first scan chain), in which the registers in each scan chain are connected in series (the Q end of the left register is connected to the SI end of the adjacent right register). q[0]~q

[36] form the left-to-right shift path of the RS_L0 module, which is used to output the ATPG test vector received from the EDT module to the left-to-right buffer chain of the THR module.

[0108] The parallel scan chains in the lower region of the RS_L0 module are m[0]~m

[36] (a total of 37, which are part of the third scan chain), in which the registers in each scan chain are connected in series (the Q end of the right register is connected to the SI end of the adjacent left register). m[0]~m

[36] form a shift path from right to left, which is used to receive the ATPG test response from the right-to-left buffer link of the THR module.

[0109] The THR module is located between the RS_L0 and RS_L1 modules. Internally, the THR module contains two pre-embedded buffer chains in opposite directions: one for left-to-right transmission (first buffer chain) and the other for right-to-left transmission (second buffer chain). These two buffer chains are used to transmit functional signals in functional mode and are multiplexed in test mode as transmission channels for the ATPG test vector and ATPG test response. Specifically, the ATPG test vector is transmitted from the RS_L0 module to the RS_L1 module via the first buffer chain; the ATPG test response is transmitted from the RS_L1 module to the RS_L0 module via the second buffer chain, thus achieving signal transmission across hard-core modules without penetrating the THR module's internal registers.

[0110] The RS_L1 module is located to the right of the THR module. It also contains two independent parallel scan chains. One of them is Si[0]~Si

[36] (part of the second scan chain), which is used to receive the ATPG test vector from the left-to-right buffer chain of the THR module and transmit the ATPG test vector to the DES module via the Scan_in_to_des port. The other group (part of the fourth scan chain) is connected to the Scan_out_from_des port of the DES module and is used to receive the ATPG test response from the DES module via the Scan_out_from_des port and transmit the ATPG test response to the right-to-left buffer chain of the THR module.

[0111] The DES module is located to the right of the RS_L1 module. Its internal scan chains are automatically completed by the ATPG test tool. It also contains 37 scan chains from left to right (part of the second scan chain) and 37 scan chains from right to left (part of the fourth scan chain).

[0112] Write path (ATPG test vector loading, from left to right): The ATPG test vector (37-bit parallel) output by the EDT module is output through the Scan_in[36:0] port, passes through the left-to-right scan chain inside the SRC module, the q[0]~q

[36] scan chain group of the RS_L0 module, enters the left-to-right buffer chain of the THR module, passes through the THR module and enters the left-to-right scan chain group (Si[0]~Si

[36] ) of the RS_L1 module, enters the Scan_in_to_des port of the DES module and the left-to-right scan chain inside the DES module, and completes the test vector loading.

[0113] Readout path (ATPG test response readout, from right to left): After the ATPG test response passes through the right-to-left scan chain inside the DES module, it is output from the Scan_out_from_des port, enters the right-to-left scan chain group of the RS_L1 module, is output from the left side of the RS_L1 module, enters the right-to-left buffer chain of the THR module, passes through the THR module, enters the m[0]~m

[36] scan chain group of the RS_L0 module, is output from the left side of the RS_L0 module, passes through the right-to-left scan chain inside the SRC module, and finally returns to the EDT module through the Scan_out[36:0] port.

[0114] The write path and read path can work simultaneously. For example, while the ATPG test vector moves in from left to right through the q[0]~q

[36] scan chain group, the ATPG test response moves out from right to left through the m[0]~m

[36] scan chain group. The two use different scan chain groups and different buffer chain channels, and do not interfere with each other. Moreover, the scan chains of the RS_L0 and RS_L1 modules are connected in a manual manner to ensure accurate docking with the buffer chain port of the THR module; the scan chain of the DES module is automatically connected by the EDA tool.

[0115] Thus, combined Figure 3 As shown in the application example, the implementation of this invention reuses two buffer chains with opposite directions pre-embedded in the THR module, and can complete ATPG testing of multiple logic modules on both sides of the hard core using a single EDT module. Test vector loading and test response reading can be performed simultaneously, realizing ATPG testing across untestable hard core modules.

[0116] Figure 4 This is an exemplary structural diagram of a cross-module ATPG testing apparatus according to an embodiment of the present invention. Figure 4As shown, the device 400 includes: a writing module 401, used to write the ATPG test vector provided by a single EDT module sequentially through a first scan chain, a first buffer chain, and a second scan chain into a first logic module group and a second logic module group; and a reading module 402, used to return the ATPG test response read from the second logic module group and the first logic module group sequentially through a fourth scan chain, a second buffer chain, and a third scan chain to the EDT module; wherein the first logic module group is located on the first side of the unmeasurable hard core module, the second logic module group is located on the second side of the hard core module, the first scan chain and the third scan chain shift in opposite directions within the first logic module group, the second scan chain and the fourth scan chain shift in opposite directions within the second logic module group, and the first buffer chain and the second buffer chain are disposed in the hard core module.

[0117] The present invention also proposes an electronic device with a processor-memory architecture. Figure 5 This is a structural diagram of an electronic device according to an embodiment of the present invention. Figure 5 As shown, the electronic device includes a processor 501, a memory 502, and a computer program stored on the memory 502 and executable on the processor 501. When executed by the processor 501, the computer program implements any of the cross-module ATPG testing methods described above. Specifically, the memory 502 can be implemented as various storage media such as electrically erasable programmable read-only memory (EEPROM), flash memory, and programmable programmable read-only memory (PROM). The processor 501 can be implemented as including one or more central processing units (CPUs) or one or more field-programmable gate arrays (FPGAs), wherein the FPGA integrates one or more CPU cores. Specifically, the CPU or CPU core can be implemented as a CPU, MCU, or DSP, etc.

[0118] It should be noted that not all steps and modules in the above processes and structural diagrams are mandatory; some steps or modules can be omitted as needed. The execution order of the steps is not fixed and can be adjusted as required. The division of modules is merely for the convenience of description and functional division. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0119] The hardware modules in each embodiment can be implemented mechanically or electronically. For example, a hardware module may include specially designed permanent circuitry or logic devices (such as dedicated processors, such as FPGAs or ASICs) to perform specific operations. A hardware module may also include programmable logic devices or circuitry (such as general-purpose processors or other programmable processors) temporarily configured by software to perform specific operations. The choice between mechanical implementation, dedicated permanent circuitry, or temporarily configured circuitry (such as software-configured circuitry) for the hardware module can be made based on cost and time considerations.

[0120] The present invention also provides a machine-readable storage medium storing instructions for causing a machine to perform the methods described in this application. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and causing a computer (e.g., CPU, MCU, or MPU) of the system or apparatus to read and execute the program code stored in the storage medium. Furthermore, an operating system or similar device operating on a computer can perform some or all of the actual operations through instructions based on the program code. The program code read from the storage medium can also be written to a memory located in an expansion board inserted into a computer or to a memory located in an expansion unit connected to the computer. Subsequently, a control unit or similar device installed on the expansion board or expansion unit can perform some or all of the actual operations based on the instructions of the program code, thereby implementing the functions of any of the embodiments described above. Storage medium embodiments for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer or the cloud via a communication network.

[0121] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A cross-module automatic test vector generation ATPG test method, characterized in that, include: The ATPG test vector provided by a single embedded deterministic test EDT module is sequentially written into the first logic module group and the second logic module group via the first scan chain, the first buffer chain and the second scan chain. The ATPG test response read from the second logic module group and the first logic module group is returned to the EDT module via the fourth scan chain, the second buffer chain and the third scan chain in sequence. The first logic module group is located on the first side of the unmeasurable hard core module, the second logic module group is located on the second side of the hard core module, the first scan chain and the third scan chain are shifted in opposite directions within the first logic module group, the second scan chain and the fourth scan chain are shifted in opposite directions within the second logic module group, and the first buffer chain and the second buffer chain are disposed in the hard core module; the first buffer chain and the second buffer chain are two independent channels formed by multiplexing the buffer chain used for functional signal interaction in the hard core module.

2. The method according to claim 1, characterized in that, Also includes: In response to receiving a valid test mode selection signal, the input of the first buffer chain is switched from the function signal corresponding to the first buffer chain to the ATPG test vector, and the input of the second buffer chain is switched from the function signal corresponding to the second buffer chain to the ATPG test response.

3. The method according to claim 1, characterized in that, The first scan chain includes a first group of registers in the first logic module group, and the registers in the first group of registers are connected in series. The third scan chain includes a second group of registers in the first logic module group, and the registers in the second group of registers are connected in series. The second scan chain includes a third group of registers in the second logic module group, and the registers in the third group of registers are connected in series. The fourth scan chain includes a fourth group of registers in the second logic module group, and the registers in the fourth group of registers are connected in series.

4. The method according to any one of claims 1-3, characterized in that, The first logic module group includes multiple logic modules, and the scan sub-chains of each of the multiple logic modules are connected in series to form the first scan chain and the third scan chain; the second logic module group includes multiple logic modules, and the scan sub-chains of each of the multiple logic modules are connected in series to form the second scan chain and the fourth scan chain.

5. The method according to claim 4, characterized in that, In the scan subchain of the logic module directly adjacent to the hard core module, there are registers that are connected in series manually. In the scan subchain of logic modules that are not directly adjacent to the hard core module, there are registers that are automatically concatenated using EDA tools.

6. The method according to any one of claims 1-3, characterized in that, Also includes: Based on the number of registers in the second logic module group that need to be tested for ATPG, the ATPG test vector and the bit width of the ATPG test response are statically determined.

7. A cross-module ATPG testing device, characterized in that, include: The write module is used to write the ATPG test vector provided by a single EDT module into the first logic module group and the second logic module group in sequence through the first scan chain, the first buffer chain and the second scan chain. The readout module is used to return the ATPG test response read from the second logic module group and the first logic module group sequentially via the fourth scan chain, the second buffer chain and the third scan chain to the EDT module; The first logic module group is located on the first side of the unmeasurable hard core module, the second logic module group is located on the second side of the hard core module, the first scan chain and the third scan chain are shifted in opposite directions within the first logic module group, the second scan chain and the fourth scan chain are shifted in opposite directions within the second logic module group, and the first buffer chain and the second buffer chain are disposed in the hard core module; the first buffer chain and the second buffer chain are two independent channels formed by multiplexing the buffer chain used for functional signal interaction in the hard core module.

8. A cross-module ATPG testing system, characterized in that, include: A single EDT module is used to provide ATPG test vectors and receive ATPG test responses; The first logic module group is located on the first side of the unmeasurable hard core module. The first logic module group includes a first scan chain and a third scan chain. The first scan chain and the third scan chain have opposite shifting directions within the first logic module group. The second logic module group is located on the second side of the hard core module. The second logic module group includes a second scan chain and a fourth scan chain. The second scan chain and the fourth scan chain have opposite shift directions within the second logic module group. The first buffer chain and the second buffer chain are set in the hard core module; the first buffer chain and the second buffer chain are two independent channels formed by reusing the buffer chain used for functional signal interaction in the hard core module. The output of the EDT module, the first scan chain, the first buffer chain, and the second scan chain are connected in sequence to form the write path of the ATPG test vector; the fourth scan chain, the second buffer chain, the third scan chain, and the input of the EDT module are connected in sequence to form the read path of the ATPG test response.

9. The system according to claim 8, characterized in that, It also includes a test mode selection signal input terminal for receiving the test mode selection signal; The test mode selection signal is used to switch the function signal corresponding to the first buffer chain to the ATPG test vector and to switch the input of the second buffer chain from the function signal corresponding to the second buffer chain to the ATPG test response when it is active.

10. The system according to claim 8, characterized in that, The first scan chain includes a first group of registers in the first logic module group, and the registers in the first group of registers are connected in series. The third scan chain includes a second group of registers in the first logic module group, and the registers in the second group of registers are connected in series. The second scan chain includes a third group of registers in the second logic module group, and the registers in the third group of registers are connected in series. The fourth scan chain includes a fourth group of registers in the second logic module group, and the registers in the fourth group of registers are connected in series.

11. A chip, characterized in that, The ATPG testing system comprising any one of claims 8 to 10 is a cross-module system.

12. An electronic device, characterized in that, include: processor; A memory storing a computer program executable by the processor for causing the processor to perform the cross-module ATPG test method as described in any one of claims 1 to 6.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the cross-module ATPG testing method as described in any one of claims 1 to 6.

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