Heat dissipation substrate and its manufacturing method, power semiconductor module, power converter

Abstract

This application relates to a heat dissipation substrate and its manufacturing method, a power semiconductor module, and a power converter. Embodiments relate to a heat dissipation substrate for power semiconductors, a power semiconductor module including the same, a power converter including the same, and a manufacturing method thereof. The method for manufacturing a heat dissipation substrate for power semiconductors according to an embodiment may include the following steps: preparing a first ceramic substrate; forming a bonding metal layer having a first thickness by sputtering on one or another surface of the first ceramic substrate; disposing a metal plate on the first ceramic substrate on which the bonding metal layer can be formed; and performing a hot pressing process while disposing the metal plate. In the hot pressing process step, the bonding metal layer may react with the first ceramic substrate to become an oxide bonding layer.

Description

Technical Field

[0001] The embodiments relate to a heat dissipation substrate for a power semiconductor module, a power semiconductor module including the same, a power converter including the same, and a method for manufacturing the same. Background Technology

[0002] A power conversion module is a device that performs power conversion (AC->DC, DC->AC), voltage transformation (buck, boost), power distribution, or power control. It is a core component that improves energy efficiency and controls voltage variations to provide system stability and reliability during power transmission and control. A power conversion module can also be referred to as a power module or a power system.

[0003] Power conversion modules may include various components such as power semiconductor devices, heat sinks, base plates, molded silicon, housings and covers, and terminals.

[0004] Recently, environmentally friendly electric or hydrogen-based vehicles have gained attention as alternatives to fossil fuel-based internal combustion engine vehicles, and these vehicles utilize numerous power semiconductor devices. Environmentally friendly vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), and fuel cell electric vehicles (PCEVs).

[0005] Previously, silicon (Si) power semiconductor devices were widely used, but as Si power semiconductors have reached their physical limits, there is active research into wide bandgap (WBG) power semiconductors such as silicon carbide (SiC) or gallium nitride (GaN).

[0006] WBG power semiconductor devices have a bandgap energy approximately three times that of Si power semiconductor devices, resulting in a high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and a large electron saturation velocity (approximately 2 to 2.5 times). These characteristics enable operation in high-temperature and high-voltage environments, and offer the advantages of high switching speed and low switching losses.

[0007] For example, Si-based power semiconductor modules used in conventional electric vehicles, hybrid electric vehicles, etc., for performing power conversion, motor drive switching, control, etc., operate in a temperature environment of about 150°C. However, recently, due to the need for increased switching performance and power density, there is active research on wide bandgap (WBG) based power semiconductor devices (e.g., SiC or GaN) that can operate at operating temperatures of about 300°C or higher (e.g., at about 300°C to 700°C).

[0008] Furthermore, the heat generated from power semiconductors creates thermomechanical stresses in various parts of the power semiconductor module, and the lifespan of the junction and the power semiconductor device may be degraded due to thermal fatigue at the junction. Therefore, it is crucial to design a power semiconductor module that properly dissipates the heat generated from the power semiconductor device through a heat dissipation substrate and maintains the junction temperature of the power semiconductor device below an appropriate temperature to ensure reliability.

[0009] In addition, the heat dissipation substrate used for power semiconductors has the function of transferring the heat generated during the operation of the power semiconductor device to the outside, and the heat dissipation substrate also has the important function of electrically connecting the power semiconductor device.

[0010] Traditional power semiconductor heat dissipation substrates can be classified into two methods based on their bonding methods: DBC (Direct Copper Bonding) and AMB (Active Metal Brazing). The DBC method involves forming an oxide film on a copper (Cu) layer and then directly bonding it to the ceramic. The AMB method performs brazing by inserting a paste containing relatively low-melting-point metal particles as an intermediate material between the base metal and the ceramic.

[0011] also, Figure 1A This is a SAT (Scanning Acoustic Tomography) image of the first heat dissipation substrate using the traditional AMB bonding method.

[0012] In conventional AMB technology, degassing can occur when the flux solvent contained in the paste evaporates during heat treatment. As a result, microvoids (mV) may form at the bonding interface due to gases that cannot completely escape.

[0013] Therefore, in the case of traditional AMB technology, there is a problem that the heat dissipation characteristics are degraded due to the micro-voids that appear at the bonding interface of the heat dissipation substrate, and the bonding strength may also be degraded.

[0014] In addition, microvoids (mV) refer to voids smaller than 1 mm in size, and in the traditional power semiconductor heat dissipation substrate industry, they are considered unavoidable because it is difficult to prevent the occurrence of microvoids smaller than 1 mm.

[0015] For example, voids smaller than about 5 μm are currently excluded from void inspection, and although void inspection criteria exclude voids smaller than 5 μm, the void level at the bonding interface is currently maintained at about 3% or lower.

[0016] However, recently, 1200V, 200A high-voltage / high-power SiC power conversion modules are being used to improve the performance of hybrid and electric vehicles, as well as autonomous vehicles. During the operation of these high-performance electric vehicles, the operating temperature of the power semiconductor devices needs to be achieved to an average of 300°C or higher, and these high-performance electric vehicles are facing ultra-high temperature operation conditions with instantaneous maximum operating temperatures of 350°C or higher.

[0017] In such an ultra-high temperature, high pressure and high current operating environment, the existing bonding material itself may remelt, and thermal trapping may occur due to the micropores present in the bonding region, which may rapidly degrade the life of the power semiconductor module.

[0018] For example, Figure 1B These are scanning electron microscope (SEM) images of the second heat sink substrate using the conventional AMB bonding method, for reference. Figure 1B Cracks appeared due to defects at the interface between the ceramic substrate and the copper sheet of the heat sink, and the cracks in the heat sink caused damage to the power semiconductor device.

[0019] in addition, Figure 1C These are SEM images of a heat sink substrate manufactured using the traditional DBC method, for reference. Figure 1C The DBC substrate requires the formation of a thick copper oxide film on the copper foil through a thermal oxidation process, and then a direct thermal bonding process can be performed on a ceramic substrate such as Al2O3.

[0020] However, due to the difficulty in forming a uniform copper oxide film for manufacturing the DBC substrate, the copper foil cannot be properly bonded to the ceramic substrate, resulting in micron-level voids at the bonding points. Consequently, heat dissipation substrates manufactured using conventional DBC methods are susceptible to thermal shock, leading to a rapid degradation of the reliability or lifespan of the power semiconductor module. In particular, in cases of power semiconductor module degradation occurring in ultra-high operating temperature environments, damage to the power semiconductor device caused by a failure of the power semiconductor module installed in a vehicle could have a serious impact on driver safety.

[0021] Furthermore, in the internal comparison technique, the application of sputtering and thermoforming bonding techniques was investigated to reduce the porosity level at the bonding interface. However, in the internal comparison technique, there is a problem of micro-voids appearing at the bonding interface of the heat dissipation substrate due to the antioxidant layer and the thick bonding metal layer (e.g., Ti, etc.). A solution to this problem is needed considering the ultra-high operating temperature environment. Summary of the Invention

[0022] One of the technical objectives of this disclosure is to solve the problem of micro-voids appearing at the interface of the heat dissipation substrate.

[0023] In addition, one of the technical objectives of this disclosure is to solve the problem of cracks appearing at the interface of the heat dissipation substrate.

[0024] The technical objectives of this disclosure are not limited to those described herein, but include those that can be understood from the description of the invention. At least one technical objective is addressed by the features of the independent claim.

[0025] According to one aspect of this disclosure, a method for manufacturing a heat dissipation substrate for power semiconductors is provided, the method comprising the steps of: preparing a (first) ceramic substrate; forming a bonding metal layer of a first thickness on one or the other side of the (first) ceramic substrate by sputtering; arranging a metal plate on the (first) ceramic substrate on which the bonding metal layer can be formed; and performing a hot pressing process while arranging the metal plate.

[0026] According to another aspect of this disclosure, a method for manufacturing a heat dissipation substrate for a power semiconductor module is provided, the method comprising the steps of: preparing an oxide-based substrate and / or a ceramic substrate having a first side (or one side) and a second side (or the other side, i.e., opposite to the first side or one side); forming a bonding metal layer by sputtering on at least one of the first side and the second side of the substrate; disposing a metal plate on the bonding metal layer; and performing a hot pressing process such that the bonding metal layer reacts with the substrate and / or becomes (or transforms into) an oxide bonding layer.

[0027] A method of manufacturing a heat dissipation substrate for a power semiconductor module according to any of these aspects may include one or more of the following features:

[0028] The substrate can be a ceramic substrate and / or an oxide-based substrate.

[0029] The substrate may include or be composed of Al2O3.

[0030] In the hot pressing process, the bonding metal layer can react with (first) oxide-based substrate and / or ceramic substrate to become an oxide bonding layer.

[0031] (First) The substrate may include an oxide-based ceramic substrate.

[0032] An oxide bonding layer may be disposed at the interface between the (first) oxide-based substrate and / or ceramic substrate and the metal plate. After a hot-pressing process, the oxide bonding layer may be disposed between the substrate and the metal plate.

[0033] The metal plate may include or be composed of copper.

[0034] The bonding metal layer may include Ti or TiW.

[0035] The bonding metal layer can be formed to a thickness of 0.01 μm to 0.03 μm.

[0036] The oxide bonding layer may include titanium oxide.

[0037] The oxide bonding layer can be formed to a thickness of 0.01 μm to 0.03 μm.

[0038] Sputtering can be performed in an inert atmosphere (e.g., under argon).

[0039] The hot pressing process can be performed at temperatures above 500°C, preferably above 800°C, and most preferably between 900°C and 1100°C. The hot pressing process can be performed under vacuum conditions (e.g., at a vacuum level of 0.1 Torr). In the hot pressing process, the pressure on the metal plate can be greater than 0.5 MPa and / or less than 100 MPa, preferably greater than 1 MPa, and more preferably between 1 MPa and 20 MPa.

[0040] According to another aspect, a heat dissipation substrate for a power semiconductor module is provided, the heat dissipation substrate comprising: a first metal plate; a (first) oxide-based substrate and / or ceramic substrate bonded to the first metal plate; a second metal plate bonded to the substrate; and an oxide bonding layer between the substrate and the first metal plate and / or between the substrate and the second metal plate.

[0041] The heat dissipation substrate in this respect may include one or more of the following features:

[0042] The heat dissipation substrate can be manufactured by any method according to any aspect or embodiment of this disclosure.

[0043] The substrate may include or may be an oxide-based substrate and / or a ceramic substrate.

[0044] The substrate may include or be composed of Al2O3.

[0045] The first and / or second metal plates may include copper (Cu) or be composed of Cu.

[0046] The oxide bonding layer may include titanium oxide.

[0047] The thickness of the oxide bonding layer can be from 0.01 μm to 0.03 μm.

[0048] According to another aspect of this disclosure, a power semiconductor module includes at least one power semiconductor heat sink substrate, at least one lead frame, and at least one power semiconductor device according to any aspect or embodiment described herein.

[0049] According to another aspect of this disclosure, a power converter includes at least one power semiconductor module according to one aspect of this disclosure.

[0050] Technical effect

[0051] The method of manufacturing a heat dissipation substrate for a semiconductor module, the heat dissipation substrate, and the power semiconductor module having the same may include one or more of the following technical effects:

[0052] According to the power semiconductor heat dissipation substrate, the power semiconductor module including the same, the power converter including the same, and the manufacturing method thereof according to the embodiments, there is a technical effect that can solve the problem of micro-voids appearing at the bonding interface of the heat dissipation substrate.

[0053] The bonding process with the existing metal plates does not require a separate oxidation process. No anti-oxidation layer is needed.

[0054] For example, refer to Figure 6A There is a special technical effect that there are no micropores at the interface between the oxide ceramic substrate (410b) and the Cu material metal plate (410c) of the first heat dissipation substrate (410) according to the embodiment.

[0055] For example, in an implementation, in such a way Figure 4E and Figure 5A After forming a bonding metal layer (411) on an oxide ceramic substrate (410b), a high-temperature and high-pressure hot pressing process can be performed on metal plates (410a, 410c) made of Cu without the need for a separate oxidation process.

[0056] Refer to together Figure 5B and Figure 6A According to the embodiment, the bonding metal layer (411) reacts with the oxide ceramic substrate (410b) through a hot pressing process of the metal plate (410a, 410c) and the oxide ceramic substrate (410b) to form an oxide bonding layer (412) without the need for a separate oxidation process. The oxide bonding layer (412) can obtain a strong bond between the Cu metal plate (410a, 410c) and the oxide ceramic substrate (410b).

[0057] Therefore, according to the embodiment, since a separate oxidation process is not performed on the metal plates (410a, 410c) before bonding, the bonding metal layer (411) formed uniformly and thinly becomes an oxide bonding layer (412), thereby achieving the special technical effect that strong bonding force can be obtained and there are no micropores at the bonding interface between the oxide-based ceramic substrate (410b) and the Cu-based metal plate (410c).

[0058] Therefore, according to the implementation method, it has the following special technical effect: by achieving the absence of micro-gaps in power semiconductor modules operating at ultra-high temperatures of 350°C or higher, high-temperature reliability is enhanced and high-temperature bonding strength is improved.

[0059] Furthermore, according to the embodiments, there is a special technical effect in solving the problem of cracks appearing at the interface of the heat sink substrate. For example, according to the embodiments, cracks can be prevented from appearing at the interface between the ceramic substrate and the copper sheet of the heat sink substrate, thereby improving the reliability of the power semiconductor device.

[0060] The technical effects of the implementation methods are not limited to those described in this clause, but may include those that can be understood from the description of the present invention. Attached Figure Description

[0061] Figure 1A This is a SAT (Scanning Acoustic Tomography) image of the first heat dissipation substrate using the traditional AMB bonding method.

[0062] Figure 1B This is a SEM (scanning electron microscope) image of the second heat dissipation substrate using the traditional AMB bonding method.

[0063] Figure 1C This is an SEM image of a heat sink substrate manufactured using the traditional DBC method.

[0064] Figure 2 This is a circuit diagram of a power converter (1000) that uses a power semiconductor module according to the embodiment.

[0065] Figure 3A This is a cross-sectional view of a power semiconductor module (500) including a heat dissipation substrate for power semiconductors according to an embodiment.

[0066] Figure 3B This is a manufacturing process diagram of a power semiconductor module (500) including a heat dissipation substrate for power semiconductors according to an embodiment.

[0067] Figures 4A to 4E as well as Figure 5A and Figure 5B This is a cross-sectional view of the manufacturing process of a power semiconductor heat sink substrate according to an embodiment.

[0068] Figure 6A yes Figure 5B An analytical photograph of the first region (P1) of the first heat dissipation substrate (410) shown.

[0069] Figure 6B These are SEM images of the brazed interface based on traditional AMB technology.

[0070] Figures 7A to 7C Examples of etching, laser scribing and inspection processes for the first heat dissipation substrate (410).

[0071] Figure 8A This is a SAT (scanning acoustic tomography) image of the heat dissipation substrate according to the embodiment.

[0072] Figure 8B This is a SAT photograph of a third heat sink substrate using the conventional AMB bonding method.

[0073] Figure 8CThese are peeling defect data from the SAT image of the fourth heat sink substrate using the traditional AMB bonding method. Detailed Implementation

[0074] In the following, the invention according to the embodiments for solving the above problems will be described in more detail with reference to the accompanying drawings.

[0075] The suffixes "module" and "part" used for components in the following description are provided for the convenience of writing this specification only and do not inherently imply any particular significance or function. Therefore, "module" and "part" are used interchangeably.

[0076] Ordinal terms (e.g., first, second, etc.) can be used to describe various components, but the components are not limited by these terms. These terms are used only to distinguish one component from another.

[0077] Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0078] In this application, the terms “comprising” or “having” are intended to specify the presence of the features, quantities, steps, operations, components, parts or combinations thereof described in this specification, but should not be construed as precluding the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof.

[0079] In this embodiment, the power semiconductor device can be used in inverters or converters in automobiles, computers, home appliances, solar power plants, smart grids, etc. In this embodiment, the power semiconductor device may include one or more power semiconductor modules. Alternatively, a power semiconductor module may include multiple power semiconductor devices.

[0080] In the following embodiments, a power semiconductor device is described as an automotive inverter for driving a motor; however, the power semiconductor device described in these embodiments can be applied to inverters or converters in the various technical fields described above. Here, "automobile" includes hybrid vehicles (HEVs), plug-in hybrid vehicles (PHEVs), electric vehicles (EVs), fuel cell vehicles (PCEVs), etc. In the description of the following embodiments, switching elements and power semiconductor devices are used interchangeably.

[0081] (Implementation Method)

[0082] Figure 2 This is a circuit diagram of a power converter (1000) that uses a power semiconductor module according to the embodiment.

[0083] The power converter (1000) according to the embodiment can receive DC power from a battery or fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power converter (1000) according to the embodiment may include an inverter that receives DC power from a battery, converts it into three-phase AC power, and supplies it to a motor (M), and the motor (M) can provide power to an electric vehicle, a fuel cell vehicle, etc.

[0084] The power converter (1000) according to the embodiment may include a power semiconductor device (100). The power semiconductor device (100) may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but is not limited thereto, and may include an IGBT (Insulated Gate Bipolar Transistor).

[0085] For example, the power converter (1000) may include multiple power semiconductor devices (100a, 100b, 100c, 100d, 100e, 100f) and may include multiple diodes (not shown). Each of the multiple diodes may be embedded in the power semiconductor device (100a, 100b, 100c, 100d, 100e, 100f) as an internal diode, but is not limited thereto, and may be arranged individually.

[0086] The implementation can convert DC power to AC power through the switching control of multiple power semiconductor devices (100a to 100f). For example, the power converter (1000) according to the implementation can supply positive power to the motor (M) by turning on the first power semiconductor device (100a) and turning off the second power semiconductor device (100b) in a first time period of a cycle, and supply negative power to the motor (M) by turning off the first power semiconductor device (100a) and turning on the second power semiconductor device (100b) in a second time period of a cycle.

[0087] In an implementation, a group of power semiconductor devices arranged in series on the high-voltage and low-voltage lines on the input side can be referred to as an arm. For example, a first power semiconductor device and a second power semiconductor device (100a, 100b) can constitute a first arm (12a), a third power semiconductor device and a fourth power semiconductor device (100c, 100d) can constitute a second arm (12b), and a fifth power semiconductor device and a sixth power semiconductor device (100e, 100f) can constitute a third arm (12c).

[0088] Figure 2 The multiple power semiconductor devices (100a to 100f) shown can be packaged into a power semiconductor module, or the power semiconductor devices constituting the respective arms can be packaged into a power semiconductor module.

[0089] In the arm, the upper power semiconductor device and the lower power semiconductor device can be controlled to not be turned on at the same time. For example, in the first arm, the first power semiconductor device (100a) and the second power semiconductor device (100b) can not be turned on at the same time, but can be turned on and off alternately.

[0090] The power semiconductor device (100) of the embodiment may be a silicon carbide (SiC) power semiconductor device, and is capable of operating in high temperature and high pressure environments, and can have high switching speed while having low switching losses.

[0091] Next, Figure 3A This is a cross-sectional view of a power semiconductor module (500) including a heat dissipation substrate for power semiconductors according to an embodiment. Figure 3B This is a manufacturing process diagram of a power semiconductor module (500) including a heat dissipation substrate for power semiconductors according to an embodiment.

[0092] Reference Figure 3A The power semiconductor module (500) according to the embodiment may include a first heat dissipation substrate (410), a second heat dissipation substrate (420), and one or more power semiconductor devices (100a, 100b), and may include a first lead frame (310), a second lead frame (320), and may be packaged by a mold (201). The mold (201) may include, but is not limited to, EMC (epoxy molding compound).

[0093] For example, refer to Figure 3B According to the embodiment, the power semiconductor module (500) can be manufactured by arranging a first lead frame (310), a second lead frame (320) and one or more power semiconductor devices (100a, 100b) between a first heat dissipation substrate (410) and a second heat dissipation substrate (420) and then pressing them together.

[0094] The power semiconductor devices (100a, 100b) can be bonded to the first heat dissipation substrate (410) and the second heat dissipation substrate (420) using a predetermined adhesive member (not shown). The adhesive member can be a Sn-Ag series adhesive member or an Ag series adhesive member. Alternatively, the first heat dissipation substrate and the second heat dissipation substrate (410, 420) can be bonded to the power semiconductor devices (100a, 100b) by welding or sintering.

[0095] Refer to Figure 3A In the power semiconductor module (500) according to the embodiment, the first power semiconductor device (100a) and the second power semiconductor device (100b) may form an arm. For example, as Figure 3AAs shown, the first power semiconductor device (100a) and the second power semiconductor device (100b) may be connected in series with electrodes arranged in opposite directions, but are not limited thereto. For example, the first power semiconductor device (100a) and the second power semiconductor device (100b) may be connected in parallel.

[0096] In the embodiment, the first heat dissipation substrate and the second heat dissipation substrate (410, 420) can be arranged on the lower side and the upper side of the power semiconductor module (500), respectively.

[0097] The first heat dissipation substrate (410) may include a first metal plate (410a), a first ceramic substrate (410b), and a second metal plate (410c).

[0098] The first ceramic substrate (410b) can electrically insulate the first metal plate (410a) and the second metal plate (410c). The first ceramic substrate (410b) may comprise a ceramic material with high thermal conductivity. For example, the first ceramic substrate (410b) may be one of AlN or Si3N4, but is not limited thereto.

[0099] One side of the first metal plate (410a) can contact the first ceramic substrate (410b) and dissipate heat to the other side. A heat dissipation means, including a cooling medium, can be arranged near the other side of the first metal plate (410a).

[0100] The second metal plate (410c) may include a wiring pattern formed by a patterning process such as etching, the wiring pattern being electrically connected to the electrodes of the power semiconductor device (100).

[0101] For example, the second metal plate (410c) may include electrically separated second-first wiring patterns (410c1) and second-second wiring patterns (410c2), and may be electrically connected to the first power semiconductor device (100a) and the second power semiconductor device (100b), respectively. The first metal plate (410a) and the second metal plate (410c) may include, but are not limited to, a Cu-based metal.

[0102] In addition, the second heat dissipation substrate (420) may include a third metal plate (420a), a second ceramic substrate (420b), and a fourth metal plate (420c). The second heat dissipation substrate (420) may adopt the technical features of the first heat dissipation substrate (410).

[0103] The third metal plate (420a) may include a wiring pattern (not shown) that is electrically connected to the power semiconductor device (100). For example, the third metal plate (420a) may be electrically connected to the first power semiconductor device (100a) and the second power semiconductor device (100b).

[0104] One side of the fourth metal plate (420c) can contact the second ceramic substrate (420b), and the other side can dissipate heat. A heat dissipation means, including a cooling medium, can be arranged near the other side of the fourth metal plate (420c).

[0105] Reference Figure 3A One side of each of the first lead frame (310) and the second lead frame (320) can be electrically connected to the power semiconductor device (100), and the other side of each can be connected to an external connection terminal. The external connection terminal may include an input power supply, a motor or an inverter controller.

[0106] For example, the first lead frame (310) and the second lead frame (320) can be electrically connected to the power semiconductor device (100) via the first heat sink substrate (410) and the second heat sink substrate (420).

[0107] For example, the first lead frame (310) may include a first-first lead frame (310a) electrically connected to a second-first wiring pattern (410c1) of the first heat sink substrate (410) and a first-second lead frame (310b) electrically connected to a third metal plate (420a) of the second heat sink substrate (420).

[0108] Additionally, the second lead frame (320) may include a second-first lead frame (320a) electrically connected to a second-second wiring pattern (410c2) of the first heat sink substrate (410) and a second-second lead frame (320b) electrically connected to a third metal plate (420a) of the second heat sink substrate (420).

[0109] In the following text, reference will be made to Figures 4A to 5B The manufacturing process of a heat dissipation substrate for a power semiconductor module according to an embodiment is described.

[0110] First, refer to Figure 4A A first ceramic substrate (410b) can be prepared. The first ceramic substrate (410b) can be an oxide-based substrate or a nitride-based substrate. For example, the first ceramic substrate (410b) can be Al2O3, AlN, Si3N4, etc., but is not limited to these.

[0111] A CDA (clean dry air) cleaning process and a thickness measurement process can be performed on the first ceramic substrate (410b), but are not limited thereto. The thickness of the first ceramic substrate (410b) can be from 200 μm to 1000 μm, but is not limited thereto. Preferably, the thickness of the first ceramic substrate (410b) can be from 300 μm to 800 μm, but is not limited thereto.

[0112] Figure 4BThis is a photograph showing the inherent surface non-uniformity (R) of the first ceramic substrate (410b) in the internal comparison technique.

[0113] Non-uniformities (R) ranging in size from a few μm to several hundred μm can exist on the surface of a ceramic substrate. When conventional techniques are used, these non-uniformities (R) can lead to voids in the bonding process.

[0114] For example, in traditional AMB technology, the flux solvent in the paste degassing during the brazing heat treatment, or in traditional DBC technology, the difficulty of achieving a uniform copper oxide film results in micro-voids at the bonding interface.

[0115] As mentioned above, in the traditional power semiconductor heat dissipation substrate industry, the appearance of micro-gaps smaller than 1 mm is considered unavoidable because they are difficult to control.

[0116] Furthermore, the applicant's internal comparative techniques have been extensively studied to reduce the porosity level at the bonding interface by applying sputtering and hot-press bonding techniques. However, despite this extensive study, and although the internal comparative techniques have reduced the porosity level at the bonding interface of the heat dissipation substrate, there is a problem of micro-voids caused by the anti-oxidation layer and the thick bonding metal layer (e.g., Ti layer, etc.).

[0117] Reference Figure 4B In conventional or internal comparison techniques, the presence of microvoids, ranging in size from a few μm to several hundred μm, on the surface of ceramic substrates is considered more unavoidable. However, considering the ultra-high temperature operating environment of power semiconductor modules, a solution is needed to prevent the formation of microvoids.

[0118] Furthermore, in conventional technologies, since copper foil (Cu foil) does not have good bonding strength with oxide ceramic substrates (e.g., Al2O3), in order to manufacture conventional DBC substrates, a copper oxide film is formed on the copper foil (Cu foil) through a thermal oxidation process, and then heat treatment is performed to bond it with the ceramic substrate (e.g., Al2O3).

[0119] However, in traditional DBC technology, not only is a separate heat treatment process required for the copper foil, but also micro-voids exist at the bonding interface due to the lack of a uniform copper oxide film, which significantly reduces the reliability of the power semiconductor module.

[0120] In the following example, in order to solve the problem of micro-voids at the bonding interface of the heat dissipation substrate, a bonding metal layer (411) can be formed on the oxide ceramic substrate (410b), and then a hot pressing process of the metal plate and the oxide ceramic substrate (410b) can be performed without the need for a separate oxidation process of the metal plate made of Cu.

[0121] For example, refer to Figure 4C A bonding metal layer (411) with a first thickness can be uniformly formed on one surface of the first ceramic substrate (410b) by sputtering.

[0122] For example, refer to Figure 4D A first ceramic substrate (410b) can be mounted on the anode electrode plate of a predetermined PVD apparatus (700), and a bonding metal layer (411) comprising Ti or TiW can be formed in an inert atmosphere such as Ar to a thin first thickness of about 0.05 μm or less. For example, the bonding metal layer (411) can be formed to a thickness of about 0.01 μm to 0.03 μm, but is not limited thereto.

[0123] Next, refer to Figure 4E A first ceramic substrate (410b) on which a bonding metal layer (411) is formed on one surface can be flipped, and another bonding metal layer (411) can be formed on the opposite surface by sputtering, thereby manufacturing the first ceramic substrate (410b).

[0124] Next, refer to Figure 5A The first metal plate (410a) and the second metal plate (410c) are respectively disposed on the lower and upper sides of each of the plurality of first ceramic substrates (410b), and a hot pressing process can be performed under vacuum to manufacture such a Figure 5B Each of the first heat dissipation substrates (410) shown.

[0125] The first and second metal plates (410a, 410c) may include, but are not limited to, copper or copper alloy materials. Additionally, the first and second metal plates (410a, 410c) may have a thickness of approximately 200 μm to 400 μm, but are not limited to this.

[0126] At this point, the hot pressing process can be performed by inserting multiple spacers (415). For example, the spacers (415) can be carbon spacers, ceramic spacers, etc., but are not limited to these.

[0127] The temperature of the hot pressing process can be from about 900°C to 1100°C. Preferably, the temperature of the hot pressing process can be from about 950°C to 1080°C, but is not limited thereto.

[0128] The vacuum level for hot pressing can be 1.0 × 10⁻⁶. -1 The vacuum level can be Torr or higher, but is not limited to this. Additionally, the pressure of the hot pressing process can be about 100 MPa or lower, but is not limited to this. For example, the pressure of the hot pressing process can be from about 1 MPa to about 20 MPa, but is not limited to this.

[0129] Next, Figure 6A yes Figure 5BAn analytical photograph of the first region (P1) of the first heat dissipation substrate (410) shown.

[0130] Reference Figure 6A There is a special technical effect that there are no micropores at the interface between the oxide ceramic substrate (410b) and the Cu metal plate (410c) of the first heat dissipation substrate (410) according to the embodiment.

[0131] According to the implementation method, the following special technical effects are achieved: by achieving a void-free power semiconductor module operating at ultra-high temperatures of 300°C or higher, high-temperature reliability can be enhanced and high-temperature bonding strength can be improved.

[0132] In addition, according to the embodiment, cracks can be prevented at the interface between the ceramic substrate and the copper sheet of the heat dissipation substrate, thereby improving the reliability of the power semiconductor device.

[0133] Specifically, refer to Figure 6A The first heat dissipation substrate (410) may include an oxide bonding layer (412) between the first ceramic substrate (410b) and the second metal plate (410c).

[0134] For example, refer to together Figure 5B and Figure 6A In one embodiment, after forming a bonding metal layer (411) on an oxide ceramic substrate (410b), a high-temperature and high-pressure hot-pressing process can be performed on the metal plate and the oxide ceramic substrate (410b) without the need for a separate oxidation process on the Cu material metal plates (410a, 410c).

[0135] According to the embodiment, without a separate oxidation process, the bonding metal layer (411) can be reacted with the oxide ceramic substrate (410b) through a hot pressing process to form an oxide bonding layer (412). This oxide bonding layer (412) achieves a strong bond between the Cu material metal plate (410a, 410c) and the oxide ceramic substrate (410b). Furthermore, because no separate oxidation process is performed, the oxide bonding layer (412) can be formed uniformly and thinly, resulting in a unique technical effect where there are no micropores at the bonding interface between the oxide ceramic substrate (410b) and the Cu material metal plate (410c).

[0136] also, Figure 6B These are SEM images of the brazed interface based on traditional AMB technology.

[0137] When using conventional AMB technology, there is an intermediate material in the form of Ti-Ag-Cu alloy between the Si3N4 ceramic substrate and the Cu sheet, and there are micropores (mV) with a size of a few μm to tens of μm at the bonding interface with a thickness of about 15 μm.

[0138] On the other hand, according to the implementation method, it has the following special technical effect: by achieving the absence of micro-gaps in power semiconductor modules operating at ultra-high temperatures of 350°C or higher, high-temperature reliability is enhanced and high-temperature bonding strength is improved.

[0139] In addition, according to the embodiment, it has the following technical effect: preventing cracks from appearing at the interface between the ceramic substrate and the copper sheet of the heat dissipation substrate, thereby improving the reliability of the power semiconductor device.

[0140] Next, Figures 7A to 7C Examples of etching, laser scribing and inspection processes for the first heat dissipation substrate (410).

[0141] Reference Figure 7A Wiring patterns can be formed on the first heat dissipation substrate (410) that has undergone hot pressing by etching. For example, wiring patterns can be formed by partially removing the second metal plate (410c) of the first heat dissipation substrate (410). At this time, the bonding metal layer (411) and the bonding layer (413) can also be removed.

[0142] Next, refer to Figure 7B It can perform laser scribing and fracture processes.

[0143] Subsequently, refer to Figure 7C Inspection processes can be performed. These processes may include ultrasonic testing (SAT), which uses ultrasound to inspect for voids or cracks in the interface.

[0144] Next, Figure 8A This is a SAT photograph of the heat sink substrate according to the embodiment.

[0145] on the other hand, Figure 8B This is a SAT image of a third heat sink substrate using the conventional AMB bonding method.

[0146] Reference Figure 8B Traditional AMB technology has the following problem: when the flux solvent included in the paste evaporates during heat treatment, degassing occurs, and microvoids (mV) appear at the bonding interface because the gas may not escape completely.

[0147] In the case of traditional AMB technology, there is a problem that the heat dissipation performance may be degraded due to micro-voids at the interface of the heat dissipation substrate, and the bonding strength may also be degraded.

[0148] On the other hand, refer to Figure 8A According to the embodiment, after forming a bonding metal layer (411) on an oxide ceramic substrate (410b), a high-temperature and high-pressure hot pressing process can be performed on a metal plate (410a, 410c) made of Cu without a separate oxidation process.

[0149] According to the embodiment, the bonding metal layer (411) can be reacted with the oxide ceramic substrate (410b) by a hot pressing process of the metal plate (410a, 410c) and the oxide ceramic substrate (410b) to form an oxide bonding layer (412) without a separate oxidation process, and the oxide bonding layer (412) can obtain a strong bonding force between the Cu metal plate (410a, 410c) and the oxide ceramic substrate (410b).

[0150] Therefore, according to the embodiment, since a separate oxidation process is not performed on the metal plates (410a, 410c) before bonding, the uniformly formed bonding metal layer (411) can be changed to an oxide bonding layer (412). Furthermore, in power semiconductor modules operating at ultra-high temperatures of 350°C or higher, a void-free bonding interface can be achieved between the oxide ceramic substrate (410b) and the Cu material metal plate (410c), resulting in special technical effects of enhanced high-temperature reliability and improved high-temperature bonding strength.

[0151] Next, Figure 8C These are peeling defect data from the SAT image of the fourth heat sink substrate using the traditional AMB bonding method.

[0152] In the case of heat dissipation substrates using the traditional AMB bonding method, there is a problem of peeling during thermal shock reliability testing.

[0153] In addition, under the conventional AMB bonding method, warping may occur in environments with repeated temperature changes due to the difference in the coefficients of thermal expansion between the ceramic substrate and the metal plate. Furthermore, in high-vibration and high-impact operating environments, there is a problem that micro-voids can lead to cracks when the substrate warps.

[0154] On the other hand, according to the implementation method, by preventing micro-gaps from appearing at the interface between the ceramic substrate and the copper sheet of the heat dissipation substrate, there is a technical effect that even if warping occurs due to the difference in thermal expansion coefficients, cracks will not appear.

[0155] Although the invention has been described above with reference to embodiments, those skilled in the art will readily understand that various modifications and alterations can be made to the invention without departing from the scope of the invention as described in the following claims.

Claims

1. A method for manufacturing a heat dissipation substrate for a power semiconductor module, the method comprising the following steps: Fabrication of an oxide-based substrate (410b); A bonding metal layer (411) is formed on at least one side of the substrate (410b) by sputtering; Metal plates (410a, 410c) are arranged on the bonding metal layer (411); as well as A hot pressing process is performed to transform the bonding metal layer (411) into an oxide bonding layer (412).

2. The method according to claim 1, wherein, The substrate (410b) includes an oxide-based ceramic substrate.

3. The method according to claim 1, wherein, After the hot pressing process, the oxide bonding layer (412) is disposed between the substrate (410b) and the metal plates (410a, 410c).

4. The method according to any one of claims 1 to 3, wherein, The bonding metal layer (411) includes Ti or TiW.

5. The method according to any one of claims 1 to 3, wherein, The bonding metal layer (411) is formed with a thickness of 0.01 μm to 0.03 μm.

6. The method according to any one of claims 1 to 3, wherein, The oxide bonding layer (412) includes titanium oxide.

7. The method according to any one of claims 1 to 3, wherein, The hot pressing process is performed at a temperature above 500°C and / or at a pressure greater than 0.5 MPa and less than 100 MPa.

8. A heat dissipation substrate for a power semiconductor module, the heat dissipation substrate comprising: First metal plate (410a); An oxide-based substrate (410b) bonded to the first metal plate (410a); A second metal plate (410c) is attached to the substrate (410b); as well as An oxide bonding layer (412) is located between the substrate (410b) and the first metal plate (410a) and / or between the substrate (410b) and the second metal plate (410c). The oxide bonding layer (412) is formed by hot pressing.

9. The heat dissipation substrate according to claim 8, wherein, The substrate (410b) includes an oxide-based ceramic substrate.

10. The heat dissipation substrate according to claim 8, wherein, The oxide bonding layer (412) includes titanium oxide.

11. The heat dissipation substrate according to any one of claims 8 to 10, wherein, The thickness of the oxide bonding layer (412) is 0.01 μm to 0.03 μm.

12. The heat dissipation substrate according to any one of claims 8 to 10, wherein, The first metal plate and / or the second metal plate comprise copper.

13. A power semiconductor module, the power semiconductor module comprising: At least one heat dissipation substrate according to any one of claims 8 to 10; At least one lead frame (310, 320); as well as At least one power semiconductor device (100a, 100b).

14. A power converter comprising the power semiconductor module of claim 13.

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