A BMCA implementation method of a gPTP protocol based on an FPGA

Abstract

The application discloses a BMCA implementation method of a gPTP protocol based on FPGA, and relates to the technical field of high-precision time synchronization and network communication. In view of the problems of large software BMCA processing delay, slow multi-port convergence and excessively high logic complexity of complete hardware implementation, the application provides a simplified BMCA hardware acceleration method: core priority vector comparison logic is extracted, an independent comparison module and a timeout timer are instantiated for each port in the FPGA; an event-driven mechanism is adopted, real-time iterative updating is triggered as soon as an Announce message is received; local best master clock is automatically announced when power is turned on or a link is timed out; a global arbitrator adopts a multi-stage pipeline tree-shaped comparator, and parameters of each port are compared in parallel, so that the role of the port is quickly determined. The application greatly reduces the convergence time and CPU load under the premise of ensuring the correctness of the election, and plays the parallel processing advantage of FPGA.

Description

Technical Field

[0001] This invention relates to the field of high-precision time synchronization and network communication technology, and in particular to a BMCA implementation method based on the gPTP protocol of FPGA. Background Technology

[0002] In Time-Sensitive Networking (TSN), the IEEE 802.1AS (gPTP) protocol is the foundation for achieving microsecond-level or even nanosecond-level time synchronization. The Optimal Master Clock Algorithm (BMCA) is the core component of gPTP, responsible for electing a unique time source within the network and determining the Master / Slave / Passive roles of each switching device port. While gPTP simplifies the BMCA compared to IEEE 1588v2, it still involves complex priority vector calculations, multi-port dataset comparisons, and timeout state machine interactions.

[0003] Existing gPTP protocol implementations mostly employ an architecture of FPGA for hardware timestamping and CPU for implementing the upper-layer protocol stack. In this architecture, the BMCA algorithm and state machine still run on CPU software, which has significant shortcomings.

[0004] CPU processing of Announce messages involves interrupt response and software scheduling, and the processing latency is uncertain in multi-port scenarios.

[0005] When network topology changes, such as the addition of new nodes or link failures, the software serial processing of BMCA leads to slow election convergence, affecting network recovery performance.

[0006] The software has difficulty in accurately maintaining the Announce timeout timer for multiple ports, which can easily lead to false timeouts or delayed responses.

[0007] While implementing the complete BMCA algorithm entirely in hardware can improve speed, the standard BMCA involves dozens of management objects and complex timer interactions, making a pure hardware implementation extremely large in scale and inflexible. Therefore, there is an urgent need for a gPTP BMCA implementation scheme that balances hardware processing efficiency with logical resource overhead to address the issues of rapid convergence and hardware timing when the network is dynamically changing. Summary of the Invention

[0008] To address the issues of slow software processing, overly complex hardware implementation, and timing violation risks in existing BMCA technologies, this invention provides a BMCA implementation method based on the gPTP protocol using FPGA. By extracting the core election logic and implementing a simplified hardware version, and introducing pipelined arbitration and event-driven mechanisms, a low-latency, high-reliability master clock election is achieved.

[0009] To solve the above technical problems, the technical solution adopted by the present invention is: a BMCA implementation method based on FPGA gPTP protocol, comprising the following steps:

[0010] S1: Construct a gPTP protocol hardware processing framework within the FPGA, mapping the local system priority vector and each port's dataset to hardware registers. During system power-on initialization, clear the port priority vectors of each port and start the hardware Announce receive timer;

[0011] S2: Receive gPTP Announce messages via FPGA multi-port MAC, and extract time synchronization parameters from the messages by the message parsing module. The parameters include root system identifier, step value, source port identifier and receiving port number.

[0012] S3: Based on the extracted time synchronization parameters, a simplified version of BMCA port-level real-time election is performed within the FPGA. For any PTP port, whenever a new Announce message is received, the hardware comparator corresponding to that port is immediately triggered to compare the newly received time synchronization parameters with the historical best parameters temporarily stored in the port register. If the new parameters are better, the temporarily stored best parameters for that port are updated in real time, and the port update flag is set.

[0013] S4: When the Announce receive timer times out or the port update flag is set, a simplified version of BMCA global election is performed. The optimal parameters temporarily stored in each port register are compared in parallel with the local system priority vector input to the FPGA global arbitrator, and the globally optimal time synchronization parameters are output as the best master clock parameters.

[0014] S5: Based on the global best master clock parameters and the optimal parameter sources temporarily stored in each port, the clock role state of each port is determined through parallel calculation by the hardware state machine. The role state includes master clock port, slave clock port and passive port.

[0015] S6: Based on the port role status, the FPGA controls the hardware transmission and reception of time synchronization messages and the capture of timestamps to achieve network-wide clock synchronization. If the Announce receive timer of a slave clock port times out without receiving a message, the hardware automatically ages the port information and triggers a global re-election.

[0016] Furthermore, the power-on bootstrapping logic in S1 is as follows: after the system is powered on, if the Announce receive timers of all ports time out and no external Announce message is received, the FPGA determines that there is no better master clock at present, directly uses the local system priority vector as the global best master clock parameter, sets the status of all valid ports to the master clock port, and starts sending Announce messages outward.

[0017] Furthermore, for a newly added gPTP system in an operational network, the operating logic is as follows: After the new system powers on, each port is in a listening state. If an external Announce message is received before the timer expires, a port-level real-time comparison of S3 is performed. If the root system identifier carried by the external message is superior to that of the local system, local bootstrapping is suppressed, the receiving port is set as a slave clock port, and other ports are set as master clock ports or passive ports according to the global election results.

[0018] Furthermore, the simplified BMCA in S3 specifically omits non-core complex state transitions and timer interactions from the standard protocol, retaining only the core election logic based on priority vectors. The comparison priority order of the hardware comparators is as follows: smaller root system identifier value, smaller step value, smaller source port identifier, and smaller receive port number. If a new message comes from a source port with the same temporary parameters as the current one, it is directly overwritten and updated.

[0019] Furthermore, the global arbiter in S4 adopts a multi-stage pipelined tree comparator structure, dividing the temporary parameters of N ports and 1 local system parameter (a total of N+1 vectors) into multiple comparison stages according to the tree topology. Register pacing is inserted between each stage of comparators, and the globally optimal time synchronization parameters are obtained through pipelined processing over multiple clock cycles to alleviate timing violations caused by wide-bit-width combinational logic.

[0020] Furthermore, the timeout reset logic in S6 is as follows: the FPGA maintains an independent hardware countdown timer for each port, and resets the timer when the port receives an Announce message. If the timer of the slave clock port times out without receiving a message, the hardware automatically clears the temporary optimal parameters of the port and resets the port state to the initial state, while triggering the global arbiter to recalculate the optimal master clock parameters and port role.

[0021] This invention proposes a power-on bootstrapping and dynamic joining mechanism based on a hardware timer. When the network is cold-started or a new node comes online, the entire process of listening, comparing and bootstrapping can be completed at hardware speed, compressing the algorithm convergence time from milliseconds to microseconds.

[0022] This invention addresses the issue of timing violations that are easily generated by wide-bit-width priority vector comparison. It employs a multi-stage pipelined tree arbiter, which uses register slicing to cut combinational logic paths. This ensures stable operation under high-frequency clocks while enabling parallel processing of multi-port data.

[0023] This invention employs a simplified version of BMCA hardware logic, stripping away the complex non-core state transitions in the protocol and only accelerating the core priority vector comparison through event-driven methods, thus achieving a balance between performance improvement and resource overhead within the limited logic resources of the FPGA. Attached Figure Description

[0024] Figure 1 A system architecture diagram of BMCA implementation based on FPGA gPTP protocol is provided for embodiments of the present invention;

[0025] Figure 2 The BMCA flowchart provided for embodiments of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0027] Example 1.

[0028] like Figure 1 As shown, a BMCA implementation system architecture based on the gPTP protocol is deployed in FPGA programmable logic, including a multi-port MAC module, a PTP message parsing module, a port-level parameter storage and comparison engine array, a global arbitrator, a port role state machine, and a hardware timer array.

[0029] The multi-port MAC module is used to receive Ethernet frames, identify gPTP packets with EtherType 0x88F7, and extract the Start-of-Frame Delimiter (SFD) signal for hardware timestamp generation.

[0030] The PTP message parsing module extracts key fields from the Announce message and constructs a message priority vector. In gPTP, this vector contains the root system identifier (14 bytes), step value (2 bytes), source port identifier (10 bytes), and receive port number (2 bytes), totaling 28 bytes.

[0031] The parsing module concatenates these fields into a 224-bit hardware-width vector, which is then fed into the subsequent comparison engine.

[0032] The port-level parameter temporary storage and comparison engine array is instantiated for each port. Each port maintains a 224-bit wide register to store the port priority vector.

[0033] When a new message arrives, the hardware comparator completes a bit-by-bit comparison of the old and new 224-bit vectors within one clock cycle. If the new vector is better, it is immediately overwritten into the temporary register, and the update flag signal is pulled high.

[0034] The hardware timer array maintains an Announce receive timeout timer for each port. It is based on the FPGA local clock and is reset when a valid Announce message is received.

[0035] When the count reaches the preset Announce receive timeout interval, a timeout signal is output, the temporary vector of the corresponding port is cleared, and a forced re-election is triggered.

[0036] The global arbiter receives the temporary vectors of all ports and one local system priority vector, and outputs the globally optimal master clock priority vector.

[0037] Since the 224-bit wide multi-way comparison combinational logic path is too long and prone to timing violations, the global arbiter in this embodiment adopts a multi-stage pipelined tree comparator structure, which compares N port temporary parameters and 1 local system parameter, a total of N+1 vectors, in a tree topology.

[0038] Registers are inserted between each comparator stage to time the data. Through multi-clock-cycle pipeline processing, the globally optimal time synchronization parameters are obtained, thereby cutting the combinational logic path and ensuring high-frequency timing convergence.

[0039] The port role state machine calculates the port role through hard-wired logic based on the global best master clock priority vector and the source of each port, and controls the message sending and receiving of the MAC layer.

[0040] Example 2.

[0041] Combination Figure 2 The BMCA operation process of this invention will be described in detail below:

[0042] During the system power-on initialization phase, the FPGA loads its configuration and builds a gPTP protocol hardware processing framework within the FPGA, mapping the local system priority vector and the datasets for each port to hardware registers. The port priority vectors for each port are cleared, and the hardware Announce receive timer for all ports is started, putting all ports into a listening state.

[0043] The FPGA multi-port MAC receives gPTP Announce messages, and the message parsing module extracts the time synchronization parameters from the messages.

[0044] During this phase, if all ports experience receive timeouts and no external Announce message is received, the FPGA determines that there is no better master clock in the network, performs power-on bootstrapping, directly uses the local system priority vector of the local system as the global best master clock priority vector, sets all valid ports to master clock ports, and starts sending Announce and Sync messages. At this point, the device becomes the best master clock in the network.

[0045] If a port receives an external Announce message before the timer expires, dynamic addition and port-level real-time election are performed, triggering the hardware comparator corresponding to that port to compare the extracted message priority vector with the port's temporary vector. If the external vector is better, the port's temporary optimal parameters are updated in real time, and the port update flag is set.

[0046] When the port update flag is set, a simplified version of BMCA global election is performed, comparing the optimal parameters temporarily stored in each port register with the local system priority vector in parallel with the FPGA global arbiter. If the external vector is better than the local system priority vector, the external vector is output as the globally optimal master clock priority vector, while local bootstrapping is suppressed.

[0047] Based on the globally optimal master clock parameters and the optimal parameter sources temporarily stored at each port, the clock role state of each port is determined through parallel calculations using a hardware state machine. The port that receives the optimal vector is determined to be a slave clock port, while other ports are determined to be either master clock ports or passive ports based on comparison results. Newly added devices complete role switching in microseconds through the above hardware logic.

[0048] Based on the port role status, the FPGA controls the hardware transmission and reception of time synchronization messages and timestamp capture to achieve network-wide clock synchronization. During network operation, if the Announce timer of the clock port times out without receiving a message, it indicates that the upstream master clock is disconnected. In this case, the hardware automatically ages the port information, clears the temporary vector, and resets the port status to the initial state. At the same time, it triggers the global arbitrator to recalculate the optimal master clock parameters and port role.

[0049] If no other better external clock is available, the local system will automatically bootstrap to become the new best master clock, enabling fast hardware-level switching.

[0050] This invention implements a simplified hardware acceleration within an FPGA by extracting the core vector comparison logic of gPTP BMCA. By utilizing event-driven and pipelined parallel comparison, it avoids the latency and uncertainty of software processing.

[0051] It also avoids the huge logical overhead and long-path timing violations of the standard BMCA implemented in full hardware, and significantly improves the real-time performance of BMCA election and network reconfiguration capability of multi-port devices.

[0052] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A BMCA implementation method for the gPTP protocol based on FPGA, characterized in that, Includes the following steps: S1: Construct a gPTP protocol hardware processing framework within the FPGA, mapping the local system priority vector and each port's dataset to hardware registers. During system power-on initialization, clear the port priority vectors of each port and start the hardware Announce receive timer; S2: Receive gPTP Announce messages via FPGA multi-port MAC, and extract time synchronization parameters from the messages by the message parsing module. The parameters include root system identifier, step value, source port identifier and receiving port number. S3: Based on the extracted time synchronization parameters, a simplified version of BMCA port-level real-time election is performed within the FPGA. For any PTP port, whenever a new Announce message is received, the hardware comparator corresponding to that port is immediately triggered to compare the newly received time synchronization parameters with the historical best parameters temporarily stored in the port register. If the new parameters are better, the temporarily stored best parameters for that port are updated in real time, and the port update flag is set. S4: When the Announce receive timer times out or the port update flag is set, a simplified version of BMCA global election is performed. The optimal parameters temporarily stored in each port register are compared in parallel with the local system priority vector input to the FPGA global arbitrator, and the globally optimal time synchronization parameters are output as the best master clock parameters. S5: Based on the global best master clock parameters and the optimal parameter sources temporarily stored in each port, the clock role state of each port is determined through parallel calculation by the hardware state machine. The role state includes master clock port, slave clock port and passive port. S6: Based on the port role status, the FPGA controls the hardware transmission and reception of time synchronization messages and the capture of timestamps to achieve network-wide clock synchronization. If the Announce receive timer of a slave clock port times out without receiving a message, the hardware automatically ages the port information and triggers a global re-election.

2. The implementation method according to claim 1, characterized in that, The power-on bootstrapping logic in S1 is as follows: After the system is powered on, if the Announce receive timers of all ports time out and no external Announce message is received, the FPGA determines that there is no better master clock at present, directly uses the local system priority vector as the global best master clock parameter, sets the status of all valid ports to the master clock port, and starts sending Announce messages outward.

3. The implementation method according to claim 1, characterized in that, For a newly added gPTP system in an operational network, the operating logic is as follows: After the new system powers on, all ports are in listening mode. If an external Announce message is received before the timer expires, a port-level real-time comparison is performed using S3. If the root system identifier carried by the external message is superior to that of the local system, local bootstrapping is suppressed, the receiving port is set as the slave clock port, and other ports are set as master clock ports or passive ports according to the global election results.

4. The implementation method according to claim 1, characterized in that, The simplified BMCA in S3 specifically omits non-core, complex state transitions and timer interactions from the standard protocol, retaining only the core election logic based on priority vectors. The hardware comparator's comparison priority order is as follows: smaller root system identifier value, smaller step value, smaller source port identifier, and smaller receive port number. If a new message originates from a source port with the same currently stored parameters, it is directly overwritten and updated.

5. The implementation method according to claim 1, characterized in that, The global arbiter in S4 adopts a multi-stage pipelined tree comparator structure, dividing the temporary parameters of N ports and 1 local system parameter (a total of N+1 vectors) into multiple comparison stages according to the tree topology. Register pacing is inserted between each stage of comparators, and the globally optimal time synchronization parameters are obtained through pipelined processing over multiple clock cycles to alleviate timing violations caused by wide-bit-width combinational logic.

6. The method according to claim 1, characterized in that, The timeout reset logic in S6 is as follows: The FPGA maintains an independent hardware countdown timer for each port, and resets the timer when the port receives an Announce message. If the timer of the slave clock port times out without receiving a message, the hardware automatically clears the temporary optimal parameters of the port and resets the port state to the initial state. At the same time, it triggers the global arbiter to recalculate the optimal master clock parameters and port role.

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