A transistor structure and a method of fabricating the same

Abstract

The application provides a transistor structure and a preparation method thereof, and the preparation method comprises the following steps: providing a semiconductor structure, the semiconductor structure comprising a substrate, a well region of a first conductive type, a gate oxide layer, a gate, a first side wall layer and a second side wall layer, etching the second side wall layer and the first side wall layer in sequence to form a first side wall and a second side wall, in a vertical direction, the height percentage of the second side wall relative to the height of the gate is 1% to 8%, performing a first ion implantation of a second conductive type on the substrate to form a lightly doped region, the second conductive type is opposite to the first conductive type, performing a second ion implantation of the second conductive type on the substrate to form a source-drain region, and the implantation angle of the first ion implantation is larger than the implantation angle of the second ion implantation. The preparation method of the transistor structure of the application can obtain a transistor structure with effectively inhibited hot carrier injection effect without an additional LDD mask.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a transistor structure and its fabrication method. Background Technology

[0002] Hot carrier injection (HCI) refers to the phenomenon where charge carriers in the channel gain kinetic energy exceeding the Si / SiO2 interface barrier (approximately 3.2 eV for electrons and 4.5 eV for holes) under a strong electric field, and are then injected from the silicon substrate into the oxide layer. This generates interface states and oxide layer trap charges, leading to drift in the flat-band voltage and threshold voltage of the device, as well as transconductance degradation. Since the electron injection barrier is lower than that for holes, the HCI effect is more pronounced in NMOS devices than in PMOS devices.

[0003] Currently, in the semiconductor manufacturing field, to suppress the high-concentration ionization (HCI) effect in MOS devices, a lightly doped drain (LDD) structure is typically introduced between the channel and drain. The LDD structure reduces the concentration gradient between the channel and the source / drain regions, widening the electric field, separation field peak, and current density peak in the space charge region. This reduces impact ionization and subsequent hot electron injection, effectively suppressing the HCI effect. However, fabricating the LDD structure requires an additional mask, increasing the manufacturing cost of the transistor device. Therefore, the industry has developed an alternative solution without adding an additional mask: for NMOS devices, a lightly doped drain (LDD) structure is introduced between the channel and drain regions. + An additional high-energy, low-dose (N) injection process is added to the injection process. - Large-angle ion implantation allows the implanted doping concentration to fall between the channel P-well and the source / drain regions, with the implanted region located between the P-well and the source / drain regions, thus approximately achieving the doping distribution of LDD.

[0004] However, when LDD implantation is combined with source / drain implantation, the MOSFET forms a spacer structure. This spacer is relatively large and significantly obstructs high-energy, large-angle ion implantation (i.e., LDD implantation). This results in a reduced effective implantation region after LDD implantation. When HCI occurs in the device, the expansion width of its space charge region is smaller than that of a regular LDD structure, and the separation between the peak electric field strength and current density is insufficient. Consequently, the effect of suppressing hot carrier injection is far from ideal, and it is impossible to balance cost control and reliable anti-HCI performance.

[0005] Therefore, how to provide a transistor structure and its fabrication method that can increase the effective range of LDD injection, suppress the hot carrier injection effect of the transistor structure, and improve the reliability of the transistor structure without adding an additional LDD mask has become an important problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a transistor structure and its fabrication method, which solves the problem that, without adding an additional mask, the effective range of the injection region formed after LDD implantation is small, the suppression effect of hot carrier injection effect on the transistor structure is poor, and the cost control and reliability performance cannot be balanced.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a transistor structure, comprising the following steps:

[0009] A semiconductor structure is provided, including a substrate, a well region of a first conductivity type, a gate oxide layer, a gate, a first sidewall layer and a second sidewall layer, wherein the well region is located on the upper surface of the substrate, the gate oxide layer is located on the substrate and covers the well region, the gate is located on the gate oxide layer, and the first sidewall layer and the second sidewall layer are stacked on the gate oxide layer from bottom to top and enclose the gate.

[0010] The second sidewall layer and the first sidewall layer are etched sequentially to form a first sidewall and a second sidewall. The first sidewall includes a horizontal portion on the gate oxide layer and a vertical portion on the gate sidewall. The second sidewall is located at the corner formed by the intersection of the horizontal portion and the vertical portion and forms a step structure with the horizontal portion. In the vertical direction, the height of the second sidewall is 1% to 8% of the height of the gate.

[0011] A first ion implantation of a second conductivity type is performed on the substrate to form a lightly doped region on the upper surface of the well region, the lightly doped region being located on both sides of the second sidewall layer and extending toward the second sidewall, the second conductivity type being opposite to the first conductivity type;

[0012] A second ion implantation of a second conductivity type is performed on the substrate to form a source / drain region located on the upper surface of the lightly doped region and on both sides of the second sidewall. The implantation concentration of the second ion implantation is greater than that of the first ion implantation, and the implantation angle and implantation energy of the first ion implantation are greater than those of the second ion implantation.

[0013] Optionally, forming the semiconductor structure includes the following steps:

[0014] A substrate is provided, and ions of a first conductivity type are implanted into the substrate to form the well region on the upper surface of the substrate, and a predetermined source region and a predetermined drain region are selected on the upper surface of the well region;

[0015] The gate oxide layer is formed on the substrate, and the gate oxide layer covers the well region;

[0016] The gate is formed on the gate oxide layer, and the gate is located between the preset source region and the preset drain region and is spaced from the preset source region and the preset drain region by a preset distance;

[0017] A first sidewall layer and a second sidewall layer are formed on the gate oxide layer in a bottom-up manner, and the first sidewall layer and the second sidewall layer encapsulate the gate.

[0018] Optionally, the thickness of the first sidewall ranges from 1 nm to 10 nm.

[0019] Optionally, in the vertical direction, the height of the second sidewall ranges from 1 nm to 10 nm.

[0020] Optionally, the height of the gate in the vertical direction ranges from 150 nm to 250 nm.

[0021] Optionally, the implantation concentration range for the first ion implantation is 4 × 10⁻⁶. 15 cm -2 ~6×10 15 cm -2 .

[0022] Optionally, the implantation concentration range of the second ion implantation is 2 × 10⁻⁶. 15 cm -2 ~4×10 15 cm -2 .

[0023] Optionally, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0024] Optionally, the implanted ions in the first ion implantation include arsenic ions, and the implanted ions in the second ion implantation include phosphorus ions.

[0025] The present invention also provides a transistor structure, comprising:

[0026] Substrate;

[0027] A well region of the first conductivity type is located on the upper surface of the substrate;

[0028] A gate oxide layer is located on the substrate and covers the well region;

[0029] The gate is located on the gate oxide layer;

[0030] A first sidewall and a second sidewall, the first sidewall comprising a horizontal portion on the gate oxide layer and a vertical portion on the gate sidewall, the second sidewall being located at the corner formed by the intersection of the horizontal portion and the vertical portion and forming a stepped structure with the horizontal portion, and in the vertical direction, the height of the second sidewall being a percentage of 1% to 8% of the height of the gate;

[0031] The lightly doped region of the second conductivity type is located on the upper surface of the well region and on both sides of the gate, and the second conductivity type is opposite to the first conductivity type;

[0032] The source / drain regions of the second conductivity type are located on the upper surface of the lightly doped region and on both sides of the second sidewall, and the doping concentration of the source / drain regions is greater than that of the lightly doped region.

[0033] The transistor structure is fabricated using any one of the transistor structure fabrication methods described above.

[0034] As described above, the method for fabricating a transistor according to the present invention includes the steps of: providing a semiconductor structure, including a substrate, a well region of a first conductivity type, a gate oxide layer, a gate, a first sidewall layer, and a second sidewall layer, wherein the well region is located on the upper surface layer of the substrate, the gate oxide layer is located on the substrate and covers the well region, the gate is located on the gate oxide layer, and the first sidewall and the second sidewall layer are sequentially stacked on the gate oxide layer from bottom to top and encapsulate the gate; sequentially etching the second sidewall layer and the first sidewall layer to form the first sidewall and the second sidewall, wherein the first sidewall includes a horizontal portion located on the gate oxide layer and a vertical portion located on the gate sidewall, and the second sidewall is located at the corner formed by the intersection of the horizontal portion and the vertical portion and forms a platform with the horizontal portion. The transistor structure has a stepped structure, and in the vertical direction, the height of the second sidewall is 1% to 8% of the gate height. A first ion implantation of the second conductivity type is performed on the substrate to form a lightly doped region on the upper surface of the well region. The lightly doped region is located on both sides of the second sidewall layer and extends towards the second sidewall. The second conductivity type is opposite to the first conductivity type. A second ion implantation of the second conductivity type is performed on the substrate to form source / drain regions. The source / drain regions are located on the upper surface of the lightly doped region and on both sides of the second sidewall. The implantation concentration of the second ion implantation is greater than that of the first ion implantation, and the implantation angle and energy of the first ion implantation are greater than those of the second ion implantation. The method for fabricating the transistor structure of the present invention has the following beneficial effects:

[0035] (1) The preparation method optimizes the shape of the sidewall structure of the gate for the source and drain injection process conditions. After the gate is formed, there is no need to add an additional mask for LDD injection. Instead, after the sidewall structure is formed, LDD injection and source and drain injection are performed directly on the substrate according to the optimized sidewall structure. This can increase the effective range of LDD injection, suppress the hot carrier injection effect of the transistor structure, and improve the reliability of the transistor structure.

[0036] (2) This preparation method saves LDD mask plates and reduces the manufacturing cost of transistor structure.

[0037] (3) The preparation method is based on 0.18 μm integrated circuit manufacturing process and is compatible with most process platforms. Attached Figure Description

[0038] Figure 1 This diagram illustrates the hot carrier injection effect in an NMOS device.

[0039] Figure 2 This is a graph showing the relationship between the gate voltage and substrate current of an NMOS device (V). ds =5.5 V).

[0040] Figure 3 The diagram shown is a structural schematic of an NMOS device.

[0041] Figure 4 The diagram shows a process flow chart of the method for fabricating the transistor structure of the present invention.

[0042] Figure 5 The diagram shown is a schematic of the semiconductor structure in the method for fabricating the transistor structure of the present invention.

[0043] Figure 6 The diagram shows a substrate used in the fabrication method of the transistor structure of the present invention.

[0044] Figure 7 The diagram shown is a schematic of the structure obtained after forming the well region in the method for fabricating the transistor structure of the present invention.

[0045] Figure 8 The diagram shown is a schematic of the structure obtained after forming the gate oxide layer in the method for fabricating the transistor structure of the present invention.

[0046] Figure 9 The diagram shown is a schematic of the structure obtained after forming the gate in the method for fabricating the transistor structure of the present invention.

[0047] Figure 10 The diagram shown is a schematic of the structure obtained after forming the first sidewall and the second sidewall in the method for fabricating the transistor structure of the present invention.

[0048] Figure 11 The diagram shown is a schematic of the structure obtained after forming a lightly doped region in the method for fabricating the transistor structure of the present invention.

[0049] Figure 12 The diagram shown is a schematic of the structure obtained after forming the source and drain regions in the method for fabricating the transistor structure of the present invention.

[0050] Explanation of reference numerals in the attached figures

[0051] 101 Drain 102 Source 103、203、304 gate 104 space charge region 105 electronic 106、202、303 Gate oxide layer 107 Hole 108、201 P-type substrate 204 Sidewall structure 2041 First side wall 2042 Second side wall 301 substrate 302 Tunnel 305 First side wall layer 306 Second side wall layer 307 Preset source area 308 Preset leak area 309 First side wall 310 Second side wall 311 Lightly doped region 312 Source / Leakage Area α The implantation angle of the first ion implantation β The implantation angle of the second ion implantation S1~S4 step Detailed Implementation

[0052] Please see Figure 1 The diagram illustrates the hot carrier injection effect of an NMOS device. In the diagram, the drain 101 of the NMOS device is connected to voltage VDD, the gate 103 is applied with 0.5VDD, and the source 102 is grounded. At this time, the device satisfies VDD. gs >V th And V ds >V gs -V th Therefore, the device is in a saturated on state, and the channel is pinched off at the drain end. The movement of electrons in the channel is as follows: they move from the source 102 into the channel towards the drain 101. After reaching the pinch-off point, under the action of the electric field force, they pass through the space charge region 104 and reach the drain end N. +In this region, when electrons pass through the space charge region 104, they gain high energy under the acceleration of the electric field. After these high-energy electrons collide and ionize in the space charge region 104, additional electron-hole pairs are generated. Electrons 105 in the electron-hole pairs will cross the Si / SiO2 interface barrier and enter the gate oxide layer 106, while holes 107 move in the opposite direction to electrons and are collected by the P-type substrate 108, becoming the substrate current (I0). sub Since the electron current injected into the gate oxide layer 106 is difficult to observe, it is usually represented by I. sub To characterize the strength of the HCI effect, I sub The larger the value, the more intense the collisional ionization, and the more significant the HCI effect.

[0053] For deep submicron CMOS process devices (e.g., 0.18 μm platform), NMOS devices V ds When fixed, I sub With V gs Changes such as Figure 2 As shown, I sub It is mainly affected by two mechanisms: V gs Starting from 0 and gradually increasing, the device turns on and quickly pinches off. I ds As this increases, the collisional ionization of charge carriers in the space charge region gradually intensifies, I sub It continues to increase. Meanwhile, due to V gs The potential difference between the gate and drain continuously increases (V) gd As V decreases, the electric field strength in the space charge region near the drain continuously weakens. gs Increase it to a certain level (usually 0.5V) ds ), I sub Reaching its maximum, V gs As the number of collisions continues to increase, the electric field strength caused by collision ionization decreases further, I sub It starts to get smaller.

[0054] Typically, devices have a long HCI lifetime under normal operating conditions, so the actual characterization of the hot carrier injection lifetime of NMOS devices uses an accelerated testing method: employing 3 sets of V ds Voltage, as the hot carrier injection condition of the device under high, medium and low stress, respectively, at a fixed V ds Find I below sub V at its maximum gs By obtaining these conditions, three sets of hot carrier injection conditions under different stresses are obtained. The lifetime curves obtained from these three sets of conditions can be fitted and extrapolated to obtain the HCI lifetime of the device under normal operation.

[0055] In the fabrication of transistor devices, a common practice to suppress the HCI effect is to introduce an LDD structure between the channel and drain. Taking a 3.3V NMOS device as an example, the dopant concentration in the channel (P-Well) region is typically 1×10⁻⁶. 17 cm -3 The source / drain region (N) + The dopant concentration is 1×10 20 cm -3 The LDD dopant concentration falls between these two values. This LDD structure reduces the concentration gradient between the channel and the source / drain regions, acting as a concentration buffer. Simultaneously, under applied HCI voltage, the LDD region widens the electric field in the space charge region, reducing the electric field strength and separating the peak field strength from the peak current density. Thus, both important factors contributing to impact ionization are suppressed, effectively inhibiting the HCI effect.

[0056] However, simply introducing the LDD structure requires adding an extra photomask (i.e., a mask), which increases production costs and reduces product competitiveness.

[0057] To achieve LDD structures without adding additional photomasks, there are several approaches in the industry. Please refer to [link / reference needed]. Figure 3 Taking NMOS as an example, the most common method is to complete the P-type substrate 201, gate oxide layer 202, gate 203 and sidewall structure 204, and then... + In the injection process, an additional high-energy, low-dose (N) step is added. - ), large-angle injection (such as Figure 3 (As indicated by the dashed arrow in the middle), this additional ion implantation dose is between that of the P-type substrate 201 and the source / drain (N... + The injection region is located between the P-type substrate 201 and the source / drain (N) region. + This achieves a doping effect close to that of an LDD structure. However, this ion implantation step is separate from the source / drain (N) phase in the process flow. + The implantation process is combined, at which point the NMOS transistor has formed a sidewall structure 204 (including a first sidewall 2041 and a second sidewall 2042). The second sidewall 2042 is relatively large and acts as a barrier to high-energy, large-angle ion implantation, hindering the formation of the LDD (N...) after implantation. - The effective area is reduced, and the space charge region formed when the HCI effect occurs in the device is also smaller than that of the normal LDD structure, making the suppression effect of the HCI effect in transistor devices less than ideal.

[0058] To address the above problems, this application provides a transistor structure and its fabrication method. This fabrication method optimizes the sidewall structure to enable a larger LDD-injected region, thereby effectively suppressing the hot carrier injection effect of the transistor structure without adding an additional LDD mask.

[0059] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0061] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0062] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0063] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0064] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0065] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0066] Please see Figure 4 The diagram shows a process flow chart for fabricating a transistor structure, which includes at least the following steps:

[0067] S1: A semiconductor structure is provided, including a substrate, a well region of a first conductivity type, a gate oxide layer, a gate, a first sidewall layer and a second sidewall layer, wherein the well region is located on the upper surface of the substrate, the gate oxide layer is located on the substrate and covers the well region, the gate is located on the gate oxide layer, and the first sidewall layer and the second sidewall layer are stacked on the gate oxide layer from bottom to top and enclose the gate.

[0068] S2: Sequentially etch the second sidewall layer and the first sidewall layer to form a first sidewall and a second sidewall. The first sidewall includes a horizontal portion on the gate oxide layer and a vertical portion on the gate sidewall. The second sidewall is located at the corner formed by the intersection of the horizontal portion and the vertical portion and forms a step structure with the horizontal portion. In the vertical direction, the height of the second sidewall is 1% to 8% of the height of the gate.

[0069] S3: Perform a first ion implantation of the second conductivity type into the substrate to form a lightly doped region on the upper surface of the well region, the lightly doped region being located on both sides of the second sidewall layer and extending toward the second sidewall, the second conductivity type being opposite to the first conductivity type;

[0070] S4: Perform a second ion implantation of the second conductivity type into the substrate to form a source / drain region, the source / drain region being located on the upper surface of the lightly doped region and on both sides of the second sidewall, the implantation concentration of the second ion implantation being greater than the implantation concentration of the first ion implantation, and the implantation angle and implantation energy of the first ion implantation being greater than the implantation angle and implantation energy of the second ion implantation.

[0071] The following section, using a structural diagram, details the specific implementation methods of each of the above steps.

[0072] Please refer to the following first. Figure 5Step S1: Provide a semiconductor structure including a substrate 301, a well region 302 of a first conductivity type, a gate oxide layer 303, a gate 304, a first sidewall layer 305, and a second sidewall layer 306. The well region 302 is located on the upper surface of the substrate 301. The gate oxide layer 303 is located on the substrate 301 and covers the well region 302. The gate 304 is located on the gate oxide layer 303. The first sidewall layer 305 and the second sidewall layer 306 are stacked on the gate oxide layer 303 from bottom to top and enclose the gate 304.

[0073] As an example, forming the semiconductor structure includes the following steps:

[0074] (1) Please refer to Figures 6 to 7 A substrate 301 is provided, and ions of a first conductivity type are implanted into the substrate 301 to form the well region 302 on the upper surface of the substrate 301. A predetermined source region 307 and a predetermined drain region 308 are selectively disposed on the upper surface of the well region 302. Figure 6 The diagram shown illustrates the substrate 301 used in the fabrication method of the transistor structure of the present invention. Figure 7 The diagram shown is a schematic diagram of the structure obtained after forming the well region 302 in the method for fabricating the transistor structure of the present invention.

[0075] (2) Please refer to Figure 8 The gate oxide layer 303 is formed on the substrate 301, and the gate oxide layer 303 covers the well region 302.

[0076] (3) Please refer to Figure 9 The gate 304 is formed on the gate oxide layer 303, and the gate 304 is located between the preset source region 307 and the preset drain region 308 and is spaced apart from the preset source region 307 and the preset drain region 308 by a preset distance.

[0077] (4) Please refer to the following: Figure 5 The first sidewall layer 305 and the second sidewall layer 306 are formed in a bottom-up manner on the gate oxide layer 303, and the first sidewall layer 305 and the second sidewall layer 306 enclose the gate 304.

[0078] Specifically, after implanting ions of a first conductivity type into the substrate 301 to form the well region 302 on the upper surface of the substrate 301, the process further includes an annealing activation step.

[0079] As an example, the process of forming the gate oxide layer 303 on the substrate 301 includes a thermal oxidation process.

[0080] As an example, the thickness of the gate oxide layer 303 ranges from 10 nm to 20 nm. In this embodiment, the thickness of the gate oxide layer 303 is 14 nm.

[0081] As an example, forming the gate 304 on the gate oxide layer 303 includes the following steps:

[0082] (1) A polysilicon layer is deposited on the gate oxide layer 303;

[0083] (2) Photolithography is performed on the polysilicon layer to form the gate 304.

[0084] As an example, the height of the gate 304 in the vertical direction ranges from 150 nm to 250 nm. In this embodiment, the height of the gate 304 is 200 nm.

[0085] As an example, the length of the gate 304 in the horizontal direction ranges from 0.5 μm to 0.7 μm. In this embodiment, the length of the gate 304 is 0.65 μm.

[0086] As an example, the thickness of the first sidewall layer 305 ranges from 10 nm to 30 nm, and the thickness of the second sidewall layer 306 ranges from 50 nm to 150 nm. In this embodiment, the thickness of the first sidewall layer 305 is 20 nm, and the thickness of the second sidewall layer 306 is 100 nm.

[0087] As an example, the material of the first sidewall layer 305 includes silicon dioxide, and the material of the second sidewall layer 306 includes silicon nitride.

[0088] Please see again Figure 10 Step S2: Sequentially etch the second sidewall layer 306 and the first sidewall layer 305 to form a first sidewall 309 and a second sidewall 310. The first sidewall 309 includes a horizontal portion on the gate oxide layer 303 and a vertical portion on the sidewall of the gate 304. The second sidewall 310 is located at the corner formed by the intersection of the horizontal portion and the vertical portion and forms a step structure with the horizontal portion. In the vertical direction, the height of the second sidewall 310 is 1% to 8% of the height of the gate 304.

[0089] As an example, the thickness of the first sidewall 309 ranges from 1 nm to 10 nm.

[0090] As an example, in the vertical direction, the height of the second sidewall 310 ranges from 1 nm to 10 nm. In this embodiment, the height of the second sidewall 310 is 6 nm.

[0091] As an example, in the horizontal direction, the length of the second sidewall 310 ranges from 60 nm to 80 nm. In this embodiment, the length of the second sidewall 310 is 70 nm.

[0092] Please see again Figure 11 Step S3: Perform a first ion implantation of the second conductivity type into the substrate 301 to form a lightly doped region 311. The lightly doped region 311 is located on the upper surface of the well region 302 and is situated on both sides of the gate 304, thereby forming a lightly doped region 311 on the upper surface of the well region 302. The lightly doped region 311 is located on both sides of the second sidewall 310 and extends towards the second sidewall 310. The second conductivity type is opposite to the first conductivity type. Figure 11 The dashed arrow in the middle indicates the direction of ion implantation, and α is the implantation angle.

[0093] Specifically, the ion implantation forming the lightly doped region 311 is LDD implantation. The LDD implantation energy is relatively high (greater than 70 keV), and the thickness (i.e., the vertical height) of the second sidewall 310 is relatively thin, allowing implanted ions to directly penetrate the second sidewall 310, the horizontal portion, and the gate oxide layer 303 to be implanted below the second sidewall 310, forming an effective connection with the channel. This increases the effective area of ​​the ion implantation region (i.e., the volume of the lightly doped region 311), thereby increasing the effective range of LDD implantation without adding an additional LDD mask, suppressing the hot carrier injection effect of the transistor structure, and improving the reliability of the transistor structure. Other sidewall structures of transistors fabricated using the same implantation conditions (see reference...) Figure 3 Even with a large implantation angle (30°~45°), the implantation energy is high because the second sidewall 2042 is thicker, blocking the implanted ions and preventing the formation of an effective lightly doped region at the HCI location. Therefore, by changing the structure of the second sidewall 310 and setting its height to 1%~8% of the height of the gate 304, LDD-implanted ions can pass through the second sidewall 310, the horizontal portion, and the gate oxide layer 303 to be implanted below the second sidewall 310, thereby increasing the effective area of ​​the ion implantation region. This increases the effective range of LDD implantation without adding an additional LDD mask and suppresses the hot carrier injection effect in the transistor structure.

[0094] As an example, the implantation angle α of the first ion implantation is in the range of 20°≤α≤45°.

[0095] Please see again Figure 12Step S4: Perform a second ion implantation of the second conductivity type into the substrate 301 to form source / drain regions 312. The source / drain regions 312 are located on the upper surface of the lightly doped region 311 and on both sides of the second sidewall 310. The implantation concentration of the second ion implantation is greater than that of the first ion implantation, and the implantation angle α and implantation energy of the first ion implantation are greater than those of the second ion implantation. Figure 12 The dashed arrow in the middle indicates the direction of ion implantation, and β is the implantation angle.

[0096] Specifically, the source-drain region 312 includes a source region formed in the preset source region 307 and a drain region formed in the preset drain region 308.

[0097] As an example, the implantation angle β of the second ion implantation is in the range of 0° < β ≤ 10°.

[0098] As an example, the implantation concentration range for the first ion implantation is 4 × 10⁻⁶. 15 cm -2 ~6×10 15 cm -2 .

[0099] As an example, the implantation concentration range of the second ion implantation is 2 × 10⁻⁶. 15 cm -2 ~4×10 15 cm -2 .

[0100] As an example, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, the first conductivity type is P-type and the second conductivity type is N-type.

[0101] As an example, the implanted ions in the first ion implantation include arsenic ions, and the implanted ions in the second ion implantation include phosphorus ions.

[0102] Specifically, the injection energy in step S4 is relatively low and will be blocked by the second sidewall 310, allowing injection only into the substrate 301 region outside the second sidewall 310, thereby forming a high-concentration doped region (e.g., N). + This area allows for good ohmic contact with the metal electrodes manufactured in subsequent processes.

[0103] This completes the fabrication of a transistor structure. Please refer to [link / reference]. Figure 12The transistor structure includes: a substrate 301, a well region 302 of a first conductivity type, a gate oxide layer 303, a gate 304, a first sidewall 309, a second sidewall 310, a lightly doped region 311 of a second conductivity type, and a source / drain region 312 of a second conductivity type, wherein the second conductivity type is opposite to the first conductivity type. The well region 302 is located on the upper surface of the substrate 301, the gate oxide layer 303 is located on the substrate 301 and covers the well region 302, the gate 304 is located on the gate oxide layer 303, and the first sidewall 309 includes a horizontal [missing information - likely a horizontal component] located on the gate oxide layer 303. The gate 304 has a horizontal portion and a vertical portion located on its sidewall. The second sidewall 310 is located at the corner formed by the intersection of the horizontal portion and the vertical portion and forms a stepped structure with the horizontal portion. In the vertical direction, the height of the second sidewall 310 is 1% to 8% of the height of the gate 304. The lightly doped region 311 is located on the upper surface of the well region 302 and is located on both sides of the gate 304. The source / drain region 312 is located on the upper surface of the lightly doped region 311 and is located on both sides of the second sidewall 310. The doping concentration of the source / drain region 312 is greater than that of the lightly doped region 311.

[0104] It is important to note that the dominant factors causing device degradation due to hot carrier injection differ with the device's process node. This application primarily concerns the 0.18 μm node process, where the HCI effect of NMOS is mainly characterized by I0... ds / I sub Ratio Model (I) ds Represents the drain current, I sub (Representing the substrate current), in this model, the HCI intensity of the NMOS is mainly related to I. ds and I sub / I ds The ratio is related to I sub / I ds The smaller the ratio, the better the suppression of the HCI effect in the transistor structure; therefore, I sub / I ds It is an important indicator of the HCI lifetime of NMOS devices.

[0105] To better demonstrate the HCI effect suppression effect of the transistor structure of this invention, software simulation was used to demonstrate the effect of HCI suppression. Figure 3 The sidewall structure shown and the sidewall structure of this invention, along with transistors obtained under the same P-well and LDD injection process conditions, were electrically compared. The comparison results are shown in the table below:

[0106] Table 1. Comparison of electrical properties of transistors fabricated by LDD implantation using different sidewall structures.

[0107]

[0108] In the table, transistor one is used Figure 3 The transistor shown is fabricated using LDD implantation with the sidewall structure of this invention. Transistor two is fabricated using LDD implantation with the sidewall structure of this invention (i.e., the transistor structure obtained by the fabrication method of this invention). VTG represents the gate 304 threshold voltage, IDL represents the linear region drain current, IDS represents the saturation region drain current, IBMAX represents the maximum substrate current, and IB / ID represents the ratio of substrate current to drain current. As can be seen from the table, the transistor structure obtained by the fabrication method of this invention has higher linear region current IDL and saturation region current IDS, and lower currents IBMAX and IB / ID in the HCI state, indicating that compared with the method using… Figure 3 Compared to the transistor structure fabricated by LDD implantation using the sidewall structure shown, the second sidewall 310 in this invention is thinner and does not obstruct high-energy ion implantation during LDD implantation, allowing for the formation of a larger N-type transistor below the second sidewall 310. - In the region (i.e., the lightly doped region 311), the effective channel length is shorter. Under the same ion implantation conditions, the fabrication method of the present invention can more effectively mitigate the electric field distribution of the device in the HCI state and suppress the HCI effect of the device. Thus, a transistor structure with more effective suppression of the HCI effect can be obtained without adding an additional LDD photomask, which is of great significance for process platform development and device design.

[0109] In summary, the transistor fabrication method of the present invention includes the following steps: providing a semiconductor structure, including a substrate, a well region of a first conductivity type, a gate oxide layer, a gate, a first sidewall layer, and a second sidewall layer, wherein the well region is located on the upper surface layer of the substrate, the gate oxide layer is located on the substrate and covers the well region, the gate is located on the gate oxide layer, and the first sidewall and the second sidewall layer are sequentially stacked on the gate oxide layer from bottom to top and encapsulate the gate; sequentially etching the second sidewall layer and the first sidewall layer to form the first sidewall and the second sidewall, wherein the first sidewall includes a horizontal portion located on the gate oxide layer and a vertical portion located on the gate sidewall, and the second sidewall is located at the corner formed by the intersection of the horizontal portion and the vertical portion and forms a platform with the horizontal portion. The transistor structure has a stepped structure, and in the vertical direction, the height of the second sidewall is 1% to 8% of the gate height. A first ion implantation of the second conductivity type is performed on the substrate to form a lightly doped region on the upper surface of the well region. The lightly doped region is located on both sides of the second sidewall layer and extends towards the second sidewall. The second conductivity type is opposite to the first conductivity type. A second ion implantation of the second conductivity type is performed on the substrate to form a source / drain region. The source / drain region is located on the upper surface of the lightly doped region and on both sides of the second sidewall. The implantation concentration of the second ion implantation is greater than that of the first ion implantation, and the implantation angle and energy of the first ion implantation are greater than those of the second ion implantation. The transistor structure fabrication method of this invention can increase the effective range of LDD implantation, suppress the hot carrier injection effect of the transistor structure, and improve the reliability of the transistor structure without adding an additional LDD mask. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a transistor structure, characterized in that, Includes the following steps: A semiconductor structure is provided, including a substrate, a well region of a first conductivity type, a gate oxide layer, a gate, a first sidewall layer and a second sidewall layer, wherein the well region is located on the upper surface of the substrate, the gate oxide layer is located on the substrate and covers the well region, the gate is located on the gate oxide layer, and the first sidewall layer and the second sidewall layer are stacked on the gate oxide layer from bottom to top and enclose the gate. The second sidewall layer and the first sidewall layer are etched sequentially to form a first sidewall and a second sidewall. The first sidewall includes a horizontal portion on the gate oxide layer and a vertical portion on the gate sidewall. The second sidewall is located at the corner formed by the intersection of the horizontal portion and the vertical portion and forms a step structure with the horizontal portion. In the vertical direction, the height of the second sidewall is 1% to 8% of the height of the gate. A first ion implantation of a second conductivity type is performed on the substrate to form a lightly doped region on the upper surface of the well region, the lightly doped region being located on both sides of the second sidewall and extending toward the second sidewall, the second conductivity type being the opposite of the first conductivity type; A second ion implantation of the second conductivity type is performed on the substrate to form a source / drain region, which is located on the upper surface of the lightly doped region and on both sides of the second sidewall. The implantation concentration of the second ion implantation is greater than that of the first ion implantation, and the implantation angle and implantation energy of the first ion implantation are greater than those of the second ion implantation.

2. The method for fabricating a transistor structure according to claim 1, characterized in that, Forming the semiconductor structure includes the following steps: A substrate is provided, and ions of a first conductivity type are implanted into the substrate to form the well region on the upper surface of the substrate, and a predetermined source region and a predetermined drain region are selected on the upper surface of the well region. The gate oxide layer is formed on the substrate, and the gate oxide layer covers the well region; The gate is formed on the gate oxide layer, and the gate is located between the preset source region and the preset drain region and is spaced from the preset source region and the preset drain region by a preset distance; A first sidewall layer and a second sidewall layer are formed on the gate oxide layer in a bottom-up manner, and the first sidewall layer and the second sidewall layer encapsulate the gate.

3. The method for fabricating a transistor structure according to claim 1, characterized in that: The thickness of the first sidewall ranges from 1 nm to 10 nm.

4. The method for fabricating a transistor structure according to claim 1, characterized in that: In the vertical direction, the height of the second sidewall ranges from 1 nm to 10 nm.

5. The method for fabricating a transistor structure according to claim 1, characterized in that: In the vertical direction, the height of the gate ranges from 150 nm to 250 nm.

6. The method for fabricating a transistor structure according to claim 1, characterized in that: The implantation concentration range for the first ion implantation is 4 × 10⁻⁶. 15 cm -2 ~6×10 15 cm -2 .

7. The method for fabricating a transistor structure according to claim 1, characterized in that: The implantation concentration range for the second ion implantation is 2 × 10⁻⁶. 15 cm -2 ~4×10 15 cm -2 .

8. The method for fabricating a transistor structure according to claim 1, characterized in that: The first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is P-type and the second conductivity type is N-type.

9. The method for fabricating a transistor structure according to claim 1, characterized in that: The implanted ions in the first ion implantation include arsenic ions, and the implanted ions in the second ion implantation include phosphorus ions.

10. A transistor structure, characterized in that, include: Substrate; A well region of the first conductivity type is located on the upper surface of the substrate; A gate oxide layer is located on the substrate and covers the well region; The gate is located on the gate oxide layer; A first sidewall and a second sidewall, the first sidewall comprising a horizontal portion on the gate oxide layer and a vertical portion on the gate sidewall, the second sidewall being located at the corner formed by the intersection of the horizontal portion and the vertical portion and forming a stepped structure with the horizontal portion, and in the vertical direction, the height of the second sidewall being a percentage of 1% to 8% of the height of the gate; The lightly doped region of the second conductivity type is located on the upper surface of the well region and on both sides of the gate, and the second conductivity type is opposite to the first conductivity type; The source / drain regions of the second conductivity type are located on the upper surface of the lightly doped region and on both sides of the second sidewall, and the doping concentration of the source / drain regions is greater than that of the lightly doped region. The transistor structure is fabricated using the method for fabricating a transistor structure as described in any one of claims 1 to 9.

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