A method of forming a shared contact hole and a semiconductor structure

Abstract

The application provides a shared contact hole forming method and a semiconductor structure, which comprises the following steps: forming a first hard mask layer on a region requiring a shared contact hole to be formed on a metal gate structure in a semiconductor process, achieving accurate protection of a region at the junction of an active region and a metal gate region, solving the problem of metal gate damage that may be caused in a traditional etching process, and through a step-by-step etching process, stopping the etching endpoint on the first hard mask layer and the second hard mask layer when etching a first interlayer dielectric layer, avoiding the generation of by-products due to over-etching of the metal gate, and completely etching the first hard mask layer and the second hard mask layer to expose part of the active region and the metal gate, finally forming a shared contact hole, achieving sufficient contact between the active region and the metal gate through a conductive layer formed in the shared contact hole, and finally improving the yield and reliability of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a method for forming a shared contact hole and a semiconductor structure. Background Technology

[0002] With the rapid development of integrated circuit technology, the size of transistors is constantly shrinking to achieve higher integration and more powerful functions. However, the continuous shrinking of transistor size also brings huge challenges to process development. In the fabrication process of semiconductor devices, contact holes (CTs) usually play a crucial role, responsible for connecting the source, drain, and gate of the transistor to external circuits, thereby enabling the semiconductor device to perform its functions through the metal layer.

[0003] Traditional contact holes (or ordinary contact holes) are typically square in top view and exhibit a columnar structure after fabrication. However, with the continuous changes in process requirements, some semiconductor processes require simultaneous connection of the metal gate with the source and drain regions. Traditional contact holes cannot meet the requirements of such semiconductor support, thus giving rise to shared contact holes (shared contact holes).

[0004] While shared contact vias enable the simultaneous routing of the metal gate and source / drain regions, their significant morphological differences from conventional contact holes (CTs) present additional challenges to semiconductor manufacturing processes. Firstly, the thin film composition of shared contact vias differs from that of conventional CTs. This often leads to issues during etching, such as the inability of a conventional CT to connect properly to the metal gate or source / drain regions while the shared contact via fails. Secondly, shared contact vias are more prone to contacting the metal gate during etching, and the etching process generates byproducts that can coat the active region, potentially hindering etching and resulting in poor contact between the conductive layer formed within the shared contact via and the active region. This is particularly evident in NMOS devices.

[0005] Currently, there is no particularly effective method to improve the problem of byproducts generated during metal gate etching hindering the etching of shared contact holes in metal gate fabrication processes. Therefore, there is an urgent need for a new method for forming shared contact holes to solve the above-mentioned problems, thereby ensuring good contact between the conductive layer formed in the shared contact hole and the active region and the metal gate.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions in this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. The existence of this problem not only affects the manufacturing yield of Shared CTs but may also adversely affect the performance and reliability of integrated circuits. Summary of the Invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for forming a shared contact hole and a semiconductor structure to solve the problem that in the existing metal gate process, the shared contact hole cannot properly connect to the metal gate or source and drain regions, or that by-products generated by over-etching of the metal gate block the etching of the shared contact hole, thereby affecting the yield and reliability of semiconductor devices.

[0008] To achieve the above objectives, the present invention provides a method for forming a shared contact hole, the method comprising:

[0009] A semiconductor substrate is provided, wherein at least two active regions are formed on the semiconductor substrate and shallow trench isolation is located between the active regions, and a plurality of gate structures are formed on the active regions and the gate structures are planarized.

[0010] A first hard mask layer is formed on the gate structure, and the first hard mask layer is etched to remove a portion of the first hard mask layer, with the remaining first hard mask layer covering the area where a shared contact hole needs to be formed.

[0011] A first interlayer dielectric layer is formed on the gate structure, and the first interlayer dielectric layer covers the gate structure and the first hard mask layer;

[0012] A first etching process is performed on the first interlayer dielectric layer to etch away the first interlayer dielectric layer, thereby forming an opening between adjacent gate structures, the opening exposing the first hard mask layer and a second hard mask layer located in the gate structure.

[0013] A second etching process is performed on the first hard mask layer and the second hard mask layer based on the opening, etching away the exposed first hard mask layer and the second hard mask layer to form a shared contact hole.

[0014] Optionally, the gate structure includes a silicide layer located within the active region and a second dielectric layer located on the silicide layer, wherein a second hard mask layer is further formed on the sidewalls and bottom of the second dielectric layer, and a metal gate is further formed between adjacent second hard mask layers located on the sidewalls of the second dielectric layer.

[0015] Optionally, the metal gate includes at least one of aluminum, titanium, tantalum, zirconium, cobalt, nickel, and their oxides.

[0016] Optionally, the thickness of the first hard mask layer is equal to the thickness of the second hard mask layer.

[0017] Optionally, the first etching process selects high selectivity etching of the first interlayer dielectric layer relative to the first hard mask layer and the second hard mask layer, and the second etching process selects high selectivity etching of the first hard mask layer and the second hard mask layer relative to the first interlayer dielectric layer.

[0018] Optionally, the material of the first hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride, and the material of the second hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

[0019] Optionally, after forming the shared contact hole, a conductive layer is formed by depositing metal within the shared contact hole, and the conductive layer forms an electrical connection with the silicide layer and the metal gate.

[0020] Optionally, the semiconductor substrate includes an NMOS device region, and the gate structure is formed on the semiconductor substrate in the NMOS device region.

[0021] The present invention also provides a semiconductor structure formed using the method for forming a shared contact hole described above, the semiconductor structure comprising:

[0022] A semiconductor substrate having at least two active regions and a shallow trench isolation between the active regions, wherein a plurality of gate structures are formed on the active regions;

[0023] A first hard mask layer is located on top of the gate and covers the area where a shared contact hole needs to be formed;

[0024] A first interlayer dielectric layer covers the gate structure and the first hard mask layer;

[0025] A shared contact hole is located on the gate structure and exposes a portion of the active region and the gate structure;

[0026] A conductive layer is located in the shared contact hole and connected to the active region and the gate structure.

[0027] Optionally, the metal gate includes at least one of aluminum, titanium, tantalum, zirconium, cobalt, nickel, and their oxides.

[0028] As described above, the shared contact hole formation method and semiconductor structure of the present invention have the following beneficial effects: By forming a first hard mask layer on the area where the shared contact hole needs to be formed on the gate structure, precise protection of the boundary area between the active region and the metal gate region is achieved, solving the problem of metal gate damage that may be caused in traditional etching processes. In addition, by using a step-by-step etching process, the etching endpoint can be stopped on the first hard mask layer and the second hard mask layer when etching the first interlayer dielectric layer, avoiding over-etching of the metal gate and generating byproducts. Then, the first hard mask layer and the second hard mask layer are completely etched to expose part of the active region and the metal gate, and finally a shared contact hole is formed. By forming a conductive layer in the shared contact hole, sufficient contact between the active region and the metal gate is achieved, ultimately improving the yield and reliability of the semiconductor device. Attached Figure Description

[0029] Figure 1 The diagram shows a process flow diagram of the method for forming the shared contact hole of the present invention.

[0030] Figure 2 The diagram shows a schematic representation of the substrate provided in the method for forming the shared contact hole of the present invention.

[0031] Figure 3 The diagram shown is a structural schematic of the first hard mask layer after it has been formed in the method for forming the shared contact hole of the present invention.

[0032] Figure 4 The diagram shown is a structural schematic after the formation of the first interlayer dielectric layer in the method for forming the shared contact hole of the present invention.

[0033] Figure 5 The diagram shown is a structural schematic after the first etching process is performed in the method for forming the shared contact hole of the present invention.

[0034] Figure 6 The diagram shows the structure after performing the second etching process in the method for forming the shared contact hole of the present invention.

[0035] Figure 7 The diagram shown is a structural schematic of the conductive layer formed in the method for forming the shared contact hole of the present invention.

[0036] Figure 8 The diagram shows a semiconductor structure formed using the method for forming shared contact holes according to the present invention.

[0037] Component designation explanation

[0038] 10. Substrate; 11. Active region; 12. Silicide layer; 13. Second hard mask layer; 14. Second dielectric layer; 15. Metal gate; 16. Shallow trench isolation; 17. First hard mask layer; 18. First interlayer dielectric layer; 19. Opening; 20. Shared contact hole; 21. Conductive layer; S1~S5: Steps. Detailed Implementation

[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0041] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0042] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0043] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0044] like Figure 1As shown, this embodiment provides a method for forming a shared contact hole, which includes the following steps:

[0045] S1: A semiconductor substrate 10 is provided, wherein at least two active regions 11 and shallow trench isolation 16 located between the active regions 11 are formed on the semiconductor substrate 10, and a plurality of gate structures are formed on the active regions 11 and the gate structures are planarized.

[0046] S2: A first hard mask layer 17 is formed on the gate structure. The first hard mask layer 17 is etched to remove part of the first hard mask layer 17. The remaining first hard mask layer 17 covers the area where the shared contact hole 20 needs to be formed.

[0047] S3: A first interlayer dielectric layer 18 is formed on the gate structure, the first interlayer dielectric layer 18 covering the gate structure and the first hard mask layer 17;

[0048] S4: Perform a first etching process on the first interlayer dielectric layer 18 to etch away the first interlayer dielectric layer 18 to form an opening 19 between adjacent gate structures, the opening 19 exposing the first hard mask layer 17 and the second hard mask layer 13 located in the gate structure.

[0049] S5: Perform a second etching process on the first hard mask layer 17 and the second hard mask layer 13 based on the opening 19, and etch away the exposed first hard mask layer 17 and the second hard mask layer 13 to form a shared contact hole 20.

[0050] It should be noted that the above order does not strictly represent the order of the method for forming the shared contact hole 20 protected by this invention. Those skilled in the art can modify it according to the actual preparation steps. The method for forming the shared contact hole 20 will be further described below with reference to the accompanying drawings:

[0051] In step S1, please refer to Figure 1 and Figure 2 A semiconductor substrate 10 is provided, wherein at least two active regions 11 and shallow trench isolation 16 located between the active regions 11 are formed on the semiconductor substrate 10, and a plurality of gate structures are formed on the active regions 11 and the gate structures are planarized.

[0052] like Figure 2As shown, a semiconductor substrate 10 is provided. The semiconductor substrate 10 can be a single-crystal or polycrystalline silicon substrate 10, or at least one of silicon-on-insulator (SOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). It can also include other types, such as compound semiconductors and / or alloy semiconductors, such as gallium nitride and gallium arsenide. In this embodiment, the semiconductor substrate 10 is a common single-crystal silicon substrate 10, and the semiconductor substrate 10 includes an NMOS device region. The gate structure is formed on the semiconductor substrate 10 in the NMOS device region.

[0053] At least two active regions 11 are formed on the semiconductor substrate 10, and a shallow trench isolation structure 16 is formed between the two active regions 11. Exemplarily, a method for forming the shallow trench isolation structure 16 in the semiconductor substrate 10 includes: first forming a patterned hard mask layer on the surface of the semiconductor substrate 10; etching using the patterned hard mask layer as a mask to form shallow trenches; filling the shallow trenches; planarizing the filled shallow trenches; and finally removing the hard mask layer to obtain the shallow trench isolation structure 16. Non-limiting examples of this planarization method include mechanical planarization and chemical mechanical polishing (CMP) planarization. CMP planarization is typically chosen. Preferably, the top surface of the shallow trench isolation structure 16 is flush with the surface of the semiconductor substrate 10.

[0054] Multiple gate structures are formed above the active region 11 and the shallow trench isolation 16 structure. Each gate structure includes a silicide layer 12 located within the active region 11 and a second dielectric layer 14 located on the silicide layer 12. A second hard mask layer 13 is formed on the sidewalls and bottom of the second dielectric layer 14, and a metal gate 15 is formed between adjacent second hard mask layers 13 located on the sidewalls of the second dielectric layer 14. The material constituting the metal gate 15 includes one or more of aluminum, titanium, tantalum, zirconium, cobalt, nickel, and their oxides. The second dielectric layer 14 is located directly above the silicide layer 12, and the width of the second dielectric layer 14 and the width of the second hard mask layers 13 on both sides are equal to the width of the silicide layer 12. The second hard mask layer 13, located at the bottom of the second dielectric layer 14, serves as a contact hole etching stop layer during contact hole etching. The material of the second hard mask layer 13 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride; for example, the material of the second hard mask layer 13 is silicon nitride. A planarization process is performed on the top of the gate structure to obtain a flat surface, which helps improve the yield of the formed semiconductor structure. Non-limiting examples of this planarization method include mechanical planarization and chemical mechanical polishing (CMP) planarization. CMP planarization is typically chosen. It should be understood that the gate structure in this example is for a metal-gate-after-gate process, but the invention is not limited thereto, and other gate structures can also be used.

[0055] In step S2, please refer to Figure 1 and Figure 3 A first hard mask layer 17 is formed on the gate structure. The first hard mask layer 17 is etched to remove a portion of the first hard mask layer 17, and the remaining first hard mask layer 17 covers the area where the shared contact hole 20 needs to be formed.

[0056] In this embodiment, as Figure 3 As shown, a first hard mask layer 17 is formed on the gate structure by depositing dielectric material using a chemical vapor deposition process. The material of the first hard mask layer 17 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, the first hard mask layer can be silicon nitride. Since multiple etching operations are only required in the area where the shared contact hole 20 needs to be formed, the first hard mask layer 17 needs to be pre-etched to remove a portion of it, leaving only the first hard mask layer 17 above the area where the shared contact hole 20 needs to be formed. This pre-etched first hard mask layer 17 serves as a contact hole etching stop layer during the etching of the shared contact hole 20.

[0057] As an example, the thickness of the first hard mask layer is equal to the thickness of the second hard mask layer. Specifically, setting the thickness of the first hard mask layer to be equal to the thickness of the second hard mask layer allows the first hard mask layer 17 and the second hard mask layer 13 to be completely removed simultaneously during the second etching, thereby reducing production costs.

[0058] In step S3, please refer to Figure 1 and Figure 4 A first interlayer dielectric layer 18 is formed on the gate structure, and the first interlayer dielectric layer 18 covers the gate structure and the first hard mask layer 17.

[0059] like Figure 4 As shown, a first interlayer dielectric layer 18 is formed on the gate structure. The material of the first interlayer dielectric layer 18 can be one or more of silicon oxide, silicon nitride, and silicon oxynitride. The height of the first interlayer dielectric layer 18 is greater than the height of the first hard mask layer. Specifically, in this embodiment, the material of the first interlayer dielectric layer 18 is silicon oxide, which can be formed using atomic layer deposition (ALD).

[0060] In step S4, please refer to Figure 1 and Figure 5 A first etching process is performed on the first interlayer dielectric layer 18 to etch away the first interlayer dielectric layer 18, thereby forming an opening 19 between adjacent gate structures, the opening 19 exposing the first hard mask layer 17 and the second hard mask layer 13 located in the gate structure.

[0061] Please refer to Figure 5 The first etching process is performed, specifically, a photoresist mask layer is formed on the first interlayer dielectric layer 18, and the photoresist mask layer is exposed and developed to form a patterned photoresist mask layer. Based on the patterned photoresist mask layer, the first interlayer dielectric layer 18 is etched back to form an opening 19 in the area where the shared contact hole 20 needs to be formed. The opening 19 spans the metal gate 15 and the silicide layer 12.

[0062] The first etching process selects the first interlayer dielectric layer 18 for high selectivity etching relative to the first hard mask layer 17 and the second hard mask layer 13. This ensures that after the first etching process is completed, the etching endpoint is on the first hard mask layer 17 and the second hard mask layer 13. Compared to when the first hard mask layer 17 is not formed, the first etching process will not etch the metal gate 15, and therefore will not generate etching byproducts. This will not affect the quality of the formed shared contact hole 20. The composition, flow rate, and process conditions of the etching gas used in the first etching process are well known in the art. Those skilled in the art can select and adjust them according to actual needs. Further details are not provided here.

[0063] In step S5, please refer to Figure 1 and Figure 6 A second etching process is performed on the first hard mask layer 17 and the second hard mask layer 13 based on the opening 19 to etch away the exposed first hard mask layer 17 and the second hard mask layer 13, forming a shared contact hole 20.

[0064] Please refer to Figure 6 The second etching process is then performed. Specifically, the second etching process involves etching the first hard mask layer 17 and the second hard mask layer 13 with a high selectivity relative to the first interlayer dielectric layer 18. This allows the first hard mask layer 17 and the second hard mask layer 13 located within the opening 19 to be completely removed after the second etching process is completed. The resulting shared contact hole 20 exposes the silicide layer 12 and the metal gate 15 located in the active region 11. The composition, flow rate, and process conditions of the etching gas used in the second etching process are well known in the art, and those skilled in the art can select and adjust them according to actual needs. Further details are not provided here.

[0065] After the step of forming the shared contact hole 20, the following steps are also included: Please refer to Figure 7 A conductive layer 21 is formed by depositing metal in the shared contact hole 20. This can be achieved using a physical vapor deposition process. The conductive layer 21 is made of materials such as tungsten. A chemical mechanical polishing process is used to planarize the conductive layer 21 so that its top has a flat surface. The conductive layer 21 forms good contact with the silicide layer 12 in the active region 11 and the metal gate 15, thereby achieving better electrical connection.

[0066] In another embodiment of the present invention, a semiconductor structure is also proposed, which is formed using the method for forming the shared contact hole 20 described above, such as... Figure 8As shown, the semiconductor structure includes a semiconductor substrate 10, on which at least two active regions 11 are formed and a shallow trench isolation 16 is located between the active regions 11. A plurality of gate structures are formed on the active regions 11; a first hard mask layer 17, which is located on top of the gate and covers the area where a shared contact hole 20 needs to be formed; a first interlayer dielectric layer 18, which covers the gate structure and the first hard mask layer 17; a shared contact hole 20, which is located on the gate structure and exposes a portion of the active regions 11 and the gate structure; and a conductive layer 21, which is located on the shared contact hole 20 and connected to the active regions 11 and the gate structure.

[0067] As an example, the metal gate 15 includes at least one of aluminum, titanium, tantalum, zirconium, cobalt, nickel and their oxides.

[0068] In summary, the shared contact hole formation method and semiconductor structure proposed in this invention achieve precise protection of the boundary region between the active region and the metal gate region by first forming a first hard mask layer on the area where the shared contact hole needs to be formed on the gate structure. This solves the problem of metal gate damage that may occur in traditional etching processes. Furthermore, the step-by-step etching process allows the etching endpoint to be stopped at the first and second hard mask layers during the etching of the first interlayer dielectric layer, avoiding over-etching of the metal gate and the generation of byproducts. Then, the first and second hard mask layers are completely etched to expose part of the active region and the metal gate, ultimately forming the shared contact hole. The conductive layer formed within the shared contact hole achieves sufficient contact between the active region and the metal gate, ultimately improving the yield and reliability of the semiconductor device. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for forming a shared contact hole, characterized in that, The method for forming the shared contact hole includes: A semiconductor substrate is provided, wherein at least two active regions are formed on the semiconductor substrate and shallow trench isolation is located between the active regions, and a plurality of gate structures are formed on the active regions and the gate structures are planarized. A first hard mask layer is formed on the gate structure, and the first hard mask layer is etched to remove a portion of the first hard mask layer, with the remaining first hard mask layer covering the area where a shared contact hole needs to be formed. A first interlayer dielectric layer is formed on the gate structure, and the first interlayer dielectric layer covers the gate structure and the first hard mask layer; A first etching process is performed on the first interlayer dielectric layer to etch away the first interlayer dielectric layer, thereby forming an opening between adjacent gate structures, the opening exposing the first hard mask layer and a second hard mask layer located in the gate structure. A second etching process is performed on the first hard mask layer and the second hard mask layer based on the opening, etching away the exposed first hard mask layer and the second hard mask layer to form a shared contact hole.

2. The method for forming a shared contact hole according to claim 1, characterized in that, The gate structure includes a silicide layer located in the active region and a second dielectric layer located on the silicide layer, wherein a second hard mask layer is formed on the sidewalls and bottom of the second dielectric layer, and a metal gate is formed between adjacent second hard mask layers located on the sidewalls of the second dielectric layer.

3. The method for forming a shared contact hole according to claim 2, characterized in that, The metal gate includes at least one of aluminum, titanium, tantalum, zirconium, cobalt, nickel, and their oxides.

4. The method for forming a shared contact hole according to claim 1, characterized in that, The thickness of the first hard mask layer is equal to the thickness of the second hard mask layer.

5. The method for forming a shared contact hole according to claim 4, characterized in that, The first etching process selects the first interlayer dielectric layer to be etched with a high selectivity relative to the first hard mask layer and the second hard mask layer, and the second etching process selects the first hard mask layer and the second hard mask layer to be etched with a high selectivity relative to the first interlayer dielectric layer.

6. The method for forming a shared contact hole according to claim 1, characterized in that, The material of the first hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride, and the material of the second hard mask layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

7. The method for forming a shared contact hole according to claim 2, characterized in that, After forming the shared contact hole, a conductive layer is formed by depositing metal in the shared contact hole, and the conductive layer forms an electrical connection with the silicide layer and the metal gate.

8. The method for forming a shared contact hole according to claim 1, characterized in that, The semiconductor substrate includes an NMOS device region, and the gate structure is formed on the semiconductor substrate in the NMOS device region.

9. A semiconductor structure, characterized in that, The shared contact hole is formed using the method for forming a shared contact hole according to any one of claims 1 to 8, comprising: A semiconductor substrate having at least two active regions and a shallow trench isolation between the active regions, wherein a plurality of gate structures are formed on the active regions; A first hard mask layer is located on top of the gate and covers the area where a shared contact hole needs to be formed; A first interlayer dielectric layer covers the gate structure and the first hard mask layer; A shared contact hole is located on the gate structure and exposes a portion of the active region and the gate structure; A conductive layer is located in the shared contact hole and connected to the active region and the gate structure.

10. The semiconductor structure according to claim 9, characterized in that, The metal gate includes at least one of aluminum, titanium, tantalum, zirconium, cobalt, nickel, and their oxides.

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