Back contact cells and methods of making the same

Abstract

A back contact cell and a preparation method thereof, the back contact cell comprising a silicon wafer, a dielectric layer, a P-type passivation layer, a protruding passivation layer and a P-type electrode, the dielectric layer being arranged on a back light surface of the silicon wafer; the P-type passivation layer and the protruding passivation layer are both arranged on a side of the dielectric layer away from the silicon wafer; wherein the thickness of the protruding passivation layer is less than the thickness of the P-type passivation layer, the protruding passivation layer is formed of a passivation material, and the protruding passivation layer and the P-type passivation layer are in electrical contact; the P-type electrode is electrically connected to the P-type passivation layer, thus, the present application can improve the open circuit voltage and the short circuit current, while ensuring the long-term reliability of the ohmic contact between the electrode and the emitter.

Description

Technical Field

[0001] This application relates to the field of solar energy, and more specifically, to a back contact battery and a method for its preparation. Background Technology

[0002] With the escalating global energy crisis and growing environmental awareness, solar energy, as a clean and renewable energy source, has become an important component of global energy strategies for its development and efficient utilization. Among solar energy utilization technologies, solar cells, as the core device for directly converting sunlight into electricity, have consistently been a focus of attention for both academia and industry in terms of photoelectric conversion efficiency and long-term operational reliability.

[0003] Back-contact solar cells, with their unique structural design—arranging all electrodes on the back surface of the cell—effectively avoid the blocking of incident light by traditional front-surface electrodes, thus significantly improving the effective light-receiving area and short-circuit current density. They have shown outstanding advantages in high-efficiency solar cell technology and have become one of the research hotspots in the photovoltaic field in recent years.

[0004] However, existing back-contact batteries still face several key technical bottlenecks in terms of structural design and material application. First, in the P-type emitter structure, the poor surface passivation results in a high interface state density and severe non-radiative recombination of charge carriers, thus limiting further improvements in the battery's open-circuit voltage (Voc) and short-circuit current (Isc). Second, some back-contact batteries suffer from insufficient ohmic contact stability between the emitter and the metal electrode, making them prone to contact degradation under actual operating conditions such as high temperature, high humidity, or prolonged sunlight exposure. This leads to increased contact resistance, affecting battery output performance and lifespan. Summary of the Invention

[0005] This application provides a back contact battery and its preparation method, which can improve the open circuit voltage and short circuit current, while ensuring the long-term reliability of the ohmic contact between the electrode and the emitter.

[0006] The embodiments of this application are implemented as follows: In a first aspect, the present invention provides a back contact battery, comprising: Silicon wafers; A dielectric layer disposed on the back surface of the silicon wafer; Both a P-type passivation layer and a protruding passivation layer are disposed on the dielectric layer on the side opposite to the silicon wafer; wherein, the thickness of the protruding passivation layer is less than the thickness of the P-type passivation layer, the protruding passivation layer is formed of a passivation material, and the protruding passivation layer and the P-type passivation layer are in electrical contact; And a P-type electrode electrically connected to the P-type passivation layer.

[0007] In an optional embodiment, the width of the protruding passivation layer is 1~6μm.

[0008] In an optional embodiment, the length of the protruding passivation layer is 150~230mm.

[0009] In an optional embodiment, the protruding passivation layer is composed of one or more of silicon oxide, P-type doped polysilicon, and N-type doped polysilicon.

[0010] In an optional embodiment, the protruding passivation layer is composed of silicon oxide and P-type polycrystalline silicon in a mass ratio of 1:4 to 3:7; or, The protruding passivation layer is composed of silicon oxide, P-type polycrystalline silicon and N-type polycrystalline silicon in a mass ratio of 1:0.5:0.2 to 1:2:1.

[0011] In an optional embodiment, a groove is formed on the side of the dielectric layer facing away from the silicon wafer, and the protruding passivation layer is located within the groove; The P-type passivation layer is located outside the groove.

[0012] In an optional embodiment, an insulating separation band is formed on the backlight surface, and the dielectric layer is separated into a first dielectric layer and a second dielectric layer by the insulating separation band. The P-type passivation layer and the protruding passivation layer are both located in the first dielectric layer. The back contact battery also includes an N-type passivation layer disposed on the second dielectric layer and an N-type electrode electrically connected to the N-type passivation layer.

[0013] Secondly, the present invention provides a method for preparing a back contact battery, used to prepare the back contact battery described in the foregoing embodiments, the method comprising the following steps: A dielectric layer is deposited on the back surface of the silicon wafer; A protruding passivation layer and a P-type passivation layer are deposited on the dielectric layer; A P-type electrode is printed on the P-type passivation layer.

[0014] In an optional embodiment, in the step of depositing the protruding passivation layer and the P-type passivation layer on the dielectric layer, a groove is first formed on the dielectric layer by laser and etching processes, and then deposition is performed to form the protruding passivation layer in the groove and the P-type passivation layer outside the groove.

[0015] In an optional embodiment, after the step of depositing a protruding passivation layer and a P-type passivation layer on the dielectric layer, the fabrication method further includes: An insulating separation band is formed on the backlight surface, wherein the insulating separation band separates the dielectric layer into a first dielectric layer and a second dielectric layer; After the step of depositing a dielectric layer on the back surface of the silicon wafer, the fabrication method further includes: An N-type passivation layer is deposited on the second dielectric layer; An N-type electrode is printed on the N-type passivation layer; In the step of depositing a protruding passivation layer and a P-type passivation layer on the dielectric layer, the protruding passivation layer and the P-type passivation layer are deposited on the first dielectric layer.

[0016] The advantages of this application compared to the prior art include: Because a dielectric layer is formed on the back surface of the silicon wafer, and P-type passivation layers and protruding passivation layers of different thicknesses are formed on it simultaneously, and the two are electrically connected to each other, while the P-type electrode is only electrically connected to the P-type passivation layer, a composite passivation-contact structure with a local carrier selective enhancement channel is constructed. Therefore, in the P-type emitter region, the dielectric layer and the P-type passivation material together provide high-quality surface passivation, effectively suppress the interface state density, and significantly reduce the nonradiative recombination rate of carriers. Meanwhile, the thinner protruding passivation layer acts as a local tunneling barrier reduction region, forming an efficient channel for preferential hole transport and enhancing the tunneling and collection efficiency of majority carriers (holes) from the silicon bulk to the metal electrode. Thus, while maintaining a high open-circuit voltage (Voc), it effectively reduces the contact resistance between the P-type region and the electrode, and improves the short-circuit current density (Jsc) and fill factor (FF), ultimately achieving a synergistic improvement in photoelectric conversion efficiency.

[0017] Furthermore, since the protruding passivation layer forms a local protrusion structure geometrically, it constitutes a microscale three-dimensional contact interface with the P-type passivation layer covering it and the subsequent metal electrode; thus, it increases the effective electrical contact area between the P-type emitter and the metal electrode and introduces a certain degree of mechanical interlocking effect. Meanwhile, the protruding passivation layer is formed of passivation material, which has good matching with the metal electrode in terms of thermal expansion coefficient and chemical stability. Thus, under harsh working conditions such as high temperature, high humidity or long-term light exposure, it effectively alleviates the problems of interface stress concentration and metal diffusion, and inhibits the degradation of the contact interface. This significantly improves the long-term reliability and stability of the electrode contact and extends the service life of the back contact solar cell. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the back contact battery structure according to an embodiment of this application; Figure 2 for Figure 1 A partial schematic diagram of a P-type emitter.

[0020] Icons: 1-Silicon wafer; 2-P-type passivation layer; 3-Protruding passivation layer; 4-P-type electrode; 5-First dielectric layer; 6-Second dielectric layer; 7-N-type passivation layer; 8-N-type electrode; 9-Insulating separation strip; 10-Backlight surface; 11-Light-receiving surface; 12-Light-receiving passivation layer; 13-Antireflection layer. Detailed Implementation

[0021] As used in this article: "Prepared from" is synonymous with "comprising". The terms "comprising", "including", "having", "containing", or any other variations thereof as used herein are intended to cover non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that includes the listed elements is not necessarily limited to those elements, but may include other elements not expressly listed or elements inherent to such composition, step, method, article, or apparatus.

[0022] When a quantity, concentration, or other value or parameter is expressed as a range, a preferred range, or a range defined by a series of upper and lower preferred values, this should be understood as specifically disclosing all ranges formed by any pair of any upper or preferred value with any lower or preferred value, regardless of whether the range is disclosed individually. For example, when the range “1–5” is disclosed, the described range should be interpreted as including ranges “1–4”, “1–3”, “1–2”, “1–2 and 4–5”, “1–3 and 5”, etc. When numerical ranges are described herein, unless otherwise stated, the range is intended to include its endpoints and all integers and fractions within that range.

[0023] This application discloses a back contact battery, which includes: Silicon wafer 1; A dielectric layer is disposed on the backlight surface 10 of the silicon wafer 1; A P-type passivation layer 2 and a protruding passivation layer 3 are disposed on the side of the dielectric layer facing away from the silicon wafer 1; wherein, the protruding passivation layer 3 is formed of a passivation material, the thickness of the protruding passivation layer 3 is less than the thickness of the P-type passivation layer 2, and the protruding passivation layer 3 and the P-type passivation layer 2 are in electrical contact. And a P-type electrode 4 electrically connected to the P-type passivation layer 2.

[0024] In this way, since a dielectric layer is provided on the back surface 10 of silicon wafer 1, and a P-type passivation layer 2 and a protruding passivation layer 3 of different thicknesses are formed on it simultaneously and are electrically in contact with each other, while the P-type electrode 4 is only electrically connected to the P-type passivation layer 2, a composite passivation-contact structure with a local carrier selective enhancement channel is constructed. Therefore, in the P-type emitter region, the dielectric layer and the P-type passivation material together provide high-quality surface passivation, effectively suppress the interface state density, and significantly reduce the nonradiative recombination rate of carriers. Meanwhile, the thinner protruding passivation layer 3 serves as a local tunneling barrier reduction region, forming an efficient channel for preferential hole transport and enhancing the tunneling and collection efficiency of majority carriers (holes) from the silicon bulk to the metal electrode. Thus, while maintaining a high open-circuit voltage (Voc), it effectively reduces the contact resistance between the P-type region and the electrode, and improves the short-circuit current density (Jsc) and fill factor (FF), ultimately achieving a synergistic improvement in photoelectric conversion efficiency.

[0025] Furthermore, since the protruding passivation layer 3 forms a local protrusion structure in geometry, it constitutes a microscale three-dimensional contact interface with the P-type passivation layer 2 covering it and the subsequent metal electrode; thus, it increases the effective electrical contact area between the P-type emitter and the metal electrode and introduces a certain degree of mechanical interlocking effect. Meanwhile, the protruding passivation layer 3 is formed of passivation material, so it has good matching with the metal electrode in terms of thermal expansion coefficient and chemical stability; thus, under harsh working conditions such as high temperature, high humidity or long-term light exposure, it effectively alleviates the problems of interface stress concentration and metal diffusion, and inhibits the degradation of the contact interface; thereby significantly improving the long-term reliability and stability of the electrode contact and extending the service life of the back contact solar cell.

[0026] Optionally, a groove is formed on the side of the dielectric layer facing away from the silicon wafer 1, and the protruding passivation layer 3 is located within the groove; the P-type passivation layer 2 is located outside the groove. Thus, since a groove is provided on the side of the dielectric layer away from the silicon wafer 1, and the protruding passivation layer 3 is precisely embedded in the groove, while the P-type passivation layer 2 covers the outer area of ​​the groove, and the protruding passivation layer 3 and the P-type passivation layer 2 are in electrical contact with each other and together form a continuous P-type emitter functional layer; therefore, the groove structure plays a role in spatially limiting and thickness control of the protruding passivation layer 3, enabling it to achieve a thinner passivation layer thickness in a local area, thereby effectively reducing the carrier tunneling barrier; Meanwhile, the stepped structure formed at the edge of the groove naturally guides the metal electrode to preferentially cover the protruding passivation layer 3 during subsequent deposition, ensuring that the P-type electrode 4 establishes ohmic contact with the P-type region only through a low-resistance channel, avoiding direct contact in the high-passivation but high-resistance region; thus, the protruding passivation layer 3 formed in the groove serves as a localized high-conductivity path, working in synergy with the P-type passivation layer 2 outside the groove, which has excellent passivation performance, to achieve the functional zoning of "high passivation + low contact resistance": it both maximizes the suppression of interface recombination to maintain a high open-circuit voltage (Voc) and ensures efficient hole collection to improve short-circuit current (Isc) and fill factor (FF); ultimately significantly improving the overall photoelectric conversion efficiency of the battery.

[0027] Furthermore, since the protruding passivation layer 3 is embedded in the groove of the dielectric layer, it forms a physically encapsulated three-dimensional contact configuration with the upper metal electrode. The sidewalls of the groove anchor the metal electrode material, enhancing the mechanical interlocking effect of the interface. At the same time, the groove structure restricts the lateral diffusion path of metal atoms under high temperature or long-term operation, reducing the risk of chemical degradation of the metal-semiconductor interface. Combined with the thermally stable material system (such as ultrathin silicon oxide / doped polycrystalline silicon stack) used in the protruding passivation layer 3, the contact interface maintains a low and stable contact resistance under actual operating conditions such as humid heat, light exposure, or thermal cycling. This significantly improves the long-term reliability and environmental tolerance of the back contact battery electrode connection, extending the service life of the device.

[0028] The width of the protruding passivation layer 3 is 1~6μm. In this way, on the one hand, when the width is ≥1μm, it is sufficient to form a continuous and stable carrier tunneling channel, ensuring that holes are efficiently transported to the metal electrode in the local area, avoiding current congestion or a significant increase in contact resistance due to too small contact area, thereby effectively supporting the improvement of short-circuit current density (Jsc) and fill factor (FF).

[0029] On the other hand, when the width is ≤6μm, it can prevent the passivation coverage integrity of the dielectric layer on the non-contact area from being weakened due to the excessive width of the area, and avoid problems such as alignment deviation, material overflow or poor step coverage caused by the excessive size of the pattern in subsequent photolithography, deposition or etching processes, thus ensuring the feasibility and yield of high-precision micro-nano processing.

[0030] In addition, this width range matches the finger electrode pitch of a typical back-contact battery, which is conducive to achieving a high-density staggered arrangement of P-type and N-type contact areas, maximizing the effective power generation area within a limited back surface space. Therefore, the 1~6μm width design achieves a good balance between electrical performance optimization and manufacturing process compatibility. It fully leverages the functional advantages of the prominent passivation layer 3 in reducing contact recombination and improving carrier collection efficiency, while also taking into account process robustness and structural controllability under mass production conditions, ultimately promoting the simultaneous improvement of battery conversion efficiency and reliability.

[0031] The length of the protruding passivation layer 3 is 150~230mm. This size range covers the single-side length range of current mainstream large-size silicon wafers 1 (such as M6, M10, G12, etc.) (typical values ​​are 166mm, 182mm, 210mm), allowing the protruding passivation layer 3 to extend continuously along a whole edge of the battery back surface or in the direction of the finger electrode, forming a through-type low-resistance contact channel; thereby ensuring uniform and low-loss hole collection throughout the entire effective area of ​​the battery, avoiding uneven current distribution and a decrease in fill factor due to interruption of the contact path or local high resistance, thus supporting high-efficiency output.

[0032] Meanwhile, this length range reserves a process tolerance window of approximately ±2mm, which can effectively accommodate micron to millimeter-level positional offsets caused by factors such as equipment alignment errors, thermal expansion / contraction of silicon wafer 1, and thin film stress deformation during semiconductor and photovoltaic manufacturing processes; it avoids defects such as contact area breakage, missing edge coverage, or metal ramp failure during high-temperature processes or mechanical transmission due to excessive contact between the pattern length and the edge of silicon wafer 1 (e.g., designed to be strictly equal to 182mm); thereby improving the process window width and production yield of key processes such as photolithography, deposition, etching, and metallization.

[0033] It should be noted that the width of the protruding part is the D direction shown in the figure, and the length is the direction perpendicular to the D direction and the thickness direction.

[0034] Specifically, the protruding passivation layer 3 is composed of one or more of silicon oxide, P-type doped polycrystalline silicon, and N-type doped polycrystalline silicon. These materials are standard functional layers in the passivation contact structures of current high-efficiency crystalline silicon solar cells (such as TOPCon, POLO, IBC, etc.), and their deposition, doping, annealing, and patterning processes are highly mature and deeply compatible with mainstream photovoltaic manufacturing processes. Therefore, when preparing the protruding passivation layer 3, there is no need to introduce new materials or develop independent process modules. Existing equipment and process parameters can be directly reused, significantly improving process compatibility and integration efficiency with the overall battery manufacturing process, and reducing the difficulty and cost of mass production implementation. Meanwhile, the selected silicon oxide and doped polycrystalline silicon material system exhibits excellent interfacial chemical stability and thermal expansion matching with the subsequently deposited metal electrodes (such as silver, aluminum, or silver-aluminum composite electrodes): the ultrathin silicon oxide layer can effectively block the diffusion of metal atoms into the silicon substrate and suppress the formation of metal-silicon alloy spikes or interfacial reaction layers under high temperature or long-term working conditions; doped polycrystalline silicon (especially highly doped p-type silicon) + -polySi) provides a stable semiconductor-metal interface with a thermal expansion coefficient between that of silicon wafer 1 and metal, which can alleviate interface stress concentration caused by temperature cycling. In addition, when the protruding passivation layer 3 is embedded in the dielectric layer groove and forms a three-dimensional encapsulated contact with the metal electrode, the stability advantage of the above materials is further amplified, effectively suppressing contact degradation mechanisms (such as electromigration, corrosion or interface oxidation) under damp heat, light or bias stress.

[0035] Optionally, the protruding passivation layer 3 is composed of silicon oxide and p-type polycrystalline silicon in a mass ratio of 1:4 to 3:7. That is, the mass percentage of silicon oxide is controlled between 20% and 30%, which is the core range for balancing passivation performance and conductivity. When the mass percentage of silicon oxide is less than 20% (i.e., the mass ratio is worse than 1:4): the silicon oxide phase is insufficient to form a continuous, dense silicon-rich oxide (SiO2) on the surface of silicon wafer 1. x The passivation network results in a high density of dangling bonds at the silicon / dielectric interface, and the interface states (Dit) fail to saturate effectively. Carriers undergo significant nonradiative recombination in the contact region, limiting the improvement of open-circuit voltage (Voc). Although the P-type polycrystalline silicon network has good connectivity and strong conductivity at this time, the overall cell efficiency is limited due to insufficient passivation.

[0036] When the mass percentage of silicon oxide is between 20% and 30% (i.e., a mass ratio of 1:4 to 3:7, with a ratio closer to 1:3 being preferred): a high-quality tunneling oxide layer can be formed, effectively passivating interface defects, significantly reducing recombination rate, and supporting high Voc; at the same time, the p-type polycrystalline silicon phase (accounting for 70%–80%) forms a continuous, highly doped hole transport channel, ensuring low contact resistance and efficient carrier collection, and improving the fill factor (FF) and short-circuit current density (Jsc); the two form a "passivation-conductivity" functional coupling structure at the nanoscale, achieving highly selective contact in the same local area.

[0037] When the mass ratio of silicon oxide exceeds 30% (i.e., the mass ratio is worse than 3:7): although the interface passivation capability is further enhanced, the excessive silicon oxide will break the conductive network of P-type polycrystalline silicon and increase the carrier tunneling barrier; leading to a decrease in the overall conductivity of the material, and a significant increase in contact resistance (Rc) and cell series resistance (Rs); which in turn causes a significant decrease in fill factor (FF) and short-circuit current (Jsc), offsetting or even exceeding the gain of Voc; ultimately, the cell efficiency decreases instead of increasing, showing an unbalanced state of "excessive passivation and insufficient conductivity".

[0038] In addition, the protruding passivation layer 3 can also be composed of silicon oxide, P-type polycrystalline silicon and N-type polycrystalline silicon in a mass ratio of 1:0.5:0.2 to 1:2:1.

[0039] The rationale for limiting this range is that by introducing an appropriate amount of N-type polysilicon phase, localized N-type doped regions can be formed in the hole transport network dominated by P-type polysilicon, thereby constructing a weak built-in electric field in the PN junction at the nanoscale. This built-in electric field helps to further suppress the reverse injection of electrons from the silicon substrate to the P-type emitter interface, while not hindering the forward tunneling and transport of holes. This adds an additional carrier selective filtering effect beyond the traditional passivation contact mechanism, synergistically improving the open-circuit voltage (Voc) and fill factor (FF).

[0040] When the mass ratio of silicon oxide, P-type polysilicon, and N-type polysilicon is lower than the minimum value of the range (1:0.5:0.5~1:2:1) (i.e., the mass percentage of silicon oxide is lower than approximately 12.5%, or the proportion of P-type polysilicon is too low and the proportion of N-type polysilicon is too high): If the silicon oxide content is too low, the ultrathin tunneling oxide layer cannot form a continuous and dense passivation network at the silicon / dielectric interface, resulting in a significant increase in the interface state density (Dit), intensified nonradiative recombination of charge carriers, and a significant decrease in the open-circuit voltage (Voc). If the proportion of N-type polysilicon is too high (relative to P-type polysilicon), a continuous N-type conductive channel will form inside the protruding passivation layer 3, and even a bicontinuous phase structure with interpenetrating P-type and N-type regions will appear. In this case, holes will encounter a large number of PN junction barriers during transport, causing a sharp increase in the effective contact resistance (Rc) and battery series resistance (Rs), severe degradation of the fill factor (FF), and even causing the P-type emitter to lose its selective hole collection function, resulting in a catastrophic decline in battery efficiency.

[0041] When the mass ratio of silicon oxide, P-type polysilicon, and N-type polysilicon exceeds the maximum value of the range (i.e., the mass percentage of silicon oxide exceeds approximately 25%, or the proportion of P-type polysilicon is too high and the proportion of N-type polysilicon is too low): If the silicon oxide content is too high, the excessive silicon oxide phase will break the conductive network of doped polycrystalline silicon (including P-type and N-type), which will significantly thicken the carrier tunneling barrier, greatly reduce the overall conductivity of the material, significantly increase the contact resistance (Rc) and series resistance (Rs), and suppress the fill factor (FF) and short-circuit current density (Jsc). If the proportion of P-type polysilicon is too high and the proportion of N-type polysilicon is too low, the additional field-effect passivation and carrier selective filtering functions introduced by N-type doping will be weakened. The open-circuit voltage (Voc) of the battery will not reach the theoretical optimal value that the ternary system can provide. The passivation performance will approach the upper limit of the binary (silicon oxide + P-type polysilicon) system, and the synergistic gain effect of the ternary composite passivation layer will not be fully utilized.

[0042] Therefore, by limiting the mass ratio to the range of 1:0.5:0.2 to 1:2:1, an optimal balance can be achieved between the interface passivation function of silicon oxide, the hole transport function of P-type polycrystalline silicon, and the electron blocking / field effect passivation function of N-type polycrystalline silicon, thereby synergistically improving the photoelectric conversion efficiency of the back contact cell in three dimensions: open-circuit voltage, fill factor, and short-circuit current density.

[0043] The cross-sectional shape of the passivation layer 3 is not specifically limited; for example, it can be rectangular, trapezoidal, arc-shaped, or inverted triangular.

[0044] The resistivity of silicon wafer 1 can be 1~50 Ω·cm, and the thickness can be 80~200 μm. The dielectric layer is made of silicon oxide and has a thickness of 0.1~5 nm. The P-type passivation layer 2 is P-type doped polycrystalline silicon and has a thickness of 15~400 nm.

[0045] An insulating separation band 9 is formed on the backlight surface 10. The dielectric layer is divided into a first dielectric layer 5 and a second dielectric layer 6 by the insulating separation band 9. The P-type passivation layer 2 and the protruding passivation layer 3 are both located in the first dielectric layer 5. The back contact battery also includes an N-type passivation layer 7 disposed on the second dielectric layer 6 and an N-type electrode 8 electrically connected to the N-type passivation layer 7.

[0046] In this way, an insulating separation band 9 is introduced on the back surface 10 of silicon wafer 1, which physically separates the originally continuous dielectric layer into a first dielectric layer 5 (P-type region) and a second dielectric layer 6 (N-type region) that are electrically isolated from each other. This effectively blocks the lateral leakage path between the P-type contact region and the N-type contact region, and significantly suppresses the lateral recombination and shunt effect of charge carriers caused by doping cross or metal contamination on the back surface, thereby improving the parallel resistance (Rsh) and open circuit voltage (Voc) of the battery. Simultaneously, this partitioned structure achieves strict spatial separation and functional independence of the P-type emitter and N-type back field. The first dielectric layer 5 integrates a P-type passivation layer 2 and a protruding passivation layer 3 embedded in a groove (preferably composed of silicon oxide and P-type polysilicon in a mass ratio of 1:4 to 3:7), specifically for selective hole extraction and low-resistance transport. The second dielectric layer 6 is then provided with an N-type passivation layer 7 (such as n...). + -polySi / SiO x The structure and the corresponding N-type electrode 8 are specifically designed for selective electron collection; the two are electrically isolated by the middle insulating separation band 9, avoiding local short circuits or performance fluctuations caused by overlapping or misalignment of the P / N region edges in the traditional back contact structure. The N-type passivation layer 7 is N-type doped polycrystalline silicon with a thickness of 10~300nm; the insulating separation band 9 is a silicon oxide or silicon nitride insulating layer with a width of 10~200μm; the P-type electrode 4 and the N-type electrode 8 can be made of silver, copper or silver-copper alloy.

[0047] Understandably, the light-receiving surface 11 of silicon wafer 1 has a light-receiving passivation layer 12 and an anti-reflection layer 13 on the light-receiving passivation layer 12. The light-receiving passivation layer 12 can effectively passivate the dangling bonds and defect states on the front silicon surface, significantly reducing the surface recombination rate of minority carriers (holes in P-type silicon) on the incident light side, thereby improving carrier lifetime and open-circuit voltage (Voc). At the same time, its dielectric properties can also provide field-effect passivation, further suppressing interface recombination.

[0048] The antireflection layer 13, which covers the passivation layer, reduces the average reflectivity of sunlight in the 300–1200 nm band to <5% through optical interference effect, greatly improving the optical coupling efficiency; it also allows more photons to enter the silicon absorption layer, generating more electron-hole pairs and directly increasing the short-circuit current density (Jsc).

[0049] The light-receiving passivation layer 12 is made of aluminum oxide and has a thickness of 1~20nm; the antireflection layer 13 is a stacked structure of silicon nitride and silicon oxide and has a thickness of 50~150nm.

[0050] This application also discloses a method for preparing a back contact battery, which is used to prepare the aforementioned back contact battery. The preparation method includes the following steps S0 to S3: S0, a light-receiving passivation layer 12 and an anti-reflection layer 13 are sequentially deposited on the light-receiving surface 11 of silicon wafer 1; In detail, an N-type monocrystalline silicon wafer 1 is selected. First, its light-receiving surface 11 is texturized to form a pyramid structure, enhancing the absorption of sunlight. Then, an aluminum oxide passivation layer 12 is deposited on the light-receiving surface 11 using an ALD process to effectively reduce carrier recombination. Afterwards, a silicon nitride antireflection layer 13 is deposited using a PECVD process, with a refractive index controlled between 2.0 and 2.2, to reduce the reflectivity of sunlight, thereby improving the light-receiving efficiency of the back-contact cell.

[0051] S1, deposit a dielectric layer on the back surface 10 of silicon wafer 1; In detail, the backlight surface 10 can be polished first to ensure surface flatness. Then, a uniform and dense dielectric layer (such as SiO2) is formed on the back surface of the silicon wafer 1 using processes such as LPCVD, which serves as the basis for the subsequent passivation contact structure. This dielectric layer not only provides initial surface passivation, but can also serve as an etching mask or ion implantation barrier layer for subsequent patterning processes. S2, depositing a protruding passivation layer 3 and a P-type passivation layer 2 on the dielectric layer; In detail, a micron-scale groove is first formed on the dielectric layer using laser and etching processes, and then a LPCVD process is used to deposit a thinner protruding passivation layer 3 inside the groove and a thicker P-type passivation layer 2 outside the groove.

[0052] Preferably, the protruding passivation layer 3 is composed of silicon oxide and P-type polycrystalline silicon in a mass ratio of 1:4 to 3:7 to achieve the best balance between passivation and conductivity; the protruding passivation layer 3 and the P-type passivation layer 2 are physically continuous and electrically connected, together forming a P-type carrier selective contact region.

[0053] S3, Print a P-type electrode 4 on the P-type passivation layer 2.

[0054] In detail, metallization processes such as screen printing, electroplating, or vapor deposition are used to form a P-type metal electrode on the P-type passivation layer 2. Since the protruding passivation layer 3 is located in the groove and has a low tunneling barrier, the metal electrode can form a low-resistance ohmic contact with it through local sintering or low-temperature burn-through mechanism. At the same time, the outer area of ​​the P-type passivation layer 2 remains completely passivated to avoid the increase in recombination caused by direct contact between the metal and the silicon body.

[0055] Optionally, after step S2, which involves depositing the protruding passivation layer 3 and the P-type passivation layer 2 on the dielectric layer, the fabrication method further includes the following steps S4 to S6: S4, an insulating separation band 9 is formed on the backlight surface 10, wherein the insulating separation band 9 separates the dielectric layer into a first dielectric layer 5 and a second dielectric layer 6. Thus, in the step of depositing the protruding passivation layer 3 and the P-type passivation layer 2 on the dielectric layer, the protruding passivation layer 3 and the P-type passivation layer 2 are deposited on the first dielectric layer 5; In detail, an insulating separation band 9 is formed on the backlight surface 10 through laser technology and wet process to insulate and isolate the P-type emitter region and the N-type emitter region to avoid leakage.

[0056] S5, deposit an N-type passivation layer 7 on the second dielectric layer 6; In detail, an N-type passivation layer 7 is formed in the area outside of the protruding passivation layer 3 and the P-type passivation layer 2 using LPCVD process. S6, Print an N-type electrode 8 on the N-type passivation layer 7.

[0057] In detail, metallization processes such as screen printing, electroplating, or vapor deposition are used to form an N-type metal electrode in the N-type passivation layer 7.

[0058] The embodiments of this application will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of this application. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all commercially available conventional products.

[0059] In these embodiments, unless otherwise specified, the parts and amounts are all by weight.

[0060] Example 1 refer to Figure 1 and Figure 2 This embodiment provides a back contact battery, the specific structure of which is as follows: 1. N-type silicon wafer 1: An N-type single crystal silicon wafer 1 with a resistivity of 15Ω·cm and a thickness of 135μm is selected. Its light-receiving surface 11 is texturized to form a pyramid structure to enhance the absorption of sunlight; the back-lighting surface 10 is polished to ensure surface flatness.

[0061] 2. Structure of the light-receiving surface 11: A light-receiving passivation layer 12 and an anti-reflection layer 13 are sequentially stacked on the light-receiving surface 11 of the N-type silicon wafer 1. The light-receiving passivation layer 12 is made of Al2O3 material and prepared using atomic layer deposition (ALD) technology, with a thickness of 5 nm, effectively reducing carrier recombination on the light-receiving surface 11. The anti-reflection layer 13 is made of SiNx material and prepared using plasma-enhanced chemical vapor deposition (PECVD) technology, with a thickness of 80 nm and a refractive index controlled between 2.0 and 2.2 to reduce the reflectivity of sunlight and improve the light-receiving efficiency of the battery.

[0062] 3. Backlight surface 10 structure: (1) Dielectric layer: A SiO2 dielectric layer with a thickness of 1 nm is prepared on the back surface 10 of the N-type silicon wafer 1 using LPCVD process, which serves as insulation and preliminary passivation.

[0063] (2) Protruding passivation layer 3 and P-type passivation layer 2: Grooves are formed on the dielectric layer using laser and etching processes. Then, P-type polysilicon material is deposited in the grooves and non-grooves using LPCVD process to form protruding passivation layer 3 and P-type doped polysilicon. The length of protruding passivation layer 3 is 182 mm and the width is 2 μm. It is tightly bonded to the dielectric layer. The thickness of P-type doped polysilicon is 300 nm. Together with protruding passivation layer 3 and dielectric layer, it forms a P-type emitter, further improving the passivation effect.

[0064] (3) N-type passivation layer 7: N-type passivation layer 7 with a thickness of 200 nm is prepared in the area outside the protruding passivation layer 3 and the P-type passivation layer 2 using LPCVD process.

[0065] (4) Insulation separation strip 9: Prepared in a specific area of ​​the backlight surface 10 by laser process and wet process, with a width of 50 micrometers, to insulate and isolate the P-type emitter area from the N-type emitter area to avoid leakage.

[0066] (5) Electrode: silver paste material is used to prepare the backlight surface 10 by screen printing process, including a positive electrode that is electrically connected to the P-type emitter and a negative electrode that is electrically connected to the N-type silicon wafer 1.

[0067] Example 2 Unlike Example 1, in this example, the passivation layer 3 is composed of silicon oxide and P-type polysilicon in a mass ratio of 1:3.

[0068] Example 3 Unlike Example 2, in this example, the length of the protruding passivation layer 3 is 180 mm, the width is 1.8 μm, and the mass ratio of silicon oxide to P-type polycrystalline silicon is 1:4. Example 4 Unlike Example 2, in this example, the length of the protruding passivation layer 3 is 185 mm, the width is 2.2 μm, and the mass ratio of silicon oxide to P-type polycrystalline silicon is 3:7. Example 5 Unlike Example 1, in this example, the passivation layer 3 is composed of silicon oxide and P-type polysilicon in a mass ratio of 1:2:1 (i.e., silicon oxide accounts for 25%, P-type polysilicon accounts for 50%, and N-type polysilicon accounts for 25%).

[0069] The length of the passivation layer 3 is 200 mm and the width is 4 μm.

[0070] Example 6 Unlike Example 5, in this example, the protruding passivation layer 3 is composed of silicon oxide, P-type polysilicon and N-type polysilicon in a mass ratio of 1:0.5:0.2 (i.e., silicon oxide accounts for about 58.8%, P-type polysilicon accounts for about 29.4%, and N-type polysilicon accounts for about 11.8%).

[0071] The length of the passivation layer 3 is 150 mm and the width is 1 μm.

[0072] Example 7 Unlike Example 5, in this example, the length of the protruding passivation layer 3 is 230 mm and the width is 6 μm.

[0073] Example 8 Unlike Example 5, in this example, the passivation layer 3 is composed of silicon oxide and P-type polycrystalline silicon in a mass ratio of 1:1:1.

[0074] The performance of the back contact batteries in Examples 1-8 was tested, and the results are shown in Table 1 below: Table 1

[0075] It can be seen from the above table: 1. Performance comparison of binary systems (silicon oxide + P-type polycrystalline silicon): Compared to Example 1 (pure P-type polycrystalline silicon), Example 2 (mass ratio 1:3) showed an increase in open-circuit voltage (Voc) from 745mV to 748mV and a fill factor (FF) from 85.0% to 85.2%, indicating that the introduction of an appropriate amount of silicon oxide enhanced the interface passivation effect. At the same time, the P-type polycrystalline silicon could still maintain a good conductive network, achieving a simultaneous slight increase in Voc and FF.

[0076] Example 3 (mass ratio 1:4, width 1.8μm) achieved a fill factor of 85.3%, the highest among binary systems, but the Voc dropped to 730mV. This is because the low proportion of silicon oxide (20%) resulted in slightly weaker interface passivation. However, the narrow width design shortened the lateral transport path of charge carriers, effectively reducing the contact resistance and highlighting the advantage of prioritizing conductivity.

[0077] In Example 4 (mass ratio 3:7, width 2.2μm), Voc increased to 736mV, but FF decreased to 84.5%, indicating that although the high proportion of silicon oxide (30%) enhanced passivation, it disrupted the polycrystalline silicon conductive network, causing the contact resistance to increase.

[0078] 2. Significant advantages of the ternary system (silicon oxide + P-type polysilicon + N-type polysilicon): Example 5 (mass ratio 1:2:1, width 4μm, length 200mm) achieved the highest Voc (752mV) and the highest FF (86.1%), demonstrating that the introduction of an appropriate amount of N-type polysilicon creates a local built-in electric field in the P-type conductive network, effectively suppressing electron reverse injection without significantly disrupting hole transport channels, thus achieving optimal synergy between passivation and conductivity.

[0079] Example 6 (mass ratio 1:0.5:0.2, width 1μm, length 150mm) achieved the highest Voc (755mV), but the FF dropped sharply to 83.2%. This was because the high proportion of silicon oxide (about 58.8%) severely increased the tunneling barrier and series resistance. Although the passivation was excellent, the conductivity was severely compromised.

[0080] Example 7 (mass ratio 1:2:1, width 6μm, length 230mm) has a Voc of 750mV and an FF of 84.8%, which is lower than that of Example 5. This indicates that the excessively wide protruding passivation layer 3 will weaken the spatial confinement effect of the groove structure and increase the probability of lateral recombination of carriers; while the excessively long size may introduce process edge defects and slightly degrade the fill factor.

[0081] Example 8 (mass ratio 1:1:1, width 4 μm, length 200 mm) exhibited a higher Voc (754 mV), but the FF (84.9%) was significantly lower than that of Example 5. This indicates that when the proportion of N-type polysilicon increased from 25% to 33.3% and the proportion of P-type polysilicon decreased from 50% to 33.3%, although the electron blocking effect was further enhanced (Voc slightly increased), the P-type conductive network was excessively diluted, and the equal amount of P / N phase formed more PN junction interfaces, hindering hole transport. Therefore, 1:1:1 is not the optimal ratio, and P-type polysilicon needs to maintain a relative advantage (such as 50% in Example 5) to achieve a high FF.

[0082] 3. Verification of optimality and reasonableness of the scope: Example 5 (ternary system, ratio 1:2:1, width 4μm, length 200mm) performed best among all examples, demonstrating that the median region of the ternary mass ratio range (1:0.5:0.2~1:2:1) has the optimal passivation-conductivity balance.

[0083] When the ratio is lower than the minimum value in the range (as in Example 6), although the Voc is high, the FF loss is too large, and the battery efficiency decreases instead of increasing; when the ratio is higher than the maximum value in the range (the material ratio cannot be higher, but the geometric dimensions exceed those in Example 7), both Voc and FF decrease.

[0084] Experiments have verified that a geometric range of 1~6μm width and 150~230mm length has good process window and electrical performance boundary. Exceeding this range (e.g., width <1μm easily leads to contact breakage, width >6μm increases recombination; length <150mm reduces effective collection area, length >230mm exceeds the silicon wafer size and easily generates edge defects) will significantly affect device consistency and yield.

[0085] In summary, this application achieves a synergistic improvement in open-circuit voltage, fill factor, and short-circuit current density in back-contact batteries by optimizing the material composition (especially by introducing a ternary system) and geometry of the prominent passivation layer 3.

[0086] The above description is merely a specific embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A back-contact battery, characterized in that, include: Silicon wafer (1); A dielectric layer is disposed on the back surface (10) of the silicon wafer (1); A P-type passivation layer (2) and a protruding passivation layer (3) are disposed on the side of the dielectric layer opposite to the silicon wafer (1); wherein the thickness of the protruding passivation layer (3) is less than the thickness of the P-type passivation layer (2), the protruding passivation layer (3) is formed of passivation material, and the protruding passivation layer (3) and the P-type passivation layer (2) are in electrical contact; And a P-type electrode (4) electrically connected to the P-type passivation layer (2).

2. The back contact battery according to claim 1, characterized in that, The width of the protruding passivation layer (3) is 1~6μm.

3. The back contact battery according to claim 1, characterized in that, The length of the protruding passivation layer (3) is 150~230mm.

4. The back contact battery according to claim 1, characterized in that, The protruding passivation layer (3) is composed of one or more of silicon oxide, P-type doped polysilicon and N-type doped polysilicon.

5. The back contact battery according to claim 4, characterized in that, The protruding passivation layer (3) is composed of silicon oxide and P-type polycrystalline silicon in a mass ratio of 1:4 to 3:7; or, The protruding passivation layer (3) is composed of silicon oxide, P-type polycrystalline silicon and N-type polycrystalline silicon in a mass ratio of 1:0.5:0.2 to 1:2:

1.

6. The back contact battery according to claim 1, characterized in that, The dielectric layer has a groove formed on the side facing away from the silicon wafer (1), and the protruding passivation layer (3) is located in the groove; The P-type passivation layer (2) is located outside the groove.

7. The back contact battery according to claim 1, characterized in that, An insulating separation band (9) is formed on the backlight surface (10). The dielectric layer is divided into a first dielectric layer (5) and a second dielectric layer (6) by the insulating separation band (9). The P-type passivation layer (2) and the protruding passivation layer (3) are both located on the first dielectric layer (5). The back contact battery also includes an N-type passivation layer (7) disposed on the second dielectric layer (6) and an N-type electrode (8) electrically connected to the N-type passivation layer (7).

8. A method for preparing a back contact battery, used to prepare the back contact battery of claim 1, characterized in that, The preparation method includes the following steps: A dielectric layer is deposited on the back surface (10) of the silicon wafer (1); A protruding passivation layer (3) and a P-type passivation layer (2) are deposited on the dielectric layer; A P-type electrode (4) is printed on the P-type passivation layer (2).

9. The method for preparing a back contact battery according to claim 8, characterized in that, In the step of depositing the protruding passivation layer (3) and the P-type passivation layer (2) on the dielectric layer, a groove is first formed on the dielectric layer by laser and etching processes, and then deposition is performed to form the protruding passivation layer (3) in the groove and the P-type passivation layer (2) outside the groove.

10. The method for preparing a back contact battery according to claim 8, characterized in that, After the step of depositing the protruding passivation layer (3) and the P-type passivation layer (2) on the dielectric layer, the fabrication method further includes: An insulating separation band (9) is formed on the backlight surface (10), wherein the insulating separation band (9) separates the dielectric layer into a first dielectric layer (5) and a second dielectric layer (6). After the step of depositing a dielectric layer on the back surface (10) of the silicon wafer (1), the fabrication method further includes: An N-type passivation layer (7) is deposited on the second dielectric layer (6); N-type electrodes (8) are printed on the N-type passivation layer (7); In the step of depositing the protruding passivation layer (3) and the P-type passivation layer (2) on the dielectric layer, the protruding passivation layer (3) and the P-type passivation layer (2) are deposited on the first dielectric layer (5).

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