A board level package structure and fabrication process thereof

Abstract

This invention provides a board-level packaging structure and its manufacturing process, which solves the detection blind zone problem of traditional QFN, greatly improves production quality and efficiency, significantly enhances the mechanical strength and vibration and bending resistance of solder joints, and provides additional heat dissipation paths. It includes: several chipsets, each chipet including at least one chip; a molding compound; a first passivation layer; a redistribution layer; and a second passivation layer; each chipet is spaced apart and embedded on the corresponding upper surface of the molding compound, and the upper surface of the chip is provided with the first passivation layer, the redistribution layer, and the second passivation layer. The second passivation layer, the redistribution layer, the first passivation layer, and the upper layer of the molding compound have recessed grooves corresponding to the cut-out positions of each product, the grooves extending in the depth direction to the upper layer of the molding compound. The second passivation layer has an opening at the corresponding connection area position of the redistribution layer.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor device packaging, specifically to a board-level packaging structure. The invention also provides a manufacturing process for the board-level packaging structure. Background Technology

[0002] As mobile consumer electronics products such as mobile phones, computers, and digital gadgets demand increasingly higher levels of functional integration, large storage space, high reliability, and miniaturized packaging, high-density microelectronic assembly technology has become mainstream in next-generation electronic products. To keep pace with this rapid development, chips are evolving towards higher density, faster speeds, smaller sizes, and lower costs. Simultaneously, with the increasing richness of electronic product functions, the number of I / O ports in fan-in packaging structures can no longer meet product needs. Fan-out (FO) packaging structures, as a type of wafer-level packaging, are a leading advanced packaging technology for high-numbered input / output (I / O) ports and high integration flexibility (enabling vertical and horizontal multi-chip integration). They are widely used in multi-chip, ultra-thin packaging, and 3D system-in-package (SiP) applications. The emergence of wafer-level fan-out package (WLFOP) has significantly increased the number of I / O ports in the package, aligning with the trend towards multi-functional chips. However, due to the increasing market demand, in order to break through the existing methods, it is necessary to combine the PCB board-level production concept with the semiconductor wafer-level packaging method to break the original wafer size limitations. It is necessary to propose a packaging structure that can accommodate more I / Os, reduce chip size and thickness, integrate more heterogeneous chips to meet the miniaturization requirements of packaging, effectively reduce production costs, improve production efficiency, and ultimately be applied to consumer, high-speed computing and professional electronic products.

[0003] To further reduce costs, manufacturers have begun using larger panels as carriers, introducing panel-level fan-out packages (PLFOPs). The emergence of PLFOP technology effectively enables larger-area overall packaging, further increasing packaging efficiency, reducing packaging costs, and offering broader development prospects. Currently, a 300x300mm² silicon wafer can produce approximately 600 ICs. Using PLFOP technology, up to 2600 ICs can be packaged on a 500x500mm² panel. This means the yield of fan-out packaging on a 500x500mm² panel is more than four times that of fan-out packaging on a 300x300mm² wafer, thus effectively reducing costs and increasing product competitiveness. PLFOP technology offers advantages such as lower cost, flexible design, good electrothermal performance, diverse business models, and a wide range of applications.

[0004] In the field of integrated circuit packaging, QFN (Quad Flat No-Leader) is widely used in consumer electronics, communication equipment, and other products due to its thinness, lightness, and excellent electrical performance. However, the traditional QFN packaging process has significant technical shortcomings: after the finished product is cut into individual chips, the cut sides of the leads are bare copper without plating protection, making them prone to oxidation. This directly results in the inability to form a "wettable flank" on the leads. In the subsequent SMT (Surface Mount Technology) soldering process, it is impossible to form additional solder connections through the sides. This not only reduces the mechanical strength and electrical connection reliability of the soldering but also affects the accurate judgment of soldering quality by AOI (Automated Optical Inspection) due to the lack of solder coverage on the sides.

[0005] Therefore, how to combine QFN with wettable flank technology in board-level packaging is a technical problem that urgently needs to be solved in the packaging field. Summary of the Invention

[0006] To address the aforementioned issues, this invention provides a board-level packaging structure that solves the detection blind zone problem of traditional QFN, greatly improves production quality and efficiency, significantly enhances the mechanical strength and vibration and bending resistance of solder joints, and provides additional heat dissipation paths.

[0007] A board-level packaging structure, characterized in that it comprises: Several chipsets, each chipset containing at least one chip; Plastic encapsulation; First passivation layer; Rewire layer; And a second passivation layer; Each chip group is spaced apart and embedded on the corresponding upper surface of the molded package. The upper surface of the chip is provided with a first passivation layer, a redistribution layer, and a second passivation layer. The second passivation layer, the redistribution layer, the first passivation layer, and the upper layer of the molded package are provided with recessed grooves corresponding to the dicing positions of each product. The grooves extend to the upper layer of the molded package in the depth direction. The second passivation layer is provided with an opening at the corresponding connection area of ​​the redistribution layer. The surface of the grooves and the opening positions and surrounding areas of the second passivation layer are provided with copper-tin exposed structures. The copper-tin exposed structures extend the solder joints of the chip to the surrounding sidewalls corresponding to the dicing positions.

[0008] Its further features are: The copper in the copper-tin exposed structure is an inner layer structure, and the tin is an outer layer structure; The copper-tin exposed structure corresponding to the position of the second passivation layer protrudes from the second passivation layer. The inner layer of the copper-tin exposed structure is used to link the corresponding link area of ​​the redistribution layer. The inner end of the redistribution layer links to the corresponding chip, which causes the invisible bottom solder joint of the chip to extend to the side of the product.

[0009] A manufacturing process for a board-level packaging structure is characterized by: preparing wettable side wings on the surface of the board-level molding compound by pre-cutting grooves and electroplating, thereby realizing wettable side wings for board-level QFN packaging.

[0010] Its further features are: It includes the following steps: S1, apply an adhesive film to the first carrier sheet, and mount the chips of each chipset onto the adhesive film; S2, The chips of the chipset are encapsulated on the first carrier chip for chip mounting to form a board-level encapsulation; S3, remove the first carrier sheet and adhesive film, and flip the molding compound 180 degrees so that the chip is located on the upper layer and the chip's solder joints are exposed on the upper layer; S4, the bottom layer of the molding compound is temporarily bonded to the second carrier plate; S5, a first passivation layer, a redistribution layer, and a second passivation layer are formed above the surface of the chip and the molding compound, wherein the redistribution layer connects to the corresponding chip solder joints; S6, a groove is formed at the position of the preset cutting channel by removal, and the depth of the groove extends to the upper layer of the encapsulation body; S7, by removing the openings placed on the second passivation layer, the opening positions correspond to the corresponding link areas of the redistribution layer; S8, through electroplating, forms an exposed copper-tin structure on the surface of the groove, as well as at the window opening and around it; S9, Remove the second support plate at the bottom of the molding compound; S10 cuts the product into individual pieces along the cutting path.

[0011] Its further characteristic is: In step S6, a groove is formed at the cutting path location by removal methods such as cutting, laser, or etching. The groove depth is 50um-200um and the groove width is 100-300um.

[0012] This invention enables automated optical inspection by extending the previously invisible bottom solder joints of the chip to the side of the device, completely solving the blind spot problem of traditional QFN and greatly improving production quality and efficiency. Furthermore, the solder filling of the dicing path corresponding to the side of the product forms a three-dimensional connection composed of chip solder joints, redistribution layers, and exposed copper-tin structures, significantly enhancing the mechanical strength and vibration and bending resistance of the solder joints, and providing additional heat dissipation paths around the perimeter. Ultimately, it achieves comprehensive optimization in terms of manufacturability, connection reliability, and thermal performance, becoming a key component of high-reliability electronic products. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of the structure of a specific embodiment of the present invention and a schematic diagram of step S9 of the manufacturing process; Figure 2 This is a schematic diagram of step S1 of the manufacturing process of the present invention; Figure 3 This is a schematic diagram of step S2 in the manufacturing process of the present invention: Figure 4 This is a schematic diagram of step S3 in the manufacturing process of the present invention; Figure 5 This is a schematic diagram of step S4 in the manufacturing process of the present invention; Figure 6 This is a schematic diagram of step S5 in the manufacturing process of the present invention; Figure 7 This is a schematic diagram of step S6 in the manufacturing process of the present invention; Figure 8 This is a schematic diagram of step S7 in the manufacturing process of the present invention; Figure 9 This is a schematic diagram of step S8 in the manufacturing process of the present invention; Figure 10 This is a schematic diagram of step S10 of the manufacturing process of the present invention; The names corresponding to the serial numbers in the diagram are as follows: 10, encapsulation body, 20, first passivation layer, 30, second passivation layer, 40, groove, 50, window, 60, copper-tin exposed structure, 70, first carrier sheet, 80, adhesive film, 81, second carrier plate, 90; First chip 1, second chip 2. Detailed Implementation

[0014] A board-level packaging structure, see Figure 1 It includes several chipsets, a molding compound 10, a first passivation layer 20, a redistribution layer 30, and a second passivation layer 40; Each chipset contains at least one chip; Each chip group is spaced apart and embedded on the corresponding upper surface of the molded package 10. The upper surface of the chip is provided with a first passivation layer 20, a redistribution layer 30, and a second passivation layer 40. The second passivation layer 40, the redistribution layer 30, the first passivation layer 20, and the upper layer of the molded package 10 are provided with recessed grooves 50 corresponding to the dicing positions of each product. The grooves 50 extend to the upper layer of the molded package 10 in the depth direction. The second passivation layer 40 is provided with an opening 60 corresponding to the connection area of ​​the redistribution layer 30. The surface of the grooves 50, the opening 60, and the surrounding area are provided with copper-tin exposed structures 70. The copper-tin exposed structures 70 extend the solder joints of the chip to the sidewalls corresponding to the dicing positions.

[0015] In a specific embodiment, each chipset includes a first chip 1 and a second chip 2; In the copper-tin exposed structure 70, the copper is the inner layer and the tin is the outer layer, ensuring that the copper in the inner layer is reliably protected after cutting.

[0016] In a specific embodiment, the copper-tin exposed structure 70 corresponding to the position of the second passivation layer 40 protrudes from the second passivation layer 40. The inner layer of the copper-tin exposed structure 70 is used to connect the corresponding connection area of ​​the redistribution layer 30. The inner end of the redistribution layer 30 connects to the first chip 1 and the second chip 2, which makes the invisible bottom solder joints of the chip extend to the side of the product.

[0017] A fabrication process for a board-level packaging structure, see Figures 1-10 It prepares wettable wing on the surface of the board-level molding compound by pre-cutting grooves and electroplating, thus realizing the wettable wing of the board-level QFN package.

[0018] In a specific embodiment, each product includes a chipset consisting of a first chip 1 and a second chip 2.

[0019] It includes the following steps: S1, an adhesive film 81 is attached to the first carrier sheet 80, and the first chip 1 and the second chip 2 of each chip group are attached to the adhesive film 81. S2, The chips of the chipset are encapsulated on the first carrier chip 81 to form a board-level encapsulation body 10; S3, remove the first carrier sheet 80 and the adhesive film 81, and flip the molding compound 10 180 degrees so that the chip is located on the upper layer and the chip's solder joints are exposed on the upper layer. S4, the bottom layer of the molding compound 10 is temporarily bonded to the second carrier plate 90; S5, a first passivation layer 20, a redistribution layer 30, and a second passivation layer 40 are formed above the surface of the chip and the molding compound 10, wherein the redistribution layer 30 connects the corresponding chip solder joints. S6, a groove 50 is formed at the position of a preset cutting channel by means of cutting, laser or etching. The depth of the groove 50 extends to the upper layer of the molding compound. The depth of the groove 50 is 50um-200um and the width of the groove 50 is 100-300um. S7, an opening 60 is formed on the second passivation layer 40 by laser and etching. The position of the opening 60 corresponds to the corresponding link area of ​​the redistribution layer 30. S8, a copper-tin exposed structure 70 is formed on the surface of the groove 50, the window 60 and the surrounding area by electroplating; S9, remove the second support plate 90 at the bottom of the plastic seal 10; S10 cuts the product into individual pieces along the cutting path.

[0020] Its innovation lies in: 1. Wettable side wings are prepared by pre-cutting grooves and electroplating. 2. A support plate is added during the preparation process to improve warping during sample preparation; 3. Wettable winglets can be fabricated through board-level packaging, reducing production costs and improving production efficiency.

[0021] This invention enables automated optical inspection by extending the previously invisible bottom solder joints of the chip to the side of the device, completely solving the blind spot problem of traditional QFN and greatly improving production quality and efficiency. Furthermore, the solder filling of the dicing path corresponding to the side of the product forms a three-dimensional connection composed of chip solder joints, redistribution layers, and exposed copper-tin structures, significantly enhancing the mechanical strength and vibration and bending resistance of the solder joints, and providing additional heat dissipation paths around the perimeter. Ultimately, it achieves comprehensive optimization in terms of manufacturability, connection reliability, and thermal performance, becoming a key component of high-reliability electronic products.

[0022] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0023] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A board-level packaging structure, characterized in that, It includes: Several chipsets, each chipset containing at least one chip; Plastic encapsulation; First passivation layer; Rewire layer; And a second passivation layer; Each chip group is spaced apart and embedded on the corresponding upper surface of the molded package. The upper surface of the chip is provided with a first passivation layer, a redistribution layer, and a second passivation layer. The second passivation layer, the redistribution layer, the first passivation layer, and the upper layer of the molded package are provided with recessed grooves corresponding to the dicing positions of each product. The grooves extend to the upper layer of the molded package in the depth direction. The second passivation layer is provided with an opening at the corresponding connection area of ​​the redistribution layer. The surface of the grooves and the opening positions and surrounding areas of the second passivation layer are provided with copper-tin exposed structures. The copper-tin exposed structures extend the solder joints of the chip to the surrounding sidewalls corresponding to the dicing positions.

2. The board-level packaging structure according to claim 1, characterized in that: In the copper-tin exposed structure, copper is the inner layer and tin is the outer layer.

3. The board-level packaging structure according to claim 1, characterized in that: The copper-tin exposed structure corresponding to the position of the second passivation layer protrudes from the second passivation layer. The inner layer of the copper-tin exposed structure is used to link the corresponding link area of ​​the redistribution layer. The inner end of the redistribution layer links to the corresponding chip, which causes the invisible bottom solder joint of the chip to extend to the side of the product.

4. A process for manufacturing a board-level packaging structure, used to manufacture a board-level packaging structure as described in any one of claims 1-3, characterized in that: Wettable wing is prepared on the surface of the board-level molding compound by pre-cutting grooves and electroplating, thus realizing the wettable wing of the board-level QFN package.

5. The manufacturing process of a board-level packaging structure according to claim 4, characterized in that, It includes the following steps: S1, apply an adhesive film to the first carrier sheet, and mount the chips of each chipset onto the adhesive film; S2, The chips of the chipset are encapsulated on the first carrier chip for chip mounting to form a board-level encapsulation; S3, remove the first carrier sheet and adhesive film, and flip the molding compound 180 degrees so that the chip is located on the upper layer and the chip's solder joints are exposed on the upper layer; S4, the bottom layer of the molding compound is temporarily bonded to the second carrier plate; S5, a first passivation layer, a redistribution layer, and a second passivation layer are formed above the surface of the chip and the molding compound, wherein the redistribution layer connects to the corresponding chip solder joints; S6, a groove is formed at the position of the preset cutting channel by removal, and the depth of the groove extends to the upper layer of the encapsulation body; S7, by removing the openings placed on the second passivation layer, the opening positions correspond to the corresponding link areas of the redistribution layer; S8, through electroplating, forms an exposed copper-tin structure on the surface of the groove, as well as at the window opening and around it; S9, Remove the second support plate at the bottom of the molding compound; S10 cuts the product into individual pieces along the cutting path.

6. The manufacturing process of a board-level packaging structure according to claim 5, characterized in that: In step S6, a groove is formed at the cutting path location by removal methods such as cutting, laser, or etching. The groove depth is 50um-200um and the groove width is 100-300um.

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