An intelligent dynamic scheduling method and system for a chip test flow

Abstract

The application relates to the technical field of chip testing, and discloses an intelligent dynamic scheduling method and system for a chip testing process. The method comprises the following steps: acquiring wafer batch records of a chip testing production line, the number of parallel test heads of a machine table, and the current slot occupation state, and the wafer residual data and the number of idle slots of the current testing production line; performing queue matching, aggregation screening, time consumption alignment and sequence planning according to the wafer batch records, the number of parallel test heads of the machine table and the current slot occupation state, so as to obtain a test instruction set; and performing timing conflict detection according to the wafer residual data, the number of idle slots and the test instruction set, so as to obtain a scheduling signal sequence and output the scheduling signal sequence. The method can realize space-time dynamic cooperation of the whole chip testing process, completely eliminate the timing mismatch between material handling and testing actions, and significantly improve the production line testing efficiency and the equipment resource utilization rate.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to an intelligent dynamic scheduling method and system for chip testing processes. Background Technology

[0002] Currently, with the rapid development of semiconductor manufacturing technology and the increasing demand for mass production, chip testing production lines need to manage the testing of massive wafers and packaging batches. This has led to the generation and analysis of test data gradually evolving into a big data processing process in the industrial manufacturing field, which places extremely high demands on the automation of the testing process and the real-time dynamic decision-making.

[0003] In existing technologies, chip testing process scheduling typically relies on preset static rules or production plans based on fixed time gradients. The system matches the corresponding physical testing equipment according to the wafer batch information entering the production line to maintain the basic scheduling requirements under normal mass production conditions. However, analysis of the aforementioned existing technologies reveals a complex constraint relationship between the batch flow patterns within the chip testing production line and the parallel processing capabilities of test head resources. Especially when facing scenarios such as the dense arrival of diverse wafer batches or transient disturbances in equipment operation, the existing control logic lacks precise perception of the current slot occupancy status of the equipment and the test task time window. It cannot respond in real time to the physical coupling relationship between batch characteristics and equipment capacity, which can easily lead to unreasonable structural arrangement of batch testing units, resulting in a lack of synchronization between the triggering sequence of batch instructions and the front-end material handling.

[0004] Existing technologies suffer from a technical problem of unbalanced dynamic scheduling in chip testing processes. Summary of the Invention

[0005] This invention provides an intelligent dynamic scheduling method and system for chip testing processes to solve the technical problem of unbalanced dynamic scheduling in chip testing processes in the prior art.

[0006] Firstly, to address the aforementioned technical problems, this invention provides an intelligent dynamic scheduling method for chip testing processes, comprising:

[0007] Obtain the wafer batch record, the number of parallel test heads on the machine, and the current slot occupancy status of the chip testing production line; calculate the matching degree between the wafer batch record and the number of parallel test heads on the machine to obtain the batch matching sequence.

[0008] When it is determined that the current slot occupancy status is lower than the preset slot occupancy threshold, the batch matching sequence is aggregated and filtered to obtain a set of batches to be aggregated.

[0009] Extract the associated batch time set based on the batch set to be aggregated, and perform maximum time alignment calculation between the batch time set and the number of parallel test heads on the machine to obtain the test run cycle;

[0010] Based on the aforementioned test execution cycle, a test sequence plan is performed to obtain a set of test instructions;

[0011] Obtain the remaining wafer data and the number of free slots in the current test production line, perform timing conflict detection on the test instruction set, the remaining wafer data and the number of free slots, and obtain the scheduling signal sequence.

[0012] In a second aspect, the present invention provides an intelligent dynamic scheduling system for chip testing processes, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the methods described above.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] (1) This invention calculates the matching degree and screens the occupancy threshold of wafer batch records, the number of parallel test heads of the machine and the current slot occupancy status in multiple dimensions, accurately locks the set of high-potential batches to be aggregated, effectively breaks the rigidity of traditional static rules, realizes the dynamic and accurate adaptation of complex batch characteristics and machine underlying hardware carrying capacity, significantly improves the physical resource utilization rate of machine slots, and avoids the ineffective idleness and excessive load of production line equipment.

[0015] (2) This invention performs maximum time-alignment calculation on the time set of aggregated batches and performs rigorous sequence planning and instruction filling. It abandons the rough average time estimation strategy, accurately deduces the test running cycle that conforms to the physical parallel logic, overcomes the hardware bottleneck effect in the multi-batch mixed test environment, and ensures the absolute timeliness and high concurrency flow efficiency of batch test instruction generation and issuance.

[0016] (3) This invention performs in-depth boundary constraint comparison and timing conflict detection on the test instruction set, wafer remaining data and number of idle slots, and introduces an exponential smooth feedback closed-loop mechanism based on physical slot status. This invention successfully breaks down the spatiotemporal coordination barrier between the test process in the logical dimension and the loading and unloading actions of the robotic arm in the physical dimension. It fundamentally eliminates the production line congestion caused by mismatch between instructions and actions, and gives the system the ability to continuously adapt and optimize, ensuring the high efficiency and extreme stability of the mass production test process. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the intelligent dynamic scheduling method for chip testing provided in the first embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Reference Figure 1 The first embodiment of the present invention provides an intelligent dynamic scheduling method for chip testing processes, including the following steps:

[0020] S1. Obtain the wafer batch record, the number of parallel test heads on the machine and the current slot occupancy status of the chip testing production line. Calculate the matching degree between the wafer batch record and the number of parallel test heads on the machine to obtain the batch matching sequence.

[0021] S2, when it is determined that the current slot occupancy status is lower than the preset slot occupancy threshold, the batch matching sequence is aggregated and filtered to obtain a set of batches to be aggregated;

[0022] S3, extract the associated batch time set based on the batch set to be aggregated, perform maximum time alignment calculation between the batch time set and the number of parallel test heads of the machine, and obtain the test run cycle;

[0023] S4. Based on the test run cycle, plan the test sequence to obtain the test instruction set;

[0024] S5, obtain the remaining wafer data and the number of free slots in the current test production line, perform timing conflict detection on the test instruction set, the remaining wafer data and the number of free slots, and obtain the scheduling signal sequence.

[0025] In step S1, the wafer batch record, the number of parallel test heads on the machine, and the current slot occupancy status of the chip testing production line are obtained. The matching degree between the wafer batch record and the number of parallel test heads on the machine is calculated to obtain the batch matching sequence.

[0026] Specifically, the matching degree between the wafer batch record and the number of parallel test heads on the machine is calculated to obtain a batch matching sequence, including:

[0027] Obtain the total batch test time associated with the wafer batch record, and divide the total batch test time by the number of parallel test heads on the machine to obtain the base load ratio;

[0028] The basic load ratio is normalized to the preset fixture slot reference to obtain the matching score for each batch.

[0029] The matching scores of all batches are sorted in descending order to obtain the batch matching sequence.

[0030] In one implementation, the physical and process parameter files of all wafers to be tested within the current production schedule are extracted through the data interface of the manufacturing execution system and identified as wafer batch records. These batch records include the total number of wafers corresponding to each batch and the testing time per wafer. Simultaneously, the hardware activation status parameters of the target testing machine are collected in real time through the equipment control system interface. The total number of hardware channels of the test modules that are currently powered on and have physical communication response capabilities is extracted and identified as the number of parallel test heads on the machine. Simultaneously, the number of slots on the physical fixture support mechanism that are currently occupied by wafer entities is collected and identified as the current slot occupancy status.

[0031] It should be noted that this embodiment obtains the total batch test time associated with the wafer batch record. The total number of wafers and the test time per wafer for a specific batch are extracted from the wafer batch record. An algebraic multiplication operation is performed on the total number of wafers and the test time per wafer, and the calculated product is absolutely determined as the total batch test time for that specific batch. In this embodiment, the total batch test time is divided by the number of parallel test heads on the machine to calculate the theoretical scalar value of the time consumed by the machine to process that batch under ideal absolute concurrency conditions, and this value is strictly determined as the base load ratio.

[0032] It is worth noting that this embodiment normalizes the basic load ratio and the preset fixture slot reference to obtain the matching score for each batch. Regarding the determination of the preset fixture slot reference, this embodiment adopts an engineering calibration method. The physical load-bearing extreme value parameters are extracted from the machine's factory configuration specifications, identifying the maximum total number of fixture slots that the machine can simultaneously accommodate in physical space. This total number of fixture slots is objectively calibrated and solidified as the preset fixture slot reference. This embodiment divides the basic load ratio by the preset fixture slot reference to calculate the average load ratio borne by each slot. By employing deviation standardization, the average load ratios corresponding to all batches under test are extracted to form a set, and the maximum and minimum limit values ​​in this set are extracted. The minimum limit value is subtracted from the average load ratio of a specific batch to obtain a first difference. The minimum limit value is subtracted from the maximum limit value to obtain a second difference. The first difference is divided by the second difference to calculate a continuous floating-point value between zero and one, and this continuous floating-point value is objectively determined as the matching score of each batch.

[0033] Furthermore, in this embodiment, the matching scores of all batches are sorted in descending order to obtain a batch matching sequence. The matching scores corresponding to all batches to be tested are extracted, and the matching scores are rearranged according to the descending order of values ​​to generate a linear one-dimensional data arrangement structure that gradually decreases from high fit to low fit, which is determined as the batch matching sequence.

[0034] For example, the system obtains the wafer batch record with batch number B001 through the manufacturing execution system interface, and parses it to find that it contains a total of 25 wafers, with a single wafer testing time of 120 seconds. The system multiplies 25 and 120 to obtain a total batch testing time of 3000 seconds. Simultaneously, the system acquires information through the equipment control system interface that the current machine has 4 parallel test heads. The system divides 3000 seconds by 4 to calculate a base load ratio of 750 seconds. The system extracts a preset fixture slot reference of 8 slots determined through engineering physical calibration. The system divides 750 seconds by 8 to obtain an average load ratio per slot of 93.75 seconds. Assume that the system identifies a minimum limit of 50 seconds and a maximum limit of 250 seconds among the average load ratios of all current batches. The system performs deviation standardization calculations: subtracting 50 from 93.75 yields 43.75; subtracting 50 from 250 yields 200; dividing 43.75 by 200 calculates the matching score for a specific batch B001 to be 0.21875. For all processed batches, such as B001 with a score of 0.21875, B002 with a score of 0.82, and B003 with a score of 0.67, the system sorts the values ​​in descending order, ultimately generating a linked list structure with the order B002, B003, and B001, and outputs this as the batch matching sequence.

[0035] In step S2, when it is determined that the current slot occupancy status is lower than a preset slot occupancy threshold, the batch matching sequence is aggregated and filtered to obtain a set of batches to be aggregated, including:

[0036] The current slot occupancy status is analyzed to obtain the occupied value;

[0037] When it is determined that the occupied value is lower than the preset slot occupancy threshold, the difference between the preset slot occupancy threshold and the occupied value is calculated to obtain the number of available slots;

[0038] The aggregation potential value of each batch is obtained by multiplying the number of available slots with the matching score of each batch in the batch matching sequence.

[0039] Extract the target batches whose aggregation potential value is greater than a preset potential threshold, and combine all the target batches to obtain a set of batches to be aggregated.

[0040] In one implementation, the current slot occupancy status obtained in step S1 is parsed, the slot distribution matrix that has been occupied by the wafer entity on the current physical fixture support mechanism is extracted, the total number of occupied independent slots is counted, and the occupied value is determined.

[0041] It should be noted that the preset slot occupancy threshold is determined using an engineering calibration method. By extracting the hardware limit capacity of the test machine under continuous full-load operation and combining it with the physical handling timing overlap tolerance of the loading and unloading robotic arms, the upper limit of physical slot occupancy that can maintain continuous high-concurrency operation of the test unit and avoid hardware material congestion is calculated, and the upper limit of physical slot occupancy is objectively calibrated as the preset slot occupancy threshold.

[0042] It is worth noting that this embodiment performs a logical comparison between the occupied value and the preset slot occupancy threshold. When the occupied value is determined to be lower than the preset slot occupancy threshold, a dynamic aggregation condition is triggered, and the occupied value is subtracted from the preset slot occupancy threshold by performing an algebraic subtraction operation. The positive difference scalar value is then used to determine the number of available slots. This value is used to calculate the net remaining hardware space available for new wafer batches on the machine in real time. If the occupied value is determined to be greater than or equal to the preset slot occupancy threshold, it indicates that the current physical load of the machine has reached its saturation limit. The system triggers a waiting scheduling instruction, suspending subsequent aggregation filtering and calculation operations in this cycle, maintaining the normal flow of the current existing test tasks until the next scheduling cycle polls and detects that a slot is released and the occupied value is lower than the preset slot occupancy threshold, at which point the aggregation filtering operation is restarted. This avoids redundant calculations and system freezes under overload conditions.

[0043] Based on this, the number of available slots is multiplied by the matching score of each batch in the batch matching sequence to obtain the aggregation potential value of each batch. The system sequentially retrieves the batch matching sequence generated in step S1, traverses the matching score corresponding to each batch to be tested, multiplies the number of available slots by each matching score, performs algebraic multiplication, and defines the calculated product results as the aggregation potential value of each corresponding batch. This potential value, at the physical level, comprehensively reflects the combined benefits of hardware space overhead and process adaptability for a specific batch to enter the machine for parallel testing.

[0044] Furthermore, this embodiment performs a boundary logic comparison of the aggregation potential value of each batch with a preset potential threshold. Specific batches whose aggregation potential value is greater than the preset potential threshold are extracted and objectively identified as target batches. Subsequently, all identified target batches undergo concurrent data structure aggregation and tensor combination to generate a set of batches to be aggregated that meets the aggregation requirements of the current batch.

[0045] Furthermore, to prevent production line scheduling disruptions due to all batches failing to meet parameters, this embodiment sets up an anomaly defense branch. After traversing all batches to be tested, if it is determined that the aggregation potential value of all batches is less than or equal to the preset potential threshold, meaning no target batch can be extracted, and the set of aggregated batches is empty, the system triggers a dynamic threshold degradation mechanism. The preset potential threshold is updated according to a preset attenuation coefficient, such as a single reduction of 10%, and the comparison and extraction operation is re-executed based on the updated potential threshold. If the number of consecutive degradation iterations reaches the preset safety limit and the target batch still cannot be extracted, the system intercepts the current scheduling task and sends an idle anomaly warning signal to the manufacturing execution system, thereby ensuring the continuous operation capability of the production line under extremely low adaptability conditions.

[0046] It should be noted that the preset potential threshold is determined using a performance-driven method. Multiple historical samples are extracted from a historical mass production test database. This database is constructed by the manufacturing execution system continuously collecting large batches of continuous operation data from the test production line over a preset time period. The parallel concurrency records of the machines and the corresponding batch space overhead characteristics are structurally cleaned, labeled with corresponding status tags, and then archived. In this embodiment, a grid search is performed within a preset floating-point candidate range to calculate the load imbalance of the test head and the computational overhead of scheduling decisions under different potential thresholds.

[0047] The specific calculation method for the load imbalance of the test head is as follows: Extract the cumulative running time of each test head under the corresponding potential threshold simulation allocation scheme, and calculate the arithmetic mean of the cumulative running time of all test heads; calculate the difference between the cumulative running time of each test head and the arithmetic mean, square the difference to obtain the squared difference, sum the squared differences corresponding to all test heads to obtain the sum of squares; divide the sum of squares by the total number of test heads to obtain the variance, and take the square root of the variance to obtain the standard deviation; finally, divide the standard deviation by the arithmetic mean, and objectively determine the calculated floating-point value as the load imbalance of the test head. Subsequently, the system selects the critical potential value when the load imbalance is lower than the preset balance tolerance and the scheduling overhead reaches the global minimum value, objectively calibrates it, and solidifies it as the preset potential threshold. The preset balance tolerance is determined by statistical analysis. By extracting multiple parallel test records under the historical qualified state of the equipment, the historical distribution of the load imbalance of all test heads is calculated according to the same discreteness calculation logic. The scalar value corresponding to the 95th percentile of the historical distribution set is extracted and objectively determined as the preset balance tolerance.

[0048] For example, the system reads the current machine status through a real-time interface and parses the current slot occupancy status to find that there are 5 slots occupied. The system retrieves the preset slot occupancy threshold of 8 slots. Since the occupied value of 5 is lower than the preset slot occupancy threshold of 8, the system triggers the aggregation condition, calculates 8 minus 5, and obtains the number of available slots as 3. Next, the system extracts the matching score of the current test batch B002 in the batch matching sequence, which is 0.82. The system performs a product operation on the number of available slots 3 and the matching score 0.82, that is, 3 multiplied by 0.82, and calculates the aggregation potential value of batch B002 as 2.46. The system retrieves the preset potential threshold of 1.5 determined by historical data grid search. After logical comparison of the numerical values, since the aggregation potential value of batch B002, 2.46, is greater than the preset potential threshold of 1.5, the system determines batch B002 as the target batch. Similarly, if the matching score of the adjacent batch B003 is 0.40, its corresponding aggregation potential value is 3 multiplied by 0.40, which equals 1.20. Since 1.20 is lower than the preset potential threshold of 1.5, batch B003 is excluded. Finally, the system performs tensor combination on all target batches that meet the conditions, generating a set of batches to be aggregated, including batch B002, and pushes this set to the subsequent time-consuming alignment process in real time.

[0049] In step S3, the associated batch time set is extracted based on the batch set to be aggregated, and the maximum time consumption is aligned between the batch time set and the number of parallel test heads on the machine to obtain the test run cycle.

[0050] The step of extracting the associated batch time set based on the batch set to be aggregated includes:

[0051] Analyze the number of wafers and the single-wafer testing time in each batch of the batch set to be aggregated;

[0052] The total required time for each batch is obtained by multiplying the number of wafers by the single-wafer testing time.

[0053] The set of all the total required time is defined as the batch time set.

[0054] In one implementation, the set of batches to be aggregated is retrieved from a temporary data storage area or the data structure output from a preceding aggregation and screening step. The unique identifier code of each wafer batch to be tested contained within the set is then parsed. The system retrieves a wafer process parameter database based on each unique identifier code. This database is formed by the manufacturing execution system synchronously collecting the physical attributes and process requirements of each batch at the time of wafer batch entry, and then cleaning and storing the data. The system extracts the wafer quantity and corresponding single-wafer testing time for each batch from the wafer process parameter database.

[0055] It should be noted that the total required time for each batch is obtained by multiplying the number of wafers and the single-wafer testing time. For each independent batch in the set of batches to be aggregated, the system performs an algebraic multiplication operation on the parsed number of wafers and the single-wafer testing time, and calculates the output product results, which represent the net hardware resource consumption time of the corresponding batch in single-channel testing mode. This product is then absolutely determined as the total required time for each batch.

[0056] It is worth noting that the set of all the total required times is defined as the batch time set. The system collects the total required times calculated for all batches in the batch set to be aggregated, encapsulates these time scalar data into a one-dimensional numerical array according to a preset linear sequence rule, and defines this one-dimensional numerical array as the batch time set, which serves as the basic input for subsequent time-series parallel inference.

[0057] For example, the system parses three batches, B002, B004, and B005, from the set of batches to be aggregated. For batch B002, which has 18 wafers and a single-wafer testing time of 110 seconds, the system performs a multiplication operation to obtain a total required time of 1980 seconds. For batch B004, which has 15 wafers and a single-wafer testing time of 95 seconds, the system performs a multiplication operation to obtain a total required time of 1425 seconds. For batch B005, which has 9 wafers and a single-wafer testing time of 125 seconds, the system performs a multiplication operation to obtain a total required time of 1125 seconds. Finally, the system combines and encapsulates 1980 seconds, 1425 seconds, and 1125 seconds to construct a batch time set containing three numerical components.

[0058] The test cycle is obtained by aligning the batch time set with the number of parallel test heads on the machine, and performing maximum time-consolidation calculations. This includes:

[0059] Divide the total required time of each batch in the batch time set by the number of parallel test heads on the machine to obtain the basic parallel time of each batch.

[0060] Select the target time parameter with the largest value from all the aforementioned basic parallel times, and determine the target time parameter as the reference alignment time;

[0061] The test cycle is obtained by performing an addition operation on the reference alignment time and the preset feeding buffer delay parameter.

[0062] In one implementation, the total required time for each batch in the batch time set is divided by the number of parallel test heads on the machine to obtain the basic parallel time for each batch. The system sequentially extracts the total required time for each batch in the batch time set, divides each total required time by the number of parallel test heads on the machine, performs algebraic division, and calculates the quotient value, which represents the theoretical processing time of each batch in the multi-channel full-load split mode, and determines it as the basic parallel time for each batch.

[0063] It should be noted that among all the aforementioned basic parallel times, the target time parameter with the largest value is selected and determined as the baseline alignment time. The system inputs the calculated basic parallel times of each batch into the numerical comparison module, performs a full numerical comparison operation in ascending order, filters out the maximum limit value, and determines the maximum limit value as the target time parameter, which is then used as the baseline alignment time. This step is based on the "barrel effect" alignment constraint in parallel physical testing, where the hardware channel with the longest processing time determines the final material feeding trigger node of the entire mixed test unit, thereby avoiding material handling interference caused by premature hardware actions.

[0064] It is worth noting that the test running cycle is obtained by adding the reference alignment time to the preset unloading buffer delay parameter. The preset unloading buffer delay parameter is determined by engineering calibration. During the offline debugging phase, the system controls the unloading robot arm to perform physical unloading actions under different motion speed gradients. The system continuously collects the time interval from the disconnection of the machine's electrical contact signal to the complete disengagement of the robot arm and the decay of the robot arm's structural vibration to within 0.01 mm. The arithmetic mean of the time intervals collected multiple times is calculated and a preset safety mechanical redundancy is added. The final time parameter is calibrated as the preset unloading buffer delay parameter.

[0065] Regarding the preset safety mechanical redundancy, it is determined using statistical analysis. By extracting jitter delay distribution data of the mechanical transmission system under historical standard operating conditions, the scalar value corresponding to the 95th percentile of this distribution set is calculated and objectively designated as the preset safety mechanical redundancy. The system performs algebraic addition on the reference alignment time and the preset material feeding buffer delay parameter. The resulting sum objectively determines the boundary of the complete physical time dimension occupied by the entire aggregation task on the machine platform, which is then defined as the test run cycle.

[0066] For example, the system extracts the number of parallel test heads obtained through hardware interface calibration as 3 test heads. The system divides the total required time of batch B002 (1980 seconds) by 3 to calculate the corresponding basic parallel time as 660 seconds; divides the total required time of batch B004 (1425 seconds) by 3 to calculate the corresponding basic parallel time as 475 seconds; and divides the total required time of batch B005 (1125 seconds) by 3 to calculate the corresponding basic parallel time as 375 seconds. The system performs a full comparison of 660 seconds, 475 seconds, and 375 seconds, identifying the largest target time parameter as 660 seconds, and determines it as the baseline alignment time. Subsequently, the system retrieves the preset unloading buffer delay parameter of 15 seconds, determined through offline debugging calibration, and performs an addition operation between the baseline alignment time of 660 seconds and the preset unloading buffer delay parameter of 15 seconds (660 plus 15) to calculate the final test run cycle as 675 seconds, which is then output to the subsequent sequence planning module.

[0067] In step S4, test sequence planning is performed according to the test execution cycle to obtain a set of test instructions, including:

[0068] Extract the priority weight parameters and the number of wafers in each batch from the set of batches to be aggregated;

[0069] Based on the test run cycle, the number of wafers in the batch, and the priority weight parameter, priority scores are calculated to obtain the unit score sequence;

[0070] Obtain the test head configuration corresponding to the number of parallel test heads on the machine, and map and allocate the unit score sequence from high to low to each of the test head configurations to obtain the unit allocation structure;

[0071] The test instruction set is obtained by filling in the instructions according to the unit allocation structure.

[0072] In one implementation, the batch set to be aggregated output from the preceding steps is parsed, and the unique identifier code of each independent batch within the set is extracted. The corresponding batch wafer quantity is then queried in the Manufacturing Execution System (MES) database based on this unique identifier code. Simultaneously, the priority weight parameter for each batch is extracted. The priority weight parameter is determined using statistical analysis. The remaining delivery time span of the corresponding batch's customer orders is extracted along with the pre-assigned business level code. Deviation standardization is used to map the remaining delivery time span to a reverse-order value from zero to one. A weighted summation calculation is then performed using a fixed coefficient corresponding to the business level code, and the resulting continuous floating-point value is objectively labeled as the priority weight parameter. The fixed coefficient is set using a business rule mapping method. For example, based on the customer service level agreement, expedited orders are mapped to a weight coefficient of 0.8, and regular orders are mapped to 0.4, etc. The specific value is determined by the MES initialization configuration.

[0073] It should be noted that in this embodiment, priority scores are calculated based on the test run cycle, the number of wafers in each batch, and the priority weight parameters to obtain a unit score sequence. The system first calculates the arithmetic sum of the priority weight parameters for all batches within the set of batches to be aggregated. The priority weight parameter of a single batch is divided by the arithmetic sum to obtain the weight ratio. An algebraic multiplication operation is performed between the previously generated test run cycle and the weight ratio to calculate the theoretical allocation time for each batch. Subsequently, the single-wafer testing time data for each batch is extracted, and the allocation time is divided by the single-wafer testing time to calculate the priority score. The system rearranges the priority scores of all batches according to a descending order rule to generate a one-dimensional numerical arrangement structure, which is strictly determined as the unit score sequence.

[0074] It is worth noting that the test head configuration corresponding to the number of parallel test heads on the machine is obtained, and the unit score sequence is mapped and allocated to each test head configuration from high to low to obtain the unit allocation structure. The number of parallel test heads on the machine is extracted, and a logical channel identifier sequence corresponding to this number is generated internally by the system, which is then identified as the test head configuration. The system traverses the unit score sequence, introduces a greedy algorithm, and prioritizes allocating all wafers of the corresponding batch to the test head configuration with the lowest cumulative processing time, according to the priority from high to low scores. If the cumulative wafer processing time of a certain test head configuration reaches the upper limit of the test run cycle during the allocation process, then the remaining unallocated wafers are subjected to batch splitting and dicing operations. Specifically, the system extracts the remaining available time of the test head configuration, which is the test cycle minus the currently allocated cumulative time. The remaining available time is divided by the single-wafer test time of this batch, and the quotient is rounded down to obtain the number of allocable wafers. The system then truncates the original batch into a first half containing the number of allocable wafers and a second half containing the remaining wafers. The first half is mapped to the current test head configuration, and the second half is sequentially mapped to the next available test head configuration with the lowest cumulative time, until all wafers in all batches are allocated. The set of data mapping relationships between the test head physical channels and the corresponding wafer allocation slices is determined as the unit allocation structure.

[0075] For example, the system extracts the priority weight parameters of batch B002 (0.85), batch B004 (0.78), and batch B005 (0.72) from the batch set to be aggregated. The system calculates the arithmetic sum of the weights to be 2.35. Combining this with a test run cycle of 675 seconds, the system calculates the allocation duration for B002 as 0.85 divided by 2.35, then multiplied by 675, resulting in 244.1 seconds. Dividing this by the single-chip test time of 110 seconds, the priority score is calculated to be 2.22. Similarly, the allocation duration for B004 is calculated to be 224.0 seconds with a priority score of 2.36; the allocation duration for B005 is calculated to be 206.8 seconds with a priority score of 1.65. The system generates a unit score sequence sorted as [2.36, 2.22, 1.65]. The system then retrieves the test header configuration containing three physical channels. The system performs a greedy allocation based on score priority, initially assigning B004 to Test Head 1. Test Head 1 currently has no tasks and 675 seconds of remaining time. Dividing this by the single-wafer testing time of B004 (95 seconds) yields 7.1. The system rounds down to determine the number of allocable wafers: 7. The system triggers a batch splitting operation, mapping the first 7 wafers of B004 to Test Head 1. Since Test Head 1 has reached its time limit, the system sequentially maps the 8th to 15th wafers of B004 to Test Head 2, and so on, filling all wafers in the score queue into the respective test heads. The system outputs this determined physical association mapping table as the cell allocation structure.

[0076] Specifically, the test instruction set is obtained by filling in instructions according to the unit allocation structure, including:

[0077] Extract the test program number for each batch;

[0078] The combined execution parameters are obtained by combining the unit allocation structure, the test program number, and the test execution cycle;

[0079] The combined execution parameters are filled into the corresponding fields of the preset instruction configuration template to obtain the test instruction set.

[0080] In one implementation, the batch identification codes of each wafer in the pre-generated unit allocation structure are parsed, and the corresponding standard test operation specification documents are retrieved from the process specification database using the identification codes. The mixed alphanumeric code string for machine identification is extracted and strictly identified as the test program number.

[0081] It should be noted that the combined execution parameters are obtained by combining the unit allocation structure, the test program number, and the test run cycle. The system traverses each test head mapping entry in the unit allocation structure, and concatenates the execution test head identifier, associated batch number, number of wafers allocated for execution recorded in the entry with the extracted corresponding test program number and the test run cycle into a structured string to generate a multi-dimensional device execution parameter object dictionary. This parameter object dictionary is then used as the combined execution parameters.

[0082] It is worth noting that the combined execution parameters are filled into the corresponding fields of a preset instruction configuration template to obtain a test instruction set. The construction of the preset instruction configuration template employs an engineering calibration method. The semiconductor device communication protocol specification is extracted, and the basic skeleton of the machine control message in the protocol is parsed out. The fixed header, control checksum, and end character in the message skeleton are retained, and the variable area is defined as a key-value pair empty field. This data structure containing the empty field is then solidified into the preset instruction configuration template. The system parses the generated combined execution parameters into key-value pairs and writes them one-to-one into the empty fields of the preset instruction configuration template according to the field names, generating instruction entities that the device can directly parse and execute. All instruction entities associated with the test header are grouped together to determine the test instruction set.

[0083] For example, the system extracts the test program number TP-7821 corresponding to the batch B004 in the test head 1 entry of the unit allocation structure. The system packages the test head number 1, the first 7 pieces of batch B004, the test program number TP-7821, and the test duration of 675 seconds into a dictionary structure to generate the first set of combined execution parameters. The system retrieves a preset instruction configuration template built based on the semiconductor communication protocol and accurately fills the first set of combined execution parameters into the corresponding [Head_ID], [Lot_Slice], [Recipe_ID], and [Duration] fields to generate the first low-level action instruction. The system repeats this step to generate the second and third low-level action instructions, combines these three complete instructions to form a test instruction set, and sends it to the downstream conflict detection module.

[0084] In step S5, the remaining wafer data and the number of free slots of the current test production line are obtained, and timing conflict detection is performed on the test instruction set, the remaining wafer data and the number of free slots to obtain the scheduling signal sequence.

[0085] Specifically, timing conflict detection is performed on the test instruction set, the remaining wafer data, and the number of free slots to obtain a scheduling signal sequence, including:

[0086] The test duration of each instruction in the test instruction set and the total instruction duration are analyzed. The test duration of each instruction is divided by the total instruction duration to obtain the duration weight.

[0087] The product operation is performed on the duration ratio weight and the number of idle slots to obtain the theoretical number of slots to be allocated;

[0088] The boundary constraint ratio is calculated between the theoretically allocated number of slots and the remaining wafer data, and the smaller value is determined as the target number of wafers to be loaded and unloaded.

[0089] The estimated handling time period is obtained by converting the target number of loading and unloading pieces and the preset handling efficiency parameters.

[0090] The execution order of the test instruction set is extracted, an initial timeline is constructed based on the execution order, and the estimated transport time period is compared with the initial timeline to obtain a scheduling signal sequence without overlap.

[0091] In one implementation, the untested wafer count records of the online batches within the current production cycle are extracted through the real-time communication interface of the material tracking system and identified as the remaining wafer data. Simultaneously, miniature electrical contact sensors or photoelectric array sensors deployed inside the test machine's slots scan the total number of physical slots not occupied by actual wafers in real time and determine this as the number of free slots.

[0092] It should be noted that this embodiment analyzes the instruction test duration and total instruction duration of the test instruction set. The hardware occupancy time allocated to each independent execution control block in the test instruction set is retrieved sequentially and determined as the instruction test duration. Simultaneously, the values ​​of all instruction test durations are algebraically summed to obtain the total instruction duration. The instruction test duration corresponding to a specific instruction is divided by the total instruction duration to calculate the proportion coefficient of that specific instruction in the total time consumption dimension, which is determined as the duration proportion weight. In this embodiment, the duration proportion weight is algebraically multiplied by the extracted number of free slots, and the resulting floating-point number is rounded to the nearest integer to obtain the theoretical number of allocated slots.

[0093] It is worth noting that in this embodiment, a boundary constraint ratio calculation is performed between the theoretically allocated number of slots and the remaining wafer data. The smaller of the calculated values ​​is then determined as the target number of wafers to be loaded and unloaded. The system inputs the theoretically allocated number of slots corresponding to a specific batch and the remaining wafer data associated with that batch into a numerical comparison module, performs a boundary constraint calculation to find the minimum value, and determines the smaller of the two values ​​as the target number of wafers to be loaded and unloaded. This operation establishes a hard boundary defense between the logical allocation limit and the underlying physical inventory, avoiding hardware execution idle conflicts caused by the allocated number exceeding the physical inventory.

[0094] It should be noted that the system performs time conversion calculations based on the target number of wafers to be loaded and unloaded and the preset handling efficiency parameters to obtain the estimated handling time period. The preset handling efficiency parameters are determined using an engineering calibration method. During the no-load trial operation phase of the production line, the system controls the loading and unloading robotic arms to repeatedly perform loading and unloading actions on standard-sized wafers. The system uses a high-precision industrial camera to capture the entire process time of the robotic arm from starting to grasp, physical movement, precise placement in the slot, to complete disengagement and reset of the mechanical structure. The average time of multiple cycles is calculated and superimposed with the preset electrical control response delay. The final time parameter is then calibrated as the preset handling efficiency parameter.

[0095] The preset electrical control response delay is determined using statistical analysis. This involves extracting the handshake instruction logs of the machine's programmable logic controller (PLC) under historical standard communication conditions, statistically analyzing the time difference set from instruction issuance to actuator feedback, and extracting the scalar value corresponding to the 95th percentile of this time difference set. This scalar value is then objectively determined as the preset electrical control response delay. In this embodiment, the target number of loading / unloading pieces is multiplied algebraically with the preset handling efficiency parameter. The calculated duration yields the net physical time window required for the robotic arm to perform the current handling action, which is then determined as the estimated handling time period.

[0096] It is worth noting that the system extracts the execution order of the test instruction set, constructs an initial timeline based on the execution order, and compares the estimated transport time periods with the initial timeline to obtain a non-overlapping scheduling signal sequence. The system constructs a one-dimensional time coordinate axis with zero seconds as the starting point and determines it as the initial timeline. According to the execution order, the estimated transport time periods corresponding to each batch are sequentially mapped and arranged on the initial timeline, and the start and end time nodes of each estimated transport time period on the initial timeline are extracted.

[0097] The system sequentially traverses two adjacent estimated transport time periods according to the execution order, extracting the end time node of the first transport time period (which is in the preceding order) and the start and end time nodes of the second transport time period (which is in the following order). The system compares the start time node of the second transport time period with the end time node of the first transport time period; if the start time node of the second transport time period is less than or equal to the end time node of the first transport time period, it determines that they overlap in the projection interval. The system subtracts the start time node of the second transport time period from the end time node of the first transport time period, performing an algebraic subtraction operation to obtain the basic difference; it extracts the minimum time resolution value of the machine control system, for example, one second, and performs an algebraic addition operation between the basic difference and the minimum time resolution value to obtain the time offset; it then performs algebraic addition operations between the start and end time nodes of the second transport time period and the time offset to obtain the translated and updated second transport time period.

[0098] The system uses the updated second transport time period as the new baseline parameter and continues to iteratively perform the overlap comparison and translation calculation downstream until there is no overlap between any two time periods on the time axis. After translation calibration, the action trigger nodes corresponding to each time period are combined and encapsulated with the machine control code string to generate a serialized action instruction entity that directly drives the robotic arm actuator, which is then identified as a non-overlapping scheduling signal sequence.

[0099] For example, the system parses the remaining wafer data for batch B002 in the current test production line through the material system interface, finding 18 wafers remaining for batch B004, 24 wafers remaining for batch B005, and 15 wafers remaining for batch B005. Simultaneously, sensor scanning reveals 29 available slots. The system parses the test instruction set, extracting the instruction test durations for the three batches as 292.1 seconds, 251.6 seconds, and 131.3 seconds, respectively, for a total instruction duration of 675 seconds. For batch B002, the system calculates its duration weight as 292.1 divided by 675, equaling 43.3%. The system multiplies 43.3% by the number of available slots (29), obtaining 12.557 slots. After rounding, the theoretical allocated slot number is 13. The system compares the theoretical allocated slot number of 13 with the remaining wafer data of 18 wafers. Since 13 is less than 18, the smaller value of 13 wafers is taken as the target number of wafers to be loaded and unloaded.

[0100] Similarly, the system calculates the target number of loading / unloading pieces for B004 to be 11 pieces, and for B005, 6 pieces. The system retrieves preset handling efficiency parameters determined through engineering physical calibration, such as a single piece handling time of 3.46 seconds. Multiplying 13 pieces by 3.46 seconds, the estimated handling time for batch B002 is calculated to be 45 seconds. Similarly, B004 is calculated to be 38 seconds, and B005 to be 21 seconds. The system performs timing conflict comparison and shifting on the initial time axis, accumulating the time offsets to generate a timing table for the following actions: the first signal controls the loading of 13 pieces onto test head 1 within 0 to 45 seconds; the second signal controls loading within 46 to 84 seconds; and the third signal controls loading within 85 to 106 seconds. This sequence is strictly defined as a scheduling signal sequence and pushed to the material control system for execution.

[0101] The process, following the acquisition of the scheduling signal sequence, further includes:

[0102] Analyze the updated slot status corresponding to the scheduling signal sequence, and extract the physical slot occupancy rate corresponding to the updated slot status;

[0103] Extract the historical matching score of the current record of each batch in the batch matching sequence;

[0104] The historical matching score, physical slot occupancy rate and preset smoothing attenuation coefficient of each batch are weighted and fused to obtain the feedback weight value corresponding to each batch.

[0105] The matching score of the corresponding batch in the batch matching sequence is updated based on the feedback weight value.

[0106] In one implementation, after the scheduling signal sequence is executed by the underlying material handling mechanism, the system rereads the physical slot occupancy index stream through the machine's main control program and determines it as the updated slot status. The system calculates the total number of slots currently occupied by physical wafers, divides it by the machine's inherent total slot capacity, performs algebraic division, and calculates the output floating-point number, which objectively represents the transient saturation level of the current production line hardware environment and determines it as the physical slot occupancy rate.

[0107] It should be noted that this embodiment extracts the historical matching scores of each batch currently recorded in the batch matching sequence. The system enters the data cache area and sequentially extracts the values ​​assigned to each circulating batch in the batch matching sequence in the preceding calculation loop, and determines them as historical matching scores.

[0108] It is worth noting that this embodiment utilizes exponential smoothing to perform weighted fusion calculations on the historical matching scores, physical slot occupancy rates, and preset smoothing attenuation coefficients for each batch, obtaining the feedback weight value corresponding to each batch. The preset smoothing attenuation coefficient is determined using a performance-driven method. On a pre-built chip scheduling simulation platform, the system sets multiple fixed step sizes for the attenuation coefficient value within a continuous interval from zero to one, injects diverse wafer arrival disturbance flows to perform dynamic simulation tests, and statistically analyzes the average waiting time of each batch in the machine in real time. The convergence response coefficient that makes the average waiting time reach a global minimum is selected, and its value is objectively calibrated as the preset smoothing attenuation coefficient. The simulation platform is built based on historical production line operation data, which includes the arrival rates of different wafer batches, machine failure rates, and test duration distributions.

[0109] The system subtracts the preset smoothing attenuation coefficient from the numerical value, performing algebraic subtraction to obtain the historical weighting coefficient. The system then multiplies the historical matching score of each batch by the historical weighting coefficient to obtain a first weighted score; simultaneously, it multiplies the physical slot occupancy rate by the preset smoothing attenuation coefficient to obtain a second weighted score; finally, it performs algebraic addition on the first and second weighted scores, objectively determining the final sum as the feedback weight value for each batch. This operation, through a gradual smoothing of the environmental occupancy status, achieves dynamic smoothing of queue priority, eliminating oscillations caused by jumps in system control parameters.

[0110] Furthermore, in this embodiment, the matching score of the corresponding batch in the batch matching sequence is updated according to the feedback weight value. The system extracts the calculated feedback weight value of a specific batch, calls the memory overwrite mechanism, and directly replaces the original matching score of the corresponding batch in the batch matching sequence with the value of the feedback weight value, thereby completing the iterative update of the scheduling queue data status and enabling the updated sequence to directly participate in the aggregation and filtering closed loop of the next cycle.

[0111] For example, after the scheduling signal sequence is executed, the number of occupied slots out of the total 48 slots in the fixture is updated from 29 to 41. The system analyzes the updated slot status and calculates the physical slot occupancy rate as 41 divided by 48, which equals 0.854. The system enters the scheduling queue and extracts the historical matching score of the current record for batch B002, which is a fixed value of 0.82. The system retrieves the preset smoothing attenuation coefficient determined by the simulation platform, which is 0.3, and calculates the historical weight coefficient as 1 minus 0.3, which equals 0.7. The system starts the exponential smoothing weighted fusion calculation, multiplying the historical matching score of 0.82 by 0.7 to obtain 0.574, multiplying the physical slot occupancy rate of 0.854 by 0.3 to obtain 0.2562, and then performing an addition operation on 0.574 and 0.2562 to calculate the final feedback weight value of 0.8302. The system directly writes the value 0.8302 into the batch matching sequence to replace the original score, dynamically corrects the scheduling priority of the batch, and drives the system to seamlessly enter the next round of chip scheduling closed loop.

[0112] In summary, this invention achieves precise matching degree calculation and descending sorting by acquiring wafer batch records, the number of parallel test heads on the machine, and the current slot occupancy status of the chip testing production line. When the slot occupancy status is below a threshold, dynamic aggregation filtering is triggered to lock the set of batches to be aggregated. Subsequently, the maximum time consumption set of each aggregated batch is aligned by calculating the maximum time consumption, accurately deducing the test operation cycle that meets the multi-channel full-load current distribution constraints, and completing the test sequence planning and instruction filling with high load balancing based on this. Finally, the remaining wafer data and the number of idle slots in the online flow are obtained. Timing conflict detection is performed under the boundary constraint ratio calculation and time conversion calculation that strictly eliminates dimensional discontinuities. Combined with the exponential smoothing feedback mechanism based on physical slot status updates, a complete data control closed loop is constructed, realizing intelligent dynamic scheduling of the chip testing process. This effectively overcomes the defects of traditional scheduling logic perception lag and action mismatch, and significantly improves the concurrent processing energy efficiency and overall flow stability of the testing equipment.

[0113] The second embodiment of the present invention provides an intelligent dynamic scheduling system for chip testing process, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the method described in any of the above-mentioned embodiments.

[0114] It should be noted that the intelligent dynamic scheduling system for chip testing process provided in this embodiment of the invention is used to execute all process steps of the intelligent dynamic scheduling method for chip testing process in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0115] It should be noted that the system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0116] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A smart dynamic scheduling method for chip testing processes, characterized in that, include: Obtain the wafer batch record, the number of parallel test heads on the machine, and the current slot occupancy status of the chip testing production line; calculate the matching degree between the wafer batch record and the number of parallel test heads on the machine to obtain the batch matching sequence. When it is determined that the current slot occupancy status is lower than the preset slot occupancy threshold, the batch matching sequence is aggregated and filtered to obtain a set of batches to be aggregated. Extract the associated batch time set based on the batch set to be aggregated, and perform maximum time alignment calculation between the batch time set and the number of parallel test heads on the machine to obtain the test run cycle; Based on the aforementioned test execution cycle, a test sequence plan is performed to obtain a set of test instructions; Obtain the remaining wafer data and the number of free slots in the current test production line, perform timing conflict detection on the test instruction set, the remaining wafer data and the number of free slots, and obtain the scheduling signal sequence.

2. The intelligent dynamic scheduling method for chip testing process according to claim 1, characterized in that, The step of calculating the matching degree between the wafer batch record and the number of parallel test heads on the machine to obtain the batch matching sequence includes: Obtain the total batch test time associated with the wafer batch record, and divide the total batch test time by the number of parallel test heads on the machine to obtain the base load ratio; The basic load ratio is normalized to the preset fixture slot reference to obtain the matching score for each batch. The matching scores of all batches are sorted in descending order to obtain the batch matching sequence.

3. The intelligent dynamic scheduling method for chip testing process according to claim 1, characterized in that, When it is determined that the current slot occupancy status is lower than a preset slot occupancy threshold, the batch matching sequence is aggregated and filtered to obtain a set of batches to be aggregated, including: The current slot occupancy status is analyzed to obtain the occupied value; When it is determined that the occupied value is lower than the preset slot occupancy threshold, the difference between the preset slot occupancy threshold and the occupied value is calculated to obtain the number of available slots; The aggregation potential value of each batch is obtained by multiplying the number of available slots with the matching score of each batch in the batch matching sequence. Extract the target batches whose aggregation potential value is greater than a preset potential threshold, and combine all the target batches to obtain a set of batches to be aggregated.

4. The intelligent dynamic scheduling method for chip testing process according to claim 1, characterized in that, The step of extracting the associated batch time set based on the batch set to be aggregated includes: Analyze the number of wafers and the single-wafer testing time in each batch of the batch set to be aggregated; The total required time for each batch is obtained by multiplying the number of wafers by the single-wafer testing time. The set of all the total required time is defined as the batch time set.

5. The intelligent dynamic scheduling method for chip testing process according to claim 1, characterized in that, The step of aligning the batch time set with the number of parallel test heads on the machine to calculate the maximum time consumption to obtain the test run cycle includes: Divide the total required time of each batch in the batch time set by the number of parallel test heads on the machine to obtain the basic parallel time of each batch. Select the target time parameter with the largest value from all the aforementioned basic parallel times, and determine the target time parameter as the reference alignment time; The test cycle is obtained by performing an addition operation on the reference alignment time and the preset feeding buffer delay parameter.

6. The intelligent dynamic scheduling method for chip testing process according to claim 1, characterized in that, The step of planning the test sequence according to the test execution cycle to obtain a set of test instructions includes: Extract the priority weight parameters and the number of wafers in each batch from the set of batches to be aggregated; Based on the test run cycle, the number of wafers in the batch, and the priority weight parameter, priority scores are calculated to obtain the unit score sequence; Obtain the test head configuration corresponding to the number of parallel test heads on the machine, and map and allocate the unit score sequence from high to low to each of the test head configurations to obtain the unit allocation structure; The test instruction set is obtained by filling in the instructions according to the unit allocation structure.

7. The intelligent dynamic scheduling method for chip testing process according to claim 6, characterized in that, The step of filling in the test instruction set according to the unit allocation structure includes: Extract the test program number for each batch; The combined execution parameters are obtained by combining the unit allocation structure, the test program number, and the test execution cycle; The combined execution parameters are filled into the corresponding fields of the preset instruction configuration template to obtain the test instruction set.

8. The intelligent dynamic scheduling method for chip testing process according to claim 1, characterized in that, The timing conflict detection of the test instruction set, the remaining wafer data, and the number of free slots to obtain the scheduling signal sequence includes: The test duration of each instruction in the test instruction set and the total instruction duration are analyzed. The test duration of each instruction is divided by the total instruction duration to obtain the duration weight. The product operation is performed on the duration ratio weight and the number of idle slots to obtain the theoretical number of slots to be allocated; The boundary constraint ratio is calculated between the theoretically allocated number of slots and the remaining wafer data, and the smaller value is determined as the target number of wafers to be loaded and unloaded. The estimated handling time period is obtained by converting the target number of loading and unloading pieces and the preset handling efficiency parameters. The execution order of the test instruction set is extracted, an initial timeline is constructed based on the execution order, and the estimated transport time period is compared with the initial timeline to obtain a scheduling signal sequence without overlap.

9. The intelligent dynamic scheduling method for chip testing process according to claim 1, characterized in that, After obtaining the scheduling signal sequence, the process further includes: Analyze the updated slot status corresponding to the scheduling signal sequence, and extract the physical slot occupancy rate corresponding to the updated slot status; Extract the historical matching scores of the current record of each batch in the batch matching sequence; The historical matching score, physical slot occupancy rate and preset smoothing attenuation coefficient of each batch are weighted and fused to obtain the feedback weight value corresponding to each batch. The matching score of the corresponding batch in the batch matching sequence is updated based on the feedback weight value.

10. An intelligent dynamic scheduling system for chip testing processes, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 9.

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