An on-chip integrated architecture and dual-laser lidar calibration device

Abstract

The application discloses a kind of on-chip integrated architecture and dual-laser laser radar calibration device, dual-laser laser radar calibration device includes on-chip integrated architecture, laser light source module, transimpedance amplifier conversion module, data acquisition module, data processing and control module;On-chip integrated architecture includes coupler module, first optical splitter module, first frequency mixer module, first balanced detector module, second optical splitter module, second frequency mixer module, second balanced detector module and on-chip delay line module, on-chip delay line module includes at least one on-chip delay line module;The application proposes a kind of dual-laser heteroslope dual-chirp on-chip integrated architecture, realizes the chip level miniaturization integration of full-link nonlinear calibration, solves the defects of bulky, environment-sensitive, poor stability and high integration difficulty caused by external long optical fiber or off-chip auxiliary interferometer, reduces system volume, reduces power consumption and cost, significantly improves calibration consistency and long-term reliability.

Description

Technical Field

[0001] This invention relates to the technical field of dual-laser, different-slope, dual-chirped lidar, specifically to an on-chip integrated architecture and a dual-laser lidar calibration device. Background Technology

[0002] LiDAR (Light Detection and Ranging) is an active optical system that detects the position and velocity of a target by emitting a laser beam. This technology utilizes linearly frequency-modulated continuous laser light and simultaneously calculates distance and Doppler velocity by measuring the beat frequency of the echo and local oscillator light. It has advantages such as anti-interference, high ranging and velocity measurement accuracy, and eye safety, and is widely regarded as an important technological path for next-generation automotive LiDAR.

[0003] However, traditional single-laser FMCW radars require decoupling range and velocity information in two chirped time periods, limiting point cloud density and real-time performance. To address this, a dual-laser, opposite-slope, dual-chirped system has emerged. This system uses two lasers simultaneously to generate chirped signals with opposite or different frequency modulation slopes, achieving range-velocity decoupling within a single time window and significantly improving point cloud density. However, this system demands extremely high linearity in laser frequency modulation. Real-world lasers exhibit significant nonlinearity due to thermal effects and carrier dynamics; without precise calibration, this will lead to severe distortion of the beat frequency signal and a substantial decrease in ranging and velocity measurement accuracy.

[0004] Currently, mainstream nonlinear calibration methods include open-loop predistortion compensation, equal-frequency resampling, and opto-phase-locked loop (PLL) technology. Among these, open-loop schemes rely on external long fiber delay lines, resulting in large size, high cost, environmental sensitivity, easy delay time drift, and difficulty in integration. While equal-frequency resampling can compensate for nonlinearity, it suffers from poor real-time performance and limited effectiveness for complex nonlinearities. Opto-phase-locked loops offer high accuracy but are hardware-complex and lack adaptability to high-speed frequency sweeps. Particularly in open-loop predistortion compensation, while current-iterative pre-calibration methods show potential, they are limited by the short on-chip delay line length (only nanoseconds), failing to meet the requirements of dual-chirp calibration. Summary of the Invention

[0005] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention provides an on-chip integrated architecture and a dual-laser lidar calibration device, solving the problems of existing lidar systems being bulky, environmentally sensitive, having poor stability, being difficult to integrate, and unable to achieve efficient and highly stable microsecond-level long-delay calibration.

[0006] According to a first aspect of the present invention, an on-chip integrated architecture includes: a coupler module, a first beam splitter module, a first mixer module, a first balanced detector module, a second beam splitter module, a second mixer module, a second balanced detector module, and an on-chip delay line module, wherein the on-chip delay line module includes at least one on-chip delay line module. The dual-laser asymmetrical slope dual-chirped lidar generates different first chirped light signals and second chirped light signals, which are coupled into the on-chip integrated architecture through the coupler module. The first chirped optical signal is split into two paths by the first beam splitter module. One part of the first chirped optical signal enters the on-chip delay line module to generate a time delay, and the other part of the first chirped optical signal directly enters the first mixer module and is optically mixed with the time-delayed part of the first chirped optical signal to obtain the first beat frequency signal. The first beat frequency signal outputs an electrical signal through the first balanced detector module. The second chirped optical signal is split into two paths by the second beam splitter module. One part of the second chirped optical signal enters the on-chip delay line module to generate a time delay, and the other part of the second chirped optical signal directly enters the second mixer module and is optically mixed with the time-delayed part of the second chirped optical signal to obtain the second beat frequency signal. The second beat frequency signal outputs an electrical signal through the second balanced detector module.

[0007] The method for nonlinear calibration of lidar based on dual lasers with different slopes and dual chirps according to embodiments of the present invention has at least the following beneficial effects: This invention presents an integrated on-chip architecture for nonlinear calibration of dual-laser, different-slope, dual-chirped lidar. It employs two lasers with different wavelengths and chirped slopes to generate two optical signals, completing the entire nonlinear calibration signal processing chain—coupling, splitting, delaying, mixing, and balanced detection—on a single chip. Unlike traditional solutions that combine a single laser with an external long fiber, this invention addresses the drawbacks of external long fibers or off-chip auxiliary interferometers, such as large size, environmental sensitivity, poor stability, and high integration difficulty. This reduces the system size by several orders of magnitude, significantly lowers power consumption and cost, and substantially improves calibration consistency and long-term reliability.

[0008] According to some embodiments of the present invention, the on-chip delay line module includes two on-chip delay line modules, wherein a portion of the first chirped optical signal and a portion of the second chirped optical signal after splitting are respectively time-delayed by the two on-chip delay line modules.

[0009] According to some embodiments of the present invention, the on-chip delay line module includes a dual-wavelength beam combining module, an on-chip delay line module, and a dual-wavelength beam splitting module. A portion of the first chirped optical signal and a portion of the second chirped optical signal after beam splitting are combined by the dual-wavelength beam combining module and then enter the on-chip delay line module to generate a time delay. The delayed first chirped optical signal and the second chirped optical signal are then split into different optical paths by the dual-wavelength beam splitting module and then enter the first mixer module and the second mixer module respectively.

[0010] According to some embodiments of the present invention, the on-chip delay line module includes at least one on-chip delay line unit, the on-chip delay line unit is a spiral structure, including an Euler spiral and two Archimedean spirals smoothly connected to the two ends of the Euler spiral, the curvature of the Euler spiral changes linearly and is in a smoothly connected S-shape, the two Archimedean spirals alternately coil around the Euler spiral and the bending radius increases linearly with the angle.

[0011] According to some embodiments of the present invention, the waveguide width of the Euler spiral gradually decreases from both ends toward the center, and the minimum width of the Euler spiral at the center position is the single-mode waveguide width.

[0012] According to some embodiments of the present invention, the widths of the two Archimedean spirals are W1 and W2, respectively, and the values ​​of W1 and W2 are not equal, and the values ​​of W1 and W2 satisfy the superlattice periodic structure.

[0013] According to some embodiments of the present invention, the on-chip delay line module includes two on-chip delay line units, which form a double-layer waveguide along the top and bottom, the axes of the two on-chip delay line units overlap, and the Archimedean spirals of the two on-chip delay line units are arranged alternately in the radial direction.

[0014] According to some embodiments of the present invention, the on-chip delay line module further includes a multi-level mode multiplexing module and a multi-level mode demultiplexing module. The multi-level mode multiplexing module includes mode multiplexing module 1, ..., mode multiplexing module N, and the multi-level mode multiplexing modules are cascaded at the input terminal of the on-chip delay line module. The multi-level mode demultiplexing module includes mode demultiplexing module N, ..., mode demultiplexing module 1, and the multi-level mode demultiplexing modules are cascaded at the output terminal of the on-chip delay line module. The optical signal entering the on-chip delay line module is input from the mode multiplexing module 1 in TE0 mode, and then passes through the mode multiplexing modules at each level in sequence. It enters the on-chip delay line unit in TE0 for the first delay transmission. After the first delay transmission, TE0 passes through the mode demultiplexing modules at each level and is output from the mode demultiplexing module 1. TE0 is fed back to the mode multiplexing module 1 and converted into TE1 output, completing the first cyclic multiplexing transmission. TE1 starts from mode multiplexing module 1 and passes through each level of mode multiplexing module in sequence. It enters the on-chip delay line unit in TE1 mode for the second delay transmission. After the second delay transmission, TE1 passes through each level of mode demultiplexing module and is then input into mode demultiplexing module 1 and converted into TE0 output. TE0 is fed back to mode multiplexing module 2 and converted into TE2, completing the second cyclic multiplexing transmission. And so on, TE n Starting from mode multiplexing module n, the data sequentially passes through each of the aforementioned mode multiplexing modules, enters the on-chip delay line unit for the (n+1)th delayed transmission, and is converted into TE0 output in mode demultiplexing module n. TE0 is then fed back to mode multiplexing module (n+1) for conversion into TE. （n+1） The (n+1)th cyclic multiplexing transmission is completed; where 2≤n≤(N-1), and N is the number of levels of the mode multiplexing module; after completing the aforementioned N cyclic multiplexing transmissions, the final TE is... N Starting from the mode multiplexing module N, the system enters the on-chip delay line unit to perform the (N+1)th delay transmission, and is converted to TE0 output in the mode demultiplexing module N. This TE0 no longer provides feedback, thus completing all delays and leaving the on-chip delay line module.

[0015] According to some embodiments of the present invention, the first beam splitter module and the second beam splitter module adopt an adjustable beam splitter structure. The adjustable beam splitter structure is composed of a first beam splitter, two thermally tuned phase shifters and a 2×2 coupler cascaded together. The optical signal entering the adjustable beam splitter structure is split into two paths proportionally by the first beam splitter and then input to the two thermally tuned phase shifters respectively. The two thermally tuned phase shifters introduce different phase differences into the two optical signals respectively. The two optical signals with introduced phase differences enter the 2×2 coupler to achieve arbitrary beam splitting ratio output.

[0016] According to a second aspect of the present invention, a dual-laser lidar calibration device is characterized in that it comprises: the above-described on-chip integrated architecture, laser source module, transimpedance amplifier conversion module, data acquisition module, data processing and control module, and signal generation module; The laser source module includes a first laser and a second laser, which are used to output a first chirped light signal and a second chirped light signal, respectively. The on-chip integrated architecture converts the optical signal generated by the laser source module into an electrical signal; The transimpedance amplifier conversion module performs transimpedance amplification and voltage conversion on the electrical signal; The data acquisition module is used to sample the amplified electrical signal; The data processing and control module is used to perform digital signal processing, algorithm calculations, and system control on the sampled data. The signal generation module is used to provide signal feedback to the laser source module based on the processed data.

[0017] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. Attached Figure Description

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 A schematic diagram of an embodiment of a dual-laser lidar calibration device provided by the present invention; Figure 2 The present invention provides a dual-laser lidar calibration device, and schematic diagrams of two embodiments thereof; Figure 3 A schematic diagram of the on-chip delay line unit in one embodiment of an on-chip integrated architecture provided by the present invention is shown below: Figure 3 (a) is the case where the widths of the two Archimedean spirals are equal; Figure 3 (b) is the case where the widths of the two Archimedean spirals are not equal and the superlattice periodic structure is satisfied; Figure 4 A schematic diagram of the structure of the on-chip delay line module in two embodiments of an on-chip integrated architecture provided by the present invention; Figure 5 for Figure 4 The diagram shows a cross-sectional view of the on-chip delay line module along line A-A'. Figure 6 A schematic diagram of the structure of the on-chip delay line module in three embodiments of an on-chip integrated architecture provided by the present invention; Figure 7 This invention provides a schematic diagram illustrating the mode conversion of a multi-level mode multiplexing module and a multi-level mode demultiplexing module in an on-chip integrated architecture. Figure 7 (a) is a schematic diagram of optical signal mode conversion in the first-level mode multiplexing module. Figure 7 (b) is a schematic diagram of the optical signal mode conversion of the nth level mode multiplexing module. Figure 7 (c) is a schematic diagram of optical signal mode conversion in the first-level mode demultiplexing module. Figure 7 (d) is a schematic diagram of optical signal mode conversion for the nth-level mode demultiplexing module; Figure 8 A schematic diagram of the adjustable beam splitter structure in the on-chip integrated architecture provided by the present invention; Figure 9 This is a schematic diagram of the heating electrode and waveguide of the adjustable beam splitter structure in the on-chip integrated architecture provided by the present invention. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the drawings and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0021] In the description of this invention, "multiple" refers to two or more. The use of "first" and "second" is for distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features or their sequential relationship.

[0022] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0023] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are some embodiments of the present invention, not all embodiments.

[0024] LiDAR (Light Detection and Ranging) is an active optical system that detects the position and velocity of a target by emitting a laser beam. In recent years, with the rapid development of autonomous driving and robotics technologies, frequency-modulated continuous wave (FMCW) LiDAR, which can directly acquire velocity point cloud information, has become a research hotspot. This technology utilizes linearly frequency-modulated continuous lasers to simultaneously calculate distance and Doppler velocity through the beat frequency of the echo and local oscillator light. It offers advantages such as anti-interference capabilities, high ranging and velocity measurement accuracy, and eye safety, and is widely regarded as an important technological path for next-generation automotive LiDAR.

[0025] However, traditional single-laser FMCW radar requires decoupling range and velocity information in two chirped time periods, limiting point cloud density and real-time performance, making it difficult to meet the needs of high-resolution or high-speed target scenarios. In high-speed moving target measurement, Doppler beat frequency is prone to aliasing with range beat frequency, increasing range-velocity decoupling error and reducing measurement accuracy. In addition, single-laser scanning cycles are long and have poor real-time performance, making it impossible to achieve high frame rate point cloud output. To address this, a dual-laser, opposite-slope, dual-chirped system has emerged, which uses two lasers simultaneously to generate chirped signals with opposite or different frequency modulation slopes, achieving range-velocity decoupling within a single time window and significantly improving point cloud density. However, this system requires extremely high linearity of laser frequency modulation. Actual lasers exhibit significant nonlinearity due to thermal effects, carrier dynamics, and other factors. Without precise calibration, this will lead to severe distortion of the beat frequency signal and a significant decrease in ranging and velocity measurement accuracy.

[0026] Currently, mainstream nonlinear calibration methods include open-loop predistortion compensation, equal-frequency resampling, and opto-phase-locked loop (PLL) technology. Open-loop schemes rely on external long fiber delay lines, resulting in large size, high cost, environmental sensitivity, easy delay time drift, and difficulty in integration. While equal-frequency resampling can compensate for nonlinearity, it suffers from poor real-time performance and limited effectiveness for complex nonlinearities. Opto-phase-locked loops offer high accuracy but are hardware-complex and lack adaptability to high-speed frequency sweeps. Current iterative pre-calibration methods, while promising, are limited by the short length of on-chip delay lines (only nanoseconds), failing to meet the requirements of dual-chirped calibration. Current iterative pre-calibration methods primarily rely on external fiber or on-chip delay lines for nonlinear error feedback; however, existing on-chip delay lines are limited by high waveguide loss, large bending radii, and severe crosstalk, resulting in low delay density. On a limited chip area, the effective delay length is typically only in the range of a few to tens of nanoseconds, which cannot meet the delay requirements of dual-chirped nonlinear calibration.

[0027] To address the aforementioned issues, this invention proposes an on-chip integrated architecture and a dual-laser lidar calibration device, which effectively solves the problems of existing lidar systems being bulky, environmentally sensitive, having poor stability, being difficult to integrate, and unable to achieve efficient and stable microsecond-level long-delay calibration.

[0028] refer to Figures 1 to 8 As shown, the present invention provides an on-chip integrated architecture and a dual-laser lidar calibration device, which are implemented in the following embodiments: Reference Figure 1 As shown, the dual-laser lidar calibration device includes: an on-chip integrated architecture, a laser source module, a transimpedance amplifier conversion module, a data acquisition module, and a data processing and control module. The on-chip integrated architecture includes: a coupler module, a first beam splitter module, a first mixer module, a first balanced detector module, a second beam splitter module, a second mixer module, a second balanced detector module, and an on-chip delay line module.

[0029] The laser source module includes a first laser and a second laser, which are used to output a first chirped light signal and a second chirped light signal, respectively. The first chirped light signal and the second chirped light signal are two optical signals with different slopes and wavelengths. The first chirped light signal and the second chirped light signal enter the on-chip integrated architecture through a coupler module. In this embodiment, the structure of the coupler module is not limited. The coupler module can adopt an edge coupler or a grating coupler structure. It is only necessary to realize the simultaneous coupling of two different optical signals into the same on-chip integrated architecture.

[0030] After entering the on-chip integrated architecture, the first chirped optical signal and the second chirped optical signal enter the first beam splitter module and the second beam splitter module, respectively.

[0031] The first chirped optical signal is split into two paths by the first beam splitter module. One part of the first chirped optical signal enters the on-chip delay line module to generate a time delay, while the other part of the first chirped optical signal directly enters the first mixer module as the local oscillator light. The local oscillator light is a reference beam from the same source as the emitted light source and can be used as a scale to detect distortion of the emitted signal. The part of the local oscillator light is optically mixed with the part of the first chirped optical signal after the time delay to obtain the first beat frequency signal. The first beat frequency signal outputs an electrical signal through the first balanced detector module. The first beat frequency signal enters the first balanced detector module and obtains the output electrical signal through photoelectric detection.

[0032] Similarly, the second chirped optical signal is split into two paths by the second beam splitter module. One part of the second chirped optical signal enters the on-chip delay line module to generate a time delay, while the other part of the second chirped optical signal directly enters the second mixer module and is optically mixed with the time-delayed part of the second chirped optical signal to obtain the second beat frequency signal. The second beat frequency signal enters the second balanced detector module, and the output electrical signal is obtained through photoelectric detection.

[0033] The transimpedance amplifier conversion module amplifies and converts the electrical signal output from the on-chip integrated architecture. The data acquisition module samples the amplified and converted electrical signal. The sampled data is then transmitted to the data processing and control module for subsequent digital signal processing, algorithm calculations, and system control. The data processing and control module can be implemented using a general-purpose computer, embedded processor (such as a microcontroller or FPGA), or other dedicated computing devices to ensure efficient nonlinear calibration and real-time response.

[0034] Furthermore, for on-chip delay line modules with on-chip integrated architecture, refer to Figure 1As shown in one embodiment, the on-chip delay line module includes two on-chip delay line modules. A portion of the split first chirped optical signal and a portion of the split second chirped optical signal are time-delayed by the two on-chip delay line modules, respectively.

[0035] Furthermore, for Figure 1 The illustrated embodiment has been optimized, with reference to Figure 2 As shown, according to some embodiments of the present invention, the on-chip delay line module includes a dual-wavelength beam combining module, an on-chip delay line module, and a dual-wavelength beam splitting module. A portion of the first chirped optical signal and a portion of the second chirped optical signal after beam splitting are combined by the dual-wavelength beam combining module and then enter the on-chip delay line module to generate a time delay. The delayed first chirped optical signal and the second chirped optical signal are then split into different optical paths by the dual-wavelength beam splitting module and then enter the first mixer module and the second mixer module, respectively. By introducing the dual-wavelength beam combining module and the dual-wavelength beam splitting module, the delay processing of dual-wavelength signals can be realized through an on-chip delay line module, which greatly reduces the chip area, reduces manufacturing costs, and ensures the miniaturization, low power consumption, and high stability of the system.

[0036] According to some embodiments of the present invention, with reference to Figure 3 As shown, the on-chip delay line module includes an on-chip delay line module, which in turn includes on-chip delay line units. These on-chip delay line units are key chip units affecting the nonlinear calibration performance of lidar. To obtain sufficient time delay to improve calibration results, delay lines typically need to have a relatively long optical path length. However, increasing the delay line length significantly increases the chip area footprint and imposes stringent requirements on waveguide loss.

[0037] In this embodiment, the on-chip delay line unit is a spiral structure, including an Euler spiral and two Archimedean spirals that are smoothly connected to both ends of the Euler spiral. By smoothly connecting the Euler spiral and the two Archimedean spirals, abrupt changes are eliminated, scattering and mode mismatch are suppressed when the light turns. At the same time, by replacing right-angle bends with smooth connections, the waveguide can be bent with low loss by a large margin.

[0038] In this embodiment, the curvature of the Euler spiral changes linearly and forms a smoothly connected S-shape. In other embodiments, the S-shape of the Euler spiral can also be formed by other forms, such as a Bessel function or an S-bend formed by splicing ordinary semicircles. The waveguide width of the Euler spiral gradually decreases from both ends towards the center and contracts to the minimum width W at the center. min Furthermore, the minimum width W of the Euler spiral at its center position min The value is set to the single-mode waveguide width, thereby further suppressing the excitation of higher-order modes and reducing insertion loss, thus achieving more stable single-mode or weak multimode transmission.

[0039] For an Archimedean spiral, the spacing between adjacent turns of the Archimedean spiral is equal. The Archimedean spiral coils around an Euler spiral and the bending radius increases linearly with the angle. By designing the bending radius variation of the Archimedean spiral, effective mode mismatch will occur between adjacent waveguides (adjacent turns of the Archimedean spiral) due to differences in bending radius and waveguide width, thereby significantly reducing inter-waveguide crosstalk.

[0040] Furthermore, the widths of the two Archimedean spirals are W1 and W2, respectively, referring to... Figure 3 (a) is the case when W1 and W2 are equal. In this case, the transmission loss of the waveguide mainly comes from the sidewall scattering caused by the roughness of the sidewall caused by etching. A wider waveguide can reduce the electric field intensity in the sidewall region, thereby reducing the scattering loss. However, it will also reduce the delay density achievable per unit area. Therefore, a trade-off must be made between loss and area.

[0041] According to some embodiments of the present invention, with reference to Figure 3 (b) Set the values ​​of W1 and W2 to be unequal, and make the values ​​of W1 and W2 satisfy the superlattice periodic structure. A superlattice is an artificially designed planar optical waveguide array structure. Its core feature is that it forms a "supercell" with phase mismatch characteristics by alternating waveguides with different widths (such as W1 and W2). In this way, the difference in effective refractive index is used to effectively suppress signal crosstalk between adjacent waveguides and achieve high-density optical path arrangement. In this invention, the values ​​of W1 and W2 are designed to satisfy the superlattice periodic structure. In this way, the mismatch between effective refractive index and mode field distribution caused by the periodic difference in waveguide width is used to further enhance the mode mismatch between adjacent waveguides, so as to significantly reduce crosstalk between waveguides, make the delay line more compact, further suppress crosstalk, and reduce the waveguide gap, thereby achieving a more compact delay line structure.

[0042] Furthermore, referring to Figure 4 and Figure 5 As shown, according to some embodiments of the present invention, two on-chip delay line units are provided, and the two on-chip delay line units form a double-layer waveguide along the top and bottom, adopting a heterogeneous integrated structure. The delay density is improved by the double-layer waveguide architecture, and each layer of the double-layer waveguide can be used. Figure 3 (a) or Figure 3 The structure shown in (b) serves as an on-chip delay line unit. The axes of the two on-chip delay line units overlap, and the Archimedean spirals of the two on-chip delay line units are arranged alternately in the radial direction to improve the delay density. A greater delay density can be achieved on the same chip area.

[0043] Reference Figure 6As shown, according to some embodiments of the present invention, the on-chip delay line module further includes a multi-level mode multiplexing module and a multi-level mode demultiplexing module. In some embodiments of the present invention, the mode multiplexing module and the mode demultiplexing module adopt an asymmetric directional coupler. In other embodiments, the mode multiplexing module and the mode demultiplexing module may adopt other structures to realize the mode change of the optical signal, such as a directional coupler.

[0044] The multi-level mode multiplexing module includes mode multiplexing module 1, ..., mode multiplexing module N. Mode multiplexing module 1, ..., mode multiplexing module N are cascaded in sequence at the input end of the on-chip delay line module. The optical signal is transmitted from mode multiplexing module 1 to mode multiplexing module N and then enters the on-chip delay line module. The multi-level mode demultiplexing module includes mode demultiplexing module N, ..., mode demultiplexing module 1. Mode demultiplexing module N, ..., mode demultiplexing module 1 are cascaded in sequence at the output end of the on-chip delay line module. The delayed optical signal is fed back from each level of mode demultiplexing module to the mode multiplexing module, thereby enabling the optical signal to be transmitted multiple times in different modes within the same delay line, thus significantly improving the effective delay of a single-segment delay line structure.

[0045] Reference Figure 7 For the mode conversion logic of the multi-level mode multiplexing module and the multi-level mode demultiplexing module, when the optical signal is input from port 1 to output from port 2, the optical signal mode does not change. When it is input from port 3 to output from port 2, the optical signal is converted from a low-order mode to a high-order mode. When it is input from port 1 to output from port 4, the optical signal is converted from a high-order mode to a low-order mode.

[0046] The workflow of the input signal entering the multimode multiplexing delay line module in TE0 mode is as follows: Input TE0 enters from port 1 of mode multiplexing module 1 and is output from port 2. Then, it passes through mode multiplexing module 2, mode multiplexing module 3, ..., mode multiplexing module n in the same manner. Each stage enters from port 1 and is output from port 2, and no mode conversion occurs during this transmission process.

[0047] After multiplexing, the signal enters the on-chip delay line module in TE0 mode and completes one delay transmission. The delay output is connected to the link formed by the multi-level mode demultiplexing module. The TE0 signal passes sequentially through mode demultiplexing module n, mode demultiplexing module (n) 1) ... Mode demultiplexing module 1, each stage enters from port 1 and outputs from port 2, and no mode conversion occurs during the transmission process.

[0048] When the optical signal reaches the output of port 2 of mode demultiplexing module 1, TE0 is output to port 3 of mode demultiplexing module 1, completing the first cyclic multiplexing transmission of the optical signal. Mode conversion occurs within mode demultiplexing module 1 and is output as TE1 mode from port 2.

[0049] The TE1 signal output from mode multiplexing module 1 then enters port 1 of mode multiplexing module 2 and is output from port 2. Following the same rules, it sequentially passes through mode multiplexing module 3, ..., mode multiplexing module n, with each stage entering from port 1 and exiting from port 2. No mode conversion occurs during this transmission process. It then enters the multimode delay line module to complete the second delayed transmission. After the delay, it sequentially passes through mode demultiplexing module n, mode demultiplexing module (n... 1) ... The mode demultiplexing module 2 returns to the mode demultiplexing module 1. The TE1 input at port 1 of the mode demultiplexing module 1 is converted into TE0 and output from port 4. The output TE0 then enters port 3 of the mode demultiplexing module 2, is converted into TE2 within the module, and is output from port 2, completing the second cycle of optical signal multiplexing transmission. Then, it enters the delay line through the subsequent mode multiplexing modules for the next delay.

[0050] The module can continue to generate multiplexing-delay-demultiplexing loops of higher-order modes such as TE3, TE4, etc. In each round, demultiplexing and multiplexing between modes are completed at the corresponding mode demultiplexing module and mode multiplexing module. Finally, the signals delayed in each round are output from the designated port in a predetermined order. Thus, multiple transmissions and multiple delays are achieved in a single delay line structure through mode multiplexing and demultiplexing, which significantly improves the effective delay of a single delay line while maintaining the isolation and low loss characteristics between modes.

[0051] And so on, TE n Starting from mode multiplexing module n, the data sequentially passes through each of the aforementioned mode multiplexing modules, enters the on-chip delay line unit for the (n+1)th delayed transmission, and is converted into TE0 output in mode demultiplexing module n. TE0 is then fed back to mode multiplexing module (n+1) for conversion into TE. （n+1） The (n+1)th cyclic multiplexing transmission is completed; where 2≤n≤(N-1), and N is the number of levels of the mode multiplexing module; after completing the aforementioned N cyclic multiplexing transmissions, the final TE is... N Starting from the mode multiplexing module N, the system enters the on-chip delay line unit to perform the (N+1)th delay transmission, and is converted to TE0 output in the mode demultiplexing module N. This TE0 no longer provides feedback, thus completing all delays and leaving the on-chip delay line module.

[0052] According to some embodiments of the present invention, such as Figure 8As shown, the first and second beam splitter modules adopt an adjustable beam splitter structure. The adjustable beam splitter structure consists of a first beam splitter, two thermally tuned phase shifters, and a 2×2 coupler cascaded together. The optical signal entering the adjustable beam splitter structure is split into two paths proportionally by the first beam splitter. The first beam splitter is preferably a polarization-independent 50:50 beam splitter. The first beam splitter can be implemented using an MMI, a directional coupler, or a thermally adiabatic coupler.

[0053] The two optical signals after splitting are input to two thermally tuned phase shifters. The two thermally tuned phase shifters introduce different phase differences into the two optical signals. The two optical signals with introduced phase differences enter a 2×2 coupler. According to the principle of Mach-Zehnder interferometer, by adjusting the relative phase between the two arms, the splitting ratio can be continuously adjusted within the range of 0% to 100% between the two output ports. This allows for flexible optimization of the intensity ratio of the local oscillator light and the delayed light signal, significantly improving the signal-to-noise ratio of the beat frequency signal and the final nonlinear calibration performance.

[0054] By designing an adjustable beam splitter architecture, compared to traditional fixed-ratio beam splitters, the intensity distribution of the local oscillator beam and the delayed beam can be precisely controlled to obtain the optimal splitting ratio. Thus, the intensity ratio between the local oscillator beam and the delayed beam affects the final nonlinear calibration result, thereby achieving the maximum calibration effect.

[0055] Furthermore, the structure of the thermally tuned phase shifter is as follows: Figure 9 As shown, the thermally tuned phase shifter has two arms, with a first heating section and a second heating section respectively on the two arms: the waveguide length of the first heating section is L1 and the width is W8, and the width of the heating electrode covering it is W10; the waveguide length of the second heating section is L2 and the waveguide width is W9, and the width of the heating electrode covering it is W11.

[0056] The heating electrodes of the first and second heating sections are independently connected to an external driving circuit, changing the effective refractive index of the waveguide to achieve phase modulation. To reduce transmission loss, the waveguide preferably adopts a multimode or weakly confined single-mode waveguide structure; to simplify the process and improve thermal modulation efficiency, W8 = W9, W10 = W11, and L1 = L2 can be set, where W10 and W11 are taken as the minimum feature size allowed by the process. By reasonably designing the specific values ​​of L1, L2, W8, and W9, the two arms can obtain the required precise phase difference under the same driving voltage, achieving high-precision and high-stability splitting ratio adjustment.

[0057] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0059] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An on-chip integrated architecture, characterized in that, Nonlinear calibration applicable to dual-laser, anomalous-slope, dual-chirped lidar includes: a coupler module, a first beam splitter module, a first mixer module, a first balanced detector module, a second beam splitter module, a second mixer module, a second balanced detector module, and an on-chip delay line module, wherein the on-chip delay line module includes at least one on-chip delay line module. The dual-laser asymmetrical slope dual-chirped lidar generates different first chirped light signals and second chirped light signals, which are coupled into the on-chip integrated architecture through the coupler module. The first chirped optical signal is split into two paths by the first beam splitter module. One part of the first chirped optical signal enters the on-chip delay line module to generate a time delay, and the other part of the first chirped optical signal directly enters the first mixer module and is optically mixed with the time-delayed part of the first chirped optical signal to obtain the first beat frequency signal. The first beat frequency signal outputs an electrical signal through the first balanced detector module. The second chirped optical signal is split into two paths by the second beam splitter module. One part of the second chirped optical signal enters the on-chip delay line module to generate a time delay, and the other part of the second chirped optical signal directly enters the second mixer module and is optically mixed with the time-delayed part of the second chirped optical signal to obtain a second beat frequency signal. The second beat frequency signal outputs an electrical signal through the second balanced detector module.

2. The on-chip integrated architecture according to claim 1, characterized in that: The on-chip delay line module includes two on-chip delay line modules. A portion of the first chirped optical signal and a portion of the second chirped optical signal after splitting are respectively time-delayed by the two on-chip delay line modules.

3. The on-chip integrated architecture according to claim 1, characterized in that: The on-chip delay line module includes a dual-wavelength beam combining module, an on-chip delay line module, and a dual-wavelength beam splitting module. A portion of the first chirped optical signal and a portion of the second chirped optical signal after beam splitting are combined by the dual-wavelength beam combining module and then enter the on-chip delay line module to generate a time delay. The delayed first chirped optical signal and the second chirped optical signal are then split into different optical paths by the dual-wavelength beam splitting module and then enter the first mixer module and the second mixer module respectively.

4. The on-chip integrated architecture according to claim 1, characterized in that: The on-chip delay line module includes at least one on-chip delay line unit. The on-chip delay line unit has a spiral structure, including an Euler spiral and two Archimedean spirals that are smoothly connected to both ends of the Euler spiral. The curvature of the Euler spiral changes linearly and is in a smoothly connected S-shape. The two Archimedean spirals alternately coil around the Euler spiral and the bending radius increases linearly with the angle.

5. The on-chip integrated architecture according to claim 4, characterized in that: The waveguide width of the Euler spiral gradually decreases from both ends toward the center, and the minimum width of the Euler spiral at the center is the single-mode waveguide width.

6. The on-chip integrated architecture according to claim 4, characterized in that: The widths of the two Archimedean spirals are W1 and W2, respectively. The values ​​of W1 and W2 are not equal, and the values ​​of W1 and W2 satisfy the superlattice periodic structure.

7. The on-chip integrated architecture according to claim 4, characterized in that: The on-chip delay line module includes two on-chip delay line units, which form a double-layer waveguide along the top and bottom. The central axes of the two on-chip delay line units overlap, and the Archimedean spirals of the two on-chip delay line units are arranged alternately in the radial direction.

8. The on-chip integrated architecture according to claim 1, characterized in that: The on-chip delay line module further includes a multi-level mode multiplexing module and a multi-level mode demultiplexing module. The multi-level mode multiplexing module includes mode multiplexing module 1, ..., mode multiplexing module N, and the multi-level mode multiplexing modules are cascaded at the input end of the on-chip delay line module. The multi-level mode demultiplexing module includes mode demultiplexing module N, ..., mode demultiplexing module 1, and the multi-level mode demultiplexing modules are cascaded at the output end of the on-chip delay line module. The optical signal entering the on-chip delay line module is input from the mode multiplexing module 1 in TE0 mode, and then passes through the mode multiplexing modules at each level in sequence. It enters the on-chip delay line unit in TE0 for the first delay transmission. After the first delay transmission, TE0 passes through the mode demultiplexing modules at each level and is output from the mode demultiplexing module 1. TE0 is fed back to the mode multiplexing module 1 and converted into TE1 output, completing the first cyclic multiplexing transmission. TE1 starts from mode multiplexing module 1 and passes through each level of mode multiplexing module in sequence. It enters the on-chip delay line unit in TE1 mode for the second delay transmission. After the second delay transmission, TE1 passes through each level of mode demultiplexing module and is then input into mode demultiplexing module 1 and converted into TE0 output. TE0 is fed back to mode multiplexing module 2 and converted into TE2, completing the second cyclic multiplexing transmission. And so on, TE n Starting from mode multiplexing module n, the data sequentially passes through each of the aforementioned mode multiplexing modules, enters the on-chip delay line unit for the (n+1)th delayed transmission, and is converted into TE0 output in mode demultiplexing module n. TE0 is then fed back to mode multiplexing module (n+1) for conversion into TE. （n+1） This completes the (n+1)th cyclic multiplexing transmission; where 2≤n≤(N-1), and N is the number of levels of the mode multiplexing module; After completing the aforementioned N cyclic multiplexing transmissions, the final TE N Starting from the mode multiplexing module N, the system enters the on-chip delay line unit to perform the (N+1)th delay transmission, and is converted to TE0 output in the mode demultiplexing module N. This TE0 no longer provides feedback, thus completing all delays and leaving the on-chip delay line module.

9. The on-chip integrated architecture according to claim 1, characterized in that: The first and second beam splitter modules adopt an adjustable beam splitter structure, which consists of a first beam splitter, two thermally tuned phase shifters, and a 2×2 coupler cascaded together. The optical signal entering the adjustable beam splitter structure is split into two paths proportionally by the first beam splitter and then input to the two thermally tuned phase shifters respectively. The two thermally tuned phase shifters introduce different phase differences into the two optical signals respectively. The two optical signals with introduced phase differences enter the 2×2 coupler to achieve arbitrary beam splitting ratio output.

10. A calibration device for a dual-laser, heteroslope, dual-chirped lidar, characterized in that, include: The on-chip integrated architecture, laser source module, transimpedance amplifier conversion module, data acquisition module, data processing and control module, and signal generation module as described in any one of claims 1 to 9; The laser source module includes a first laser and a second laser, which are used to output a first chirped light signal and a second chirped light signal, respectively. The on-chip integrated architecture converts the optical signal generated by the laser source module into an electrical signal; The transimpedance amplifier conversion module performs transimpedance amplification and voltage conversion on the electrical signal; The data acquisition module is used to sample the amplified electrical signal; The data processing and control module is used to perform digital signal processing, algorithm calculations, and system control on the sampled data. The signal generation module is used to provide signal feedback to the laser source module based on the processed data.

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