A data transmission circuit, method and device of a cross-power-domain asynchronous FIFO

Abstract

The embodiment of the present application provides a data transmission circuit, method and device of a cross power domain asynchronous FIFO, and relates to the technical field of integrated circuits. The FIFO memory of the circuit is used for storing write data from a write clock domain; the read control logic module is used for generating a read pointer; the low-power unit group comprises W first low-power units and X second low-power units; and the read pointer is transmitted to a data selector; the data selector is connected to a data output end of the FIFO memory and an output end of the second low-power unit and is used for selecting write data to be transmitted corresponding to the read pointer from the FIFO memory; the first low-power unit is used for performing cross power domain signal processing on W bits of write data to be transmitted output by the data selector to obtain target write data; and a synchronizer is connected to the output end of the first low-power unit and is used for synchronizing the target write data to a read clock domain. The present application improves the operation performance of a chip.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of integrated circuit technology, and more specifically, the embodiments of the present invention relate to a data transmission circuit, method and apparatus for an asynchronous FIFO across power domains. Background Technology

[0002] With the continuous development of integrated circuit technology, more and more functional modules are integrated on chips, and different modules often operate in different voltage and clock domains. To reduce overall power consumption, chip design divides different functional modules into different power domains, and the supply voltage or switching state of each power domain can be configured independently. When data needs to be transferred between different power domains, asynchronous first-in-first-out (FIFO) memory is usually used as a buffer unit for cross-domain data transfer.

[0003] In asynchronous FIFO designs that span power domains, the write clock domain and the read clock domain belong to different power domains, with different voltage levels or on / off states. Data is written to the FIFO memory from the write clock domain and read from the FIFO memory from the read clock domain; the entire data transmission process needs to cross power domain boundaries. To ensure correct signal transmission between different voltage domains, low-power cells, such as level shifter cells, isolation cells, or enablelevel shifter cells with isolation functions, need to be inserted at the power domain boundaries to achieve voltage level conversion or signal isolation.

[0004] In existing technologies, low-power cells are typically located between the data output terminal and the data receiving terminal of the read clock domain in a FIFO memory. However, the area of ​​a low-power cell is usually much larger than that of a standard cell. When the FIFO depth and data bit width are large, a large number of low-power cells are concentrated at the power domain boundary, which not only occupies a considerable chip area but also easily causes timing violations or wiring congestion problems in the back-end physical implementation, resulting in poor chip performance. Summary of the Invention

[0005] In this context, embodiments of the present invention aim to provide a data transmission circuit, method, and apparatus for an asynchronous FIFO across power domains.

[0006] In a first aspect of the present invention, a data transmission circuit for an asynchronous FIFO across power domains is provided. The circuit includes a FIFO memory, a read control logic module, a data selector, a low-power unit group, and a synchronizer, wherein: The FIFO memory is used to store write data from the write clock domain; The read control logic module is used to generate a read pointer and transmit the read pointer to the low-power unit group; The low-power unit group comprises W first low-power units and X second low-power units; wherein, the second low-power units store the read pointer and transmit the read pointer to the data selector; W is the data bit width of the FIFO memory; X is the read pointer encoding bit width; The data selector is connected to the data output terminal of the FIFO memory and the output terminal of the second low-power unit, and is used to select the write data to be transferred corresponding to the read pointer from the FIFO memory; The first low-power unit is connected to the data output terminal of the data selector and is used to perform cross-power domain signal processing on the W bits of the write data to be transmitted output by the data selector to obtain the target write data. The synchronizer is connected to the output of the first low-power unit and is used to synchronize the target write data to the read clock domain.

[0007] In one embodiment of this implementation, the FIFO memory has a depth of N and is used to cache N sets of write data; each set of write data contains W bits.

[0008] In one embodiment of this implementation, the calculation method for the read pointer encoding bit width is as follows: ; in, X represents the integer part of the read pointer encoding, and N represents the depth of the FIFO memory.

[0009] In one embodiment of this implementation, the first low-power unit or the second low-power unit is any one of a level conversion unit, a power isolation unit, or a level conversion unit with isolation function; The first low-power unit or the second low-power unit is used to realize the signal level conversion between different voltage domains between the write clock domain and the read clock domain; The first low-power unit is used to isolate the signal output from the write clock domain when the read clock domain is powered down.

[0010] In one embodiment of this implementation, the synchronizer simultaneously receives the target write data converted by the first low-power unit and the read pointer converted by the second low-power unit; and performs synchronization processing on the asynchronous signal from the write clock domain to eliminate cross-clock domain metastability.

[0011] In one embodiment of this implementation, the layout coordinates of all first low-power units and second low-power units, as well as the signal trace channel occupancy data, are also collected. By statistically analyzing the degree of wiring congestion in the power domain boundary area and the transmission timing delay of the output signals of each low-power unit; Based on the degree of cable congestion and the value of transmission timing delay, a unit layout adjustment instruction is generated; The layout positions of the first low-power unit and the second low-power unit are rearranged according to the layout adjustment instruction.

[0012] In one embodiment of this implementation, the number of valid data stores inside the FIFO memory and the update rate of the read pointer output by the read control logic module are read. The current data transmission load level of the circuit is determined by combining the effective data storage quantity and the read pointer update rate, thus distinguishing between idle transmission state and full-load transmission state. If the data transmission circuit is in an idle transmission state, it sends a power cut-off command to the first low-power unit and the second low-power unit that are not participating in the current data transmission. When the data transmission circuit switches to full-load transmission state, the power supply paths of all first low-power units and second low-power units are restored.

[0013] In one embodiment of this implementation, the storage depth and data bit width parameters of the FIFO memory are read in advance; based on the read storage depth and data bit width parameters, the number of first low-power units and second low-power units required to be enabled for the current circuit operation are determined, so as to generate corresponding path selection control signals and transmit them to the low-power unit group. After receiving the path selection control signal, the low-power unit group closes the low-power unit signal transmission path that exceeds the current configuration requirements.

[0014] In a second aspect of the present invention, a data transmission method for an asynchronous FIFO across power domains is provided, applied to the data transmission circuit described in any one of the first aspects, the method comprising: Write data from the write clock domain is stored in the FIFO memory; A read pointer is generated by the read control logic module and transmitted to the second low-power unit of the low-power unit group; wherein the number of the second low-power units is the same as the bit width of the read pointer encoding. The read pointer is transmitted to the data selector via the second low-power unit; The data selector reads the write data to be transferred from the FIFO memory, corresponding to the read pointer; The target write data is obtained by performing cross-power domain signal processing on the write data to be transmitted through the first low-power unit; wherein, the number of the first low-power units is the same as the bit width of the write data to be transmitted. The target write data is synchronized to the read clock domain using a synchronizer.

[0015] In a third aspect of the present invention, a data transmission apparatus for an asynchronous FIFO across power domains is provided, applied to the data transmission method for an asynchronous FIFO across power domains in the second aspect. The apparatus includes: A storage unit is used to store write data from the write clock domain into a FIFO memory; The first transmission unit is used to generate a read pointer through the read control logic module and transmit the read pointer to the second low-power unit of the low-power unit group; wherein the number of the second low-power units is the same as the bit width of the read pointer encoding. The second transmission unit is used to transmit the read pointer to the data selector through the second low-power unit; A read unit is used to read the write data to be transferred corresponding to the read pointer from the FIFO memory through the data selector; The processing unit is configured to perform cross-power domain signal processing on the write data to be transmitted through the first low-power unit to obtain the target write data; wherein the number of the first low-power units is the same as the bit width of the write data to be transmitted. The synchronization unit is used to synchronize the target write data to the read clock domain via a synchronizer.

[0016] According to embodiments of the present invention, a data transmission circuit, method, and apparatus for an asynchronous FIFO across power domains are provided. By placing the low-power cells after all data outputs of the FIFO memory and after the data selector, a first low-power cell is set only on the W-bit valid data path of the data selection output, and a second low-power cell is set on the read pointer transmission path. This ensures that cross-power domain signal processing only applies to the actually read data and the read pointer, rather than storing the entire amount of data. This scheme significantly reduces the number of low-power cells used, effectively reducing the cell density at the power domain boundary and avoiding wiring loops and timing violations caused by congestion of a large number of low-power cells, thereby significantly improving the roamability and timing convergence of the chip's back-end physical implementation. Simultaneously, the reduction in the number of low-power cells directly reduces the signal transmission delay of the data path, shortens the data synchronization path between read and write clock domains, and improves the overall operating frequency and data throughput of the chip. The reduction in the area of ​​the low-power cells also frees up valuable chip wiring resources, reduces the risk of local voltage drops in the power grid, and improves the signal integrity and power integrity of the chip under high-frequency operating conditions, comprehensively improving the chip's operating performance and design robustness. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein: Figure 1 This is a schematic diagram of the data transmission circuit of an asynchronous FIFO across power domains provided in an embodiment of the present invention; Figure 2 This is a schematic flowchart of a cross-power domain asynchronous FIFO data transmission circuit method provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a data transmission circuit device for an asynchronous FIFO across power domains provided in an embodiment of the present invention. Detailed Implementation

[0018] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are given merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0019] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0020] According to an embodiment of the present invention, a data transmission circuit, method and apparatus for an asynchronous FIFO across power domains are proposed.

[0021] It should be noted that the number of any elements in the accompanying drawings is for illustrative purposes only and not as a limitation, and any naming is for distinction only and has no limiting meaning.

[0022] The principles and spirit of the present invention will be explained in detail below with reference to several representative embodiments.

[0023] The following is for reference. Figure 1 , Figure 1 This is a schematic diagram of the data transmission circuit of an asynchronous FIFO across power domains provided in an embodiment of the present invention.

[0024] Figure 1The data transmission circuit of the cross-power domain asynchronous FIFO shown includes a FIFO memory, a read control logic module, a data selector, a low-power cell group, and a synchronizer, wherein: The FIFO memory is used to store write data from the write clock domain; The read control logic module is used to generate a read pointer and transmit the read pointer to the low-power unit group; The low-power unit group comprises W first low-power units and X second low-power units; wherein, the second low-power units store the read pointer and transmit the read pointer to the data selector; W is the data bit width of the FIFO memory; X is the read pointer encoding bit width; The data selector is connected to the data output terminal of the FIFO memory and the output terminal of the second low-power unit, and is used to select the write data to be transferred corresponding to the read pointer from the FIFO memory; The first low-power unit is connected to the data output terminal of the data selector and is used to perform cross-power domain signal processing on the W bits of the write data to be transmitted output by the data selector to obtain the target write data. The synchronizer is connected to the output of the first low-power unit and is used to synchronize the target write data to the read clock domain.

[0025] from Figure 1 As can be seen, the FIFO memory has a depth of N and a data bit width of W, and is used to buffer N sets of write data from the write clock domain. Each set of write data contains W bits. Each storage cell of the FIFO memory is connected to the data input terminal of the data selector through the corresponding data output terminal. That is, the N channels of W-bit wide write data to be transmitted corresponding to address[0] to address[N-1] in the figure are all sent to the data selector.

[0026] The read control logic module generates a read pointer (read_pointer), which is a binary encoded signal with a bit width of X. The read pointer (read_pointer) undergoes cross-power domain signal processing (i.e., level conversion or isolation) via the Xth second low-power unit LP in the low-power unit group, and is then transmitted to the selection control terminal s of the data selector as the selection address of the data selector.

[0027] The data selector selects one path of write data corresponding to the read pointer from the N paths of W-bit wide data output from the FIFO memory based on the received read pointer and outputs it. The W-bit write data output by the data selector is then sent to the W first low-power units LP in the low-power unit group. The first low-power units perform cross-power domain signal processing on the W-bit data, completing the voltage level conversion or isolation protection between the write clock domain and the read clock domain, and output the converted target write data.

[0028] The target write data, converted by the first low-power unit, and the read pointer, converted by the second low-power unit, are input to the synchronizer. The synchronizer internally has a SYNC DFF (synchronous D flip-flop) to synchronize asynchronous signals from the write clock domain, eliminate metastability that may occur during cross-clock domain transmission, and finally output stable and reliable target write data synchronously to the read clock domain for use by the internal logic of the read clock domain.

[0029] With the above circuit structure, the low-power unit group (including the first low-power unit and the second low-power unit) is centrally arranged after the data selector and before the synchronizer. Only W first low-power units are needed for the data path and X second low-power units are needed for the read pointer path. The total number of low-power units is greatly reduced from N×W in the prior art to W+X, which significantly optimizes the layout area and power consumption performance of the cross-power domain asynchronous FIFO, while improving the wiring congestion and timing convergence problems at the power domain boundary.

[0030] In this embodiment, the FIFO memory has a depth of N and is used to cache N sets of write data; each set of write data contains W bits. By configuring the depth of the FIFO memory to N, the write clock domain can cache N complete sets of write data, effectively absorbing the rate difference and burst data volume between the write clock domain and the read clock domain, and avoiding data overflow or loss. Each set of write data contains W bits, ensuring the integrity and consistency of the data width, enabling the data selector to select precisely according to the bit width. This structure, while implementing the cross-clock domain data transmission buffer function, achieves an optimized balance between data cache capacity and the number of low-power units in conjunction with the subsequent layout of low-power units after the selector. This ensures both the reliability and continuity of data transmission and provides a structural basis for optimizing the overall power consumption and area of ​​the chip.

[0031] In this embodiment of the application, the calculation method for the read pointer encoding bit width is as follows: ; in, X represents the integer part of the read pointer encoding, and N represents the depth of the FIFO memory.

[0032] In this embodiment of the application, the first low-power unit or the second low-power unit is any one of a level conversion unit, a power isolation unit, or a level conversion unit with isolation function; The first low-power unit or the second low-power unit is used to realize the signal level conversion between different voltage domains between the write clock domain and the read clock domain; The first low-power unit is used to isolate the signal output from the write clock domain when the read clock domain is powered down.

[0033] In this implementation, the first and second low-power units can flexibly be selected from level conversion units, power isolation units, or level conversion units with isolation functions. This allows for signal level conversion between different voltage domains (write clock domain and read clock domain) according to actual power domain configuration requirements, ensuring voltage compatibility and correctness of cross-power domain signal transmission. Simultaneously, the first low-power unit effectively isolates the signal output from the write clock domain when the read clock domain is powered down, preventing uncontrollable signals from the powered domain from entering the powered-down domain, avoiding leakage paths or logic corruption, and ensuring signal isolation safety and power management flexibility under different power operating modes. This configuration enables the circuit to support normal communication across multiple voltage domains while also adapting to low-power operating scenarios such as power-off, improving the robustness and applicability of the chip's power management.

[0034] In this embodiment, the synchronizer simultaneously receives the target write data converted by the first low-power unit and the read pointer converted by the second low-power unit; and performs synchronization processing on the asynchronous signals from the write clock domain to eliminate cross-clock domain metastability. The synchronizer simultaneously receives the target write data converted by the first low-power unit and the read pointer converted by the second low-power unit, ensuring that both maintain the same synchronization reference and time alignment within the read clock domain, avoiding timing mismatches caused by differences in path delays. The synchronizer's synchronization processing of asynchronous signals from the write clock domain effectively eliminates the risk of metastability in cross-clock domain transmission, ensuring that the target write data is correctly sampled and latched in the read clock domain. This synchronization mechanism enhances the timing stability and data reliability of asynchronous FIFO data transmission, enabling the read clock domain to safely and orderly acquire valid data from the write clock domain, thus guaranteeing the stable operation of the chip in a multi-clock domain environment.

[0035] In this embodiment of the application, the layout coordinates of all first low-power units and second low-power units and the signal trace channel occupancy data are collected. By statistically analyzing the degree of wiring congestion in the power domain boundary area and the transmission timing delay of the output signals of each low-power unit; Based on the degree of cable congestion and the value of transmission timing delay, a unit layout adjustment instruction is generated; The layout positions of the first low-power unit and the second low-power unit are rearranged according to the layout adjustment instruction.

[0036] This implementation method, by collecting the layout coordinates and signal trace occupancy data of the first and second low-power cells, and statistically analyzing the trace congestion level at the power domain boundary and the transmission timing delay of each cell's output signal, can quantitatively evaluate the physical implementation quality of the low-power cells in the current layout. Based on this, cell arrangement adjustment instructions are generated according to the trace congestion level and transmission timing delay, and the layout positions of the low-power cells are rearranged accordingly, achieving closed-loop optimization of the low-power cell layout. This scheme effectively alleviates wiring congestion at the power domain boundary, balances the transmission delay of each signal path, improves timing convergence, enhances the automation and efficiency of back-end physical design, reduces the cost of manual intervention and iterative adjustments, and achieves a better balance between chip design area, performance, and manufacturability.

[0037] In this embodiment of the application, the number of valid data stores inside the FIFO memory and the update rate of the read pointer output by the read control logic module are read. The current data transmission load level of the circuit is determined by combining the effective data storage quantity and the read pointer update rate, thus distinguishing between idle transmission state and full-load transmission state. If the data transmission circuit is in an idle transmission state, it sends a power cut-off command to the first low-power unit and the second low-power unit that are not participating in the current data transmission. When the data transmission circuit switches to full-load transmission state, the power supply paths of all first low-power units and second low-power units are restored.

[0038] This implementation method, by reading the number of valid data stores and the read pointer update rate within the FIFO memory and combining these two data points, determines the current data transmission load level of the circuit. This allows for accurate differentiation between idle and full-load transmission states, enabling real-time awareness of the circuit's operating status. In the idle transmission state, power-off commands are issued to the first and second low-power units not currently involved in data transmission, effectively reducing static power consumption and leakage losses during non-operational states. When switching to the full-load transmission state, power supply paths to all low-power units are promptly restored, ensuring complete bandwidth and real-time response capabilities for data transmission. This dynamic power management mechanism enables low-power units to be powered on demand according to the actual data transmission load, maximizing chip power savings while ensuring normal communication performance and improving energy efficiency management in multi-power domain scenarios.

[0039] In this embodiment, the storage depth and data bit width parameters of the FIFO memory are read in advance; based on the read storage depth and data bit width parameters, the number of the first low-power units and the second low-power units required to be enabled for the current circuit operation are determined, so as to generate the corresponding path selection control signal and transmit it to the low-power unit group. After receiving the path selection control signal, the low-power unit group closes the low-power unit signal transmission path that exceeds the current configuration requirements.

[0040] This implementation method reads the pre-configured storage depth and data bit width parameters of the FIFO memory and determines the number of first and second low-power units required for the current circuit operation based on these parameters. It then generates a path selection control signal and transmits it to the low-power unit group, allowing the low-power unit group to shut down signal transmission paths exceeding the current configuration requirements as needed. This mechanism dynamically matches the number of activated low-power units with the actual configuration specifications of the FIFO memory, avoiding unnecessary power consumption overhead caused by activating all low-power units in all configuration modes. It is particularly suitable for applications where storage depth or data bit width can be reconfigured. This solution, while ensuring the integrity of signal transmission paths, further optimizes the granularity of power management and improves the chip's energy efficiency flexibility in different operating modes.

[0041] The following is for reference. Figure 2 , Figure 2 This is a flowchart illustrating a cross-power domain asynchronous FIFO data transmission method according to an embodiment of the present invention. It should be noted that the embodiments of the present invention can be applied to... Figure 1 The data transmission circuit of the asynchronous FIFO across power domains is shown.

[0042] Figure 2 The flowchart of a cross-power domain asynchronous FIFO data transmission method provided in an embodiment of the present invention, shown below, includes: Step 201: The write data from the write clock domain is stored in the FIFO memory.

[0043] Step 202: Generate a read pointer through the read control logic module and transmit the read pointer to the second low-power unit of the low-power unit group.

[0044] In this embodiment of the application, the number of the second low-power units is the same as the read pointer encoding bit width.

[0045] Step 203: The read pointer is transmitted to the data selector via the second low-power unit.

[0046] Step 204: Read the write data to be transferred corresponding to the read pointer from the FIFO memory through the data selector.

[0047] Step 205: Perform cross-power domain signal processing on the write data to be transmitted through the first low-power unit to obtain the target write data.

[0048] In this embodiment of the application, the number of the first low-power units is the same as the bit width of the write data to be transmitted.

[0049] Step 206: Synchronize the target write data to the read clock domain using a synchronizer.

[0050] This invention enables low-power cells to be placed after all data outputs of the FIFO memory and after the data selector. The first low-power cell is placed only on the W-bit valid data path of the data selection output, while a second low-power cell is placed on the read pointer transmission path. This ensures that cross-power domain signal processing only affects the actually read data and the read pointer, rather than storing the entire amount of data. This scheme significantly reduces the number of low-power cells used, effectively reducing cell density at power domain boundaries and avoiding routing and timing violations caused by congestion of numerous low-power cells. This significantly improves the roamability and timing convergence of the chip's back-end physical implementation. Simultaneously, the reduction in the number of low-power cells directly reduces signal transmission latency in the data path, shortens the data synchronization path between read and write clock domains, and improves the overall operating frequency and data throughput of the chip. The reduction in the area of ​​the low-power cells also frees up valuable chip routing resources, reduces the risk of local voltage drops in the power grid, and improves signal integrity and power integrity under high-frequency operating conditions, comprehensively enhancing the chip's performance and design robustness.

[0051] After introducing the method of exemplary embodiments of the present invention, the following references are made. Figure 3 An exemplary embodiment of the present invention will be described, which is a data transmission apparatus for an asynchronous FIFO across power domains, and is applied to... Figure 2 The data transmission method for an asynchronous FIFO across power domains shown includes the following apparatus: Storage unit 301 is used to store write data from the write clock domain into the FIFO memory; The first transmission unit 302 is used to generate a read pointer through the read control logic module and transmit the read pointer to the second low-power unit of the low-power unit group; wherein the number of the second low-power units is the same as the bit width of the read pointer encoding. The second transmission unit 303 is used to transmit the read pointer to the data selector through the second low-power unit; The reading unit 304 is used to read the write data to be transferred corresponding to the read pointer from the FIFO memory through the data selector; Processing unit 305 is configured to perform cross-power domain signal processing on the write data to be transmitted through a first low-power unit to obtain target write data; wherein the number of the first low-power units is the same as the bit width of the write data to be transmitted. Synchronization unit 306 is used to synchronize the target write data to the read clock domain through a synchronizer.

[0052] This invention enables low-power cells to be placed after all data outputs of the FIFO memory and after the data selector. The first low-power cell is placed only on the W-bit valid data path of the data selection output, while a second low-power cell is placed on the read pointer transmission path. This ensures that cross-power domain signal processing only affects the actually read data and the read pointer, rather than storing the entire amount of data. This scheme significantly reduces the number of low-power cells used, effectively reducing cell density at power domain boundaries and avoiding routing and timing violations caused by congestion of numerous low-power cells. This significantly improves the roamability and timing convergence of the chip's back-end physical implementation. Simultaneously, the reduction in the number of low-power cells directly reduces signal transmission latency in the data path, shortens the data synchronization path between read and write clock domains, and improves the overall operating frequency and data throughput of the chip. The reduction in the area of ​​the low-power cells also frees up valuable chip routing resources, reduces the risk of local voltage drops in the power grid, and improves signal integrity and power integrity under high-frequency operating conditions, comprehensively enhancing the chip's performance and design robustness.

[0053] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0054] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0055] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0056] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0057] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0058] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0059] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0060] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0061] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

Claims

1. A data transmission circuit for an asynchronous FIFO across power domains, characterized in that, The circuit includes a FIFO memory, a read control logic module, a data selector, a low-power unit group, and a synchronizer, wherein: The FIFO memory is used to store write data from the write clock domain; The read control logic module is used to generate a read pointer and transmit the read pointer to the low-power unit group; The low-power unit group comprises W first low-power units and X second low-power units; wherein, the second low-power units store the read pointer and transmit the read pointer to the data selector; W is the data bit width of the FIFO memory; X is the read pointer encoding bit width; The data selector is connected to the data output terminal of the FIFO memory and the output terminal of the second low-power unit, and is used to select the write data to be transferred corresponding to the read pointer from the FIFO memory; The first low-power unit is connected to the data output terminal of the data selector and is used to perform cross-power domain signal processing on the W bits of the write data to be transmitted output by the data selector to obtain the target write data. The synchronizer is connected to the output of the first low-power unit and is used to synchronize the target write data to the read clock domain.

2. The data transmission circuit of the cross-power domain asynchronous FIFO according to claim 1, characterized in that, in: The FIFO memory has a depth of N and is used to cache N sets of write data; each set of write data contains W bits.

3. The data transmission circuit of the cross-power domain asynchronous FIFO according to claim 2, characterized in that, The calculation method for the read pointer encoding bit width is as follows: ； in, X represents the integer part of the read pointer encoding, and N represents the depth of the FIFO memory.

4. The data transmission circuit of the cross-power domain asynchronous FIFO according to claim 1, characterized in that, in: The first low-power unit or the second low-power unit is any one of a level conversion unit, a power isolation unit, or a level conversion unit with isolation function; The first low-power unit or the second low-power unit is used to realize the signal level conversion between different voltage domains between the write clock domain and the read clock domain; The first low-power unit is used to isolate the signal output from the write clock domain when the read clock domain is powered down.

5. The data transmission circuit of the cross-power domain asynchronous FIFO according to claim 1, characterized in that, in: The synchronizer simultaneously receives the target write data converted by the first low-power unit and the read pointer converted by the second low-power unit; and performs synchronization processing on the asynchronous signals from the write clock domain to eliminate cross-clock domain metastability.

6. The data transmission circuit of the cross-power domain asynchronous FIFO according to claim 1, characterized in that, It also collects the layout coordinates of all first low-power cells and second low-power cells, as well as the signal trace channel occupancy data; By statistically analyzing the degree of wiring congestion in the power domain boundary area and the transmission timing delay of the output signals of each low-power unit; Based on the degree of cable congestion and the value of transmission timing delay, a unit layout adjustment instruction is generated; The layout positions of the first low-power unit and the second low-power unit are rearranged according to the layout adjustment instruction.

7. The data transmission circuit of the cross-power domain asynchronous FIFO according to claim 1, characterized in that, By reading the amount of valid data stored inside the FIFO memory and the update rate of the read pointer output by the read control logic module; The current data transmission load level of the circuit is determined by combining the effective data storage quantity and the read pointer update rate, thus distinguishing between idle transmission state and full-load transmission state. If the data transmission circuit is in an idle transmission state, it sends a power cut-off command to the first low-power unit and the second low-power unit that are not participating in the current data transmission. When the data transmission circuit switches to full-load transmission state, the power supply paths of all first low-power units and second low-power units are restored.

8. The data transmission circuit of the cross-power domain asynchronous FIFO according to claim 1, characterized in that, The storage depth and data bit width parameters of the FIFO memory are read in advance; based on the read storage depth and data bit width parameters, the number of the first low-power units and the second low-power units required for the current circuit operation are determined, so as to generate the corresponding path selection control signal and transmit it to the low-power unit group. After receiving the path selection control signal, the low-power unit group closes the low-power unit signal transmission path that exceeds the current configuration requirements.

9. A data transmission method for an asynchronous FIFO across power domains, applied to the data transmission circuit according to any one of claims 1 to 8, characterized in that, The method includes: Write data from the write clock domain is stored in the FIFO memory; A read pointer is generated by the read control logic module and transmitted to the second low-power unit of the low-power unit group; wherein the number of the second low-power units is the same as the bit width of the read pointer encoding. The read pointer is transmitted to the data selector via the second low-power unit; The data selector reads the write data to be transferred from the FIFO memory, corresponding to the read pointer; The target write data is obtained by performing cross-power domain signal processing on the write data to be transmitted through the first low-power unit; wherein, the number of the first low-power units is the same as the bit width of the write data to be transmitted. The target write data is synchronized to the read clock domain using a synchronizer.

10. A data transmission apparatus for an asynchronous FIFO across power domains, applied to the data transmission method of the asynchronous FIFO across power domains as described in claim 9, characterized in that, The device includes: A storage unit is used to store write data from the write clock domain into a FIFO memory; The first transmission unit is used to generate a read pointer through the read control logic module and transmit the read pointer to the second low-power unit of the low-power unit group; wherein the number of the second low-power units is the same as the bit width of the read pointer encoding. The second transmission unit is used to transmit the read pointer to the data selector through the second low-power unit; A read unit is used to read the write data to be transferred corresponding to the read pointer from the FIFO memory through the data selector; The processing unit is configured to perform cross-power domain signal processing on the write data to be transmitted through the first low-power unit to obtain the target write data; wherein the number of the first low-power units is the same as the bit width of the write data to be transmitted. The synchronization unit is used to synchronize the target write data to the read clock domain via a synchronizer.

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