Asynchronous signal transmission circuits and methods, chips, and electronic devices

Abstract

Embodiments of this disclosure provide an asynchronous signal transmission circuit, method, chip, and electronic device. The asynchronous signal transmission circuit includes a synchronization circuit, a comparison circuit, and a storage circuit. The synchronization circuit is configured to sample asynchronous input data using at least two synchronizers based on a target clock signal and output first sampled data. The target clock signal is the clock signal of the target circuit. The comparison circuit is configured to compare the first sampled data with second sampled data delayed from the first sampled data, and output a comparison result and second sampled data to the storage circuit. The storage circuit is configured to store the output data and determine whether to update the stored output data with the second sampled data based on the comparison result. This solves the problems of current asynchronous signal transmission methods, such as sampling incorrect intermediate values ​​or being unable to use circuits that are difficult to provide handshake signals.

Description

Technical Field

[0001] The embodiments of this disclosure relate to the field of integrated circuit technology, and more specifically, to asynchronous signal transmission circuits and methods, chips, and electronic devices. Background Technology

[0002] Asynchronous signal transmission is widespread in hardware design; it is typically required whenever a circuit has multiple clock domains. Common asynchronous signal transmission methods include synchronizers, asynchronous handshakes, and ping-pong buffers.

[0003] Synchronizers directly sample data values ​​to synchronize with the target clock domain. This method is very effective for single-bit signals, but for multi-bit signals, it may sample varying intermediate values. For example... Figure 1 As shown, a data signal with a bit width of 2 changes from 2'b00 to 2'b11. Due to factors such as connection delay, the two bits of data change at different times. After passing through the synchronizer, there is still a possibility of sampling the intermediate value 2'b01.

[0004] Asynchronous handshake requires handshake signals from both the source and target circuits. The specific handshake process is as follows: the source circuit outputs data and sends a request signal; the target circuit receives the request signal, latches the data, and sends a response signal; the source circuit receives the response signal, clears the request signal, and prepares for the next transmission. Asynchronous handshake is a secure asynchronous signal transmission method, but it is not suitable for circuits that have difficulty providing handshake signals.

[0005] For the asynchronous transmission method of ping-pong buffer, such as Figure 2 As shown, the signal source circuit provides data signals buf_a and buf_b, and a data selection signal adr. When the data changes, data is alternately written to buf_a and buf_b, while simultaneously changing the selection signal adr. The target circuit collects data according to the synchronized adr_d signal; when adr_d is 1'b1, data from buf_a is used; otherwise, data from buf_b is used. Figure 2 As can be seen, there is a delay of Tsta from the time the source circuit changes the data to the time the target circuit receives the data. This delay is 1 to 2 clk_target clock cycles, which is generally sufficient for the source circuit to stabilize the data. However, if the data in the source circuit changes rapidly and changes multiple times within the Tsta time, as shown by the dashed line, the target circuit may sample an incorrect intermediate value.

[0006] In summary, current asynchronous signal transmission methods suffer from problems such as sampling incorrect intermediate values ​​or being unsuitable for circuits that cannot provide handshake signals. Summary of the Invention

[0007] The embodiments described in this disclosure provide an asynchronous signal transmission circuit and method, chip, and electronic device to solve the problems of current asynchronous signal transmission methods that sample incorrect intermediate values ​​or cannot be used with circuits that are difficult to provide handshake signals.

[0008] According to a first aspect of this disclosure, an asynchronous signal transmission circuit is provided, comprising: a synchronization circuit, a comparison circuit, and a storage circuit, wherein the synchronization circuit is configured to sample asynchronous input data through at least two synchronizers based on a target clock signal and output first sampled data, the target clock signal being a clock signal of a target circuit; the comparison circuit is configured to delay the first sampled data to obtain second sampled data, and to perform a consistency comparison between the second sampled data and the first sampled data, and output a comparison result and the second sampled data to the storage circuit; the storage circuit is configured to store output data and determine whether to update the stored output data to the second sampled data based on the comparison result.

[0009] Optionally, the synchronization circuit includes: a first D flip-flop and a second D flip-flop, wherein the input terminal of the first D flip-flop receives the asynchronous input data, the output terminal of the first D flip-flop is coupled to the input terminal of the second D flip-flop, and the control terminal of the first D flip-flop receives the target clock signal; the output terminal of the second D flip-flop is coupled to the comparator circuit and outputs the first sampled data, and the control terminal of the second D flip-flop receives the target clock signal.

[0010] Optionally, the comparison circuit includes a delay module and a comparison module, wherein the delay module is configured to delay the first sampled data by n clock cycles to obtain the second sampled data, where n is an integer greater than or equal to 1; the comparison module is configured to compare the first sampled data and the second sampled data and output the comparison result.

[0011] Optionally, the delay module includes: n third D flip-flops connected in series, wherein the input of the first third D flip-flop is coupled to the synchronization circuit for receiving the first sampled data; except for the first third D flip-flop, the input of each other third D flip-flop is coupled to the output of the previous third D flip-flop; the output of the last third D flip-flop outputs the second sampled data, and except for the last third D flip-flop, the output of each other third D flip-flop is coupled to the input of the next third D flip-flop; the control terminal of each third D flip-flop receives the target clock signal; and the output of each third D flip-flop is also coupled to the comparison module.

[0012] Optionally, the comparison module includes a comparator, wherein one input of the comparator is coupled to the synchronization circuit for receiving the first sampled data, the other input of the comparator is coupled to the delay module for receiving the output data of each third D flip-flop, and the output of the comparator is coupled to the storage circuit for outputting the comparison result.

[0013] Optionally, the storage circuit includes: a selector and a fourth D flip-flop, wherein one input of the selector is coupled to the comparator circuit for receiving the second sampled data, the other input of the selector is coupled to the output of the fourth D flip-flop for receiving the output data, the output of the selector is coupled to the input of the fourth D flip-flop, and the selection signal terminal of the selector is coupled to the comparator circuit for receiving the comparison result; the output of the fourth D flip-flop serves as the output of the asynchronous signal transmission circuit for outputting the output data, and the control terminal of the fourth D flip-flop receives the target clock signal.

[0014] Optionally, the asynchronous input data can be single-bit data or multi-bit data.

[0015] According to a second aspect of this disclosure, a chip is provided, comprising the asynchronous signal transmission circuit described in any one of the first aspects above.

[0016] According to a third aspect of this disclosure, an electronic device is provided, including the chip described in the second aspect.

[0017] According to a fourth aspect of this disclosure, an asynchronous signal transmission method is provided, applied to the asynchronous signal transmission circuit described in the first aspect. The method includes: sampling asynchronous input data and outputting first sampled data based on a target clock signal through at least two synchronizers, wherein the target clock signal is a clock signal of a target circuit; delaying the first sampled data to obtain second sampled data; performing a consistency comparison between the second sampled data and the first sampled data, and outputting a comparison result; and determining, based on the comparison result, whether to update the stored output data to the second sampled data.

[0018] Optionally, determining whether to update the stored output data to the second sampled data based on the comparison result includes: if the comparison result is consistent, then updating the stored output data to the second sampled data; if the comparison result is inconsistent, then retaining the stored output data.

[0019] Optionally, obtaining the second sampled data by delaying the first sampled data includes: obtaining the second sampled data by delaying the first sampled data by n clock cycles, where n is an integer greater than or equal to 1.

[0020] The asynchronous signal transmission circuit, method, chip, and electronic device embodiments of this disclosure first sample the asynchronous input data using at least two synchronizers based on the target clock signal. This effectively reduces the probability of metastability. Then, the second sampled data, delayed from the first sampled data, is compared with the first sampled data. The comparison result determines whether to update the output data. Specifically, if the comparison result is consistent, the output data is updated; if the comparison result is inconsistent, the output data is retained. It can be seen that no handshake is required throughout the process, making it suitable for circuits where providing a handshake signal is difficult. Furthermore, after sampling with the target clock signal, the data is not directly output to the target circuit but is first compared with the second sampled data. The output data is updated only when they are consistent, effectively avoiding erroneous intermediate values. It is also not limited by the number of bits in the asynchronous input data, allowing for both single-bit and multi-bit data. In summary, the asynchronous signal transmission method of this disclosure is an improvement on the synchronizer method, integrating a spike pulse deglitch function, enabling safe sampling of multi-bit data signals and avoiding metastability and erroneous intermediate values. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. It should be understood that the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0022] Figure 1 This is an example diagram of an existing synchronizer method;

[0023] Figure 2 This is an example diagram of the existing ping-pong buffer method;

[0024] Figure 3 A schematic block diagram of an asynchronous signal transmission circuit according to an embodiment of the present disclosure;

[0025] Figure 4 This is an exemplary circuit diagram of an asynchronous signal transmission circuit according to an embodiment of the present disclosure;

[0026] Figure 5 This is a flowchart of an asynchronous signal transmission method according to an embodiment of the present disclosure;

[0027] Figure 6 This is a flowchart of another asynchronous signal transmission method according to an embodiment of the present disclosure;

[0028] The elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, statements that “connect” or “couple” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components. Furthermore, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0031] like Figure 3 The diagram shows a schematic block diagram of an asynchronous signal transmission circuit 100 according to an embodiment of the present disclosure. The asynchronous signal transmission circuit 100 includes: a synchronization circuit 110, a comparison circuit 120, and a storage circuit 130.

[0032] The synchronization circuit 110 is coupled to the comparator circuit 120 and is configured to sample the asynchronous input data data_in[a:b] according to the target clock signal target clk through at least two stages of synchronizers, and output the first sampled data data_samp1[a:b]. The target clock signal target clk is the clock signal of the target circuit. Opposite to the target circuit is the source circuit, which generates the asynchronous input data data_in[a:b] in asynchronous signal transmission. The asynchronous signal transmission circuit 100 is located between the source circuit and the target circuit. The asynchronous input data data_in[a:b] is transmitted to the target circuit after passing through the asynchronous signal transmission circuit 100. The asynchronous input data data_in[a:b] can be single-bit data or multi-bit data. The synchronizer in the synchronization circuit 110 is usually implemented by a D flip-flop. The synchronization circuit 110 uses at least two stages of synchronizers to effectively reduce the probability of metastability. Even if there is metastability at the output (Q) of the first stage synchronizer, the probability that the level at the input (D) of the second stage synchronizer will still be unstable after one clock cycle is very small. Therefore, the output (Q) of the second stage flip-flop will basically not produce metastability.

[0033] The comparison circuit 120 is coupled to the synchronization circuit 110 and the storage circuit 130, respectively. It is configured to delay the first sampled data data_samp1[a:b] to obtain the second sampled data data_samp2[a:b], perform a consistency comparison between the second sampled data data_samp2[a:b] and the first sampled data data_samp1[a:b], and output the comparison result comp_data and the second sampled data data_samp2[a:b] to the storage circuit 130. Specifically, the comparison circuit 120 consists of a delay module 121 and a comparison module 122, with the delay module 121 coupled to the comparison module 122. The delay module 121 is configured to delay the first sampled data data_samp1[a:b] output by the synchronous circuit 110 by n clock cycles to obtain the second sampled data data_samp2[a:b], where n is an integer greater than or equal to 1. The comparison module 122 is configured to compare the first sampled data data_samp1[a:b] and the second sampled data data_samp2[a:b] and output the comparison result comp_data. The comparison module 122 is used to compare whether the first sampled data data_samp1[a:b] and the second sampled data data_samp2[a:b] are consistent. This is done to detect abnormal situations where erroneous intermediate values ​​occur during asynchronous signal processing and to prevent the subsequent storage circuit 130 from updating the output data data_out, so that the storage circuit 130 can avoid erroneous intermediate values ​​being input to the target circuit. It should be noted that the value of n is related to the actual user requirements. For example, if it is necessary to filter out unstable data whose duration does not exceed one clock cycle of the target circuit, then n is 1.

[0034] The storage circuit 130 is coupled to the comparison circuit 120 and is configured to store output data. Based on the comparison result `comp_data`, it determines whether to update the stored output data `data_out` to the second sampled data `data_samp2[a:b]`. Specifically, if the comparison result `comp_data` is consistent (i.e., the second sampled data `data_samp2[a:b]` and the first sampled data `data_samp1[a:b]` are consistent), the data is stable, and therefore the output data `data_out` can be updated. Conversely, if the comparison result `comp_data` is inconsistent (i.e., the second sampled data `data_samp2[a:b]` and the first sampled data `data_samp1[a:b]` are inconsistent), the data is unstable, and therefore the output data `data_out` cannot be updated; the old output data `data_out` must be retained. Therefore, the asynchronous signal transmission circuit of this embodiment has a deglitch function, which can filter out unstable data whose duration does not exceed n clock cycles of the target circuit.

[0035] In this embodiment, the asynchronous signal transmission circuit 100 samples the asynchronous input data data_in[a:b] using at least two synchronizers based on the target clock signal target clk. This effectively reduces the probability of metastability. Furthermore, after sampling with the target clock signal target clk, instead of directly outputting to the target circuit, the first sampled data data_samp1[a:b] and the second sampled data data_samp2[a:b] are compared. The output data data_out is updated only when they match. This effectively avoids erroneous intermediate values ​​and is not limited by the number of bits in the asynchronous input data; it can be either single-bit or multi-bit data. Additionally, no handshake is required throughout the process, making it suitable for circuits where providing handshake signals is difficult.

[0036] Furthermore, Figure 4 An exemplary circuit diagram of an asynchronous signal transmission circuit 100 according to an embodiment of the present disclosure is shown.

[0037] like Figure 4As shown, the synchronization circuit 110 includes a first D flip-flop 111 and a second D flip-flop 112. The input terminal D of the first D flip-flop 111 receives asynchronous input data data_in[a:b], and the output terminal Q of the first D flip-flop 111 is coupled to the input terminal D of the second D flip-flop 112. The control terminal CP of the first D flip-flop 111 receives the target clock signal target clk. The output terminal Q of the second D flip-flop 112 is coupled to the comparator circuit 120 and outputs the first sampled data data_samp1[a:b]. The control terminal CP of the second D flip-flop 112 also receives the target clock signal target clk. The reset terminal of the first D flip-flop 111 is coupled to a reset signal reset, which is a signal that stops the asynchronous signal transmission circuit from working. The reset signal reset is determined according to the actual application scenario. The reset signals reset for the subsequent second to fourth flip-flops are the same as those reset for the first D flip-flop 111, and will not be described in detail later. The first D flip-flop 111 and the second D flip-flop 112 constitute a two-stage synchronizer, which can effectively reduce the probability of metastability.

[0038] like Figure 4 As shown, the delay module 121 includes: n third D flip-flops TRIGGER1 connected in series, wherein the input terminal D of the first third D flip-flop TRIGGER1 is coupled to the output terminal Q of the second D flip-flop 112 in the synchronization circuit 110, for receiving the first sampled data data_samp1[a:b], and the input terminal D of each of the other third D flip-flops TRIGGER1 is coupled to the output terminal Q of the previous third D flip-flop TRIGGER1; the output terminal Q of the last third D flip-flop TRIGGER1 outputs the second sampled data data_samp2[a:b], and the output terminal Q of each of the other third D flip-flops TRIGGER1 is coupled to the input terminal D of the next third D flip-flop; the control terminal CP of each third D flip-flop TRIGGER1 receives the target clock signal target clk; and the output terminal Q of each third D flip-flop TRIGGER1 is also coupled to the comparison module 122. The first sampled data, data_samp1[a:b], will be delayed by n clock cycles after passing through the third D flip-flop TRIGGER1.

[0039] like Figure 4As shown, the comparison module 122 includes a comparator COMP, wherein one input of the comparator COMP is coupled to the output Q of the second D flip-flop 112 in the synchronization circuit 110, for receiving the first sampled data data_samp1[a:b], the other inputs of the comparator COMP are coupled to the output Q of each third D flip-flop TRIGGER1 in the delay module 121, for receiving the output data of each third D flip-flop TRIGGER1, and the output of the comparator COMP is coupled to the storage circuit 130 for outputting the comparison result comp_data. It should be noted that, in this embodiment, when the comparator COMP compares the consistency of the first sampled data data_samp1[a:b] and the second sampled data data_samp2[a:b], it is necessary to compare the consistency of each delayed output data at the intermediate time between the second sampled data data_samp2[a:b] and the first sampled data data_samp1[a:b] with the first sampled data data_samp1[a:b]. That is, it is to compare the consistency of the output data of each third D flip-flop TRIGGER1 in the delay module 121 with the first sampled data data_samp1[a:b]. Only when the output data of each third D flip-flop TRIGGER1 is consistent with the first sampled data data_samp1[a:b] is it considered that the first sampled data data_samp1[a:b] and the second sampled data data_samp2[a:b] are consistent. This is to ensure that unstable data whose duration does not exceed n clock cycles of the target circuit are filtered out.

[0040] like Figure 4 As shown, the storage circuit 130 includes: a selector MUX and a fourth D flip-flop TRIGGER2. One input terminal I1 of the selector MUX is coupled to the comparator circuit 120 (specifically, the output terminal Q of the last third D flip-flop TRIGGER1 in the delay module 121 of the comparator circuit 120) to receive the second sampled data data_samp2[a:b]. The other input terminal I0 of the selector MUX is coupled to the output terminal Q of the fourth D flip-flop TRIGGER2 to receive the output data data_out. The output terminal of the selector MUX is coupled to the input terminal D of the fourth D flip-flop TRIGGER2. The selection signal terminal sel of the selector MUX is coupled to the comparator circuit 120 to receive the comparison result comp_data. The output terminal Q of the fourth D flip-flop TRIGGER2 serves as the output terminal of the asynchronous signal transmission circuit 100 to output the output data data_out. The control terminal CP of the fourth D flip-flop TRIGGER2 receives the target clock signal target clk.

[0041] Combination Figure 4 The circuit diagram in the figure illustrates the principle of the asynchronous signal transmission circuit 100 of this embodiment: The target clock signal target clk is sampled by two-stage synchronizers to obtain the synchronized data signal data_samp1 (i.e., the first sampled data data_samp1[a:b]). n TRIGGER 1s delay the synchronized data signal data_samp1 by n clock cycles to obtain data_samp2 (i.e., the second sampled data data_samp2[a:b]). The comparator COMP compares the consistency of data_samp1 and data_samp2, and uses the comparison result comp_data as the selection signal of the selector MUX. When data_samp1 and data_samp2 are consistent, it indicates that the data is stable, and the selector MUX selects to input data_samp2 to the fourth D flip-flop TRIGGER2, that is, to update the output data data_out; when data_samp1 and data_samp2 are inconsistent, it indicates that the data is unstable, and the selector MUX selects to input data_out to the fourth D flip-flop TRIGGER2, that is, to retain the old output data data_out. This method has a deglitch function, which can filter out unstable data whose duration does not exceed one clock cycle of the target circuit.

[0042] In summary, the asynchronous signal transmission circuit 100 of this disclosure uses the target circuit clock signal to sample asynchronous input data, and updates or retains the data based on the sampling results. This can filter out glitches within n clock cycles, representing a method that trades circuit area for data security. The asynchronous signal transmission circuit of this disclosure is suitable for asynchronous transmission of single-bit or multi-bit data, and is also applicable to scenarios where the source circuit cannot provide a handshake signal. It can improve the security of asynchronous signal transmission and effectively avoid metastability and sampling intermediate value problems.

[0043] Embodiments of this disclosure also provide a chip. The chip includes an asynchronous signal transmission circuit 100 according to embodiments of this disclosure. This chip is, for example, a multi-bit quantization chip (i.e., a multi-bit quantization chip) that can be used in scenarios involving analog-to-digital signal conversion.

[0044] Embodiments of this disclosure also provide an electronic device. This electronic device includes a chip according to embodiments of this disclosure. The electronic device is, for example, a smart home device or a wearable smart device.

[0045] Furthermore, this disclosure also provides an asynchronous signal transmission method, which is applied to the asynchronous signal transmission circuit 100 in the foregoing embodiments. Figure 5A flowchart of an asynchronous signal transmission method is shown: S101. Sampling the asynchronous input data according to the target clock signal through at least two synchronizers and outputting the first sampled data; S102. Delaying the first sampled data to obtain the second sampled data; S103. Comparing the second sampled data with the first sampled data and outputting the comparison result; S104. Determining whether to update the stored output data with the second sampled data based on the comparison result.

[0046] In step S101, the target clock signal is the clock signal of the target circuit, and the two-stage synchronizer is specifically the synchronization circuit 110 in the asynchronous signal transmission circuit of the aforementioned embodiment. In step S102, "delaying the first sampled data to obtain the second sampled data" specifically means delaying the first sampled data data_samp1[a:b] by n clock cycles to obtain the second sampled data data_samp2[a:b]. Step S102 is implemented through the delay module 121 in the comparison circuit 120 of the asynchronous signal transmission circuit 100 in the aforementioned embodiment. Step S103 is implemented through the comparison module 122 in the comparison circuit 120 of the asynchronous signal transmission circuit 100 in the aforementioned embodiment. Step S104 is implemented through the storage circuit 130 of the asynchronous signal transmission circuit 100 in the aforementioned embodiment. "Determine whether to update the stored output data to the second sampled data based on the comparison result" specifically means: if the comparison result is consistent, then update the stored output data data_out[a:b] to the second sampled data data_samp2[a:b]; if the comparison result is inconsistent, then retain the stored output data data_out[a:b] (i.e. retain the old output data).

[0047] Furthermore, this disclosure also provides a flowchart of an asynchronous signal transmission method, such as... Figure 6 As shown: Start—Sampling data data_samp1 and data_samp2 (corresponding to steps S101 and S102 above)—data_samp1 = data_samp2? (That is, determine whether data_samp1 and data_samp2 are consistent, corresponding to step S103 above)—If yes, then update data data_out (corresponding to step S104 above)—If no, then retain data data_out (corresponding to step S104 above)—End.

[0048] An asynchronous signal transmission method according to an embodiment of this disclosure samples asynchronous input data using at least two synchronizers based on a target clock signal. This effectively reduces the probability of metastability. Furthermore, after sampling with the target clock signal, instead of directly outputting to the target circuit, the first and second sampled data are compared. The output data is updated only when they match, effectively avoiding erroneous intermediate values ​​and thus not being limited by the number of bits in the asynchronous input data. Additionally, no handshake is required throughout the process, making it suitable for circuits where providing handshake signals is difficult.

[0049] In summary, the asynchronous signal transmission method of this disclosure is applicable to asynchronous transmission of single-bit or multi-bit data, and is also applicable to scenarios where the source circuit cannot provide a handshake signal. It can improve the security of asynchronous signal transmission and effectively avoid metastability and sampling intermediate value problems.

[0050] It should be noted that in the above embodiments of this disclosure, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0051] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0052] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0053] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0054] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. An asynchronous signal transmission circuit, characterized by comprising: The asynchronous signal transmission circuit comprises a synchronization circuit, a comparison circuit and a storage circuit, The synchronization circuit is configured to sample and output first sampling data from asynchronous input data through at least two levels of synchronizers according to a target clock signal, the target clock signal is a clock signal of a target circuit, and the asynchronous input data is single-bit data or multi-bit data; the synchronizer is implemented by a D flip-flop, an input end of a first D flip-flop in the at least two levels of synchronizers receives the asynchronous input data, and a reset end of the first D flip-flop is coupled to a signal for stopping the asynchronous signal transmission circuit from working; The comparison circuit is configured to delay the first sampling data to obtain second sampling data, and compare the second sampling data with the first sampling data for consistency, and output a comparison result and the second sampling data to the storage circuit; The delaying of the first sampling data to obtain second sampling data, and the comparison of the second sampling data with the first sampling data for consistency comprise: passing the first sampling data through n third D flip-flops in series, each third D flip-flop receives the target clock signal at a control end, the output data of each third D flip-flop is compared with the first sampling data for consistency, and when the output data of each third D flip-flop is consistent with the first sampling data, it is determined that the first sampling data and the second sampling data are consistent, so as to filter out unstable data with a duration of no more than n clock cycles of the target circuit; The storage circuit is configured to store output data, and determine whether to update the stored output data to the second sampling data according to the comparison result.

2. The asynchronous signal transmission circuit according to claim 1, characterized in that, The synchronization circuit comprises a first D flip-flop and a second D flip-flop, The input end of the first D flip-flop receives the asynchronous input data, the output end of the first D flip-flop is coupled to the input end of the second D flip-flop, and the control end of the first D flip-flop receives the target clock signal; The output end of the second D flip-flop is coupled to the comparison circuit and outputs the first sampling data, and the control end of the second D flip-flop receives the target clock signal.

3. The asynchronous signal transmission circuit of claim 1, wherein The comparison circuit comprises a delay module and a comparison module, The delay module is configured to delay the first sampling data by n clock cycles to obtain the second sampling data, and n is an integer greater than or equal to 1; The comparison module is configured to compare the first sampling data with the second sampling data, and output the comparison result.

4. The asynchronous signal transmission circuit according to claim 3, wherein The delay module comprises n third D flip-flops in series, An input terminal of a first third D flip-flop is coupled to the synchronization circuit for receiving the first sampling data; an input terminal of each third D flip-flop other than the first third D flip-flop is coupled to an output terminal of a previous third D flip-flop; an output terminal of a last third D flip-flop outputs the second sampling data; an output terminal of each third D flip-flop other than the last third D flip-flop is coupled to an input terminal of a next third D flip-flop; a control terminal of each third D flip-flop receives the target clock signal; and an output terminal of each third D flip-flop is coupled to the comparison module.

5. The asynchronous signal transmission circuit according to claim 4, wherein The comparison module comprises a comparator, An input terminal of the comparator is coupled to the synchronization circuit for receiving the first sampling data; other input terminals of the comparator are coupled to the delay module for receiving output data of each third D flip-flop; and an output terminal of the comparator is coupled to the storage circuit for outputting the comparison result.

6. The asynchronous signal transmission circuit of claim 1, wherein, The storage circuit comprises a selector and a fourth D flip-flop, An input terminal of the selector is coupled to the comparison circuit for receiving the second sampling data; another input terminal of the selector is coupled to an output terminal of the fourth D flip-flop for receiving the output data; an output terminal of the selector is coupled to an input terminal of the fourth D flip-flop; and a selection signal terminal of the selector is coupled to the comparison circuit for receiving the comparison result. An output terminal of the fourth D flip-flop serves as an output terminal of the asynchronous signal transmission circuit for outputting the output data; and a control terminal of the fourth D flip-flop receives the target clock signal.

7. A chip, characterized by The chip comprises the asynchronous signal transmission circuit according to any one of claims 1-6.

8. An electronic device, comprising: The chip comprises the chip according to claim 7.

9. An asynchronous signal transmission method, characterized by, The method is applied to the asynchronous signal transmission circuit according to any one of claims 1-6, and the method comprises: sampling asynchronous input data to output first sampling data through at least two levels of synchronizers according to a target clock signal, the target clock signal being a clock signal of a target circuit; delaying the first sampling data to obtain second sampling data; comparing the second sampling data with the first sampling data for consistency and outputting a comparison result; determining whether to update stored output data to the second sampling data according to the comparison result.

10. The asynchronous signal transmission method according to claim 9, wherein The determining whether to update the stored output data to the second sampling data according to the comparison result comprises: if the comparison result is consistent, updating the stored output data to the second sampling data; if the comparison result is inconsistent, keeping the stored output data; The delaying the first sampling data to obtain the second sampling data comprises: delaying the first sampling data by n clock cycles to obtain the second sampling data, n being an integer greater than or equal to 1.

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