An iterative error suppression method and operation system for floating-point-fraction hybrid anchored

Abstract

This invention discloses a floating-point-fractional hybrid anchoring method and computational system for suppressing iteration errors, belonging to the field of high-precision numerical computation technology. It solves the technical problems of pseudo-chaos caused by the accumulation of iteration errors in pure floating-point calculations, the computational power explosion in pure high-precision fractional calculations, and the inability to simultaneously achieve both computational power and precision. This invention completes high-speed iterative computations of nonlinear systems using a general floating-point format. After each floating-point calculation, an optimal rational number approximation algorithm is used to convert the calculation result into a simplified rational number with a denominator not exceeding a preset threshold, eliminating the original errors introduced by floating-point truncation and rounding. The purified rational number is then converted back to floating-point format to participate in the next iteration, relying on a bounded rational number anchoring mechanism to progressively block the error amplification chain. The denominator threshold is set to 10¹²~10¹ based on the effective number of bits of the floating-point number. 5 This invention can adaptively adjust to various scenarios such as embedded terminals, supercomputing, and industrial control, and optimizes the continued fraction algorithm to achieve the globally optimal rational approximation under a given upper limit of the denominator. It requires no dedicated large number hardware and combines the advantages of high-speed, low-load floating-point operations with zero approximation error in rational numbers. It can be stably used in nonlinear computing scenarios that are sensitive to initial values ​​and require long-term stable iterations, such as chaotic simulation, vehicle trajectory prediction, industrial PID closed-loop control, 5G / 6G communication channel simulation, microscale meteorological simulation, and large-scale number theory zero-point verification. It effectively eliminates numerical trajectory drift, reduces equipment computing power consumption, and minimizes the workload of manual calibration and data screening, possessing extremely high engineering and academic application value.

Description

Technical Field

[0001] This invention relates to an error suppression method and system for high-precision numerical calculations, which is particularly suitable for long-term stable iterative calculations of nonlinear dynamic systems with initial value sensitivity and chaotic characteristics in environments with limited computing resources. Specifically, it covers the fields of high-precision iterative calculation technology, such as embedded intelligent real-time computing, chaotic dynamics simulation, large-scale number theory numerical verification, and vehicle-mounted terminal trajectory iterative prediction. Background Technology

[0002] Currently, there are only two mainstream technical solutions in the global numerical iterative computing system, both of which have inherent and unavoidable defects, forming a long-term technical bottleneck in the industry. The first is the pure floating-point iterative operation scheme, which generally uses 64-bit double-precision floating-point numbers to complete various nonlinear iterative calculations. This scheme relies on natively optimized instructions for general-purpose hardware, resulting in fast operation speed, low hardware burden, and compatibility with various devices such as embedded terminals, servers, and supercomputers. However, the binary floating-point system has inherent truncation and rounding defects, making it unable to accurately represent some rational numbers and all irrational numbers. In nonlinear iterative scenarios, the tiny mantissa errors generated by a single operation will continue to accumulate and amplify exponentially, eventually giving rise to a large number of non-system-native computational pseudo-chaos, causing numerical trajectory drift, blurred data boundaries, and the masking of true features by noise. To compensate for the error defects, existing technologies need to superimpose multiple layers of error compensation algorithms, redundant verification modules, and neural network correction models, which significantly increases the software computation load, forces hardware upgrades, increases equipment costs and power consumption, and cannot eliminate the numerical distortion problem at its root. This defect is widely present in scenarios such as autonomous driving trajectory prediction, chaotic dynamics simulation, and number theory zero-point retrieval. The second approach is a pure high-precision fraction / large integer arithmetic scheme. It performs precise calculations entirely in integer form for both numerators and denominators, without truncation, rounding, or approximation errors, thus fully preserving the system's true evolutionary patterns. However, this scheme suffers from a fatal engineering flaw: as the number of iterations increases, the values ​​of the numerator and denominator expand dramatically. Large integer arithmetic operations consume a large amount of processor cache and pipeline resources, resulting in a geometric increase in computational overhead. This approach is only suitable for a limited number of low-iteration scenarios and cannot be adapted to high-frequency, long-term iterative scenarios such as in-vehicle embedded real-time computing or large-scale supercomputing numerical verification, making its engineering feasibility extremely poor. In summary, existing technologies have long suffered from a core contradiction: high-speed floating-point operations suffer from error accumulation and pseudo-chaotic interference, while high-precision fraction arithmetic is too costly and impractical for engineering implementation. Currently, the industry lacks a universal iterative computing solution that balances high-speed computation, suppression of error accumulation, and low hardware burden, representing a significant technological gap. Purpose of the invention

[0003] This invention aims to overcome the bottleneck of the mutual constraint between computing power and accuracy in existing numerical iteration techniques, and provides an iteration error suppression method and computing system with floating-point-fractional hybrid anchoring. This invention decouples the binding relationship between computing power and numerical accuracy. While retaining the advantages of high speed and low hardware load of floating-point operations, it successively offsets iteration errors through a bounded rational number anchoring mechanism, breaking the chain of error exponential amplification and eliminating pseudo-chaos phenomena generated by computation. Simultaneously, it avoids the defects of numerical inflation and computing power explosion in pure fractional operations, forming a high-precision, high-speed, low-power, and highly versatile iterative computing architecture that can cover various application scenarios such as embedded intelligent terminals, chaos simulation, and large-scale number theory verification. Summary of the Invention

[0004] This invention features a unique hybrid computing architecture combining high-speed floating-point iteration with bounded rational number anchoring and purification. The core principle is as follows: General-purpose floating-point arithmetic is used to complete the main high-speed iterative derivation, ensuring computational efficiency and broad hardware compatibility. After each iteration, an optimal rational number approximation algorithm maps the floating-point result to a simplified rational number with a limited denominator maximum value, cleaning up floating-point rounding noise and re-anchoring the value to a precise rational number grid. The purified rational number is then used as the input for the next iteration, progressively preventing error accumulation and amplification, achieving optimal speed and accuracy. Compared to conventional rational number processing methods such as decimal truncation and polynomial approximation, this invention preferentially uses a continued fraction approximation algorithm for numerical purification. Its core advantage lies in the continued fraction's globally optimal approximation mathematical property under a given denominator upper limit. Under strict constraints on denominator size and to avoid computational power expansion, it maximizes the fit to the original floating-point value, accurately eliminating invalid noise generated by floating-point rounding and truncation without introducing additional numerical deviations. This is the optimal technical path for achieving low-cost, high-precision error purification, possessing strong technical specificity and non-obviousness. The specific technical steps are as follows.

[0005] 4.1 Initialization Phase: Set the initial iteration value, the number of iteration steps, and the upper limit threshold for the denominator. The upper limit threshold for the denominator is preferably 10¹² to 10¹². 5 This numerical range is set based on the hardware characteristics of 64-bit double-precision floating-point numbers with 15-17 effective decimal bits. It can ensure that the accuracy of rational number approximations covers and exceeds the precision limit of floating-point numbers, completely eliminating the inherent rounding error of floating-point numbers. At the same time, the threshold can be adaptively adjusted according to different application scenarios such as embedded terminals and supercomputing verification, balancing the accuracy of numerical purification and computing power consumption, and preventing the infinite expansion of fraction values ​​from causing a surge in computing power.

[0006] 4.2 High-speed iterative computation stage: Calling the native floating-point arithmetic instructions of CPU / GPU to complete core numerical calculations such as nonlinear iterative computation, feature calculation, and trajectory extrapolation, making full use of the optimization features of general-purpose hardware to achieve lightweight high-speed computation without the need for dedicated large number arithmetic hardware.

[0007] 4.3 Successive Error Anchoring and Purification Stage: After a single floating-point iteration is completed, the floating-point operation result is converted into the simplest rational fraction with a limited upper limit of the denominator through the optimal rational number approximation algorithm. This completely eliminates the small human errors caused by binary floating-point truncation and rounding, removes pseudo-chaotic noise generated by the calculation, and fully preserves the inherent physical and mathematical characteristics of the system itself.

[0008] 4.4 Iterative Loop Phase: The purified simplest rational fraction is converted into floating-point format as the input value for the next iteration. The iterative calculation and fraction anchoring purification process are repeated to prevent error accumulation throughout the process and ensure the stability and numerical accuracy of the long-term iterative trajectory.

[0009] 4.5 Results Output Stage: Only in the final results visualization and data output stages is a one-time numerical conversion completed, and the intermediate iterations are kept in an error-free purification state. Specific Implementation

[0010] To verify the technical effects of this invention, comparative experiments were conducted in six typical scenarios: classical simulation of chaotic dynamics, trajectory prediction of autonomous driving, industrial closed-loop control, nonlinear iteration of wireless communication, long-term numerical simulation of meteorology, and zero-point verification of number theory. These experiments covered all dimensions, including basic theoretical simulation, industrial application, civilian intelligence, and academic verification. The core implementation examples are as follows.

[0011] 5.1 Iterative Implementation Example of Chaotic Dynamics (Logistic Mapping): This embodiment uses the classical Logistic mapping model of chaotic dynamics for iterative verification. The iterative formula is: x n+1 =4x n (1-x n The initial value is uniformly set to 0.1, and the total number of iterations is 1000. The upper limit threshold of the denominator in this invention is set to 10¹. 5 The experiment included three control groups: a pure floating-point arithmetic group, a pure high-precision fraction arithmetic group, and the floating-point-fraction hybrid anchoring group of this invention. Experimental results: In the pure floating-point group, after 50-60 iterations, the floating-point rounding error amplified exponentially, producing pseudo-chaotic phenomena not inherent to the system, completely distorting the numerical trajectory, and rendering the iteration results invalid. The pure high-precision fraction arithmetic group could achieve zero-error iteration, but the numerator and denominator values ​​continued to expand, significantly increasing computational overhead and failing to meet real-time engineering requirements. The hybrid anchoring group of this invention exhibited no error accumulation and no pseudo-chaotic disturbances throughout the entire process; after 1000 iterations, the numerical error remained stably maintained at 10⁻¹²~10⁻¹. 4 The interval and iterative trajectory closely match the actual evolution of the system, and the computing speed is basically the same as the pure floating-point scheme, balancing high precision and high computing efficiency.

[0012] 5.2 Autonomous Driving Topology Trajectory Prediction Example: This example, based on an onboard embedded computing chip, conducts a 5-second long-term iterative prediction experiment of vehicle topology trajectory, comparing the performance and accuracy of the traditional floating-point error correction iteration scheme and the hybrid anchoring scheme of this invention. The experiment uniformly uses an onboard real-world road condition iterative model, with a mid-range onboard embedded chip as the hardware environment. Experimental Results: The traditional scheme uses pure floating-point iteration superimposed with a multi-layer error correction algorithm, resulting in a chip CPU utilization rate as high as 51%. During long-term continuous iteration, floating-point errors accumulate, leading to problems such as vehicle trajectory drift, blurred obstacle boundaries, and decision jitter, requiring frequent parameter calibration. The scheme of this invention eliminates the need for redundant error correction modules, with a chip CPU utilization rate of only 27%, significantly reducing hardware load. The entire iteration process is free of trajectory drift and boundary distortion, greatly improving trajectory prediction stability under complex road conditions. It can stably complete high-precision, high-real-time autonomous driving trajectory iterative calculations on mid-range onboard embedded devices.

[0013] 5.3 Industrial Intelligent PID Closed-Loop Iterative Control Example: This example verifies a nonlinear PID closed-loop iterative control system for high-precision industrial temperature control, fluid pressure regulation, and servo motor speed control. Such systems are characterized by long-term iteration, sensitivity to initial values, and high long-term operational stability requirements. The experiment uniformly sets the upper threshold of the denominator in this invention to 10¹² to adapt to industrial control accuracy standards, comparing the long-term operational performance of the traditional pure floating-point PID iterative scheme and the hybrid anchoring scheme of this invention. Experimental Results: After 72 hours of continuous steady-state operation, the traditional pure floating-point scheme exhibits a continuous accumulation of floating-point rounding errors, resulting in a ±0.3% drift in control accuracy. The system experiences slight oscillations, requiring periodic manual parameter calibration and the application of filtering compensation algorithms, increasing maintenance costs and control delay. The proposed solution operates continuously for 168 hours without accuracy drift, maintaining a stable steady-state control error within ±0.05%, requiring no additional compensation or calibration operations, and reducing the embedded chip's computing power utilization by 22%. While ensuring the real-time performance of industrial control, it improves the long-term iterative stability and control accuracy of the closed-loop control system.

[0014] 5.4 Iterative Simulation Example of Nonlinear Channel in Wireless Communication: This example conducts iterative simulation verification for time-varying nonlinear channels in 5G / 6G millimeter-wave wireless communication, testing long-time-series iterative extrapolation of channel parameters under multipath fading and Doppler shift interference. The experiment uniformly sets the upper limit threshold of the denominator of this invention to 10¹², with a total of 2000 iteration steps. The simulation accuracy and computational cost are compared between the traditional pure floating-point simulation iteration scheme and the hybrid anchoring scheme of this invention. Experimental results: With the increase of the number of iteration steps, the rounding error of the traditional pure floating-point iteration scheme continues to accumulate and amplify. After 2000 iterations, the channel parameter fitting error drifts to 4.2%, and the bit error rate simulation results are severely distorted. Mean filtering and iterative compensation algorithms are needed to correct the deviation, resulting in high computational cost and high simulation latency. The present invention blocks the accumulation of errors throughout the process, and the parameter fitting error is stably controlled within 0.3%. There is no progressive numerical drift, no need for additional compensation algorithms, and the simulation computing power is reduced by 18%. It improves the iterative stability and simulation accuracy of dynamic modeling of wireless channels and is suitable for millimeter-wave high-precision communication simulation research and development scenarios.

[0015] 5.5 Iterative Example of Meteorological Microscale Numerical Simulation: This example verifies nonlinear fluid dynamics iterative scenarios such as local microscale meteorological simulation, atmospheric turbulent wind fields, and short-term precipitation prediction. These systems are typical initial-condition sensitive chaotic systems, and long-term iterations are prone to error divergence. The experiment uniformly sets the upper limit threshold of the denominator of this invention to 10¹³ to match the high-precision requirements of meteorological simulation, comparing the long-term simulation effects of the traditional pure floating-point iteration scheme and the hybrid anchoring scheme of this invention. Experimental results: After three hours of continuous iterative simulation using the traditional pure floating-point scheme, small floating-point errors are exponentially amplified, causing wind field turbulence, cloud evolution trajectory deviation, and a significant decrease in forecast accuracy; frequent initial field resets and manual data correction are required, resulting in extremely high algorithm redundancy and computational consumption. The present invention can achieve stable iterative simulation for 12 consecutive hours. The turbulent field and meteorological evolution characteristics are consistent with real physical laws, without pseudo-chaotic disturbances and trajectory drift, and without the need for frequent calibration of the initial field. High-precision long-term meteorological iterative simulation can be completed by relying on mid-range servers, reducing the computing power cost of numerical forecasting and the workload of manual operation and maintenance.

[0016] 5.6 Number Theory Zero-Point Verification Example (Riemann Zeta Function): This example verifies the verification of large-scale numerical retrieval of nontrivial zeros of the Riemann Zeta function. Such academic numerical verification requires extremely long time-series iterations and extremely high numerical precision, with stringent requirements for iterative stability. The experiment uses a traditional scheme involving hundreds of digits of ultra-high precision large numbers as a control group, comparing the verification performance and computational cost of the two. Experimental Results: The traditional verification scheme uses ultra-high precision large number iterations throughout, resulting in huge computational costs, high redundancy in screening due to false zeros, and severe consumption of supercomputing resources. The proposed solution, through a successive bounded fraction anchoring mechanism, eliminates spurious disturbances and false zero-point offset anomalies generated by floating-point iterations. It eliminates the need for ultra-high precision large number operations throughout, reducing noise screening workload by over 90% and reducing the overall computational cost of the supercomputing cluster by over 70%. While maintaining the accuracy of number theory verification, it reduces the hardware cost and algorithm implementation difficulty of large-scale numerical iterative verification. Beneficial effects

[0017] This invention completely breaks through the inherent bottleneck of existing numerical iteration technology, achieves decoupling of computing power and accuracy, and has outstanding theoretical innovation and engineering application value. The specific beneficial effects are as follows.

[0018] 6.1 Eliminating artificially created spurious chaos and significantly improving numerical computation accuracy. This invention, through successive bounded rational number anchoring, breaks the chain of progressively amplified floating-point rounding errors, eliminates spurious chaos and numerical disturbances generated by finite-word-length computer operations, and retains only the original mathematical and physical evolutionary characteristics of the system in the iterative results. This solves the core problems of traditional floating-point iteration trajectory drift, feature ambiguity, and data distortion, and improves the computational accuracy of various nonlinear system iterations and large-scale numerical verifications.

[0019] 6.2 Reduce hardware computing power overhead and adapt to various computing devices. This solution uses general-purpose floating-point arithmetic instructions throughout, eliminating the need for dedicated large number arithmetic chips and ultra-high-precision computing clusters. Stable long-term iterations can be achieved using mid-range embedded automotive chips and ordinary servers. It eliminates the need for multi-layered redundant error correction and noise screening modules found in traditional solutions, reducing processor cache usage, pipeline load, and device power consumption, thereby lowering hardware procurement and maintenance costs. It is also suitable for resource-constrained embedded terminals and large-scale supercomputing verification scenarios.

[0020] 6.3 Balancing computational speed and numerical rigor, with broad industry applicability. The solution retains the advantages of high-speed floating-point operations and strong hardware versatility, as well as the rigorous characteristics of rational number operations with no approximation and no rounding deviation, resolving the contradiction of traditional technologies' "low efficiency in high-precision operations and poor accuracy in high-speed operations." It can be widely applied to high-precision nonlinear iterative scenarios such as autonomous driving trajectory prediction, chaotic dynamics simulation, industrial closed-loop control iteration, 5G / 6G wireless communication channel simulation, microscale meteorological numerical simulation, and large-scale number theory proof.

[0021] 6.4 Reduce the workload of algorithm development and numerical verification. This invention eliminates false numerical anomalies caused by floating-point errors at the source, eliminating the need for repeated manual optimization of initial conditions, superposition of multi-layer compensation algorithms, and secondary screening of massive amounts of distorted data. This reduces the development difficulty and manual workload of nonlinear system modeling and large-scale numerical proof, and has high academic research value and industrial application promotion value.

[0022] Those skilled in the art should understand that the present invention is not limited to the specific operational parameters, approximation algorithms, and application scenarios listed in the above embodiments. Without departing from the overall technical concept of the present invention, various equivalent transformations and adaptive modifications can be made to the floating-point precision bits, denominator threshold range, rational number approximation implementation method, and iterative control logic of the present invention, and all such modifications fall within the protection scope defined by the claims of the present invention.

Claims

1. A method for suppressing iterative errors using floating-point-fractional hybrid anchoring, characterized in that, This method is applicable to numerical calculations of nonlinear systems that are sensitive to initial conditions, exhibit chaotic characteristics, or require long-term iterative stability, and includes the following steps: S1. Initialize the initial values ​​of the iteration, the number of iterations, and the preset upper limit threshold of the denominator; S2. Perform a single nonlinear iterative calculation using floating-point format and obtain the floating-point operation result; S3. Convert the floating-point operation result into a simplest rational number approximation value whose denominator does not exceed the preset upper limit of the denominator, thereby eliminating the iteration error introduced by the truncation and rounding of floating-point data format; S4. Convert the purified simplest rational number into floating-point format and use it as the input value for the next iteration. Repeat steps S2-S3 until all preset iteration steps are completed, preventing the accumulation and amplification of errors throughout the process. S5. After the entire iteration process is completed, output the final iteration numerical results all at once.

2. The iterative error suppression method according to claim 1, characterized in that, The preset upper limit threshold for the denominator is set to 10¹²~10¹. 5 It can adaptively adjust to different application scenarios such as resource-constrained embedded terminals, large-scale supercomputing numerical verification, and real-time industrial control, taking into account both numerical purification accuracy and equipment computing power load.

3. The iterative error suppression method according to claim 1, characterized in that, The floating-point number format is any one of the following general-purpose hardware floating-point formats: 32-bit floating-point, 64-bit double-precision floating-point, or 80-bit extended-precision floating-point.

4. The iterative error suppression method according to claim 1, characterized in that, The simplest rational number approximation is calculated by a continued fraction approximation algorithm. This algorithm can achieve the global best rational approximation of floating-point values ​​under the condition of limiting the upper limit of the denominator, accurately eliminating the inherent error of floating-point operations and without introducing secondary deviations.

5. The iterative error suppression method according to claim 1, characterized in that, Throughout the entire iteration process, only the final output stage undergoes numerical format conversion, while the intermediate iteration calculation links continuously perform error anchoring and purification processing, with no cumulative rounding errors or computational pseudo-chaos interference throughout the entire process.

6. A floating-point-fractional hybrid anchored iterative arithmetic system for implementing the iterative error suppression method according to any one of claims 1-5, characterized in that, include: Floating-point high-speed operation module, fraction anchoring and purification module, iterative loop control module, result output module; The floating-point high-speed operation module is used to call general-purpose hardware floating-point instructions to complete various nonlinear iterative high-speed operations; the fraction anchoring and purification module is used to convert floating-point results into bounded simplest fractions to clear iteration errors; the iteration loop control module is used to manage the iteration process and realize successive error purification loops; the result output module is used to output the final result in a one-time visualization.

7. The iterative computation system according to claim 6, characterized in that, The system is suitable for nonlinear system operation scenarios with high requirements for iterative accuracy and stability, such as real-time prediction of autonomous driving topology trajectories, long-term simulation of chaotic dynamics, iterative industrial closed-loop control, simulation of nonlinear channels in 5G / 6G wireless communication, numerical simulation of microscale meteorology, and large-scale numerical verification of the zero point of the Riemann zeta function.