Ota upgrading method and device based on soc chip endogenous state perception and medium thereof

Abstract

The application relates to the technical field of vehicle lamps, in particular to an OTA upgrading method based on SOC chip endogenous state perception, equipment and a medium thereof. The method comprises the following steps: an SOC chip receives an upgrading instruction, determines whether the SOC chip meets an upgrading condition according to a constructed quantitative evaluation model, and proceeds to the next step if the condition is met; the resources of a communication interface, a storage unit and a clock module of the SOC chip are quantitatively self-checked, and the next step is entered if the requirement is met; a segmented receiving and inter-segment independent checking firmware loading strategy is adopted to obtain firmware data, and all the received firmware data of segments is integrated to obtain upgrading firmware; an upgrading firmware burning procedure with an environment marker is executed; a light control link is used to perform end-to-end closed loop verification on the upgraded SOC chip, and if the verification is passed, it is determined that the SOC chip upgrading is successful, and if the verification is not passed, an abnormal rollback procedure is triggered to perform abnormal positioning. The application improves the reliability of upgrading and can meet the requirements of vehicle-level functional safety.

Description

Technical Field

[0001] This invention relates to the field of automotive lighting technology, and in particular to an OTA upgrade method, device and medium based on SOC chip intrinsic state perception. Background Technology

[0002] As intelligent vehicle lighting evolves towards more advanced functions such as matrix LED dimming, ADB adaptive high beam, and dynamic light pattern control, automotive-grade System-on-Chips (SoCs) have become the core unit of vehicle lighting controllers, undertaking critical tasks such as light driving, algorithm calculation, fault diagnosis, and load management. Throughout the vehicle's lifecycle, SoC chip firmware needs to be remotely upgraded via Over-the-Air (OTA) to fix defects, optimize algorithms, and update parameters, ensuring the stability and safety of vehicle lighting functions and reducing after-sales maintenance costs.

[0003] As an external active safety component of a vehicle, the reliability of OTA (Over-The-Air) upgrades for vehicle lights is directly related to driving safety. Compared with ordinary vehicle ECUs, SOC chips operate in a more complex environment: they are constantly in alternating conditions of "low-power intermittent wake-up - high-load operation," and their operating status is significantly affected by intrinsic factors such as their own hardware health, Flash storage lifespan, power supply ripple fluctuations, and changes in ambient temperature. At the same time, SOC chips need to drive multiple high-power LED loads, and any abnormality during the upgrade process may cause light failure, flickering, or false lighting, leading to driving safety hazards.

[0004] Existing automotive OTA upgrade technologies are mostly geared towards general ECU designs, focusing on the basic process of "firmware transmission-verification-burning". They are not fully adapted to the unique operating characteristics and safety constraints of SOC chips, resulting in poor upgrade reliability and uncontrollable risks, and are difficult to meet automotive-grade functional safety requirements. Therefore, there is an urgent need to develop an OTA upgrade method based on the intrinsic state awareness of SOC chips. Summary of the Invention

[0005] The technical problem to be solved by this invention is: in order to solve the technical problems of poor upgrade reliability, uncontrollable risks and difficulty in meeting automotive-grade functional safety requirements in the existing technology, this invention provides an OTA upgrade method based on the intrinsic state awareness of SOC chip, which improves the reliability of upgrade and can meet automotive-grade functional safety requirements.

[0006] The technical solution adopted by this invention to solve its technical problem is: an OTA upgrade method based on the intrinsic state awareness of a SOC chip, the method comprising the following steps: S1. When the SOC chip receives an upgrade instruction, it determines whether the SOC chip meets the upgrade conditions based on the constructed quantitative evaluation model. If it does, it proceeds to the next step. S2, perform quantitative self-tests on the communication interface, storage unit, and clock module resources of the SOC chip respectively. If the requirements are met, proceed to the next step. S3 uses a firmware loading strategy of segmented reception and independent inter-segment verification to obtain firmware data transmitted from the cloud, and integrates all received firmware data segments to obtain upgrade firmware. S4 executes the upgrade firmware flashing process with environment tags. While flashing the upgrade firmware, it simultaneously records the environmental parameters and running status during the upgrade process to form an upgrade log. S5, execute the lighting control link to perform end-to-end closed-loop verification of the upgraded SOC chip. If the verification passes, the SOC chip upgrade is determined to be successful. If the verification fails, the abnormal rollback process is triggered to locate the abnormality.

[0007] This invention presents an OTA upgrade method based on the intrinsic state perception of the SOC chip. It makes upgrade access decisions based on the intrinsic health status of the vehicle's lighting SOC, quantitatively assessing the SOC's stability through a comprehensive health coefficient. This avoids initiating upgrades when the SOC is unstable, improving the rationality of upgrade timing, reducing the risk of upgrade failure, and meeting automotive-grade functional safety requirements. Before the upgrade, a dedicated system self-check identifies potential risks in core modules such as communication, storage, and clock, mitigating upgrade failures at the source and improving the robustness and reliability of the upgrade process. After the upgrade, closed-loop verification of the lighting control link ensures the core functions are truly usable after firmware flashing, avoiding hidden faults after the upgrade, guaranteeing normal operation of the vehicle lights, and improving driving safety.

[0008] Furthermore, specifically, step S1 includes the following steps: S11, a quantitative evaluation model is constructed using the weighted summation method, expressed by the following formula:

[0009] in, To assess overall health, The fault state coefficient, To store health coefficients, The environmental stability coefficient, K1, K2 and K3 are weighted coefficients, satisfying K1+K2+K3=1; S12, the SOC chip obtains an upgrade instruction, inputs the current SOC chip endogenous state into the quantitative evaluation model for calculation, and obtains the current comprehensive health coefficient; S13, compare the current comprehensive health coefficient S with the preset health threshold S th Compare; like If the SOC chip's intrinsic state meets the upgrade conditions, proceed to the next step. like If the SOC chip's intrinsic state does not meet the upgrade conditions, the SOC chip will report the intrinsic state abnormality to the cloud, and the evaluation will be retried after the SOC chip's intrinsic state is restored.

[0010] Furthermore, specifically, step S2 includes the following steps: S21, calculate the current communication bit error rate between the SOC chip and the vehicle communication module. The calculation formula is as follows:

[0011] in, This represents the number of frames that failed to be verified by the receiver during the continuous transmission of N frames of verification data. N is the total number of frames sent; S22, calculate the current bad block rate of the storage unit's storage partition, using the following formula:

[0012] in, This represents the number of non-writable and non-readable storage blocks detected by the storage cell self-test command. The total number of storage blocks for the Flash upgrade partition; S23, calculate the current clock frequency deviation within the clock module, using the following formula:

[0013] in, The clock frequency is collected in real time from the SOC chip. This is the standard clock frequency for SOC chips; S24, the current communication bit error rate With bit error rate threshold Compare the current bad block rate With bad block rate threshold Compare the current clock frequency deviation. Clock frequency deviation threshold Compare; when < and and < If the SOC chip meets the upgrade requirements, the process proceeds to the next step; otherwise, the upgrade process is terminated.

[0014] Furthermore, specifically, step S3 includes the following steps: S31 divides the upgrade firmware delivered from the cloud into multiple logical segments according to functional domains, and the capacity of the upgrade firmware is the sum of the capacities of each logical segment. S32 divides the firmware structure of the SOC chip into logic segments, namely the driver logic segment, dimming algorithm segment, fault diagnosis segment, and configuration parameter segment. S33, the cloud sends each of the aforementioned logic segments to the SOC chip sequentially via the vehicle communication module; S34, while receiving the logic segment, the SOC chip also verifies the logic segment to obtain the verification value of the logic segment; S35, compare the check value of the logical segment with the firmware check value transmitted from the cloud. If they are the same, then the data in the current logical segment is correct, and the process proceeds to the next logical segment receiving process; Conversely, if the current logical segment is not found, a retransmission request is sent to the cloud via the vehicle communication module. S36. After the SOC chip has received all the logic segments, the SOC chip integrates all the logic segments into upgrade firmware and stores the upgrade firmware in the temporary cache area of ​​the storage unit.

[0015] Furthermore, specifically, step S4 includes the following steps: S41, the SOC chip performs an erase operation on the upgrade partition of the storage unit and checks whether the upgrade partition has been completely erased. If so, it proceeds to the next step; otherwise, it continues the erase operation. S42 controls the vehicle communication module, storage unit, and status detection module to remain in working state, and shuts down external devices that are not involved in the upgrade; S43 adopts a block-based writing and real-time verification burning mode, which divides the upgrade firmware into multiple burning blocks and writes them one by one to the upgrade partition of the storage unit. S44: When burning each writing block, obtain the data of the writing block and compare it with the corresponding block data in the temporary buffer. If they are the same, proceed to the next writing block; otherwise, re-burn. S45, during the burning process of the burning block, the SOC chip synchronously collects and writes the upgrade environment flag word through the status detection module. The flag word is bound to the upgrade firmware and stored in the dedicated log partition of the storage unit.

[0016] S46, after all the programming blocks have been programmed, the SOC chip saves the upgrade status flag, forming a complete upgrade log, and marks the firmware status of the Flash upgrade partition as "pending verification".

[0017] Furthermore, specifically, step S5 includes the following steps: S51 initializes all external devices, including LED light-emitting modules and fault diagnosis modules; S52, the SOC chip sends standard dimming commands to all LED light-emitting modules, the LED light-emitting modules execute the standard dimming commands, and the SOC chip collects the actual output feedback signals of the LED light-emitting modules and the actual output timing of each channel; S53 calculates the drive command deviation based on the standard dimming command and the actual output feedback signal of the LED light-emitting module. The calculation formula is:

[0018] in, Feedback signal for LED light-emitting module The standard dimming duty cycle value issued; S54, Calculate the timing difference between adjacent channels based on the actual output timing of each channel. t ; The S55 SOC chip simulates a vehicle headlight malfunction and detects the response time T of the fault diagnosis module. err Output the fault type; S56, drive command deviation Deviation threshold from drive command Compare the timing differences between adjacent channel outputs. t With respect to the set timing difference threshold t th Compare the response time T of the fault diagnosis module. err With fault response time threshold T th The comparison involves comparing the fault type with the simulated fault type. and t≤ t th And T err ≤ T th If the fault type matches the simulated fault type output, the verification is successful, and the SOC chip upgrade is considered successful; otherwise, the abnormal rollback process is triggered to locate the abnormality.

[0019] Furthermore, specifically, a hierarchical quantitative diagnostic method is adopted, combined with the upgrade logs, to locate anomalies.

[0020] Furthermore, specifically, the hierarchical quantitative diagnostic method, combined with the upgrade logs, for anomaly localization includes the following steps: Current communication bit error rate ≥Bit error rate threshold If the number of retransmissions of a logical segment exceeds 3, the communication transmission is determined to be abnormal. When the block writing verification fails and the number of writing attempts exceeds the limit, or the storage unit has a high bad block rate... If there is a timing error during the burning process, the memory burning process is determined to be abnormal. when , t or T err If any one of the requirements is not met, it is determined that the firmware is incompatible or the driver link is abnormal. All anomalies are generated into standardized fault codes, along with upgrade environment markers, upgrade logs, and quantitative indicator data, and then uploaded to cloud storage.

[0021] A computer device, comprising: processor; Memory, used to store executable instructions; The processor is used to read the executable instructions from the memory and execute the executable instructions to implement the OTA upgrade method based on the intrinsic state awareness of the SOC chip as described above.

[0022] A computer-readable storage medium storing a computer program that, when executed by a processor, causes the processor to implement the OTA upgrade method based on the intrinsic state awareness of a SOC chip as described above.

[0023] The beneficial effects of this invention are: 1. This invention realizes upgrade access decision based on the inherent health status of the vehicle headlight SOC. By comprehensively evaluating the stability of the SOC itself through a health coefficient, it avoids initiating upgrades when the SOC is unstable, improves the rationality of upgrade timing, reduces the risk of upgrade failure, and meets automotive-grade functional safety requirements. 2. By conducting a special self-inspection of the system before the upgrade, potential risks in core modules such as communication, storage, and clock can be identified in advance, avoiding upgrade failures from the source and improving the robustness and reliability of the upgrade process; 3. After the upgrade, the core functions are verified through a closed-loop system of the lighting control link to ensure that the firmware is truly usable after flashing, avoid hidden faults after the upgrade, ensure the normal operation of the headlights, and improve driving safety. Attached Figure Description

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] Figure 1 This is a schematic diagram of the method flow of Embodiment 1 of the present invention.

[0026] Figure 2 This is a detailed flowchart of step S1 in Embodiment 1 of the present invention.

[0027] Figure 3This is a detailed flowchart of step S3 in Embodiment 1 of the present invention.

[0028] Figure 4 This is a detailed flowchart of step S4 in Embodiment 1 of the present invention.

[0029] Figure 5 This is a schematic diagram of the computer device structure according to Embodiment 2 of the present invention.

[0030] In the diagram, 10 is a computer device; 1002 is a processor; 1004 is a memory; and 1006 is a transmission device. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0032] Example 1: This invention provides an OTA upgrade method based on SOC chip intrinsic state awareness, such as... Figure 1 As shown, the method includes the following steps: S1. When the SOC chip receives an upgrade instruction, it determines whether the SOC chip meets the upgrade conditions based on the constructed quantitative evaluation model. If it does, it proceeds to the next step. S2, performs quantitative self-tests on the resources of the SOC chip's communication interface, storage unit, and clock module respectively. If the requirements are met, proceed to the next step. S3 uses a firmware loading strategy of segmented reception and independent inter-segment verification to obtain firmware data transmitted from the cloud, and integrates all received firmware data segments to obtain upgrade firmware. S4 executes the upgrade firmware flashing process with environment tags. While flashing the upgrade firmware, it simultaneously records the environmental parameters and running status during the upgrade process to form an upgrade log. S5 executes the lighting control link to perform end-to-end closed-loop verification of the upgraded SOC chip. If the verification passes, the SOC chip upgrade is considered successful. If the verification fails, the abnormal rollback process is triggered to locate the abnormality.

[0033] Specifically, such as Figure 2 As shown, in step S1, when the SOC chip receives an upgrade instruction, determining whether the SOC chip meets the upgrade conditions based on the constructed quantitative evaluation model specifically includes the following steps: S11, a quantitative evaluation model is constructed using the weighted summation method, expressed by the following formula:

[0034] in, To assess overall health, The fault state coefficient, To store health coefficients, The environmental stability coefficient, K1, K2 and K3 are weighted coefficients, which satisfy K1+K2+K3=1. For example, the values ​​of K1, K2 and K3 are K1=0.4, K2=0.3 and K3=0.3 respectively, to ensure the safety of the drive link.

[0035] Furthermore, the fault state coefficient The value ranges from [0,1] and is calculated based on the number of recent failures and the frequency of driver errors. The fewer the failures and the lower the error frequency, the better. The closer it is to 1. The calculation formula is:

[0036] in, This represents the number of failures in the vehicle lighting control link within the past hour. To drive the error reporting frequency (unit: times / minute). To drive the error reporting frequency threshold (unit: times / minute), such as , T The fault statistics period is T=60 minutes.

[0037] Storage health coefficient The value ranges from [0,1] and is calculated based on the flash memory's erase / write lifespan consumption rate and ECC error count. Lower memory consumption results in fewer ECC errors. The closer it is to 1. The calculation formula is:

[0038] in, The write / erase cycle consumption rate of a storage cell is calculated as "cumulative write / erase cycles ÷ total write / erase cycle life (standard 1000 cycles)," which directly reflects the aging degree of the storage cell. ECC (Error Checking and Correction) error count (unit: errors / hour) is provided by the SOC chip, which monitors the number of Flash data read / write errors in real time to reflect storage reliability. ECC error count threshold (unit: errors / hour) ,when > If this happens, the storage unit is determined to be unstable, and the upgrade needs to be paused.

[0039] Environmental stability coefficient The value range is [0,1], calculated from the SOC chip's operating temperature and power supply ripple. The closer the temperature is to the optimal operating range, the smaller the ripple. The closer to 1, The calculation formula is:

[0040] in, The real-time operating temperature of the SOC chip is collected in real time by the built-in temperature sensor of the SOC chip, and the unit is °C. The preset operating temperature for the SOC chip is typically set to the standard operating temperature of 25°C. This represents the power supply ripple amplitude, in volts (V). This is the temperature effect coefficient, with a value of 0.02, used to quantify the impact of temperature deviation from the optimal value on the stability of the SOC chip. The power supply ripple influence coefficient is preferably set to 0.1, which is used to quantify the attenuation effect of power supply ripple on the stability of the SOC chip.

[0041] S12, the SOC chip obtains the upgrade instruction, inputs the current SOC chip's intrinsic state into the quantitative evaluation model for calculation, and obtains the current comprehensive health coefficient; S13, compare the current comprehensive health coefficient S with the preset health threshold S th In comparison, in this embodiment, a preset health threshold S is used. th Setting it to 0.8 allows for dynamic adjustment of the health threshold S based on different SOC chip models. th .

[0042] like If the SOC chip's intrinsic state meets the upgrade conditions, proceed to the next step; if... If the SOC chip's intrinsic state does not meet the upgrade conditions, the SOC chip will report the intrinsic state abnormality to the cloud, and the evaluation will be retried after the SOC chip's intrinsic state is restored.

[0043] Specifically, step S2 involves performing a quantitative self-test on the resources of the SOC chip's communication interface, storage unit, and clock module, which includes the following steps: S21, calculate the current communication bit error rate between the SOC chip and the vehicle communication module. The stability of the communication link between the SOC chip and the vehicle communication module is detected by calculating the current communication bit error rate. The formula for calculating the current communication bit error rate is:

[0044] in, This represents the number of frames that failed to be verified by the receiver during the continuous transmission of N frames of verification data. The total number of frames sent is N. For example, if N=100, the frame length of each frame is 64 bytes.

[0045] S22, calculate the current bad block rate of the storage unit's storage partition. This calculation performs a self-test on the storage unit, checking the writability and integrity of the storage partition. The formula for calculating the current bad block rate is:

[0046] in, This represents the number of non-writable and non-readable storage blocks detected by the storage cell self-test command. The total number of storage blocks for the Flash upgrade partition, with each storage block being 512 bytes in size.

[0047] S23, calculate the current clock frequency deviation within the clock module. The stability of the core clock inside the SOC chip is detected by calculating the current clock frequency deviation. The formula for calculating the current clock frequency deviation is:

[0048] in, The clock frequency is collected in real time from the SOC chip. This refers to the standard clock frequency of the SOC chip, such as; .

[0049] S24, the current communication bit error rate With bit error rate threshold Compare the current bad block rate With bad block rate threshold Compare the current clock frequency deviation. Clock frequency deviation threshold Compare; when < and and < If the SOC chip meets the upgrade requirements, the process proceeds to the next step; otherwise, the upgrade process is terminated.

[0050] It should be noted that, < Used to determine if the communication interface self-test passes and the communication link is stable. Used to determine if the storage unit has passed the self-test. < Used to determine if the clock module passes self-test, only when... < and and < If the SOC chip meets the upgrade conditions, it will send an upgrade ready signal to the vehicle communication module and start the subsequent firmware receiving process. Otherwise, if any condition is not met, the upgrade process will be terminated and a clock error message will be reported.

[0051] In this embodiment, Set to 10 -5 , Set to 0.01, Set to 0.001.

[0052] Specifically, step S3 employs a segmented reception and inter-segment independent verification firmware loading strategy to obtain firmware data transmitted from the cloud. This avoids the problems of invalid data reception consuming significant system resources and delayed anomaly identification in the traditional "full reception-overall verification" mode. It enables early identification of firmware transmission anomalies, improving upgrade fault tolerance and resource utilization. Figure 3 As shown, step S3 specifically includes the following steps: S31 divides the upgrade firmware delivered from the cloud into multiple logical segments according to functional domains. The capacity of the upgrade firmware is the sum of the capacities of each logical segment. The number of multiple logical segments is 4 to 8, and the size of each logical segment is 128KB-512KB.

[0053] S32 divides the firmware structure of the SOC chip into four segments: driver logic segment, dimming algorithm segment, fault diagnosis segment, and configuration parameter segment. This step facilitates segmented verification and anomaly location in subsequent steps.

[0054] S33, the cloud sends each logical segment to the SOC chip sequentially through the vehicle communication module; S34, while receiving the logic segment, the SOC chip also uses the CRC32 checksum algorithm to verify the logic segment and obtain its checksum value. This verification helps prevent the accumulation of invalid data. Furthermore, the expression for the CRC32 checksum algorithm is:

[0055] in, For the complete data of the i-th logical segment, CRC32 is a cyclic redundancy check algorithm, and the check value is calculated using the standard CRC32 polynomial (0xEDB88320). .

[0056] It should be noted that in some embodiments, MD5, SHA-256, and other verification algorithms can be used instead of CRC32 verification to improve verification accuracy and adapt to high-end, high-computing-power SOC chips. S35 compares the checksum of the logical segment with the firmware checksum transmitted to the cloud. If they are the same, the data of the current logical segment is correct, and the process proceeds to the next logical segment receiving process; otherwise, the current logical segment is discarded, and a retransmission request is sent to the cloud through the vehicle communication module.

[0057] In this embodiment, the maximum number of retransmissions is set to 3. If the verification still fails after the maximum number of retransmissions is exceeded, the firmware transmission is determined to be abnormal, the upgrade process is terminated, and the transmission abnormality information is reported.

[0058] S36. After the SOC chip has received all the logic segments, it integrates all the logic segments into upgrade firmware and stores the upgrade firmware in the temporary cache area of ​​the storage unit.

[0059] Specifically, such as Figure 4 As shown, step S4 specifically includes the following steps: S41, the SOC chip performs an erase operation on the upgrade partition of the storage unit and checks whether the upgrade partition has been completely erased. If so, it proceeds to the next step; otherwise, it continues the erase operation. S42 controls the vehicle communication module, storage unit, and status detection module to remain in working state, and shuts down external devices not involved in the upgrade, in order to reduce power consumption and interference during the upgrade process.

[0060] S43 adopts a block-based writing and real-time verification burning mode, dividing the upgrade firmware into multiple burning blocks and writing them one by one to the upgrade partition of the storage unit; furthermore, the upgrade firmware is divided into multiple burning blocks of 512 bytes / block.

[0061] S44: When programming each programming block, the data of the programming block is obtained and compared with the corresponding block data in the temporary cache. If they are the same, the programming proceeds to the next programming block; otherwise, the programming is re-programmed. In this embodiment, the maximum number of re-programming attempts is 3. If the maximum number is exceeded, the programming is determined to be abnormal, and the upgrade process is terminated.

[0062] S45, during the burning process of the burning block, the SOC chip synchronously collects and writes the upgrade environment flag word through the status detection module. The flag word is bound to the upgrade firmware and stored in a dedicated log partition of the storage unit. The dedicated log partition specifically includes: the operating temperature range of the SOC chip during the upgrade, the power supply voltage range, the reception time of each firmware segment, the total firmware burning time, and abnormal records during the burning process (such as the number of burning block rewrites).

[0063] S46, after all programming blocks have been programmed, the SOC chip saves upgrade status flags (such as programming success / failure, number of segments completed, and environmental parameters) to form a complete upgrade log, and marks the firmware status of the Flash upgrade partition as "pending verification".

[0064] In this embodiment, after the firmware is loaded, a firmware flashing process with environment tags is executed. While flashing the firmware, the environmental parameters and running status during the upgrade process are recorded simultaneously to form a traceable upgrade log, which facilitates the root cause location of subsequent upgrade anomalies.

[0065] Specifically, step S5 executes end-to-end closed-loop verification of the upgraded SOC chip through the lighting control link. Using multi-dimensional quantitative indicators, it verifies the actual usability of core functions such as lighting drive, dimming logic, and fault diagnosis after firmware flashing, thus avoiding hidden faults after the upgrade. Step S5 includes the following steps: S51 initializes all external devices, including LED lighting modules and fault diagnosis modules; this step restores the basic system functions and enters closed-loop verification mode. At this time, the advanced functions of the vehicle lights are not activated, and only the basic driving capabilities are retained.

[0066] S52, the SOC chip sends standard dimming commands to all LED light-emitting modules, the LED light-emitting modules execute the standard dimming commands, and the SOC chip collects the actual output feedback signals of the LED light-emitting modules and the actual output timing of each channel; S53 calculates the drive command deviation based on the standard dimming command and the actual output feedback signal of the LED light-emitting module. The calculation formula is:

[0067] in, Feedback signal for LED light-emitting module The standard dimming duty cycle value issued; S54, Calculate the timing difference between adjacent channels based on the actual output timing of each channel. t ; The S55 SOC chip simulates vehicle headlight faults, including but not limited to open circuits in the drive channel and short circuits in the light load. The response time T of the fault diagnosis module is [not specified]. err Output the fault type; S56, drive command deviation Deviation threshold from drive command Compare the timing differences between adjacent channel outputs. t With respect to the set timing difference threshold t th Compare the response time T of the fault diagnosis module. err With fault response time threshold T th The comparison involves comparing the fault type with the simulated fault type. and t≤ t th And T err ≤ T thIf the fault type matches the simulated fault type output, the verification is successful and the SOC chip upgrade is considered successful; otherwise, if any requirement is not met, the abnormal rollback process is triggered to locate the fault.

[0068] In other words, only and t≤ t th And T err ≤ T th The verification is successful only when the fault type matches the simulated fault type output. The SOC chip then marks the new firmware as valid, updates the firmware status of the Flash partition to "effective," restores all high-level functions of the headlights, and updates the upgrade status to "upgrade successful." If any verification fails, an abnormal rollback process is immediately executed, switching back to the old firmware to ensure the headlights function remains functional. In this embodiment, , t th =10us, T th =100ms.

[0069] Specifically, a hierarchical quantitative diagnostic method is adopted, combined with upgrade logs for anomaly localization. For various anomalies that may occur during the upgrade process (transmission anomalies, burning anomalies, verification anomalies), this embodiment can accurately identify the anomaly type and determine the anomaly level through the hierarchical quantitative diagnostic method. Combined with upgrade logs and environment markers, it enables full traceability of anomalies, facilitating rapid location of the cause of anomalies. This provides data support for firmware iteration and optimization, reduces troubleshooting costs, and improves the maintainability of OTA upgrades. The specific steps include: Current communication bit error rate ≥Bit error rate threshold If the number of retransmissions of a logical segment exceeds 3, the communication transmission is determined to be abnormal. The traceability indicators include the communication error rate, transmission time, and power supply ripple during the upgrade.

[0070] When the block writing verification fails and the number of writing attempts exceeds the limit, or the storage unit has a high bad block rate... If there is a timing error during the burning process, the storage burning is determined to be abnormal. The traceability indicators include the storage bad block rate, the burning environment temperature and voltage.

[0071] when , t or T err If one of the requirements is not met, that is ,or t≤ tth Or T err ≤ T th To determine if the firmware is incompatible or the driver link is abnormal, the traceability indicators include driver instruction deviation, timing difference, and fault response time.

[0072] All anomalies are generated into standardized fault codes, along with upgrade environment markers, upgrade logs, and quantitative indicator data, and uploaded to cloud storage. This facilitates staff in troubleshooting the root causes of anomalies and provides data support for firmware iteration and optimization. At the same time, the SOC chip is prohibited from automatically retrying upgrades to avoid repeated failures exacerbating system risks.

[0073] In summary, the OTA upgrade method based on SOC chip intrinsic state awareness in this embodiment makes upgrade access decisions based on the intrinsic health status of the vehicle headlight SOC. It quantitatively assesses the stability of the SOC through a comprehensive health coefficient, avoiding upgrades when the SOC is unstable, thus improving the rationality of upgrade timing, reducing the risk of upgrade failure, and meeting automotive-grade functional safety requirements. Pre-upgrade system self-checks identify potential risks in core modules such as communication, storage, and clock, preventing upgrade failures at the source and improving the robustness and reliability of the upgrade process. Post-upgrade, closed-loop verification of the headlight control link ensures the core functions are truly usable after firmware flashing, avoiding hidden faults after the upgrade, ensuring normal headlight operation, and improving driving safety.

[0074] Example 2: This application provides a computer device including a processor and a memory. The memory stores at least one instruction or at least one program. The at least one instruction or at least one program is loaded and executed by the processor to implement an OTA upgrade method based on the intrinsic state awareness of a SOC chip as provided in the above method embodiments.

[0075] Figure 5 This diagram illustrates a hardware structure of a device for implementing an OTA upgrade method based on SOC chip intrinsic state awareness provided in the embodiments of this application. The device can participate in or include the apparatus or system provided in the embodiments of this application. Figure 5As shown, the computer device 10 may include one or more processors 1002 (the processor may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.), a memory 1004 for storing data, and a transmission device 1006 for communication functions. In addition, it may also include: a display, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, a power supply, and / or a camera. Those skilled in the art will understand that... Figure 5 The structure shown is for illustrative purposes only and does not limit the structure of the aforementioned electronic device. For example, computer device 10 may also include... Figure 5 The more or fewer components shown, or having the same Figure 5 The different configurations shown.

[0076] It should be noted that the aforementioned one or more processors and / or other data processing circuits are generally referred to herein as "data processing circuits". These data processing circuits may be embodied, in whole or in part, in software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuit may be a single, independent processing module, or may be integrated, in whole or in part, into any other element within the computer device 10 (or mobile device). As involved in the embodiments of this application, the data processing circuit serves as a processor control mechanism (e.g., selection of a variable resistor termination path connected to an interface).

[0077] The memory 1004 can be used to store software programs and modules for application software, such as the program instruction / data storage device corresponding to an OTA upgrade method based on the intrinsic state awareness of a SOC chip in this embodiment of the application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 1004, thereby implementing the aforementioned method. The memory 1004 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 1004 may further include memory remotely located relative to the processor, and these remote memories can be connected to the computer device 10 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0078] The transmission device 1006 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by the communication provider of the computer device 10. In one example, the transmission device 1006 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 1006 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0079] The display may be, for example, a touchscreen liquid crystal display (LCD) that allows the user to interact with the user interface of the computer device 10 (or mobile device).

[0080] Example 3: This application embodiment also provides a computer-readable storage medium, which can be disposed in a server to store at least one instruction or at least one program related to implementing an OTA upgrade method based on SOC chip intrinsic state awareness in the method embodiment. The at least one instruction or the at least one program is loaded and executed by the processor to implement the OTA upgrade method based on SOC chip intrinsic state awareness provided in the above method embodiment.

[0081] Optionally, in this embodiment, the storage medium may be located at at least one of the multiple network servers in a computer network. Optionally, in this embodiment, the storage medium may include, but is not limited to, various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0082] Example 4: This invention also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform an OTA upgrade method based on the intrinsic state awareness of a SOC chip provided in the various optional embodiments described above.

[0083] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, the above description focuses on specific embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired results. In some implementations, multitasking and parallel processing are also possible or may be advantageous.

[0084] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device, equipment, and storage medium embodiments are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0085] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0086] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. An OTA upgrade method based on SOC chip intrinsic state awareness, characterized in that, The method includes the following steps: S1. When the SOC chip receives an upgrade instruction, it determines whether the SOC chip meets the upgrade conditions based on the constructed quantitative evaluation model. If it does, it proceeds to the next step. S2, perform quantitative self-tests on the communication interface, storage unit, and clock module resources of the SOC chip respectively. If the requirements are met, proceed to the next step. S3 uses a firmware loading strategy of segmented reception and independent inter-segment verification to obtain firmware data transmitted from the cloud, and integrates all received firmware data segments to obtain upgrade firmware. S4 executes the upgrade firmware flashing process with environment tags. While flashing the upgrade firmware, it simultaneously records the environmental parameters and running status during the upgrade process to form an upgrade log. S5, execute the lighting control link to perform end-to-end closed-loop verification of the upgraded SOC chip. If the verification passes, the SOC chip upgrade is determined to be successful. If the verification fails, the abnormal rollback process is triggered to locate the abnormality.

2. The OTA upgrade method based on SOC chip intrinsic state awareness according to claim 1, characterized in that, Step S1 specifically includes the following steps: S11, a quantitative evaluation model is constructed using the weighted summation method, expressed by the following formula: in, To assess overall health, The fault state coefficient, To store health coefficients, The environmental stability coefficient, K1, K2 and K3 are weighted coefficients, satisfying K1+K2+K3=1; S12, the SOC chip obtains an upgrade instruction, inputs the current SOC chip endogenous state into the quantitative evaluation model for calculation, and obtains the current comprehensive health coefficient; S13, compare the current comprehensive health coefficient S with the preset health threshold S th Compare; like If the SOC chip's intrinsic state meets the upgrade conditions, proceed to the next step. like If the SOC chip's intrinsic state does not meet the upgrade conditions, the SOC chip will report the intrinsic state abnormality to the cloud, and the evaluation will be retried after the SOC chip's intrinsic state is restored.

3. The OTA upgrade method based on SOC chip intrinsic state awareness according to claim 1, characterized in that, Step S2 specifically includes the following steps: S21, calculate the current communication bit error rate between the SOC chip and the vehicle communication module. The calculation formula is as follows: in, This represents the number of frames that failed to be verified by the receiver during the continuous transmission of N frames of verification data. N is the total number of frames sent; S22, calculate the current bad block rate of the storage unit's storage partition, using the following formula: in, This represents the number of non-writable and non-readable storage blocks detected by the storage cell self-test command. The total number of storage blocks for the Flash upgrade partition; S23, calculate the current clock frequency deviation within the clock module, using the following formula: in, The clock frequency is collected in real time from the SOC chip. This is the standard clock frequency for SOC chips; S24, the current communication bit error rate With bit error rate threshold Compare the current bad block rate With bad block rate threshold Compare the current clock frequency deviation. Clock frequency deviation threshold Compare; when < and and < If the SOC chip meets the upgrade requirements, the process proceeds to the next step; otherwise, the upgrade process is terminated.

4. The OTA upgrade method based on SOC chip intrinsic state awareness according to claim 1, characterized in that, Step S3 specifically includes the following steps: S31 divides the upgrade firmware delivered from the cloud into multiple logical segments according to functional domains, and the capacity of the upgrade firmware is the sum of the capacities of each logical segment. S32 divides the firmware structure of the SOC chip into logic segments, namely the driver logic segment, dimming algorithm segment, fault diagnosis segment, and configuration parameter segment. S33, the cloud sends each of the aforementioned logic segments to the SOC chip sequentially via the vehicle communication module; S34, while receiving the logic segment, the SOC chip also verifies the logic segment to obtain the verification value of the logic segment; S35, compare the check value of the logical segment with the firmware check value transmitted in the cloud; If they are the same, then the data in the current logical segment is correct, and the process proceeds to the next logical segment receiving process; Conversely, if the current logical segment is not found, a retransmission request is sent to the cloud via the vehicle communication module. S36. After the SOC chip has received all the logic segments, the SOC chip integrates all the logic segments into upgrade firmware and stores the upgrade firmware in the temporary cache area of ​​the storage unit.

5. The OTA upgrade method based on SOC chip intrinsic state awareness according to claim 1, characterized in that, Step S4 specifically includes the following steps: S41, the SOC chip performs an erase operation on the upgrade partition of the storage unit and checks whether the upgrade partition has been completely erased. If so, it proceeds to the next step; otherwise, it continues the erase operation. S42 controls the vehicle communication module, storage unit, and status detection module to remain in working state, and shuts down external devices that are not involved in the upgrade; S43 adopts a block-based writing and real-time verification burning mode, which divides the upgrade firmware into multiple burning blocks and writes them to the storage unit upgrade partition one by one. S44: When burning each writing block, obtain the data of the writing block and compare it with the corresponding block data in the temporary buffer. If they are the same, proceed to the next writing block; otherwise, re-burn. S45, during the burning process of the burning block, the SOC chip synchronously collects and writes the upgrade environment flag word through the status detection module. The flag word is bound to the upgrade firmware and stored in the dedicated log partition of the storage unit. S46, after all the programming blocks have been programmed, the SOC chip saves the upgrade status flag, forming a complete upgrade log, and marks the firmware status of the Flash upgrade partition as pending verification.

6. The OTA upgrade method based on SOC chip intrinsic state awareness according to claim 1, characterized in that, Step S5 specifically includes the following steps: S51 initializes all external devices, including LED light-emitting modules and fault diagnosis modules; S52, the SOC chip sends standard dimming commands to all LED light-emitting modules, the LED light-emitting modules execute the standard dimming commands, and the SOC chip collects the actual output feedback signals of the LED light-emitting modules and the actual output timing of each channel; S53 calculates the drive command deviation based on the standard dimming command and the actual output feedback signal of the LED light-emitting module. The calculation formula is: in, Feedback signal for LED light-emitting module This refers to the standard dimming duty cycle value issued. S54, Calculate the timing difference between adjacent channels based on the actual output timing of each channel. t ; The S55 SOC chip simulates a vehicle headlight malfunction and detects the response time T of the fault diagnosis module. err Output the fault type; S56, drive command deviation Deviation threshold from drive command Compare the timing differences between adjacent channel outputs. t With respect to the set timing difference threshold t th Compare the response time T of the fault diagnosis module. err With fault response time threshold T th The comparison involves comparing the fault type with the simulated fault type. when and t≤ t th And T err ≤ T th If the fault type matches the simulated fault type output, the verification is successful, and the SOC chip upgrade is considered successful; otherwise, the abnormal rollback process is triggered to locate the abnormality.

7. The OTA upgrade method based on SOC chip intrinsic state awareness according to claim 1 or 6, characterized in that, A hierarchical quantitative diagnostic method was adopted, combined with the upgrade log, to locate the anomaly.

8. The OTA upgrade method based on SOC chip intrinsic state awareness according to claim 7, characterized in that, The hierarchical quantitative diagnostic method, combined with the upgrade logs, is used to locate anomalies, specifically including the following steps: Current communication bit error rate ≥Bit error rate threshold If the number of retransmissions of a logical segment exceeds 3, the communication transmission is determined to be abnormal. When the block writing verification fails and the number of writing attempts exceeds the limit, or the storage unit has a high bad block rate... If there is a timing error during the burning process, the memory burning process is determined to be abnormal. when , t or T err If any one of the requirements is not met, it is determined that the firmware is incompatible or the driver link is abnormal. All anomalies are generated into standardized fault codes, along with upgrade environment markers, upgrade logs, and quantitative indicator data, and then uploaded to cloud storage.

9. A computer device, characterized in that, include: processor; Memory, used to store executable instructions; The processor is configured to read the executable instructions from the memory and execute the executable instructions to implement the OTA upgrade method based on the intrinsic state awareness of the SOC chip as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to implement the OTA upgrade method based on the intrinsic state awareness of a SOC chip as described in any one of claims 1 to 8.

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