Non-blocking risc-v shadow stack instruction processing method, apparatus and device

Abstract

Embodiments of the present application provide a non-blocking RISC-V shadow stack instruction processing method, device and equipment, relating to the technical field of computers, and applied to the SSP logical register established in the processor. The method comprises: identifying the type of the target instruction entering the decoding stage to determine the instruction type of the target instruction; if the target instruction is a shadow stack instruction type or a CSR instruction type, the target instruction is converted into an internal data flow operation instruction; the internal data flow operation instruction is renamed based on the current speculation mapping of the SSP logical register to obtain a renamed internal data flow operation instruction; and the renamed internal data flow operation instruction is dispatched to the execution path corresponding to the renamed internal data flow operation instruction to obtain the execution result corresponding to the renamed internal data flow operation instruction. The present application can improve the overall running performance of the processor.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and more specifically, the embodiments of the present invention relate to an instruction processing method, apparatus and device for a non-blocking RISC-V shadow stack. Background Technology

[0002] The RISC-V architecture introduces a Shadow Stack (SS) extension mechanism to ensure the integrity of control flow during function calls and returns, and to defend against control flow hijacking attacks caused by tampering with regular stack data. This mechanism relies on a dedicated shadow stack and a Shadow Stack Pointer (SSP) to implement the protection logic.

[0003] Currently, the industry standard implementation treats the SSP as a Control and Status Register (CSR). Because CSR registers have strict serial access constraints, instructions that read or write to the SSP must wait for the preceding instructions to complete commit and the CSR state to stabilize before execution. Simultaneously, subsequent instructions that depend on the SSP state also experience long wait times. In application scenarios with intensive function calls and return operations, SSP-related instructions and SSP-related CSR read / write instructions are frequently invoked, frequently blocking the processor's renaming pipeline or instruction commit pipeline, significantly degrading overall processor performance. Summary of the Invention

[0004] In this context, embodiments of the present invention aim to provide a method, apparatus, and device for instruction processing of a non-blocking RISC-V shadow stack.

[0005] In a first aspect of the present invention, a non-blocking RISC-V shadow stack instruction processing method is provided, applied to an SSP logic register established inside the processor, the method comprising: The target instruction entering the decoding stage is type-identified to determine the instruction type of the target instruction; wherein, the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type; If the target instruction is of the shadow stack instruction type or the CSR instruction type, then the target instruction is converted into an internal data stream operation instruction; The internal data stream operation instruction is renamed based on the current speculative mapping of the SSP logical register to obtain the renamed internal data stream operation instruction. The rename internal data stream operation instruction is dispatched to the execution path corresponding to the rename internal data stream operation instruction to obtain the execution result corresponding to the rename internal data stream operation instruction.

[0006] In one embodiment of this implementation, after determining the instruction type of the target instruction, the method further includes: If the target instruction is of the ordinary instruction type, then the target instruction is processed according to the preset ordinary instruction processing method; Furthermore, if the target instruction is of the shadow stack instruction type or the CSR instruction type, then converting the target instruction into an internal data stream operation instruction specifically includes: If the target instruction is of the shadow stack instruction type or the CSR instruction type, then the target instruction is verified to obtain the verification result; If the verification result indicates that the target instruction has passed the instruction verification, then the target instruction is converted into an internal data stream operation instruction.

[0007] In one embodiment of this implementation, the step of performing instruction verification on the target instruction to obtain a verification result specifically includes: Obtain the processor's current privilege level and the global enable flag for shadow stack extension corresponding to the target instruction; The SSP access permissions corresponding to the current privilege level of the processor are verified to obtain the SSP access permission verification result. The on / off state of the global enable flag of the shadow stack extension is verified to obtain the flag verification result. The alignment of the SSP value to be written corresponding to the target instruction is verified to obtain the alignment verification result; If the SSP access permission verification result, the flag bit verification result, and the alignment method verification result all indicate that the verification is passed, then the instruction verification of the target instruction is determined as the verification result; wherein, the passing of the SSP access permission verification result indicates that the processor currently running at the privilege level has the SSP access permission, the passing of the flag bit verification result indicates that the shadow stack extension global enable flag is in the enabled state, and the passing of the alignment method verification result indicates that the alignment method of the SSP value to be written meets the alignment requirements; If any of the SSP access permission verification results, the flag bit verification results, and the alignment verification results indicate that the verification failed, then the failure of the target instruction's instruction verification is determined as the verification result.

[0008] In one embodiment of this implementation, the shadow stack instruction type includes the SSPUSH push instruction, the SSPOPCHK pop verification instruction, the SSRDP pointer read instruction, and the SSAMOSWAP atomic swap instruction. If the target instruction is of the shadow stack instruction type, the target instruction is converted into an internal data stream operation instruction, specifically including: If the target instruction is the SSPUSH push instruction, then the SSPUSH push instruction is converted into an SSPUSH internal data stream operation instruction; wherein, the SSPUSH internal data stream operation instruction includes determining the shadow stack storage address based on the read current SSP value, writing the SSP value to be written corresponding to the SSPUSH internal data stream operation instruction into the shadow stack memory corresponding to the shadow stack storage address, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSPOPCHK stack pop verification instruction, then the SSPOPCHK stack pop verification instruction is converted into an SSPOPCHK internal data flow operation instruction; wherein, the SSPOPCHK internal data flow operation instruction includes determining the shadow stack storage address based on the read current SSP value, comparing the data read from the shadow stack storage address with the register data corresponding to the SSPOPCHK internal data flow operation instruction, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSRDP pointer read instruction, then the SSRDP pointer read instruction is converted into an SSRDP internal data stream operation instruction; wherein, the SSRDP internal data stream operation instruction includes writing the read current SSP value into the destination register; If the target instruction is the SSAMOSWAP atomic swap instruction, then the SSAMOSWAP atomic swap instruction is converted into an SSAMOSWAP internal data stream operation instruction; wherein, the SSAMOSWAP internal data stream operation instruction includes a shadow stack atomic memory access swap operation based on the address pointed to by the current SSP value.

[0009] In one embodiment of this implementation, the CSR instruction type includes SSP-related CSR read instructions, SSP-related CSR write instructions, and SSP-related CSR read / write instructions. If the target instruction is of the CSR instruction type, the target instruction is converted into an internal data stream operation instruction, specifically including: If the target instruction is the SSP-related CSR read instruction, then the SSP-related CSR read instruction is converted into a first internal data stream operation instruction; wherein, the first internal data stream operation instruction is used to perform the read and data transfer operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR write instruction, then the SSP-related CSR write instruction is converted into a second internal data stream operation instruction; wherein, the second internal data stream operation instruction is used to perform the rewrite operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR read / write instruction, then the SSP-related CSR read / write instruction is converted into a third internal data stream operation instruction; wherein, the third internal data stream operation instruction is used to sequentially execute the read and data output operations corresponding to the current SSP value and the write operation corresponding to the generated new SSP value.

[0010] In one embodiment of this implementation, dispatching the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, and obtaining the execution result corresponding to the rename internal data stream operation instruction, specifically includes: The SSPUSH push instruction is dispatched to the corresponding storage execution path to obtain the execution result of the SSPUSH push instruction; or... The SSPOPCHK stack pop verification instruction is dispatched to the loading execution path and comparison path corresponding to the SSPOPCHK stack pop verification instruction to obtain the execution result corresponding to the SSPOPCHK stack pop verification instruction; or... The SSRDP pointer read instruction is dispatched to the data movement path corresponding to the SSRDP pointer read instruction to obtain the execution result corresponding to the SSRDP pointer read instruction; or... The SSAMOSWAP atomic swap instruction is dispatched to the atomic access path corresponding to the SSAMOSWAP atomic swap instruction to obtain the execution result corresponding to the SSAMOSWAP atomic swap instruction; or... The first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction are dispatched to the integer execution path to obtain the execution results corresponding to the first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction.

[0011] In one embodiment of this implementation, after obtaining the execution result corresponding to the rename internal data stream operation instruction, the method further includes: If the rename internal data stream operation instruction is submitted normally, then update the submission mapping or architecture state; If an error occurs during the execution of the rename internal data stream operation instruction, the SSP speculative mapping is restored using checkpoints or commit mapping.

[0012] In a second aspect of the present invention, a non-blocking RISC-V shadow stack instruction processing apparatus is provided for implementing the method described in any one aspect of the present invention. The apparatus is applied to an SSP logical register established within the processor, and the apparatus includes: The identification unit is used to identify the type of the target instruction entering the decoding stage and determine the instruction type of the target instruction; wherein the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type; A conversion unit is configured to convert the target instruction into an internal data stream operation instruction if the target instruction is of the shadow stack instruction type or the CSR instruction type. The renaming unit is used to rename the internal data stream operation instruction based on the current speculative mapping of the SSP logical register to obtain the renamed internal data stream operation instruction. The dispatching unit is used to dispatch the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, and obtain the execution result corresponding to the rename internal data stream operation instruction.

[0013] In a third aspect of the present invention, a computing device is provided, the computing device comprising: at least one processor, a memory, and an input / output unit; wherein the memory is used to store a computer program, and the processor is used to invoke the computer program stored in the memory to execute the method described in any one aspect.

[0014] In a fourth aspect of the present invention, a computer-readable storage medium is provided, comprising instructions which, when executed on a computer, cause the computer to perform the method described in any one of the first aspects.

[0015] In a fifth aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in any one of the first aspects.

[0016] The non-blocking RISC-V shadow stack instruction processing method, apparatus, and device according to embodiments of the present invention can configure the SSP as a dedicated logic register that can participate in register renaming. Shadow stack instructions and SSP-related CSR instructions can be converted into standardized internal data flow operations. After renaming is completed through SSP speculative mapping, they are dispatched to the corresponding execution path for execution. Instruction execution is constrained only by local data dependencies, and ordinary instructions unrelated to the SSP can be executed in parallel out-of-order, reducing pause losses during decoding, renaming, and dispatching. Simultaneously, the processor's existing execution path and exception recovery hardware are reused, eliminating the need for additional complex control circuitry. The shadow stack security verification and exception reporting functions are fully preserved, reducing performance losses caused by frequent shadow stack instruction calls and effectively improving the overall processor performance. Attached Figure Description

[0017] The above and other objects, features, and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated in the drawings by way of example and not limitation, wherein: Figure 1 This is a flowchart illustrating an instruction processing method for a non-blocking RISC-V shadow stack according to an embodiment of the present invention. Figure 2 A flowchart illustrating a non-blocking RISC-V shadow stack instruction processing method provided in another embodiment of the present invention; Figure 3 A schematic diagram of the structure of a non-blocking RISC-V shadow stack instruction processing device provided in an embodiment of the present invention; Figure 4 A schematic diagram of the structure of a non-blocking RISC-V shadow stack instruction processing device provided in another embodiment of the present invention; Figure 5 A schematic diagram of the structure of a medium according to an embodiment of the present invention is shown. Figure 6 A schematic diagram of the structure of a computing device according to an embodiment of the present invention is shown.

[0018] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0019] The principles and spirit of the invention will now be described with reference to several exemplary embodiments. It should be understood that these embodiments are given merely to enable those skilled in the art to better understand and implement the invention, and are not intended to limit the scope of the invention in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0020] Those skilled in the art will recognize that embodiments of the present invention can be implemented as a system, apparatus, device, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0021] According to an embodiment of the present invention, a non-blocking RISC-V shadow stack instruction processing method, apparatus and device are proposed.

[0022] It should be noted that the number of any elements in the accompanying drawings is for illustrative purposes only and not as a limitation, and any naming is for distinction only and has no limiting meaning.

[0023] The principles and spirit of the present invention will be explained in detail below with reference to several representative embodiments.

[0024] The following is for reference. Figure 1 , Figure 1 This is a flowchart illustrating a non-blocking RISC-V shadow stack instruction processing method according to an embodiment of the present invention. It should be noted that the implementation of the present invention can be applied to SSP logic registers established within the processor.

[0025] In this embodiment, the SSP is abstracted as an extended logical register (i.e., the SSP logical register) inside the processor. This extended logical register is not used as a regular software-visible integer register, but is specifically used to carry the Shadow Stack pointer state. Source reads, destination writes, checkpoint saving, branch misprediction recovery, exception recovery, and commit updates of this logical register are all handled in the same way as ordinary renameable registers.

[0026] Figure 1 The flowchart of the non-blocking RISC-V shadow stack instruction processing method provided in an embodiment of the present invention, shown below, includes: Step 101: Perform type identification on the target instruction entering the decoding stage to determine the instruction type of the target instruction.

[0027] In this embodiment, the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type. The shadow stack instruction type may include the SSPUSH push instruction, the SSPOPCHK pop verification instruction, the SSRDP pointer read instruction, and the SSAMOSWAP atomic swap instruction. The CSR instruction type may include SSP-related CSR read instructions, SSP-related CSR write instructions, and SSP-related CSR read / write instructions.

[0028] In this embodiment of the application, please refer to Table 1, which is a table of abstract conversion methods for target instructions of shadow stack instruction type and CSR instruction type: Table 1. Abstraction and conversion methods of target instructions for shadow stack instruction types and CSR instruction types. Table 1 only describes the behavioral relationships and does not specify the specific pipeline level, specific coding bit, or specific internal signal name.

[0029] Step 102: If the target instruction is of the shadow stack instruction type or the CSR instruction type, then the target instruction is converted into an internal data stream operation instruction.

[0030] In this embodiment, the SSPUSH push instruction can be converted into internal data flow operation instructions corresponding to shadow stack storage and SSP update behavior; the SSPOPCHK pop verification instruction can be converted into internal data flow operation instructions corresponding to shadow stack load verification and SSP update behavior; the SSRDP pointer read instruction can be converted into internal data flow operation instructions corresponding to SSP read behavior; the SSAMOSWAP atomic swap instruction can be converted into internal data flow operation instructions corresponding to atomic memory access behavior; the SSP-related CSR read instruction can be converted into internal data flow operation instructions corresponding to read old SSP behavior; the SSP-related CSR write instruction can be converted into internal data flow operation instructions corresponding to write new SSP behavior; and the SSP-related CSR read / write instruction can be converted into internal data flow operation instructions corresponding to the combined behavior of reading old SSP and writing new SSP.

[0031] As an optional implementation, after step 101, the following steps may also be performed: If the target instruction is of the ordinary instruction type, then the target instruction is processed according to the preset ordinary instruction processing method; Furthermore, if step 102 involves converting the target instruction into an internal data stream operation instruction of the shadow stack instruction type or the CSR instruction type, the method of doing so may include: If the target instruction is of the shadow stack instruction type or the CSR instruction type, then the target instruction is verified to obtain the verification result; If the verification result indicates that the target instruction has passed the instruction verification, then the target instruction is converted into an internal data stream operation instruction.

[0032] This implementation method directly processes ordinary instructions using the existing conventional process without adding extra processing overhead. For shadow stack and SSP-related CSR instructions, a validity check is first performed; only instructions that pass the check are converted into internal data flow operation instructions. This avoids invalid instructions consuming pipeline resources, proactively intercepts illegal instructions and non-compliant accesses, reduces the pressure on exception handling during subsequent renaming and execution phases, and differentiates instruction types for different processing, streamlining invalid operations, reducing unnecessary pipeline losses, and further optimizing processor operating efficiency.

[0033] Optionally, the target instruction may be validated, and the validation result may be obtained by means of: Obtain the processor's current privilege level and the global enable flag for shadow stack extension corresponding to the target instruction; The SSP access permissions corresponding to the current privilege level of the processor are verified to obtain the SSP access permission verification result. The on / off state of the global enable flag of the shadow stack extension is verified to obtain the flag verification result. The alignment of the SSP value to be written corresponding to the target instruction is verified to obtain the alignment verification result; If the SSP access permission verification result, the flag bit verification result, and the alignment method verification result all indicate that the verification is passed, then the instruction verification of the target instruction is determined as the verification result; wherein, the passing of the SSP access permission verification result indicates that the processor currently running at the privilege level has the SSP access permission, the passing of the flag bit verification result indicates that the shadow stack extension global enable flag is in the enabled state, and the passing of the alignment method verification result indicates that the alignment method of the SSP value to be written meets the alignment requirements; If any of the SSP access permission verification results, the flag bit verification results, and the alignment verification results indicate that the verification failed, then the failure of the target instruction's instruction verification is determined as the verification result.

[0034] This implementation method employs multi-layered verification across three dimensions: privileged access permissions, shadow stack extension switching, and SSP value alignment. If any condition is not met, the instruction is deemed illegal, intercepting violations in advance. Issues such as illegal access, disabled extensions, and misaligned pointer addresses can be identified during the verification phase, eliminating the need to proceed to the renaming and execution phases to report errors. This reduces the consumption of pipeline resources by invalid instructions, lowers backend exception handling overhead, and improves processing efficiency while ensuring shadow stack security standards.

[0035] In this embodiment of the application, if the verification result indicates that the instruction verification of the target instruction has failed, the target instruction is marked as an illegal instruction, a no-operation is performed, or a result such as returning zero is obtained according to the specification requirements.

[0036] Specifically, if the SSP access permission check result indicates that the current privileged state of the target instruction does not allow access to the relevant SSP state, the target instruction can be marked as an illegal instruction or abnormal attribute during decoding or an earlier pipeline stage. If the flag check result indicates that the Shadow Stack extension of the target instruction is not enabled in the current mode, the corresponding instruction can be processed as a no-operation, return zero, or an illegal instruction according to the specification requirements. If the alignment check result indicates that the SSP write of the target instruction does not meet the alignment requirements, the low-order bits can be masked or normalized before writing the target instruction into the internal SSP logic register. In addition, if the stack check comparison of the target instruction fails, it can be handled through exception reporting and pipeline recovery mechanisms.

[0037] As an optional implementation, if the target instruction is of the shadow stack instruction type, the method of converting the target instruction into an internal data stream operation instruction may include: If the target instruction is the SSPUSH push instruction, then the SSPUSH push instruction is converted into an SSPUSH internal data stream operation instruction; wherein, the SSPUSH internal data stream operation instruction includes determining the shadow stack storage address based on the read current SSP value, writing the SSP value to be written corresponding to the SSPUSH internal data stream operation instruction into the shadow stack memory corresponding to the shadow stack storage address, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSPOPCHK stack pop verification instruction, then the SSPOPCHK stack pop verification instruction is converted into an SSPOPCHK internal data flow operation instruction; wherein, the SSPOPCHK internal data flow operation instruction includes determining the shadow stack storage address based on the read current SSP value, comparing the data read from the shadow stack storage address with the register data corresponding to the SSPOPCHK internal data flow operation instruction, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSRDP pointer read instruction, then the SSRDP pointer read instruction is converted into an SSRDP internal data stream operation instruction; wherein, the SSRDP internal data stream operation instruction includes writing the read current SSP value into the destination register; If the target instruction is the SSAMOSWAP atomic swap instruction, then the SSAMOSWAP atomic swap instruction is converted into an SSAMOSWAP internal data stream operation instruction; wherein, the SSAMOSWAP internal data stream operation instruction includes a shadow stack atomic memory access swap operation based on the address pointed to by the current SSP value.

[0038] This implementation method involves disassembling and adapting the internal data flow operations for four different types of shadow stack instructions, accurately restoring the complete functional logic of each instruction's push-on, pop-off verification, pointer reading, and atomic swapping. This is then uniformly transformed into processor-native memory access, data comparison, and value update operations, reusing the chip's existing execution hardware without requiring additional dedicated processing paths. The instruction execution logic is more aligned with out-of-order pipeline architectures, reducing additional hardware overhead and ensuring the integrity of shadow stack security functions while improving instruction processing efficiency.

[0039] As an optional implementation, if the target instruction is of the CSR instruction type, the method of converting the target instruction into an internal data stream operation instruction may include: If the target instruction is the SSP-related CSR read instruction, then the SSP-related CSR read instruction is converted into a first internal data stream operation instruction; wherein, the first internal data stream operation instruction is used to perform the read and data transfer operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR write instruction, then the SSP-related CSR write instruction is converted into a second internal data stream operation instruction; wherein, the second internal data stream operation instruction is used to perform the rewrite operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR read / write instruction, then the SSP-related CSR read / write instruction is converted into a third internal data stream operation instruction; wherein, the third internal data stream operation instruction is used to sequentially execute the read and data output operations corresponding to the current SSP value and the write operation corresponding to the generated new SSP value.

[0040] This implementation method differentiates SSP-related CSR instructions into three categories: read-only, write-only, and read-write hybrid, converting them into corresponding data stream operations and removing the limitations of traditional CSR serial access. Each instruction retains only the necessary read, move, and rewrite logic, streamlining redundant operations, reusing integer arithmetic paths, eliminating the need for a separate dedicated CSR serial path, avoiding pipeline congestion, and reducing hardware resource consumption while fully preserving the original read-write semantics of CSRs, thus improving out-of-order instruction processing performance.

[0041] Step 103: Rename the internal data stream operation instruction based on the current speculative mapping of the SSP logic register to obtain the renamed internal data stream operation instruction.

[0042] In this embodiment of the application, the SSP source and destination are processed during the renaming stage.

[0043] If the internal data flow operation instruction needs to read the SSP, the physical mapping corresponding to the SSP is obtained from the current speculative mapping of the SSP logical register, and the physical mapping corresponding to the SSP is rewritten (i.e. renamed) to the internal data flow operation instruction corresponding to the SSP read action or the old SSP read action, thus obtaining the renamed internal data flow operation instruction corresponding to the SSP read action or the old SSP read action.

[0044] If the internal data flow operation instruction needs to write to the SSP, a new physical mapping is allocated to the SSP and the current speculative mapping of the SSP logical register is updated. The new physical mapping is then rewritten to the internal data flow operation instruction corresponding to the SSP update action or write new SSP action, resulting in the rename internal data flow operation instruction corresponding to the SSP update action or write new SSP action.

[0045] Except for the internal data stream operation instructions mentioned above that need to be rewritten, other internal data stream operation instructions do not need to be rewritten. That is, other internal data stream operation instructions are directly identified as renaming internal data stream operation instructions.

[0046] This process is performed in the same way as renaming ordinary integer registers and supports checkpoint saving and recovery.

[0047] Step 104: Dispatch the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, and obtain the execution result corresponding to the rename internal data stream operation instruction.

[0048] In this embodiment, the rename internal data stream operation instruction corresponding to the shadow stack storage behavior enters the storage execution path; the rename internal data stream operation instruction corresponding to the shadow stack load verification behavior enters the load execution path and comparison path; the rename internal data stream operation instruction corresponding to the SSP update behavior enters the integer execution path; SSRDP enters the data movement path; and SSAMOSWAP enters the atomic memory access path. Different resources are constrained only by real data dependencies and structural resource conflicts, without introducing global blocking of the entire pipeline.

[0049] As an optional implementation, step 104, which dispatches the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, and obtains the execution result corresponding to the rename internal data stream operation instruction, may include: The SSPUSH push instruction is dispatched to the corresponding storage execution path to obtain the execution result of the SSPUSH push instruction; or... The SSPOPCHK stack pop verification instruction is dispatched to the loading execution path and comparison path corresponding to the SSPOPCHK stack pop verification instruction to obtain the execution result corresponding to the SSPOPCHK stack pop verification instruction; or... The SSRDP pointer read instruction is dispatched to the data movement path corresponding to the SSRDP pointer read instruction to obtain the execution result corresponding to the SSRDP pointer read instruction; or... The SSAMOSWAP atomic swap instruction is dispatched to the atomic access path corresponding to the SSAMOSWAP atomic swap instruction to obtain the execution result corresponding to the SSAMOSWAP atomic swap instruction; or... The first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction are dispatched to the integer execution path to obtain the execution results corresponding to the first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction.

[0050] In this implementation, data stream operations are assigned to matching hardware execution paths based on their functional differences, with stack pushing, stack popping, pointer reading, atomic swapping, and CSR-related operations each performing their specific tasks. This fully utilizes the processor's built-in multi-path hardware resources, allowing various operations to be scheduled in parallel without each other occupying the same execution path. It avoids pipeline delays caused by concentrated waiting, maximizes the advantages of out-of-order execution, and improves overall instruction throughput efficiency without adding new hardware.

[0051] As an optional implementation, after step 104, the following steps may also be performed: If the rename internal data stream operation instruction is submitted normally, then update the submission mapping or architecture state; If an error occurs during the execution of the rename internal data stream operation instruction, the SSP speculative mapping is restored using checkpoints or commit mapping.

[0052] This implementation method, by incorporating SSP commit and recovery into a unified mapping management system, achieves significant benefits. During normal commits, the SSP architecture state is updated synchronously without increasing pipeline latency; in case of anomalies, existing checkpoints are used to quickly restore the SSP speculative mapping, eliminating the need for independent rollback logic. This mechanism, while fully preserving the accurate exception semantics and security of the shadow stack extension, reuses existing processor hardware, reduces design verification complexity, and minimizes the impact on pipeline performance.

[0053] In this embodiment of the application, an error in instruction execution may be a comparison failure of SSPOPCHK, a permission error, or a memory access error, etc. The execution result of the error in instruction execution can be reported as a precise error; normally completed ShadowStack instructions enter the submission stage according to the original submission mechanism.

[0054] When an instruction is committed normally, the commit map receives the corresponding SSP update, advancing the SSP architecture state. When a branch misprediction, an exception, or other pipeline flushing occurs, the processor uses checkpoints or commit maps to restore the SSP speculative map, allowing subsequent re-executed Shadow Stack instructions to see the correct SSP state.

[0055] In the above implementation, the internal registerization of the SSP does not change the software visibility semantics of the RISC-V Shadow Stack extension. The software still observes the state through the prescribed Shadow Stack instructions and SSP-related access methods; the processor internally improves its execution efficiency through renaming chains, memory access execution, and precise exception mechanisms. For specific processors, the internal conversion method can also be equivalently adjusted according to the shadow stack slot width, machine word length, supported privilege levels, compression instruction support, and existing memory access splitting capabilities. These adjustments do not affect the core idea of ​​this invention: "replacing blocking CSR state access with renamable SSP data streams."

[0056] In one implementation, the decoded Shadow Stack instructions retain at least the following abstract information: instruction type, whether an SSP is accessed, whether an old SSP is read, whether a new SSP is created, memory access direction, shadow stack slot width, comparison source operand, destination register, permission check result, exception attributes, and SSP write alignment requirements. This information is not required to be limited to a fixed entry format, as long as it enables subsequent renaming and execution phases to distinguish between actions such as pushing onto the stack, popping from the stack for verification, reading pointers, writing pointers, and atomic swaps.

[0057] Taking SSPUSH as an example, after decoding, there is a shadow stack storage behavior that reads the old SSP and a pointer update behavior that generates the new SSP. During the renaming phase, a mapping is allocated for the new SSP, and subsequent instructions using the SSP read this new mapping. During the execution phase, the storage address is generated based on the old SSP, the source register data is written to the shadow stack, and the integer result corresponding to the pointer update is written back.

[0058] Taking SSPOPCHK as an example, after decoding, it forms a shadow stack loading and verification operation to read the old SSP and a pointer update operation to generate the new SSP. During the execution phase, data is read from the shadow stack and compared with the value of the specified register. If the comparison matches, the instruction completes normally; if the comparison does not match, a control flow integrity exception is generated and handled by the processor's existing exception recovery procedure. The new mapping of the SSP is still expressed by the renaming order, and during exception recovery, it can return to the correct older mapping.

[0059] Taking SSRDP as an example, after decoding, it forms a data movement behavior from the current SSP to the general purpose register. This instruction only reads the SSP and does not create a new SSP, so it will not change the SSP chain seen by subsequent Shadow Stack instructions. If extension is not enabled in the current mode, the result can be set to zero or treated as a no-operation according to the specification requirements.

[0060] Taking SSP-related CSR read / write as an example, after decoding, the instruction type determines whether to read the old SSP, write the new SSP, or a combination of both. For instructions requiring writing to the SSP, the written value can be aligned first, for example, by masking the lowest few bits to meet the shadow stack pointer alignment requirements. For instructions involving both reading and writing, the read value is written to a general purpose register, and the written value generates a new SSP mapping. For read-only or write-only instructions, only the corresponding half of the behavior can be retained, thus avoiding unnecessary blocking.

[0061] For example, if consecutive Shadow Stack push and read pointer instructions appear in the same function call-related code, the operations shown in Table 2 can be performed: Table 2. Operation instructions for consecutive Shadow Stack push and read pointer instructions. Specifically, if the ordinary CSR serial method is used, global order constraints may form before and after inst1 updates the SSP. inst3 and inst4 are prone to waiting for older instructions to commit or for the CSR state to stabilize, thus blocking subsequent instructions from entering the out-of-order window. With this invention, inst1 reads the old SSP and generates a new SSP mapping during the renaming phase, inst3 reads the SSP mapping generated by inst1, and inst4 then reads the SSP mapping generated by inst3. The order relationship between the three SSP-related instructions is expressed by data dependency, and irrelevant instructions such as inst2 do not need to be blocked because the SSP is in a CSR-like state.

[0062] For example, if a stack pop verification instruction appears in the return path, and there are subsequent ordinary instructions that do not depend on the verification result, the operations shown in Table 3 can be executed: Table 3 If SSPOPCH is treated as a blocking special instruction, inst2 might be forced to wait for inst1 to complete all memory access and verification processes before proceeding to the next stage of the pipeline. With this invention, inst1 is transformed into a combined behavior of "SSP-based shadow stack loading, comparison, and SSP update," where SSP updates are passed backward in the form of renamed data streams, and comparison failures are reported via an exception mechanism. Inst2 and inst4 do not depend on SSP or comparison data, so they can continue to proceed according to normal out-of-order execution rules; inst3 only needs to wait for the new SSP mapping generated by inst1. This maintains the return address verification semantics while reducing blocking of irrelevant instructions.

[0063] For example, if software or exception handling code accesses an SSP-related CSR and it occurs adjacent to a Shadow Stack instruction, the operations shown in Table 4 can be performed: Table 4 In typical implementations, CSR reads and writes often require a dedicated CSR path and may form a serial process of "reading the old value, calculating the new value, and committing the write". With this invention, SSP-related CSR accesses are transformed into ordinary data stream operations of reading the old SSP and writing the new SSP. The read value of CSRRW-type instructions is written to a general-purpose register, and the new SSP is written to the internal SSP logic register; CSRRS, CSRRC, and their immediate forms can form a new SSP according to the corresponding logical operations; the read-only form retains only the behavior of reading the old SSP, and the write-only form retains only the behavior of writing the new SSP. Because these behaviors enter the same SSP renaming chain, inst2, inst3, and inst4 can all see the SSP values ​​in the correct order, while eliminating the need for all CSR-type accesses to force the out-of-order window to be cleared.

[0064] In this way, the present invention separates the "architectural meaning of SSP" from the "internal execution carrier of SSP". The software still sees the SSP state and abnormal behavior that conforms to the extended semantics of RISC-V Shadow Stack; the processor internally uses SSP as a renamable, recoverable, and committable extended logical register for high-performance processing.

[0065] In the embodiments of this application, Figure 1 The non-blocking RISC-V shadow stack instruction processing method provided in the embodiment of the present invention shown can be applied to a non-blocking RISC-V shadow stack instruction processing system. This system may include an instruction identification and permission check unit, a Shadow Stack instruction translation unit, an SSP renaming unit, a dispatch and execution unit, a verification and exception handling unit, and a commit and recovery unit, wherein: The instruction recognition and privilege check unit can be used to identify SSPUSH, SSPOPCHK, SSRDP, SSAMOSWAP and SSP-related CSR read and write, and generate attributes such as allowed execution, no operation, return zero or illegal instruction based on the current privilege state, extended enable state and instruction encoding legality.

[0066] The Shadow Stack instruction translation unit can be used to convert the above instructions into an internally executable data stream.

[0067] The SSP renaming unit can be used to read old SSP maps, allocate new SSP maps, and incorporate SSPs into speculative and committed maps.

[0068] The dispatch and execution unit can be used to perform internal behaviors such as storage, loading, integer arithmetic, atomic memory access, and data movement.

[0069] The verification and exception unit can be used to handle stack pop verification comparison failures, permission exceptions, and memory access exceptions.

[0070] The commit and recovery unit can be used to update the architecture-visible state when an instruction is committed and to restore the SSP mapping during flush or abnormal recovery.

[0071] This invention can significantly reduce pipeline congestion caused by Shadow Stack instructions. SSPUSH, SSPOPCHK, SSRDP, and SSP-related CSR reads and writes no longer need to be processed serially using global CSRs, but instead enter the ordinary register data stream and memory access data stream; irrelevant instructions can continue to be renamed, dispatched, and executed.

[0072] This invention guarantees the sequential semantics of SSP. Data dependencies are naturally formed between consecutive Shadow Stack instructions through SSP renaming mappings. Newer instructions read the SSP mappings generated by older instructions, so there is no need to introduce additional coarse-grained pipeline pauses to maintain the order.

[0073] This invention enables the reuse of existing recovery mechanisms in out-of-order processors. Since the SSP is included in the rename mapping, commit mapping, and checkpoint recovery, when branch misprediction, exceptions, pipeline flushing, or commit rollback occur, the SSP can be restored to the correct state along with the ordinary register mapping, avoiding the need to design a complex speculative CSR rollback mechanism separately for the Shadow Stack.

[0074] This invention enables the reuse of existing execution resources. SSPUSH can reuse the memory-based execution format with base address updates, SSPOPCHK can reuse the load-based execution format with base address updates and add comparison exception semantics, SSRDP can reuse the ordinary register movement format, SSAMOSWAP can reuse the atomic memory access execution format, and SSP-related CSR read / write can reuse the ordinary integer logic operation format. Therefore, fewer new hardware control paths are added, and the verification boundaries are clearer.

[0075] This invention can also improve the performance of calling and returning intensive programs. Shadow Stack instructions appear frequently in such programs. If each access to the SSP causes CSR blocking, it will significantly reduce the throughput of the front-end and out-of-order windows. With this invention, Shadow Stack instructions mainly exhibit local data dependencies and memory access dependencies, with less impact on irrelevant instructions.

[0076] This invention enables the SSP to be configured as a dedicated logical register capable of participating in register renaming. Shadow stack instructions and SSP-related CSR instructions can be transformed into standardized internal data flow operations. After renaming is completed through SSP speculative mapping, the renaming is dispatched to the corresponding execution path for execution. Instruction execution is constrained only by local data dependencies, allowing ordinary instructions unrelated to the SSP to be executed in parallel out-of-order, reducing pauses during decoding, renaming, and dispatching. Simultaneously, it reuses the processor's existing execution paths and exception recovery hardware, eliminating the need for complex new control circuits. It fully retains shadow stack security verification and exception reporting functions, reducing performance losses from frequent shadow stack instruction calls and effectively improving overall processor performance. Furthermore, this invention avoids invalid instructions occupying pipeline resources, proactively intercepting illegal instructions and non-compliant accesses, reducing exception handling pressure during subsequent renaming and execution phases. It also differentiates instruction types for differentiating processing, simplifying invalid operations, reducing unnecessary pipeline losses, and further optimizing processor efficiency. Moreover, this invention can reduce invalid pipeline operations and improve processing efficiency while ensuring shadow stack security specifications. Finally, this invention can improve instruction processing efficiency while ensuring the integrity of shadow stack security functions. Furthermore, this invention can improve instruction out-of-order processing performance. Additionally, it can improve overall instruction throughput efficiency without adding new hardware. Moreover, this invention reduces design verification complexity and minimizes the impact on pipeline performance.

[0077] Please refer to the following: Figure 2 , Figure 2 A flowchart illustrating a non-blocking RISC-V shadow stack instruction processing method according to another embodiment of the present invention is shown below. Figure 2 As shown, the instruction processing flow of the non-blocking RISC-V shadow stack in this invention is as follows: Once the instruction enters the decoding stage, it first determines whether the current instruction is a shadow stack-related instruction or an SSP-related CSR access instruction. If not, execution continues according to the normal instruction processing flow; if so, it enters the shadow stack instruction-specific processing flow.

[0078] Next, it checks whether the current privileged state allows access to the shadow stack's related states, whether shadow stack expansion is enabled in the current mode, and whether the instruction encoding meets the legal constraints. If any of the above conditions are not met, the corresponding instruction is marked as an illegal instruction, a no-operation, or returns zero according to the RISC-V specification; if all conditions are met, the subsequent conversion steps continue.

[0079] Next, the corresponding internal dataflow behavior is generated based on the instruction type. For the SSPUSH instruction, shadow stack storage behavior and SSP update behavior are generated; for the SSPOPCHK instruction, shadow stack load verification behavior and SSP update behavior are generated; for the SSRDP instruction, data movement behavior of reading SSP and writing to general purpose registers is generated; for the SSAMOSWAP instruction, atomic memory access behavior is generated; for SSP-related CSR read and write instructions, combined behavior of reading the old SSP and writing to the new SSP is generated.

[0080] Subsequently, during the renaming phase, if the current instruction needs to read the SSP, the physical register mapping corresponding to the SSP is obtained from the current speculative mapping; if the current instruction needs to write to the SSP, a new physical register mapping is allocated for the SSP and the speculative mapping is updated. This process is performed in conjunction with the renaming of ordinary integer registers and supports checkpoint saving and restoration.

[0081] Subsequently, the transformed instructions are dispatched to the corresponding execution resources. Shadow stack storage enters the storage execution path, shadow stack load verification enters the load execution path and comparison path, SSP update enters the integer execution path, SSRDP enters the data movement path, and SSAMOSWAP enters the atomic memory access path. Different execution resources are constrained only by real data dependencies and structural resource conflicts, without introducing global pipeline blocking.

[0082] After the instruction is executed, it is determined whether a comparison failure or exception occurred. If the SSPOPCH checksum comparison fails, or if a permission exception or memory access exception occurs, it is reported as an exact exception, and the SSP speculative mapping is restored to the correct state before the execution of the exception instruction using checkpoints or commit mapping. Then, the instruction is fetched and executed again from the exception instruction. If the instruction completes normally, it enters the commit phase according to the original commit mechanism, and the SSP speculative mapping is committed to the architectural state, so that the SSP architectural state can move forward.

[0083] In the above process, the internal registerization of the SSP does not change the software-visible semantics of the RISC-V shadow stack extension. The SSP state is still observed through the prescribed shadow stack instructions and SSP-related access methods; internally, the processor improves execution efficiency through renaming chains, memory access execution, and precise exception mechanisms.

[0084] After introducing the method of exemplary embodiments of the present invention, the following references are made. Figure 3 An instruction processing apparatus for a non-blocking RISC-V shadow stack, according to an exemplary embodiment of the present invention, will be described. This apparatus implements... Figure 1 or Figure 2The flowchart shown is a non-blocking RISC-V shadow stack instruction processing method provided in an embodiment of the present invention. The device is applied to the SSP logic register established inside the processor, and the device includes: The identification unit 301 is used to identify the type of the target instruction entering the decoding stage and determine the instruction type of the target instruction; wherein, the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type; the shadow stack instruction type includes the SSPUSH push instruction, the SSPOPCHK pop stack verification instruction, the SSRDP pointer read instruction, and the SSAMOSWAP atomic swap instruction; the CSR instruction type includes SSP-related CSR read instructions, SSP-related CSR write instructions, and SSP-related CSR read / write instructions. The conversion unit 302 is used to convert the target instruction into an internal data stream operation instruction if the target instruction is of the shadow stack instruction type or the CSR instruction type. The renaming unit 303 is used to rename the internal data stream operation instruction based on the current speculative mapping of the SSP logical register to obtain the renamed internal data stream operation instruction. The dispatching unit 304 is used to dispatch the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, so as to obtain the execution result corresponding to the rename internal data stream operation instruction.

[0085] As an optional implementation, the identification unit 301 is also used for: After determining the instruction type of the target instruction, if the target instruction is a normal instruction type, the target instruction is processed according to a preset normal instruction processing method. Furthermore, if the target instruction is of the shadow stack instruction type or the CSR instruction type, the conversion unit 302 may convert the target instruction into an internal data stream operation instruction in the following specific ways: If the target instruction is of the shadow stack instruction type or the CSR instruction type, then the target instruction is verified to obtain the verification result; If the verification result indicates that the target instruction has passed the instruction verification, then the target instruction is converted into an internal data stream operation instruction.

[0086] This implementation method directly processes ordinary instructions using the existing conventional process without adding extra processing overhead. For shadow stack and SSP-related CSR instructions, a validity check is first performed; only instructions that pass the check are converted into internal data flow operation instructions. This avoids invalid instructions consuming pipeline resources, proactively intercepts illegal instructions and non-compliant accesses, reduces the pressure on exception handling during subsequent renaming and execution phases, and differentiates instruction types for different processing, streamlining invalid operations, reducing unnecessary pipeline losses, and further optimizing processor operating efficiency.

[0087] As an optional implementation, the conversion unit 302 performs instruction verification on the target instruction, and the specific method for obtaining the verification result can be as follows: Obtain the processor's current privilege level and the global enable flag for shadow stack extension corresponding to the target instruction; The SSP access permissions corresponding to the current privilege level of the processor are verified to obtain the SSP access permission verification result. The on / off state of the global enable flag of the shadow stack extension is verified to obtain the flag verification result. The alignment of the SSP value to be written corresponding to the target instruction is verified to obtain the alignment verification result; If the SSP access permission verification result, the flag bit verification result, and the alignment method verification result all indicate that the verification is passed, then the instruction verification of the target instruction is determined as the verification result; wherein, the passing of the SSP access permission verification result indicates that the processor currently running at the privilege level has the SSP access permission, the passing of the flag bit verification result indicates that the shadow stack extension global enable flag is in the enabled state, and the passing of the alignment method verification result indicates that the alignment method of the SSP value to be written meets the alignment requirements; If any of the SSP access permission verification results, the flag bit verification results, and the alignment verification results indicate that the verification failed, then the failure of the target instruction's instruction verification is determined as the verification result.

[0088] This implementation method employs multi-layered verification across three dimensions: privileged access permissions, shadow stack extension switching, and SSP value alignment. If any condition is not met, the instruction is deemed illegal, intercepting violations in advance. Issues such as illegal access, disabled extensions, and misaligned pointer addresses can be identified during the verification phase, eliminating the need to proceed to the renaming and execution phases to report errors. This reduces the consumption of pipeline resources by invalid instructions, lowers backend exception handling overhead, and improves processing efficiency while ensuring shadow stack security standards.

[0089] As an optional implementation, if the target instruction is of the shadow stack instruction type, the conversion unit 302 may convert the target instruction into an internal data stream operation instruction in the following specific ways: If the target instruction is the SSPUSH push instruction, then the SSPUSH push instruction is converted into an SSPUSH internal data stream operation instruction; wherein, the SSPUSH internal data stream operation instruction includes determining the shadow stack storage address based on the read current SSP value, writing the SSP value to be written corresponding to the SSPUSH internal data stream operation instruction into the shadow stack memory corresponding to the shadow stack storage address, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSPOPCHK stack pop verification instruction, then the SSPOPCHK stack pop verification instruction is converted into an SSPOPCHK internal data flow operation instruction; wherein, the SSPOPCHK internal data flow operation instruction includes determining the shadow stack storage address based on the read current SSP value, comparing the data read from the shadow stack storage address with the register data corresponding to the SSPOPCHK internal data flow operation instruction, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSRDP pointer read instruction, then the SSRDP pointer read instruction is converted into an SSRDP internal data stream operation instruction; wherein, the SSRDP internal data stream operation instruction includes writing the read current SSP value into the destination register; If the target instruction is the SSAMOSWAP atomic swap instruction, then the SSAMOSWAP atomic swap instruction is converted into an SSAMOSWAP internal data stream operation instruction; wherein, the SSAMOSWAP internal data stream operation instruction includes a shadow stack atomic memory access swap operation based on the address pointed to by the current SSP value.

[0090] This implementation method involves disassembling and adapting the internal data flow operations for four different types of shadow stack instructions, accurately restoring the complete functional logic of each instruction's push-on, pop-off verification, pointer reading, and atomic swapping. This is then uniformly transformed into processor-native memory access, data comparison, and value update operations, reusing the chip's existing execution hardware without requiring additional dedicated processing paths. The instruction execution logic is more aligned with out-of-order pipeline architectures, reducing additional hardware overhead and ensuring the integrity of shadow stack security functions while improving instruction processing efficiency.

[0091] As an optional implementation, if the target instruction is of the CSR instruction type, the conversion unit 302 may convert the target instruction into an internal data stream operation instruction in the following specific ways: If the target instruction is the SSP-related CSR read instruction, then the SSP-related CSR read instruction is converted into a first internal data stream operation instruction; wherein, the first internal data stream operation instruction is used to perform the read and data transfer operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR write instruction, then the SSP-related CSR write instruction is converted into a second internal data stream operation instruction; wherein, the second internal data stream operation instruction is used to perform the rewrite operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR read / write instruction, then the SSP-related CSR read / write instruction is converted into a third internal data stream operation instruction; wherein, the third internal data stream operation instruction is used to sequentially execute the read and data output operations corresponding to the current SSP value and the write operation corresponding to the generated new SSP value.

[0092] This implementation method differentiates SSP-related CSR instructions into three categories: read-only, write-only, and read-write hybrid, converting them into corresponding data stream operations and removing the limitations of traditional CSR serial access. Each instruction retains only the necessary read, move, and rewrite logic, streamlining redundant operations, reusing integer arithmetic paths, eliminating the need for a separate dedicated CSR serial path, avoiding pipeline congestion, and reducing hardware resource consumption while fully preserving the original read-write semantics of CSRs, thus improving out-of-order instruction processing performance.

[0093] As an optional implementation, the dispatching unit 304 dispatches the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, and obtains the execution result corresponding to the rename internal data stream operation instruction in the following specific ways: The SSPUSH push instruction is dispatched to the corresponding storage execution path to obtain the execution result of the SSPUSH push instruction; or... The SSPOPCHK stack pop verification instruction is dispatched to the loading execution path and comparison path corresponding to the SSPOPCHK stack pop verification instruction to obtain the execution result corresponding to the SSPOPCHK stack pop verification instruction; or... The SSRDP pointer read instruction is dispatched to the data movement path corresponding to the SSRDP pointer read instruction to obtain the execution result corresponding to the SSRDP pointer read instruction; or... The SSAMOSWAP atomic swap instruction is dispatched to the atomic access path corresponding to the SSAMOSWAP atomic swap instruction to obtain the execution result corresponding to the SSAMOSWAP atomic swap instruction; or... The first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction are dispatched to the integer execution path to obtain the execution results corresponding to the first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction.

[0094] In this implementation, data stream operations are assigned to matching hardware execution paths based on their functional differences, with stack pushing, stack popping, pointer reading, atomic swapping, and CSR-related operations each performing their specific tasks. This fully utilizes the processor's built-in multi-path hardware resources, allowing various operations to be scheduled in parallel without each other occupying the same execution path. It avoids pipeline delays caused by concentrated waiting, maximizes the advantages of out-of-order execution, and improves overall instruction throughput efficiency without adding new hardware.

[0095] As an optional implementation, the dispensing unit 304 is also used for: If the rename internal data stream operation instruction is submitted normally, then update the submission mapping or architecture state; If an error occurs during the execution of the rename internal data stream operation instruction, the SSP speculative mapping is restored using checkpoints or commit mapping.

[0096] This implementation method, by incorporating SSP commit and recovery into a unified mapping management system, achieves significant benefits. During normal commits, the SSP architecture state is updated synchronously without increasing pipeline latency; in case of anomalies, existing checkpoints are used to quickly restore the SSP speculative mapping, eliminating the need for independent rollback logic. This mechanism, while fully preserving the accurate exception semantics and security of the shadow stack extension, reuses existing processor hardware, reduces design verification complexity, and minimizes the impact on pipeline performance.

[0097] This invention enables the SSP to be configured as a dedicated logical register capable of participating in register renaming. Shadow stack instructions and SSP-related CSR instructions can be transformed into standardized internal data flow operations. After renaming is completed through SSP speculative mapping, the renaming is dispatched to the corresponding execution path for execution. Instruction execution is constrained only by local data dependencies, allowing ordinary instructions unrelated to the SSP to be executed in parallel out-of-order, reducing pauses during decoding, renaming, and dispatching. Simultaneously, it reuses the processor's existing execution paths and exception recovery hardware, eliminating the need for complex new control circuits. It fully retains shadow stack security verification and exception reporting functions, reducing performance losses from frequent shadow stack instruction calls and effectively improving overall processor performance. Furthermore, this invention avoids invalid instructions occupying pipeline resources, proactively intercepting illegal instructions and non-compliant accesses, reducing exception handling pressure during subsequent renaming and execution phases. It also differentiates instruction types for differentiating processing, simplifying invalid operations, reducing unnecessary pipeline losses, and further optimizing processor efficiency. Moreover, this invention can reduce invalid pipeline operations and improve processing efficiency while ensuring shadow stack security specifications. Finally, this invention can improve instruction processing efficiency while ensuring the integrity of shadow stack security functions. Furthermore, this invention can improve instruction out-of-order processing performance. Additionally, it can improve overall instruction throughput efficiency without adding new hardware. Moreover, this invention reduces design verification complexity and minimizes the impact on pipeline performance.

[0098] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of a non-blocking RISC-V shadow stack instruction processing device according to another embodiment of the present invention. The device includes an instruction recognition and permission check unit, a Shadow Stack instruction conversion unit, an SSP renaming unit, a dispatch and execution unit, a verification and exception unit, and a commit and recovery unit, wherein: The instruction recognition and privilege check unit is used to identify SSPUSH, SSPOPCHK, SSRDP, SSAMOSWAP and SSP-related CSR read and write instructions during the decoding stage. Based on the current privilege state, shadow stack extension enabled state and instruction encoding legality, it generates attributes such as allowed execution, no operation, return zero or illegal instruction, and passes the instructions that meet the execution conditions to the Shadow Stack instruction translation unit.

[0099] The Shadow Stack instruction translation unit is used to convert shadow stack-related instructions that meet the execution conditions into an internally executable data stream format. Specifically, for the SSPUSH instruction, it is converted into shadow stack storage behavior and SSP update behavior; for the SSPOPCHK instruction, it is converted into shadow stack load verification behavior and SSP update behavior; for the SSRDP instruction, it is converted into SSP read behavior; for the SSAMOSWAP instruction, it is converted into atomic memory access behavior; and for SSP-related CSR read / write instructions, it is converted into a combined behavior of reading the old SSP and writing the new SSP.

[0100] The SSP renaming unit reads the physical register mapping corresponding to the SSP from the current speculative mapping, and allocates a new physical register mapping for the SSP and updates the speculative mapping when the current instruction needs to write to the SSP. The SSP renaming unit works in conjunction with the processor's existing general register renaming / commit / restore framework, supports checkpoint saving and restoring, and enables the renaming mapping of SSPs and the renaming mapping of general integer registers to be managed uniformly under the same framework.

[0101] The dispatch and execution unit dispatches the transformed instructions to the corresponding execution resources for execution. Execution resources include integer execution paths, load-store execution paths, atomic memory access execution paths, and data movement execution paths. Shadow stack storage enters the store execution path, shadow stack load verification enters the load execution path and comparison path, SSP update enters the integer execution path, SSRDP enters the data movement path, and SSAMOSWAP enters the atomic memory access path. Different execution resources are constrained only by real data dependencies and structural resource conflicts, without introducing global pipeline blocking.

[0102] The checksum and exception unit is used to handle situations such as stack pop verification failure, permission exceptions, and memory access exceptions. When the comparison result of the SSPOPCHK instruction is inconsistent, the checksum and exception unit triggers a control flow integrity exception; when a permission exception or memory access exception occurs during shadow stack access, the checksum and exception unit reports the corresponding exception to the processor's exception handling process.

[0103] The commit and restore unit is used to commit the speculative mapping of the SSP to the architectural state when an instruction is committed normally, thus advancing the SSP architectural state; and to restore the speculative mapping of the SSP to the correct state using checkpoints or commit mappings when branch misprediction, exceptions, or other pipeline flushing occur. Since the renaming mapping of the SSP is included in the processor's unified checkpoint storage scope, the restore operation of the commit and restore unit shares the same set of restore control logic and restore data path as the restore operation of ordinary integer registers.

[0104] The aforementioned units work together to enable the SSP to participate in renaming, dispatching, execution, and speculative recovery like a normal register data stream, while fully maintaining the security semantics and precise exception capabilities required by the RISC-V shadow stack extension. This avoids blocking the pipeline front-end decoding, renaming, dispatching, and committing processes.

[0105] After introducing the methods and apparatus of exemplary embodiments of the present invention, the following references are made. Figure 5 A computer-readable storage medium according to exemplary embodiments of the present invention will be described, please refer to... Figure 5 The computer-readable storage medium shown is an optical disc 50, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it implements the steps described in the above method implementation, such as: identifying the type of the target instruction entering the decoding stage to determine the instruction type of the target instruction; wherein the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type; if the target instruction is the shadow stack instruction type or the CSR instruction type, then the target instruction is converted into an internal data stream operation instruction; the internal data stream operation instruction is renamed based on the current speculative mapping of the SSP logic register to obtain a renamed internal data stream operation instruction; the renamed internal data stream operation instruction is dispatched to the execution path corresponding to the renamed internal data stream operation instruction to obtain the execution result corresponding to the renamed internal data stream operation instruction; the specific implementation of each step will not be repeated here.

[0106] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0107] After introducing the methods, apparatus, and media of exemplary embodiments of the present invention, the following references are made. Figure 6 A computing device for instruction processing of a non-blocking RISC-V shadow stack according to an exemplary embodiment of the present invention.

[0108] Figure 6 A block diagram is shown of an exemplary computing device 60 suitable for implementing embodiments of the present invention. The computing device 60 may be a computer system or a server. Figure 6 The computing device 60 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present invention.

[0109] like Figure 6 As shown, the components of computing device 60 may include, but are not limited to: one or more processors or processing units 601, system memory 602, and bus 603 connecting different system components (including system memory 602 and processing unit 601).

[0110] The computing device 60 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 60, including volatile and non-volatile media, removable and non-removable media.

[0111] System memory 602 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 6021 and / or cache memory 6022. Computing device 60 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, ROM 6023 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 6 Not shown in the image (usually referred to as a "hard drive"). Although not shown in Figure 6 The diagram shows that disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disc drives for reading and writing to removable non-volatile optical discs (e.g., CD-ROMs, DVD-ROMs, or other optical media) can be provided. In these cases, each drive can be connected to bus 603 via one or more data media interfaces. System memory 602 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0112] A program / utility 6025 having a set (at least one) of program modules 6024 may be stored, for example, in system memory 602, and such program modules 6024 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment. Program modules 6024 typically perform the functions and / or methods described in the embodiments of the present invention.

[0113] The computing device 60 can also communicate with one or more external devices 604 (such as a keyboard, pointing device, display, etc.). This communication can be performed via input / output (I / O) interface 605. Furthermore, the computing device 60 can also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via network adapter 606. Figure 6As shown, network adapter 606 communicates with other modules of computing device 60 (such as processing unit 601) via bus 603. It should be understood that, although... Figure 6 Other hardware and / or software modules may be used in conjunction with computing device 60, as not shown in the diagram.

[0114] Processing unit 601 executes various functional applications and data processing by running programs stored in system memory 602. For example, it performs type identification on target instructions entering the decoding stage to determine the instruction type of the target instruction; wherein the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type; if the target instruction is the shadow stack instruction type or the CSR instruction type, it converts the target instruction into an internal data flow operation instruction; it renames the internal data flow operation instruction based on the current speculative mapping of the SSP logic register to obtain a renamed internal data flow operation instruction; and it dispatches the renamed internal data flow operation instruction to the execution path corresponding to the renamed internal data flow operation instruction to obtain the execution result corresponding to the renamed internal data flow operation instruction. The specific implementation of each step will not be repeated here. It should be noted that although several units / modules or sub-units / sub-modules of the non-blocking RISC-V shadow stack instruction processing device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of a unit / module described above can be further divided into multiple units / modules for specificity.

[0115] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0116] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0117] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0118] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0120] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0121] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0122] Furthermore, although the operations of the methods of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps. In an exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the methods described above.

Claims

1. A non-blocking RISC-V shadow stack instruction processing method, characterized in that, The method, applied to the SSP logical register established within the processor, includes: The target instruction entering the decoding stage is type-identified to determine the instruction type of the target instruction; wherein, the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type; If the target instruction is of the shadow stack instruction type or the CSR instruction type, then the target instruction is converted into an internal data stream operation instruction; The internal data stream operation instruction is renamed based on the current speculative mapping of the SSP logical register to obtain the renamed internal data stream operation instruction. The rename internal data stream operation instruction is dispatched to the execution path corresponding to the rename internal data stream operation instruction to obtain the execution result corresponding to the rename internal data stream operation instruction.

2. The instruction processing method for a non-blocking RISC-V shadow stack according to claim 1, characterized in that, After determining the instruction type of the target instruction, the method further includes: If the target instruction is of the ordinary instruction type, then the target instruction is processed according to the preset ordinary instruction processing method; Furthermore, if the target instruction is of the shadow stack instruction type or the CSR instruction type, then converting the target instruction into an internal data stream operation instruction specifically includes: If the target instruction is of the shadow stack instruction type or the CSR instruction type, then the target instruction is verified to obtain the verification result; If the verification result indicates that the target instruction has passed the instruction verification, then the target instruction is converted into an internal data stream operation instruction.

3. The instruction processing method for a non-blocking RISC-V shadow stack according to claim 2, characterized in that, The step of performing instruction verification on the target instruction to obtain the verification result specifically includes: Obtain the processor's current privilege level and the global enable flag for shadow stack extension corresponding to the target instruction; The SSP access permissions corresponding to the current privilege level of the processor are verified to obtain the SSP access permission verification result. The on / off state of the global enable flag of the shadow stack extension is verified to obtain the flag verification result. The alignment of the SSP value to be written corresponding to the target instruction is verified to obtain the alignment verification result; If the SSP access permission verification result, the flag bit verification result, and the alignment method verification result all indicate that the verification is passed, then the instruction verification of the target instruction is determined as the verification result; wherein, the passing of the SSP access permission verification result indicates that the processor currently running at the privilege level has the SSP access permission, the passing of the flag bit verification result indicates that the shadow stack extension global enable flag is in the enabled state, and the passing of the alignment method verification result indicates that the alignment method of the SSP value to be written meets the alignment requirements; If any of the SSP access permission verification results, the flag bit verification results, and the alignment verification results indicate that the verification failed, then the failure of the target instruction's instruction verification is determined as the verification result.

4. The instruction processing method for a non-blocking RISC-V shadow stack according to claim 1, characterized in that, The shadow stack instruction type includes the SSPUSH push instruction, the SSPOPCHK pop and check instruction, the SSRDP pointer read instruction, and the SSAMOSWAP atomic swap instruction. If the target instruction is of the shadow stack instruction type, the target instruction is converted into an internal data stream operation instruction, specifically including: If the target instruction is the SSPUSH push instruction, then the SSPUSH push instruction is converted into an SSPUSH internal data stream operation instruction; wherein, the SSPUSH internal data stream operation instruction includes determining the shadow stack storage address based on the read current SSP value, writing the SSP value to be written corresponding to the SSPUSH internal data stream operation instruction into the shadow stack memory corresponding to the shadow stack storage address, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSPOPCHK stack pop verification instruction, then the SSPOPCHK stack pop verification instruction is converted into an SSPOPCHK internal data flow operation instruction; wherein, the SSPOPCHK internal data flow operation instruction includes determining the shadow stack storage address based on the read current SSP value, comparing the data read from the shadow stack storage address with the register data corresponding to the SSPOPCHK internal data flow operation instruction, and updating the generated new SSP value to the current SSP value; If the target instruction is the SSRDP pointer read instruction, then the SSRDP pointer read instruction is converted into an SSRDP internal data stream operation instruction; wherein, the SSRDP internal data stream operation instruction includes writing the read current SSP value into the destination register; If the target instruction is the SSAMOSWAP atomic swap instruction, then the SSAMOSWAP atomic swap instruction is converted into an SSAMOSWAP internal data stream operation instruction; wherein, the SSAMOSWAP internal data stream operation instruction includes a shadow stack atomic memory access swap operation based on the address pointed to by the current SSP value.

5. The instruction processing method for a non-blocking RISC-V shadow stack according to claim 4, characterized in that, The CSR instruction type includes SSP-related CSR read instructions, SSP-related CSR write instructions, and SSP-related CSR read / write instructions. If the target instruction is of the CSR instruction type, the target instruction is converted into an internal data stream operation instruction, specifically including: If the target instruction is the SSP-related CSR read instruction, then the SSP-related CSR read instruction is converted into a first internal data stream operation instruction; wherein, the first internal data stream operation instruction is used to perform the read and data transfer operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR write instruction, then the SSP-related CSR write instruction is converted into a second internal data stream operation instruction; wherein, the second internal data stream operation instruction is used to perform the rewrite operation corresponding to the current SSP value; If the target instruction is the SSP-related CSR read / write instruction, then the SSP-related CSR read / write instruction is converted into a third internal data stream operation instruction; wherein, the third internal data stream operation instruction is used to sequentially execute the read and data output operations corresponding to the current SSP value and the write operation corresponding to the generated new SSP value.

6. The instruction processing method for a non-blocking RISC-V shadow stack according to claim 5, characterized in that, The step of dispatching the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, and obtaining the execution result corresponding to the rename internal data stream operation instruction, specifically includes: The SSPUSH push instruction is dispatched to the corresponding storage execution path to obtain the execution result of the SSPUSH push instruction; or... The SSPOPCHK stack pop verification instruction is dispatched to the loading execution path and comparison path corresponding to the SSPOPCHK stack pop verification instruction to obtain the execution result corresponding to the SSPOPCHK stack pop verification instruction; or... The SSRDP pointer read instruction is dispatched to the data movement path corresponding to the SSRDP pointer read instruction to obtain the execution result corresponding to the SSRDP pointer read instruction; or... The SSAMOSWAP atomic swap instruction is dispatched to the atomic access path corresponding to the SSAMOSWAP atomic swap instruction to obtain the execution result corresponding to the SSAMOSWAP atomic swap instruction; or... The first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction are dispatched to the integer execution path to obtain the execution results corresponding to the first internal data stream operation instruction, the second internal data stream operation instruction, and the third internal data stream operation instruction.

7. The instruction processing method for a non-blocking RISC-V shadow stack according to claim 1, characterized in that, After obtaining the execution result corresponding to the rename internal data stream operation instruction, the method further includes: If the rename internal data stream operation instruction is submitted normally, then update the submission mapping or architecture state; If an error occurs during the execution of the rename internal data stream operation instruction, the SSP speculative mapping is restored using checkpoints or commit mapping.

8. A non-blocking RISC-V shadow stack instruction processing apparatus for implementing the method as described in any one of claims 1-7, characterized in that, The device is applied to the SSP logical register established within the processor and includes: The identification unit is used to identify the type of the target instruction entering the decoding stage and determine the instruction type of the target instruction; wherein the instruction type is a shadow stack instruction type, a CSR instruction type, or a normal instruction type; A conversion unit is configured to convert the target instruction into an internal data stream operation instruction if the target instruction is of the shadow stack instruction type or the CSR instruction type. The renaming unit is used to rename the internal data stream operation instruction based on the current speculative mapping of the SSP logical register to obtain the renamed internal data stream operation instruction. The dispatching unit is used to dispatch the rename internal data stream operation instruction to the execution path corresponding to the rename internal data stream operation instruction, and obtain the execution result corresponding to the rename internal data stream operation instruction.

9. A computing device, characterized in that, The computing device includes: At least one processor, memory, and input / output unit; The memory is used to store computer programs, and the processor is used to call the computer programs stored in the memory to execute the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the method of any one of claims 1 to 7.

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