1553B bus protocol chip interrupt control and data packing method

Abstract

The present application relates to the technical field of integrated circuit design, in particular to a kind of 1553B bus protocol chip's interrupt control and data packing method, comprising the following steps: in 1553B bus message transmission, interrupt event information, command word, status word, data word length, error state and cache index are collected, package description item is generated and is bound with corresponding data word, data word range and cache reading position are determined according to package description item, and then write in package queue, according to interrupt event information, error state and package queue state, interrupt arbitration is carried out, after host processor reads package description item and corresponding data word, interrupt confirmation and cache release are executed.The present application associates interrupt reason, message boundary, cache position and data word packing relationship on chip side, so that host processor reads message data according to package, and makes interrupt output, data reading and cache release keep corresponding relationship.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an interrupt control and data packaging method for a 1553B bus protocol chip. Background Technology

[0002] The field of integrated circuit design technology revolves around the logic structure, interface timing, register configuration, on-chip memory, bus protocol adaptation, and hardware / software co-operation of semiconductor integrated circuits. Typically, on-chip data transfer and external device interaction are accomplished through the cooperation of protocol control logic, memory units, processor interfaces, transceiver circuits, and interrupt lines. The interrupt control and data packetization method of traditional 1553B bus protocol chips refers to the following approach for MIL-STD-1553B bus communication: Under the working state of the bus controller, remote terminal, or bus monitor, based on information such as command words, status words, data words, message completion flags, error flags, and buffer addresses, the received or to-be-sent data words are read and written into the on-chip buffer or host memory area in message order. An interrupt request is generated based on transmission completion, format verification, abnormal status, or buffer access conditions. The host processor then reads the interrupt status register and data buffer contents before proceeding with subsequent bus message processing.

[0003] Traditional 1553B bus protocol chips rely on interrupt status registers, error flag registers, buffer addresses, and on-chip caches to provide information after message transmission is completed or an exception occurs. The host processor needs to access the cache contents according to the register status. Message boundaries, interrupt causes, and data word ranges are scattered across different read objects. When consecutive messages or abnormal messages are intertwined, the host-side parsing order and cache release timing may be affected by the results of multiple accesses. The correspondence between interrupt confirmation and message data reading needs to be maintained again by the software side. Summary of the Invention

[0004] To achieve the above objectives, this invention provides an interrupt control and data packetization method for a 1553B bus protocol chip, comprising the following steps: during 1553B bus message transmission, collecting interrupt event information, command word, status word, data word length, error status, and cache index corresponding to the message transmission; generating a packet description item based on the interrupt event information, command word, status word, data word length, error status, and cache index, and establishing a binding relationship between the packet description item and the corresponding data word; determining the data word range and cache read position based on the packet description item, and writing the corresponding data word length into the packet queue; performing interrupt arbitration based on the interrupt event information, error status, and packet queue status, and mapping the interrupt cause obtained from the arbitration to the corresponding position in the packet queue; after the host processor reads the packet description item and the corresponding data word, performing interrupt confirmation and cache release based on the packet read status.

[0005] Furthermore, the steps for collecting interrupt event information, command word, status word, data word length, error status, and cache index corresponding to message transmission include: when the 1553B bus protocol chip is in the working state of bus controller, remote terminal, or bus monitor, the protocol control logic forms a message acquisition trigger condition at the timing points of command word parsing completion, status word return completion, data word reception completion, or data word transmission completion; when the message acquisition trigger condition is met, the current message direction, command word content, status word content, data word count value, cache start index, and error status are read; when the message acquisition trigger condition is not met, the packet write state of the previous message is maintained and the generation of new packet description items is prohibited.

[0006] Furthermore, the steps for generating a packet description item based on interruption event information, command word, status word, data word length, error status, and cache index include: writing interruption event information into the event type field, writing the current message direction into the message direction field, writing the data word count value into the data word length field, writing the cache start index into the cache index field, and writing the error status into the error status field; when the error status field indicates a format exception, a validation exception, or a cache access exception, the packet description item is marked as an abnormal packet; when the error status field does not indicate an exception, the packet description item is marked as a completed packet.

[0007] Furthermore, the packet description field also includes a packet sequence number field and a packet status field. When generating a packet description field, the packet sequence number field is written for the current message according to the packet writing order, and the packet status field is updated after the flags for abnormal packets or completed packets are written. When the packet status field indicates that the packet description field has been written, data word reading is allowed based on the data word length field and the cache index field. When the packet status field does not indicate that the packet description field has been written, data word reading is prohibited based on the data word length field and the cache index field.

[0008] Furthermore, the process of determining the data word range and cache read location based on the packet description includes: using the on-chip cache address corresponding to the cache index field as the starting point for data word reading, using the data word count value corresponding to the data word length field as the read length, and using the packet status field as the read permission condition; when the read permission condition is met, the corresponding data word is read from the on-chip cache according to the data word order in the 1553B bus message, and the read data word is written into the packet queue corresponding to the packet sequence number field.

[0009] Furthermore, the process of writing the read data words and corresponding packet sequence number fields into the packet queue includes: reading the queue write pointer and queue read pointer before writing to the packet queue, and forming a queue occupancy status based on the address relationship between the queue write pointer and queue read pointer; when the queue occupancy status has not reached the queue full status, writing to the packet queue in the order of packet sequence number field, packet description item and data words, and updating the queue write pointer after writing is completed; when the queue occupancy status reaches the queue full status, stopping the writing of data words and retaining the corresponding error status.

[0010] Furthermore, the steps for interrupt arbitration based on interrupt event information, error status, and packet queue status include: first, comparing whether the error status indicates a format exception, a verification exception, or a cache access exception; when the error status indicates any exception, the interrupt event information corresponding to the exception is determined as the current interrupt cause; when the error status does not indicate an exception, comparing whether the packet queue status has reached a preset queue level; when the packet queue status has reached the preset queue level, the interrupt event information corresponding to the completion event is determined as the current interrupt cause; when the packet queue status has not reached the preset queue level, the original state of the interrupt output is maintained.

[0011] Furthermore, the process of mapping the interrupt cause obtained from arbitration to the corresponding position in the packet queue includes: when the current interrupt cause is determined by the interrupt event information corresponding to the exception, establishing a mapping relationship between the current interrupt cause and the packet sequence number field of the exception packet, and writing the position of the corresponding exception packet in the packet queue into the interrupt status register; when the current interrupt cause is determined by the interrupt event information corresponding to the completion event, establishing a mapping relationship between the current interrupt cause and the completion packet corresponding to the current read pointer of the packet queue, and writing the position of the completion packet into the interrupt status register.

[0012] Furthermore, the process of the host processor reading the packet descriptor and the corresponding data word includes: the host processor first reads the packet queue position recorded in the interrupt status register, and then reads the packet descriptor according to the packet queue position; when the packet status field in the packet descriptor indicates that the writing is complete, the corresponding data word is read according to the data word length field in the packet descriptor; when the packet status field does not indicate that the writing is complete, the reading of the corresponding data word is stopped and the interrupt confirmation status is kept incomplete.

[0013] Furthermore, after the host processor reads the packet descriptor and the corresponding data word, it forms a packet read state, which includes a descriptor read complete state and a data word read complete state. When both the descriptor read complete state and the data word read complete state are true, the packet sequence number field corresponding to the packet descriptor is written to the interrupt confirmation register, and the queue read pointer is updated according to the packet queue position to release the corresponding buffer area. When the descriptor read complete state or the data word read complete state is not true, the interrupt confirmation state remains incomplete, and updating the queue read pointer is prohibited.

[0014] Compared with the prior art, the advantages and positive effects of the present invention are as follows: In this invention, interrupt event information is collected within the 1553B bus protocol chip and used to generate packet description items together with command words, status words, data word lengths, error states, and cache indexes. The interrupt cause, message boundary, and cache location form the same descriptive basis on the chip side. By packaging the corresponding data words according to the packet description items and writing them into the packet queue, the host processor can read complete message data according to the description items. By combining interrupt event information, error states, and packet queue states to perform interrupt arbitration, and performing interrupt confirmation and cache release after reading, a consistent processing chain is formed between interrupt output, data reading, and cache management. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is the main flowchart of interrupt control and data packaging in this invention; Figure 2 This is a schematic diagram of the structure of the packet description field in this invention; Figure 3 This is a schematic diagram of the packet queue writing relationship of the present invention; Figure 4 This is a schematic diagram illustrating the interruption of arbitration and packet mapping in this invention; Figure 5 This is a schematic diagram illustrating the host read confirmation and cache release process of the present invention; Figure 6 This is a schematic diagram illustrating the state transition between abnormal packets and completed packets in this invention. Detailed Implementation

[0017] The present invention will be further described below with reference to embodiments. Subsequent embodiments explain the processing chain of an interrupt control and data packetization method for a 1553B bus protocol chip when executed internally within the chip. From an integrated circuit design perspective, the subsequent embodiments focus on the protocol logic, register access, on-chip cache, queue control, and host interface coordination to illustrate the implementable logic of the method within the protocol chip. The 1553B bus protocol chip involved in the embodiments refers to a protocol chip used to perform 1553B bus message parsing, interrupt event acquisition, packet description item generation, data word packetization, packet queue writing, interrupt arbitration, host processor read confirmation, and cache release. This protocol chip belongs to a dedicated protocol control circuit object in integrated circuit design, and its internal processing is completed through the cooperation between hardware logic, status registers, cache resources, and the bus interface. The interrupt event information in the embodiments refers to the event record generated internally by the chip when message transmission is completed, an error state is formed, or the packet queue state meets the triggering conditions. In this embodiment, the packet description item refers to descriptive data formed by interrupt event information, command word, status word, data word length, error status, and cache index, used to represent the event type, message direction, data range, cache source, and status identifier corresponding to a 1553B bus message. The packet queue in this embodiment refers to an on-chip queue structure used to sequentially store packet description items and corresponding data words. In integrated circuit design and implementation, the packet queue can be understood as a cache organization form jointly formed by on-chip storage resources and queue read / write control logic. The packet read status in this embodiment refers to the completion status of the host processor's reading of the packet description item and corresponding data word. Component labels in this embodiment are not enclosed in parentheses; the labels are only used to identify the corresponding technical objects in the accompanying drawings and do not constitute a limitation on quantity, parameters, order, or range; technical objects without explicitly configured labels are not additionally labeled. The step numbers involved in this embodiment are only used to indicate the execution relationship between method steps and do not constitute a limitation on specific timing intervals, execution cycles, or processing times.

[0018] Please see Figures 1 to 6This embodiment provides an interrupt control and data packaging method for a 1553B bus protocol chip, applicable to interrupt association processing of bus messages by the 1553B bus protocol chip when the bus controller, remote terminal, or bus monitor is in operation. The processing object and execution carrier in this embodiment are limited to the 1553B bus protocol chip within the integrated circuit design, focusing on the organization of the relationship between protocol fields, cache addresses, and interrupt states by the on-chip control logic. During message reception, message transmission, message monitoring, or anomaly detection, the 1553B bus protocol chip first forms a unified description of the message-related states within the chip, then packages the description and data words into a queue, enabling the host processor to read the corresponding message based on the queue position, and triggering interrupt confirmation and cache release upon completion of the reading. This method includes the following steps.

[0019] S1, during the 1553B bus message transmission process, collects the interrupt event information, command word, status word, data word length, error status and cache index corresponding to the message transmission.

[0020] In S1, the 1553B bus message transmission process includes the processing of messages initiated by the bus controller, responses from remote terminals, and records from the bus monitor. Command words originate from the chip's internal parsing of the 1553B bus word sequence; status words come from the status fields during the remote terminal response or monitoring process; data word lengths are derived from the data word count corresponding to the real-time message; error states are obtained from the chip's internal detection of format anomalies, verification anomalies, or cache access anomalies; and the cache index is derived from the starting position of the cache corresponding to the real-time message in the on-chip cache. All of this data forms a single message acquisition object within the chip, which is then used to generate packet description items. In the integrated circuit design and implementation, this acquisition object is jointly provided by the on-chip protocol parsing logic, interrupt event recording logic, error state detection logic, and cache index generation logic, ensuring that the input source forms a defined data path within the chip-level circuitry.

[0021] S101, when the 1553B bus protocol chip is in the working state of bus controller, remote terminal or bus monitor, the protocol control logic forms the message acquisition trigger condition at the timing points of command word parsing completion, status word return completion, data word reception completion or data word transmission completion.

[0022] In S101, the protocol control logic uses the word sequence processing status of the 1553B bus message as the acquisition trigger. When the chip completes command word parsing, the command word content and message direction can be determined; when the status word returns completion, the status word content can be used as the message status basis; when data word reception or transmission is completed, the data word count value and the corresponding data word range in the on-chip buffer can be determined. When any of the above timing points related to the real-time message boundary meets the acquisition condition, the protocol control logic identifies the real-time message as a message object to be generated into a packet. This trigger condition belongs to the timing control condition in integrated circuit design, used to constrain the on-chip state machine to enter the packet generation path only after the protocol field is stable.

[0023] S102, when the message collection trigger condition is met, read the real-time message direction, command word content, status word content, data word count value, cache start index and error status.

[0024] In S102, the real-time message direction is used to distinguish the sending direction, receiving direction, or monitoring source of the bus message; the command word content indicates the remote terminal address, sub-address, transmit / receive attributes, and data word quantity source of the real-time message; the status word content records the remote terminal response status or monitoring status; the data word count value determines the range of data words subsequently read from the on-chip buffer; the buffer start index points to the starting read position of the real-time message in the on-chip buffer; and the error status records the status of format exception, verification exception, buffer access exception, or no exception. The read information enters the packet description generation process and is not directly parsed by the host processor. The above reading actions correspond to the internal register field retrieval and on-chip signal latching processes in integrated circuit design, the purpose of which is to associate the message direction, protocol field, and buffer location within the same chip timing.

[0025] S103, when the message collection trigger condition is not met, maintain the packet writing state of the previous message and prohibit the generation of new packet description items.

[0026] In S103, maintaining the packet write state of the previous message means that the chip does not change the already established descriptor state, queue write state, and cache read relationship in the real-time packet write link. Prohibiting the generation of new packet descriptors prevents incomplete message fields from being written into subsequent packet processes before a complete message boundary is formed, ensuring that packet generation actions correspond to message acquisition trigger conditions. This prohibition mechanism can serve as a state preservation strategy in integrated circuit design, preventing on-chip control logic from entering incorrect write paths before protocol fields are stable.

[0027] S2 generates a packet description item based on the interrupt event information, command word, status word, data word length, error status, and cache index, and establishes a binding relationship between the packet description item and the corresponding data word.

[0028] In S2, the packet descriptor serves as the header description data for real-time 1553B bus messages. Interrupt event information records the interrupt source corresponding to the real-time message; command and status words record the protocol fields of the real-time message; data word length indicates the read length of the corresponding data word; error status indicates whether the message belongs to an abnormal packet; and cache index indicates the starting point for reading the data word in the on-chip cache. By forming the packet descriptor internally, interrupt events, message fields, error statuses, and cache locations are associated within the same descriptor object. At the integrated circuit design level, the packet descriptor is equivalent to structured control data formed by combining multiple on-chip status fields, used to connect interrupt control circuits, cache access circuits, and host interface circuits.

[0029] S201, write the interruption event information to the event type field, write the real-time message direction to the message direction field, write the data word count value to the data word length field, write the cache start index to the cache index field, and write the error status to the error status field.

[0030] In S201, the event type field distinguishes between message completion events, format exception events, validation exception events, and cache access exception events. The message direction field records whether the real-time message belongs to a sending, receiving, or monitoring record. The data word length field limits the range of data words read during subsequent readings. The cache index field points to the starting position of the data word corresponding to the real-time message in the on-chip cache. The error status field, together with the event type field, determines the packet attributes of the real-time packet description item. The writing order and meaning of these fields provide constraints on the organization of packet description data in integrated circuit design, enabling on-chip logic to perform subsequent arbitration and reading according to fixed field semantics.

[0031] S202, when the error status field indicates a format error, validation error, or cache access error, mark the packet descriptor as an abnormal packet.

[0032] In S202, a format exception indicates that the protocol format of the real-time 1553B bus message does not meet the chip's internal format judgment conditions; a verification exception indicates that the real-time message forms an abnormal state during the verification process; and a cache access exception indicates that the cache read / write conditions corresponding to the real-time message do not meet normal access requirements. When the error status field indicates one of the above exceptions, an exception packet flag is written along with the packet description for priority identification by subsequent interrupt arbitration. This exception packet flag can be directly driven by the error detection logic in the integrated circuit design, avoiding the separation of the exception state and the corresponding message data within the chip.

[0033] S203, when the error status field does not indicate an exception, mark the packet description item as a completed packet.

[0034] In S203, a completion packet indicates that the real-time message has met the conditions for data word packaging. A completion packet does not indicate an evaluation of the message content, but rather that the real-time packet description can serve as the basis for subsequent data word range determination and packet queue writing. The completion packet flag, along with the event type field, data word length field, and cache index field, participates in subsequent processing. In integrated circuit design, this completion packet flag can serve as a status input for allowed data word read paths.

[0035] S204, the packet description item also includes a packet sequence number field and a packet status field. When generating the packet description item, the packet sequence number field is written for real-time messages according to the packet writing order, and the packet status field is updated after the abnormal packet or the completed packet is written.

[0036] In S204, the packet sequence number field indicates the sequential identity of the packet descriptor in the packet writing process, and the packet status field indicates whether the packet descriptor has been written completely. A correspondence is established between the packet sequence number field and the subsequent packet queue position, interrupt status register record, and host processor read confirmation. The packet status field is updated after an abnormal packet or after the packet completion marker is written, enabling subsequent read operations to determine whether the packet descriptor has reached a usable state. In integrated circuit design, the packet sequence number field can serve as a logical index for on-chip queue positioning, and the packet status field can serve as a state gating condition for the read / write control circuit.

[0037] S205, when the packet status field indicates that the packet description item has been written, data word reading is allowed based on the data word length field and the cache index field; when the packet status field does not indicate that the packet description item has been written, data word reading is prohibited based on the data word length field and the cache index field.

[0038] In S205, the packet status field serves as a prerequisite for data word reading. The data word length field and cache index field are only invoked by the subsequent packing process after the packet descriptor has been completely written. If the packet descriptor has not yet been written, even if a data word exists in the on-chip cache, the corresponding data word reading action is not initiated to maintain the integrity of the binding relationship between the descriptor and the data word. This prerequisite reflects the collaborative relationship between state gating and cache access control in integrated circuit design.

[0039] S3. Determine the data word range and cache read position based on the packet description, and write the corresponding data word length into the packet queue.

[0040] In S3, the data word range is represented by the data word length field, and the cache read location is represented by the cache index field. Internally, the chip uses the packet description as the basis for reading, retrieving the data word corresponding to the real-time message from the on-chip cache, and writing the data word into the packet queue according to the packet sequence number field in the packet description. Through this process, when the host processor reads the packet queue, it can first obtain the description and then retrieve the corresponding data word based on the description. This process belongs to the on-chip data movement and structured cache organization process in integrated circuit design; the data flow from the on-chip cache into the packet queue is constrained by the description field.

[0041] S301 uses the on-chip cache address corresponding to the cache index field as the starting point for reading data words, the data word count value corresponding to the data word length field as the reading length, and the packet status field as the read permission condition.

[0042] In S301, the cache index field, data word length field, and packet status field jointly determine the data word read action. The cache index field provides the starting position of the data word in the on-chip cache, the data word length field provides the range of data words to be read, and the packet status field provides the status conditions for whether reading is allowed. All of these fields are derived from the packet description, avoiding the host processor having to make scattered judgments on multiple registers and cache addresses during the interrupt response phase. In integrated circuit design, this combination of fields can serve as the common input for the on-chip cache read address generation logic and the read enable logic.

[0043] S302: When the read enable condition is met, the corresponding data word is read from the on-chip buffer according to the data word order in the 1553B bus message, and the read data word is written into the packet queue along with the packet sequence number field.

[0044] In S302, the data word order is consistent with the data word arrangement order in the 1553B bus message. Read data words are not written separately from the packet description field; instead, they are written to the packet queue after establishing a correspondence with the packet sequence number field. The packet sequence number field is used to identify the corresponding packet in subsequent interrupt mapping, host reads, and buffer releases. The data words received by the packet queue serve as the message content for subsequent reads by the host processor. This writing method allows the on-chip queue unit in the integrated circuit design to simultaneously carry the logical association between description information and data content.

[0045] S303 reads the queue write pointer and queue read pointer before writing to the packet queue, and forms the queue occupancy status based on the address relationship between the queue write pointer and the queue read pointer.

[0046] In the S303, the queue write pointer indicates the position for the next write operation in the packet queue, while the queue read pointer indicates the position for the host processor's next read operation or a confirmed read operation. Through the address relationship between the queue write and queue read pointers, the chip internally establishes a queue occupancy status, indicating whether the packet queue is ready to continue writing packet descriptors and data words. The queue write and queue read pointers are typical on-chip queue control signals in integrated circuit design, used to coordinate the resource boundaries between write and read paths.

[0047] S304: When the queue occupancy status has not reached the queue full status, the packet sequence number field, packet description item and data word are written to the packet queue in the order of writing, and the queue write pointer is updated after the writing is completed.

[0048] In S304, the write order first establishes a queue position relationship between the packet sequence number field and the real-time packet descriptor, and then the data word follows the corresponding packet descriptor into the packet queue. The queue write pointer is updated after the write is completed, so that the next message can be processed based on the new write position. Updating the queue write pointer does not change the read relationship of already written packets. This sequential write method matches the queue address progression control in integrated circuit design.

[0049] S305: When the queue is full, stop writing data words and retain the corresponding error status.

[0050] In S305, a full queue indicates that the packet queue is not ready to continue writing the corresponding data word. Stopping data word writing prevents new data words from overwriting packet content that has not yet been read and acknowledged by the host processor. The corresponding error state is retained so that subsequent interrupt arbitration can treat cache access errors or queue state errors as interrupt events. This process reflects the protection logic for on-chip memory resource boundaries in integrated circuit design.

[0051] S4 performs interrupt arbitration based on interrupt event information, error status, and packet queue status, and maps the interrupt cause obtained from the arbitration to the corresponding position in the packet queue.

[0052] In S4, interrupt arbitration is used to determine the interrupt cause that should be output to the host processor in real time among error events, completion events, and packet queue states. Instead of simply setting the interrupt cause and having the host processor search for the corresponding message again, a mapping relationship is established between the interrupt cause and the packet position in the packet queue, enabling the interrupt status register to record the position information related to packet reading. In integrated circuit design, interrupt arbitration logic, as a core component of the on-chip control path, is used to unify event priorities, queue states, and register outputs into a state that can be read by the host interface.

[0053] S401 First, compare whether the error status indicates a format error, a verification error, or a cache access error. When the error status indicates any of the errors, determine the interrupt event information corresponding to the error as the cause of the real-time interrupt.

[0054] In S401, error status checks precede completion event and queue level checks. Formatting errors, validation errors, and buffer access errors are all exceptions that can affect the processing status of real-time message packets. When an error status indicates any exception, the interrupt arbitration determines the corresponding interrupt event information as the cause of the real-time interrupt, which is then written into the interrupt status register and associated with the exception packet. This priority determination can be implemented in the integrated circuit design using a priority arbitration circuit or equivalent status selection logic.

[0055] S402, when the error status does not indicate an exception, compare whether the packet queue status has reached the preset queue level.

[0056] In S402, the preset queue level is used to indicate the queue state where completed packets have accumulated to the point where an interrupt can be triggered. The preset queue level is only used as a source of judgment and is not limited to a specific value in the embodiment. In integrated circuit design, the preset queue level can be provided by an on-chip configuration register, a fixed logic state, or a configuration method supported by the original disclosure. The packet queue state is reflected by the queue write pointer, queue read pointer, and queue occupancy status. When the error state does not indicate an exception, interrupt arbitration re-enters the queue level judgment, establishing a priority coverage relationship between exception events and completion events.

[0057] S403: When the packet queue status reaches the preset queue level, the interrupt event information corresponding to the completion event is determined as the real-time interrupt cause; when the packet queue status does not reach the preset queue level, the original status of the interrupt output terminal is maintained.

[0058] In S403, the interrupt event information corresponding to a completion event indicates that a completed packet in the packet queue has reached the output condition. Maintaining the original state of the interrupt output terminal means that no new completion event interrupt output is generated if the preset queue level is not reached and no abnormal event occurs. This processing associates the interrupt output of a normal completion event with the packet queue state. This processing method is suitable for interrupt output terminal control in integrated circuit design, ensuring that normal completion events are not output independently of the queue state.

[0059] S404: When the cause of a real-time interrupt is determined by the interrupt event information corresponding to the exception, a mapping relationship is established between the cause of the real-time interrupt and the packet sequence number field of the exception packet, and the position of the corresponding exception packet in the packet queue is written into the interrupt status register.

[0060] In S404, the packet sequence number field of the exception packet is used to identify the packet description item corresponding to the exception event. The interrupt status register records the packet queue position associated with the exception packet, enabling the host processor to directly enter the reading process of the corresponding exception packet after reading the interrupt status register. The mapping relationship between the real-time interrupt cause and the exception packet is used to maintain the correspondence between the exception event and the message data. In integrated circuit design, the interrupt status register not only serves as a status output register but also carries the host-readable interface function of packet location information.

[0061] S405: When the cause of the real-time interrupt is determined by the interrupt event information corresponding to the completion event, a mapping relationship is established between the cause of the real-time interrupt and the completion packet corresponding to the real-time read pointer of the packet queue, and the position of the completion packet is written into the interrupt status register.

[0062] In the S405, the completion packet corresponding to the real-time read pointer is the next completion packet object read by the host processor. After writing the position of the completion packet into the interrupt status register, the host processor can read the packet descriptor and corresponding data word using the position in the interrupt status register as the entry point. A one-to-one reading relationship is maintained between the interrupt cause corresponding to the completion event and the completion packet. This mapping relationship reflects the coordination between the on-chip queue read pointer and the external host access entry in the integrated circuit design.

[0063] S5, after the host processor reads the packet description item and the corresponding data word, performs interrupt confirmation and buffer release according to the packet read status.

[0064] In S5, the host processor obtains the packet queue position through the interrupt status register and reads the corresponding packet descriptor based on that position. After reading the packet descriptor, the host processor reads the corresponding data word according to the data word length field in the packet descriptor. Internally, the chip forms a packet read status based on the descriptor read completion status and the data word read completion status, and performs interrupt confirmation and buffer release when the packet read status meets the conditions. In integrated circuit design, this step embodies the feedback loop between the host interface access path and the on-chip buffer release path.

[0065] S501: The host processor first reads the packet queue position recorded in the interrupt status register, and then reads the packet description item according to the packet queue position.

[0066] In S501, the packet queue position in the interrupt status register is written by the aforementioned interrupt arbitration and mapping process. The host processor does not need to read multiple independent registers separately to construct message boundaries; instead, it uses the packet queue position as the read entry point. The read packet description provides the event type, data word length, error status, and cache source for subsequent readings of the corresponding data word. This read entry point design conforms to the implementation method of providing on-chip status to the host processor through register mapping in integrated circuit design.

[0067] S502, when the packet status field in the packet description item indicates that the writing is complete, the corresponding data word is read according to the data word length field in the packet description item; when the packet status field does not indicate that the writing is complete, the reading of the corresponding data word is stopped and the interruption confirmation status is not completed.

[0068] In S502, the packet status field is used to determine whether the real-time packet description item is available for the host processor to continue reading data words. When the packet status field indicates that writing is complete, the host processor reads the corresponding data words within the range specified by the data word length field. When the packet status field does not indicate that writing is complete, reading the corresponding data words stops to prevent the host processor from treating data that has not yet been completely written as complete message content, while maintaining the interrupt acknowledgment status. This determination falls under the boundary control of conflicts between host read access and on-chip write status in integrated circuit design.

[0069] S503, after the host processor reads the packet description item and the corresponding data word, it forms a packet read status, which includes the description item reading completion status and the data word reading completion status.

[0070] In S503, the descriptor read completion status indicates that the host processor has acquired the packet descriptor, and the data word read completion status indicates that the host processor has acquired the corresponding data word based on the packet descriptor. The packet read status does not depend solely on the host processor's interrupt response action; rather, it is formed jointly by the descriptor read and data word read statuses. This status is used to determine whether to proceed with interrupt confirmation and buffer release. In integrated circuit design, the packet read status can serve as a common input condition for on-chip interrupt clearing logic and queue read pointer update logic.

[0071] S504: When both the description item read completion status and the data word read completion status are true, the packet sequence number field corresponding to the packet description item is written to the interrupt confirmation register, and the queue read pointer is updated according to the packet queue position to release the corresponding buffer area.

[0072] In the S504, after the interrupt confirmation register receives the packet sequence number field, the chip internally establishes a relationship between the host processor's confirmation action and the corresponding packet descriptor. After the queue read pointer is updated according to the packet queue position, it indicates that the queue area corresponding to the packet has been read and confirmed, and the corresponding buffer area can enter the release state. Interrupt confirmation, queue read pointer update, and buffer release are all triggered based on the packet read status. This feedback path reflects the synchronous control between register write confirmation, queue pointer update, and buffer resource release in integrated circuit design.

[0073] S505: When the description item read completion status or data word read completion status is not established, the interrupt confirmation status is kept incomplete, and the queue read pointer is not updated.

[0074] In the S505, any read status not being met indicates that the host processor has not yet completed reading the real-time packet. Maintaining the interrupt acknowledgment status incomplete prevents the chip from prematurely clearing interrupt states associated with real-time packets. Disabling queue read pointer updates prevents packet descriptors or data words that have not yet been read from being overwritten by subsequent packets. This process ensures consistency between the host processor's read status and buffer release actions. This incomplete status maintenance method is a protective state control feature in integrated circuit design, used to maintain timing consistency between on-chip queues and host access.

[0075] In this embodiment, the 1553B bus protocol chip forms the following closed loop in the data flow: bus message parsing generates command words, status words, data word lengths, and error states; the on-chip cache provides the data word source corresponding to the real-time message; the packet description generation process writes interrupt event information, protocol fields, cache index, and error states into the packet description item; the data word packaging process writes data words into the packet queue according to the packet description item; the interrupt arbitration process determines the interrupt cause based on the error state and the packet queue status; the host processor reads the corresponding packet according to the packet queue position in the interrupt status register; and after reading, the cache is released by updating the interrupt confirmation register and the queue read pointer. In this closed loop, each intermediate result has a preceding source and a subsequent receiving object. From the perspective of integrated circuit design, this closed loop unifies the protocol parsing path, on-chip storage path, interrupt output path, and host access path into the same packet processing link.

[0076] In this embodiment, format errors, validation errors, cache access errors, and queue full states are all considered as exception boundaries affecting packet processing. Format errors and validation errors originate from the message parsing and validation process, while cache access errors and queue full states originate from the access status of the on-chip cache and the packet queue. Exceptional packets do not change the correspondence between packet descriptors and data words; instead, they are identified in subsequent interrupt arbitration through the error status field and event type field. Both completed and exception packets can form traceable read entries through the packet sequence number field, packet queue position, and interrupt status register. The aforementioned exception boundaries can be transformed into branch conditions and register state output conditions of the on-chip state machine in integrated circuit design.

[0077] In this embodiment, the host processor's reading process does not change the order in which packet descriptors are generated and written to the packet queue within the chip. After reading the interrupt status register, the host processor first obtains the packet queue position, then the corresponding packet descriptor, and then reads the data word based on the data word length field in the packet descriptor. The interrupt confirmation register only receives the packet sequence number field when both the descriptor read completion status and the data word read completion status are true. The update of the queue read pointer and the interrupt confirmation maintain the same triggering basis to avoid the buffer release action from being separated from the data word read status. This reading order reflects the boundary division between host interface-side read access and on-chip control-side status updates in integrated circuit design.

[0078] The specific processes, field states, processing order, judgment conditions, cache index call relationships, packet description item generation methods, packet queue writing methods, interrupt arbitration methods, host processor reading methods, and cache release methods described in the above embodiments are only used to explain the feasible implementation of the present invention in the 1553B bus protocol chip and should not be construed as limiting the present invention to the specific embodiments listed. The above embodiments are also used to illustrate that the present invention can be completed collaboratively by on-chip logic, registers, caches, and interfaces in integrated circuit design scenarios, and should not be construed as limiting specific layouts, process nodes, or physical implementation forms. Without departing from the scope of the claims and the original disclosure, any equivalent substitutions, equivalent modifications, equivalent combinations, order adjustments, equivalent transformations of field names, equivalent acceptance of execution subjects, or equivalent changes in carrier forms that can be conceived by those skilled in the art should fall within the scope of protection of this patent; however, they should not be extended to unclaimed subjects, nor should the substantive correspondence of technical objects be changed through changes in reference numerals.

[0079] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of protection of the described technical solutions.

Claims

1. A method for interrupt control and data packetization of a 1553B bus protocol chip, characterized in that, include: During the 1553B bus message transmission process, the interrupt event information, command word, status word, data word length, error status, and cache index corresponding to the message transmission are collected. Based on the interrupt event information, command word, status word, data word length, error status, and cache index, a packet description item is generated, and the packet description item is bound to the corresponding data word. Based on the packet description, determine the data word range and cache read position, and write the corresponding data word length into the packet queue; An interruption arbitration is performed based on the interruption event information, error status, and packet queue status, and the interruption cause obtained from the arbitration is mapped to the corresponding position in the packet queue. After the host processor reads the packet description item and the corresponding data word, it performs interrupt confirmation and buffer release according to the packet read status.

2. The interrupt control and data packetization method for the 1553B bus protocol chip according to claim 1, characterized in that, The steps for collecting interruption event information, command word, status word, data word length, error status, and cache index corresponding to message transmission include: When the 1553B bus protocol chip is in the working state of bus controller, remote terminal or bus monitor, the protocol control logic forms the message acquisition trigger condition at the timing points of command word parsing completion, status word return completion, data word reception completion or data word transmission completion. When the message collection trigger condition is met, read the real-time message direction, command word content, status word content, data word count value, cache start index, and error status; When the message collection triggering condition is not met, the packet writing state of the previous message is maintained and the generation of new packet description items is prohibited.

3. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 2, characterized in that, The step of generating packet description items based on interrupt event information, command word, status word, data word length, error status, and cache index includes: Write the interruption event information to the event type field, write the real-time message direction to the message direction field, write the data word count value to the data word length field, write the cache start index to the cache index field, and write the error status to the error status field. When the error status field indicates a format error, a validation error, or a cache access error, the packet description item will be marked as an abnormal packet. When the error status field does not indicate an exception, the packet description item is marked as a completed packet.

4. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 3, characterized in that, The packet description item also includes a packet sequence number field and a packet status field. When generating the packet description item, the packet sequence number field is written for real-time messages according to the packet writing order, and the packet status field is updated after the abnormal packet or the completed packet is written. When the packet status field indicates that the packet description item has been written, data word reading is allowed based on the data word length field and the cache index field. When the packet status field does not indicate that the packet description item has been written, reading data words based on the data word length field and the cache index field is prohibited.

5. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 4, characterized in that, The process of determining the data word range and cache read location based on the packet description includes: The on-chip cache address corresponding to the cache index field is used as the starting point for reading data words, the data word count value corresponding to the data word length field is used as the reading length, and the packet status field is used as the read permission condition. When the read permission condition is met, the corresponding data word is read from the on-chip cache in the order of the data words in the 1553B bus message, and the read data word is written into the packet queue along with the packet sequence number field.

6. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 5, characterized in that, The process of writing the read data words and their corresponding packet sequence number fields into the packet queue includes: Before writing to the packet queue, read the queue write pointer and queue read pointer, and form the queue occupancy status according to the address relationship between the queue write pointer and the queue read pointer; When the queue occupancy status has not reached the queue full status, the packet is written into the packet queue in the order of the packet sequence number field, packet description item and data word, and the queue write pointer is updated after the writing is completed; When the queue is full, stop writing data words and retain the corresponding error status.

7. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 1, characterized in that, The steps for interrupt arbitration based on interruption event information, error status, and packet queue status include: First, compare whether the error status indicates a format error, a validation error, or a cache access error. If the error status indicates any of these errors, determine the interrupt event information corresponding to the error as the cause of the real-time interruption. When the error state does not indicate an anomaly, compare whether the packet queue state has reached the preset queue level. When the packet queue state has reached the preset queue level, determine the interrupt event information corresponding to the completion event as the real-time interrupt cause. When the packet queue state has not reached the preset queue level, maintain the original state of the interrupt output terminal.

8. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 7, characterized in that, The process of mapping the interruption cause obtained from the arbitration to the corresponding position in the packet queue includes: When the cause of a real-time interrupt is determined by the interrupt event information corresponding to the exception, a mapping relationship is established between the cause of the real-time interrupt and the packet sequence number field of the exception packet, and the position of the corresponding exception packet in the packet queue is written into the interrupt status register. When the cause of a real-time interrupt is determined by the interrupt event information corresponding to the completion event, a mapping relationship is established between the cause of the real-time interrupt and the completion packet corresponding to the real-time read pointer of the packet queue, and the position of the completion packet is written into the interrupt status register.

9. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 1, characterized in that, The process by which the host processor reads the packet descriptor and the corresponding data words includes: The host processor first reads the packet queue position recorded in the interrupt status register, and then reads the packet description item according to the packet queue position; When the packet status field in the packet description item indicates that the writing is complete, the corresponding data word is read according to the data word length field in the packet description item; When the packet status field does not indicate that the writing is complete, the reading of the corresponding data word is stopped and the interruption confirmation status remains incomplete.

10. The interrupt control and data packetization method for a 1553B bus protocol chip according to claim 9, characterized in that, After the host processor reads the packet description item and the corresponding data word, it forms a packet reading state, which includes a description item reading completion state and a data word reading completion state. When both the description item read completion status and the data word read completion status are true, the packet sequence number field corresponding to the packet description item is written into the interrupt confirmation register, and the queue read pointer is updated according to the packet queue position to release the corresponding buffer area; When the description item read completion status or data word read completion status is not established, the interrupt confirmation status remains incomplete, and updating the queue read pointer is prohibited.

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