A hybrid control type h-bridge inverter circuit and control method

Abstract

The application provides a hybrid control type H-bridge inverter circuit and a control method, and belongs to the technical field of power electronic inverters. The circuit comprises a DC bus module, an H-bridge power module, a drive control module, a GPIO level matching unit and a load current sampling feedback unit. The DC bus module supplies power to the H-bridge power module; the left upper and left lower bridge arms of the H-bridge power module are high-frequency fast tubes, and the right upper and right lower bridge arms are power-frequency slow tubes; the EPWM controller of the drive control module outputs a complementary high-frequency PWM signal with a dead zone to the fast tube, and the GPIO controller outputs a level drive signal to the slow tube through the GPIO level matching unit; the load current sampling feedback unit collects the load current and feeds it back to the EPWM controller to form a closed-loop control. The application directly drives the high-voltage slow tube through the level matching unit, does not need a special PWM chip, reduces the hardware cost, reduces the switching loss through the division of labor of the fast and slow tubes, and improves the output precision and load adaptability in combination with the closed-loop feedback.

Description

Technical Field

[0001] This invention relates to the field of power electronic inverter technology, specifically to a hybrid control type H-bridge inverter circuit and control method. Background Technology

[0002] The H-bridge inverter is a core topology for DC-AC power conversion, widely used in new energy photovoltaic power generation, wind power grid connection, industrial drives, and residential uninterruptible power supplies. Traditional full-bridge inverter circuits use four identical power switching transistors and achieve AC output through unified PWM (Pulse Width Modulation). Under this architecture, all switching transistors operate at high frequencies, resulting in high cumulative switching losses, low overall system efficiency, and the need for multiple dedicated PWM drive circuits, leading to high hardware costs and complex control circuit design.

[0003] Among the existing improvement solutions, the H4 bridge three-level circuit disclosed in CN103580524A adopts a combination of "power frequency switching transistor + high frequency switching transistor" and optimizes the level through an external freewheeling diode. However, it still has obvious defects: First, both the power frequency and high frequency switching transistors require independent dedicated drive circuits, which does not solve the level compatibility problem between the low-voltage interface of the general purpose input / output (GPIO) and the power frequency switching transistor on the high-voltage bus side. It is impossible to achieve direct drive of the slow transistor by the GPIO, which limits the optimization of hardware costs. Second, no real-time sampling feedback mechanism for load current is set, and the bridge arm control is in open-loop mode, which makes it difficult to accurately adjust the output according to load changes, resulting in poor output accuracy and load adaptability. Third, the zero-crossing bridge arm polarity switching is in direct on / off mode, which is prone to current surges, leading to output waveform distortion and low power quality. Another type of ESP32 chip-supported motor drive solution uses only the GPIO interface as a motor direction control switch signal, with the PWM module solely responsible for speed regulation. It does not achieve direct on / off control of the slow transistor by the GPIO, nor does it build a collaborative control mechanism of "high-frequency precise adjustment of the fast transistor + power frequency polarity switching of the slow transistor". Furthermore, it lacks a targeted dead-time protection optimization strategy, resulting in a high risk of bridge arm shoot-through.

[0004] Existing technologies cannot achieve direct GPIO driving of high-voltage slow transistors, and lack load adaptive closed-loop and zero-crossing shockless switching, making it difficult to balance low cost, low loss and high precision output. Summary of the Invention

[0005] In view of this, it is necessary to provide a hybrid control type H-bridge inverter circuit and control method to solve the technical problems existing in the prior art, such as the inability to realize direct driving of high voltage slow tubes by GPIO, the lack of load adaptive closed loop and zero-crossing shockless switching, and the difficulty in balancing low cost, low loss and high precision output.

[0006] To address the aforementioned technical problems, in a first aspect, the present invention provides a hybrid control type H-bridge inverter circuit, comprising: a DC bus module, an H-bridge power module, a drive control module, a GPIO level matching unit, and a load current sampling feedback unit; The DC bus module is electrically connected to the H-bridge power module and is used to provide DC power. The H-bridge power module includes four power switching transistors: upper left bridge arm, lower left bridge arm, upper right bridge arm, and lower right bridge arm, which are used to realize DC to AC power conversion; the upper left bridge arm and lower left bridge arm are high-frequency fast transistors, and the upper right bridge arm and lower right bridge arm are power frequency slow transistors. The drive control module includes an EPWM controller and a GPIO controller; the EPWM controller is electrically connected to the upper left bridge arm and the lower left bridge arm, and is used to output complementary high-frequency PWM drive signals with dead time to the high-frequency fast transistor; the GPIO controller is electrically connected to the source, and is used to output low-voltage logic control signals. The GPIO level matching unit is electrically connected to the upper right bridge arm and the lower right bridge arm, and is used to convert the low-voltage logic control signal into a level drive signal and then output the level drive signal to the power frequency slow tube; The load current sampling feedback unit is electrically connected to the EPWM controller and is used to collect the load current and feed it back to the EPWM controller to form a closed-loop control.

[0007] In one possible implementation, the DC bus module includes a first bus capacitor connected in parallel across the DC power supply to filter out DC bus voltage ripple.

[0008] In one possible implementation, the upper left and lower left bridge arms of the high-frequency fast transistor are fast recovery MOSFETs or IGBTs with built-in freewheeling diodes, and the operating frequency is 10-50kHz. The upper right and lower right bridge arms of the power frequency slow tube are MOSFETs, and their operating frequency is consistent with the frequency of the inverter output AC power.

[0009] In one possible implementation, the GPIO level matching unit consists of a current-limiting resistor and a Zener diode connected in series, used to convert the low-voltage signal of the GPIO controller into the level drive signal required by the power frequency slow tube.

[0010] In one possible implementation, the load current sampling feedback unit consists of a precision sampling resistor and a current conditioning chip, connected in series between the midpoint A of the bridge arm and the load. The sampled signal is conditioned and then sent to the EPWM controller.

[0011] In one possible implementation, the hybrid control type H-bridge inverter circuit further includes a frequency adaptive LC filter module; The frequency adaptive LC filter module is connected in series between the H-bridge power module and the midpoint B of the bridge arm, and is used to accurately filter out high-frequency ripples in the inverter output process and optimize the sinusoidality of the output AC waveform. The frequency adaptive LC filter module consists of a magnetic core adjustable inductor and a second capacitor.

[0012] On the other hand, the present invention also provides a hybrid control type H-bridge inverter circuit control method, based on the hybrid control type H-bridge inverter circuit in any of the above implementations, including: The DC bus module is charged by a DC power supply; the upper right bridge arm is turned on and the lower right bridge arm is turned off by a GPIO controller; the dead time is set by an EPWM controller, and the load current sampling feedback unit is started to sample the load current in real time. The upper right bridge arm is kept on and the lower right bridge arm is kept off by the GPIO controller; the upper left bridge arm and the lower left bridge arm are controlled to conduct in a complementary manner by the EPWM controller according to the load current. When the load current is detected to drop to a preset low current threshold, the EPWM controller stops outputting the PWM signal; when the current crosses zero, the GPIO controller completes a shockless switching of the upper right bridge arm off and the lower right bridge arm on; after the switching is completed, the EPWM controller output is restarted. The upper right bridge arm is kept off and the lower right bridge arm is kept on by the GPIO controller; the closed-loop regulation is restored by the EPWM controller, and the upper left bridge arm and the lower left bridge arm are controlled to conduct in a complementary manner, so as to realize the polarity reversal of the output current.

[0013] In one possible implementation, the EPWM controller employs a PID closed-loop control algorithm to adjust the PWM duty cycle in real time based on the load current.

[0014] In one possible implementation, a dead time is set when the upper left bridge arm and the lower left bridge arm are complementaryly conducting. When the lower right bridge arm and the upper right bridge arm switch conduction, the EPWM controller sets the output duty cycle of the fast transistor to 0 to prevent the high-frequency fast transistor and the power frequency slow transistor from conducting at the same time. Furthermore, when an abnormal power frequency slow transistor level is detected, the high frequency fast transistor is synchronously turned off through the EPWM controller.

[0015] In one possible implementation, when the load current exceeds a preset multiple of the inverter output rated current, the duty cycle of the EPWM controller is set to 0, and the upper right bridge arm and the lower right bridge arm are shut down through the GPIO controller to achieve overload protection.

[0016] The beneficial effects of this invention are as follows: The hybrid control type H-bridge inverter circuit provided by this invention firstly provides a stable DC power supply to the circuit through the DC bus module, suppressing bus voltage ripple and absorbing surge current, ensuring reliable circuit startup; secondly, by setting the upper left and lower left bridge arms of the H-bridge power module as high-frequency fast transistors and the upper right and lower right bridge arms as power frequency slow transistors, the power frequency slow transistors switch only at the output AC frequency, thereby significantly reducing switching losses and improving the overall system efficiency; thirdly, the EPWM controller in the drive control module outputs a complementary high-frequency PWM drive signal with dead time to the high-frequency fast transistors, while the GPIO controller, via GP... The IO level matching unit outputs a level drive signal to the power frequency slow tube, which not only realizes the coordinated control of high-frequency precise adjustment of the fast tube and power frequency polarity switching of the slow tube, but also solves the level adaptation problem between the general GPIO low-voltage interface and the high-voltage bus-side power frequency slow tube. It eliminates the need for a dedicated PWM driver chip, significantly reducing hardware costs. Finally, the load current sampling feedback unit collects the load current in real time and feeds it back to the EPWM controller to form a closed-loop control. This enables the circuit to accurately adjust the output according to load changes, overcoming the problems of poor output accuracy and poor load adaptability in open-loop mode. It effectively avoids waveform distortion caused by sudden load changes and improves the output power quality. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of an embodiment of the hybrid control type H-bridge inverter circuit provided by the present invention; Figure 2 A schematic diagram of another embodiment of the hybrid control type H-bridge inverter circuit provided by the present invention; Figure 3 A schematic flowchart of an embodiment of the hybrid control type H-bridge inverter circuit control method provided by the present invention; Figure 4 This is a schematic diagram of an embodiment of the operating timing of the hybrid control type H-bridge inverter circuit provided by the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0020] In the description of the embodiments of the present invention, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0021] The terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a technical feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Before demonstrating the embodiments, the following terms will be explained.

[0024] High-frequency fast transistor: refers to a power switching transistor with an operating frequency of 10–50kHz that undertakes high-frequency PWM modulation tasks; Power frequency slow tube: refers to a power switching tube whose operating frequency is consistent with the power frequency of the inverter output AC power and is only responsible for switching the output polarity; Hierarchical dead zone protection: refers to setting up a two-level differentiated dead zone protection mechanism. The first level is the conventional dead zone for complementary conduction of high-frequency fast tubes, and the other level is the stop wave dead zone during the switching of power frequency slow tubes, which avoids the risk of bridge arm straight-through and simultaneous conduction of fast and slow tubes in a layered manner. Zero-crossing prediction and shock-free switching: This refers to a control strategy that detects the load current in advance when it reaches the near-zero threshold, shuts down the high-frequency PWM output first, and then completes the switching of the power frequency slow tube state after the current has completely crossed zero, in order to eliminate the switching current impact.

[0025] This invention provides a hybrid control type H-bridge inverter circuit and control method, which will be described below.

[0026] Figure 1 This is a schematic diagram of an embodiment of the hybrid control type H-bridge inverter circuit provided by the present invention, as shown below. Figure 1 As shown, the hybrid control type H-bridge inverter circuit includes: DC bus module 100, H-bridge power module 200, drive control module 300, GPIO level matching unit 500, and load current sampling feedback unit 400. The DC bus module 100 is electrically connected to the H-bridge power module 200 to provide DC power. The H-bridge power module 200 includes four power switching transistors: upper left bridge arm, lower left bridge arm, upper right bridge arm, and lower right bridge arm, which are used to realize DC to AC power conversion; the upper left bridge arm and lower left bridge arm are high-frequency fast transistors, and the upper right bridge arm and lower right bridge arm are power frequency slow transistors. The drive control module 300 includes an EPWM controller 301 and a GPIO controller 302; the EPWM controller 301 is electrically connected to the upper left bridge arm and the lower left bridge arm, and is used to output complementary high-frequency PWM drive signals with dead time to the high-frequency fast transistor; the GPIO controller 302 is electrically connected to the GPIO level matching unit 500, and is used to output low-voltage logic control signals. The GPIO level matching unit 500 is electrically connected to the upper right bridge arm and the lower right bridge arm, and is used to convert low-voltage logic control signals into level drive signals and then output level drive signals to the power frequency slow tube. The load current sampling feedback unit 400 is electrically connected to the EPWM controller 301 and is used to collect the load current and feed it back to the EPWM controller 301 to form a closed-loop control.

[0027] In some embodiments of the present invention, the design is for a 500W low-to-medium power AC power supply scenario with a DC input of 310V and an AC output of 220V / 50Hz.

[0028] In some embodiments of the present invention Figure 2 This is a schematic diagram of another embodiment of the hybrid control type H-bridge inverter circuit provided in this invention; wherein, the H-bridge power module 200 includes four power switching transistors: upper left bridge arm Q1, lower left bridge arm Q2, upper right bridge arm Q3, and lower right bridge arm Q4.

[0029] In some embodiments of the present invention, the main control chip of the drive control module 300 is a TMS320F28335, which has a built-in EPWM module as an EPWM controller 301 and a built-in GPIO module as a GPIO controller 302, with a GPIO output level of 3.3V. The output of the EPWM controller is directly connected to the gates of the upper left bridge arm Q1 and the lower left bridge arm Q2 to provide high-frequency PWM drive signals; the output of the GPIO controller is connected to the gates of the upper right bridge arm Q3 and the lower right bridge arm Q4 via the GPIO level matching unit to realize the direct drive of the high-voltage slow tube by the low voltage signal.

[0030] It should be noted that: This embodiment adds a GPIO level matching unit to realize the direct drive of the high-voltage bus slow tube by the 3.3V general GPIO low-voltage interface, without the need to configure a dedicated PWM driver chip and supporting circuit, thus reducing the hardware cost compared with the traditional full-bridge inverter circuit; at the same time, by utilizing the built-in freewheeling diodes of Q1 and Q2, there is no need for external freewheeling diodes, simplifying the circuit topology and improving the hardware integration. The GPIO slow transistor operates at the 50 / 60Hz mains frequency, with almost no high-frequency switching losses. Combined with the load adaptive adjustment of the EPWM fast transistor, the overall system efficiency is much higher than that of the traditional full-bridge inverter circuit.

[0031] The hybrid control type H-bridge inverter circuit provided in this embodiment of the invention first provides a stable DC power supply to the circuit through the DC bus module, suppressing bus voltage ripple and absorbing surge current to ensure reliable circuit startup. Second, the upper left and lower left arms of the H-bridge power module are configured as high-frequency fast transistors, while the upper right and lower right arms are configured as low-frequency slow transistors, ensuring that the low-frequency slow transistors switch only at the output AC frequency, thereby significantly reducing switching losses and improving overall system efficiency. Third, the EPWM controller in the drive control module outputs a complementary high-frequency PWM drive signal with dead time to the high-frequency fast transistors, while the GPIO controller, via GPIO circuitry... The level matching unit outputs a level drive signal to the power frequency slow tube, which not only realizes the coordinated control of high-frequency precise adjustment of the fast tube and power frequency polarity switching of the slow tube, but also solves the level adaptation problem between the general GPIO low-voltage interface and the power frequency slow tube on the high-voltage bus side. It eliminates the need for a dedicated PWM driver chip, significantly reducing hardware costs. Finally, the load current sampling feedback unit collects the load current in real time and feeds it back to the EPWM controller to form a closed-loop control, enabling the circuit to accurately adjust the output according to load changes. This overcomes the problems of poor output accuracy and poor load adaptability in open-loop mode, effectively avoids waveform distortion caused by sudden load changes, and improves the output power quality.

[0032] In some embodiments of the present invention, the DC bus module includes a first bus capacitor connected in parallel across the DC power supply to filter out DC bus voltage ripple.

[0033] like Figure 2 As shown, the DC bus module 100 includes a first bus capacitor C1, which is connected in parallel between the positive terminal P+ and the negative terminal N- of the DC power supply, and is also electrically connected to the input terminal of the H-bridge power module 200 to provide DC power supply to the H-bridge power module.

[0034] In this embodiment, the first bus capacitor C1 can be an aluminum electrolytic capacitor or a film capacitor, and the capacitance value is configured according to the system power level and the bus voltage level. In some embodiments of the present invention, the DC input voltage is DC310V, and the first bus capacitor C1 is selected as a 470μF / 450V high-frequency electrolytic capacitor. Through its own charging and discharging characteristics, the capacitor can filter out high-frequency ripple from the DC power supply output, providing a low-ripple, stable DC bus voltage for the H-bridge power module. On the other hand, it can provide instantaneous energy support during load changes, suppressing voltage drops or spikes on the bus and improving the dynamic stability of the system.

[0035] In some embodiments of the present invention, the upper left bridge arm Q1 and the lower left bridge arm Q2 of the high-frequency fast transistor are fast recovery MOSFETs or IGBTs with built-in freewheeling diodes, and the operating frequency is 10-50kHz. The upper right and lower right bridge arms of the power frequency slow tube are MOSFETs, and their operating frequency is the same as the frequency of the inverter output AC power.

[0036] like Figure 2 As shown, the upper left bridge arm Q1 and the lower left bridge arm Q2 are high-frequency fast transistors, the upper right bridge arm Q3 and the lower right bridge arm Q4 are power frequency slow transistors, and D1-D4 are freewheeling diodes built into the switching transistors. The operating frequencies of the upper right bridge arm Q3 and the lower right bridge arm Q4 of the power frequency slow tube are consistent with the frequency of the inverter output AC power, preferably 50Hz or 60Hz.

[0037] In some embodiments of the present invention, Q1 and Q2 can be any fast recovery MOSFET or IGBT (hereinafter referred to as EPWM fast transistor) with built-in freewheeling diode, and Q3 and Q4 can be adapted to various low voltage MOSFETs (hereinafter referred to as GPIO slow transistor). There are no mandatory restrictions on device selection, and the adaptability is strong. Preferably, the upper left bridge arm Q1 and the lower left bridge arm Q2 are IRF840 fast recovery MOSFETs (600V / 8A, with built-in freewheeling diode), operating at a frequency of 20kHz; the upper right bridge arm Q3 and the lower right bridge arm Q4 are 2N7002 low-voltage MOSFETs (60V / 0.2A), operating at a frequency of 50Hz; the load RL is a 220V / 500W resistive / inductive general purpose load; In this embodiment, the high-frequency fast transistor is selected as a fast recovery MOSFET or IGBT with built-in freewheeling diode. This type of device is a commonly used high-frequency power switching device in the art. Its integrated fast recovery freewheeling diode does not require additional external freewheeling circuit, which can reduce the reverse recovery loss during high-frequency operation and is suitable for operating frequencies of 10–50kHz. The MOSFETs selected for the power frequency slow tube are general-purpose low-voltage power devices that can be directly driven by the GPIO level matching unit without the need for a dedicated driver chip, making them suitable for low-loss operating scenarios involving power frequency switching.

[0038] The H-bridge power module adopts a hybrid architecture of "high-frequency fast diode + power frequency slow diode". The fast diode is responsible for high-frequency modulation, and the slow diode is responsible for power frequency polarity switching, which greatly reduces the switching loss of the slow diode and improves the overall system efficiency. The high-frequency fast diode uses a fast recovery device with built-in freewheeling diode, which eliminates the need for additional external freewheeling circuit, simplifies the circuit structure and reduces reverse recovery loss. The power frequency slow diode can be directly driven by GPIO without the need for a dedicated driver chip, which reduces hardware costs.

[0039] In some embodiments of the present invention, the GPIO level matching unit is composed of a current-limiting resistor R and a Zener diode D connected in series, used to convert the low-voltage signal of the GPIO controller into the level drive signal required by the power frequency slow tube.

[0040] In some embodiments of the present invention, the current limiting resistor R is selected as a 1kΩ / 2W chip resistor, and the Zener diode D is selected as a 12V / 1W Zener diode. The two are connected in series between the GPIO controller 302 and the gates of the upper right bridge arm Q3 and the lower right bridge arm Q4 to realize the level adaptation and drive protection of the 3.3V GPIO signal. A simple level conversion circuit is formed by connecting the current-limiting resistor R and the Zener diode D in series. This circuit can limit the current and clamp the voltage of the low-voltage control signal output by the GPIO controller 302, and adapt the conventional low-voltage GPIO signal to a drive level that can be recognized by the high-voltage bus-side power frequency slow tube. Signal level matching can be achieved without adding a dedicated driver chip. The circuit structure is simple and adapts to the direct drive control requirements of the power frequency slow tube of this invention.

[0041] In some embodiments of the present invention, the load current sampling feedback unit 400 is composed of a precision sampling resistor Rs and a current conditioning chip, connected in series between the midpoint A of the bridge arm and the load, and the sampling signal is conditioned and sent to the EPWM controller.

[0042] In some embodiments of the present invention, the precision sampling resistor Rs is a 0.1Ω / 5W alloy resistor, the current conditioning chip is an INA219, connected in series between the midpoint A of the left bridge arm and the load RL, with a sampling accuracy of ±0.01A, and the conditioned current signal is fed back to the EPWM controller, with PID closed-loop adjustment parameters of proportional coefficient 0.3, integral time 0.2ms, and derivative time 0.05ms. It should be noted that the precision sampling resistor Rs is connected in series in the current loop, and converts the load current into a weak voltage signal through Ohm's law. Then, the current conditioning chip amplifies, filters and performs level adaptation processing on this weak voltage signal to eliminate interference signals and output a stable and accurate feedback signal to the EPWM controller, providing reliable data support for the closed-loop regulation of the EPWM controller and ensuring regulation accuracy.

[0043] This embodiment enables accurate real-time acquisition of load current, providing a stable and reliable feedback signal for the EPWM controller and effectively establishing a load-adaptive closed-loop control system. The feedback signal processed by the current conditioning chip has strong anti-interference capability and high sampling accuracy, which facilitates the EPWM controller to dynamically adjust the PWM duty cycle according to changes in load current, significantly improving the output accuracy and load adaptability of the inverter circuit. At the same time, the overall sampling circuit structure is simplified and the hardware cost is controllable. It can also provide sampling data support for abnormal protection functions such as overload and undercurrent protection, further improving the overall operational reliability of the inverter circuit.

[0044] In some embodiments of the present invention, the hybrid control type H-bridge inverter circuit further includes a frequency adaptive LC filter module; The frequency adaptive LC filter module is connected in series between the H-bridge power module and the midpoint B of the bridge arm. It is used to accurately filter out high-frequency ripples in the inverter output process and optimize the sinusoidality of the output AC waveform. The frequency adaptive LC filter module consists of a magnetic core adjustable inductor and a second capacitor.

[0045] In some embodiments of the present invention, the core adjustable inductor L1 is selected as a 0.5-1mH core adjustable power inductor, and the second capacitor C2 is selected as a 0.1μF high-frequency ceramic capacitor to form a frequency adaptive LC filter circuit. When matching the 20kHz EPWM frequency, the core adjustable inductor L1 is adjusted to 1mH to achieve complete filtering of the 20kHz high-frequency ripple.

[0046] This embodiment combines the load current sampling feedback unit with the frequency adaptive LC filter module, resulting in a total harmonic distortion (THD) rate of less than 2% for the inverter output current, which is 1 percentage point higher than the existing solution. The zero-crossing prediction and shockless switching strategy reduces current surges by more than 85%, effectively avoiding output waveform distortion and significantly improving power quality. The closed-loop control strategy based on real-time load current feedback can adapt to various load types such as resistive and inductive, and can still maintain accurate output under load change conditions.

[0047] To better implement the hybrid control type H-bridge inverter circuit control circuit in the embodiments of the present invention, based on the hybrid control type H-bridge inverter circuit control circuit, correspondingly, as follows: Figure 3As shown, this embodiment of the invention also provides a hybrid control type H-bridge inverter circuit control method, including: S301: Charges the DC bus module with DC power supply; controls the upper right bridge arm to turn on and the lower right bridge arm to turn off with GPIO controller; sets the dead time with EPWM controller and starts the load current sampling feedback unit to sample the load current in real time. S302: The upper right bridge arm is kept on and the lower right bridge arm is turned off by the GPIO controller; the upper left bridge arm and the lower left bridge arm are controlled to conduct in a complementary manner by the EPWM controller according to the load current. S303. When the load current is detected to drop to a preset low current threshold, the EPWM controller stops outputting the PWM signal. When the current crosses zero, the GPIO controller completes a shockless switching of the upper right bridge arm off and the lower right bridge arm on. After the switching is completed, the EPWM controller output is restarted. S304: The upper right bridge arm is kept off and the lower right bridge arm is turned on through the GPIO controller; the closed-loop regulation is restored through the EPWM controller to control the upper left bridge arm and the lower left bridge arm to conduct in a complementary manner, thereby achieving polarity reversal of the output current.

[0048] It should be noted that the steps in this embodiment can be divided into the following working modes: initialization and sampling preparation mode, output positive half-cycle high-frequency modulation mode, zero-crossing prediction and shockless switching mode, and output negative half-cycle high-frequency modulation mode. During the initialization, the filter module matches the EPWM initial drive frequency to complete the parameter configuration.

[0049] This embodiment constructs a load-adaptive closed-loop control mechanism by combining real-time load current sampling with closed-loop adjustment of the EPWM controller. This mechanism can dynamically match the high-frequency PWM output according to the load conditions, effectively improving the output accuracy and load adaptability of the inverter circuit. By presetting the dead time and using a timing control method that shuts down the high-frequency signal before switching the power frequency slow transistor at the zero-crossing point, the current surge at the zero-crossing point of the inverter output is completely eliminated, while avoiding the safety hazard of bridge arm shoot-through. Relying on the time-division collaborative control logic of the high-frequency fast transistor and the power frequency slow transistor, the advantage of low switching loss of the hybrid architecture is continued. While simplifying the control logic and eliminating the need for additional complex drive circuits, it also takes into account the comprehensive performance of low cost, low loss and high-precision stable output.

[0050] In some embodiments of the present invention, the EPWM controller employs a PID closed-loop regulation algorithm to adjust the PWM duty cycle in real time according to the load current.

[0051] It should be noted that the PID closed-loop control algorithm is a mature and widely used control algorithm in the field of industrial control. It integrates three control logics: proportional, integral, and derivative. It has the inherent characteristics of fast dynamic response, high static control accuracy, and strong resistance to operating condition interference. It can sense and continuously correct the deviation of the controlled parameter in real time.

[0052] This embodiment combines a PID closed-loop control algorithm with a load current sampling feedback unit. Using real-time collected load current as the basis for control, it dynamically corrects the PWM duty cycle in conjunction with the EPWM controller. It abandons the fixed parameter output mode, allowing the modulation strategy to automatically adapt to load conditions. This precisely matches the operating characteristics of the hybrid control type H-bridge inverter circuit with its fast and slow transistors working in tandem. A simple and mature algorithm architecture enables intelligent closed-loop control design. Simultaneously, it effectively compensates for output deviations caused by load fluctuations, suppresses dynamic fluctuations in inverter voltage and current, significantly improves the quality of the inverter output waveform and voltage regulation accuracy, and perfects the load adaptive closed-loop control mechanism. This ensures the circuit maintains a stable operating state under different light and heavy load conditions, effectively enhancing circuit stability and load adaptability.

[0053] In some embodiments of the present invention, a dead time is set when the upper left bridge arm and the lower left bridge arm are complementaryly connected. When the lower right bridge arm and the upper right bridge arm switch conduction, the EPWM controller sets the output duty cycle of the fast transistor to 0 to prevent the high-frequency fast transistor and the power frequency slow transistor from conducting at the same time. Furthermore, when an abnormal power frequency slow transistor level is detected, the high frequency fast transistor is synchronously turned off through the EPWM controller.

[0054] It should be noted that: In this embodiment, a dead time is set for the complementary conduction of the upper left and lower left bridge arms on the same side of the H-bridge topology, which is a standard operation in the field of inverter circuits to avoid bridge arm shoot-through; the linkage shutdown protection when the power switching device is abnormal is also a common design in power electronic control circuits. Based on the above conventional design, this application makes a special design: during the switching of the conduction state between the upper right and lower right bridge arms, the duty cycle of the high-frequency fast transistor is set to zero by the EPWM controller to achieve timing interlock between the high-frequency fast transistor and the power frequency slow transistor; at the same time, a special logic is added to synchronously shut down the high-frequency fast transistor when an abnormal power frequency slow transistor level is detected, adapting to the special architecture of the hybrid control of fast and slow transistors in this invention.

[0055] This embodiment upgrades the hierarchical dead-zone protection and adds abnormal level detection, overload protection, and synchronous shutdown logic to fundamentally avoid bridge arm shoot-through faults; zero-crossing prediction and shockless switching eliminate current surges during the switching process; overload protection enables active protection of the circuit; the circuit can operate stably under light load, heavy load, and sudden load changes, and the failure rate is reduced by more than 90% compared to existing solutions.

[0056] This embodiment effectively avoids short-circuit faults caused by the simultaneous conduction of power switches on the same side of the bridge arm by setting a conduction dead time for the upper left and lower left bridge arms. During the switching process between the upper right and lower right bridge arms, the output state of the high-frequency fast transistor is locked by the EPWM controller, which can prevent the abnormal condition of simultaneous conduction of the high-frequency fast transistor and the power frequency slow transistor, and avoid the risk of circuit circulating current and device damage. When the power frequency slow transistor has an abnormal level, the high-frequency fast transistor is turned off synchronously to realize the linkage interlocking protection under fault conditions, which greatly improves the operational safety and reliability of the hybrid control type H-bridge inverter circuit and is suitable for the use requirements of long-term stable operation under complex operating conditions.

[0057] In some embodiments of the present invention, when the load current exceeds a preset multiple of the inverter output rated current, the duty cycle of the EPWM controller is set to 0, and the upper right bridge arm and the lower right bridge arm are turned off through the GPIO controller to achieve overload protection.

[0058] In some embodiments of the present invention, based on the polarity of the AC output grid voltage and the real-time load current feedback signal, the present invention adopts a load-adaptive PID closed-loop control strategy with periodic coordination and zero-crossing prediction to drive the EPWM fast transistor and the GPIO slow transistor differently. Simultaneously, a graded dead-time protection and abnormal shutdown mechanism are designed to fundamentally avoid bridge arm shoot-through and zero-crossing current surges. The specific control logic and operating mode are as follows: (1) Startup initialization phase The DC power supply charges the bus capacitor C1 to its rated DC voltage; the GPIO controller outputs a high level to turn on the upper right bridge arm Q3 and a low level to turn off the lower right bridge arm Q4 via the level matching unit; the EPWM controller completes initialization, sets the dead time for the switching of the upper left bridge arm Q1 / lower left bridge arm Q2 to 50-200ns, and starts the load current sampling feedback unit to collect current in real time; the filter module matches the initial drive frequency of the EPWM to complete parameter configuration and enters the standby state.

[0059] (2) Positive half-cycle working mode The GPIO controller maintains a high level to turn on the upper right bridge arm Q3 and a low level to turn off the lower right bridge arm Q4. The EPWM controller receives the real-time current signal from the load current sampling feedback unit and outputs a high-frequency PWM signal through a PID closed-loop regulation algorithm. This drives the upper left bridge arm Q1 and the lower left bridge arm Q2 to achieve complementary conduction with a dead time of 50-200ns. By adjusting the duty cycle (0-100%) of the PWM signal in real time, the output current amplitude is precisely controlled to match the dynamic current requirements of the load. The filtering module synchronously tracks the EPWM frequency and adjusts the filtering parameters in real time to filter out high-frequency ripple.

[0060] (3) Zero-crossing prediction and shock-free switching phase The load current sampling feedback unit detects the output current in real time. When the detected current drops to 5% of the rated current, it triggers a zero-crossing prediction command. The EPWM controller immediately reduces the duty cycle of the upper left bridge arm Q1 and the lower left bridge arm Q2 to the no-load threshold (5%), reducing the zero-crossing current base. When the current truly crosses zero, the GPIO controller quickly completes the level switching of the upper right bridge arm Q3 being turned off and the lower right bridge arm Q4 being turned on. The EPWM controller maintains the no-load duty cycle until the switching is completed, with no current surge throughout the process, avoiding output waveform distortion.

[0061] (4) Negative half-week working mode The GPIO controller maintains a high level to turn on the lower right bridge arm Q4 and a low level to turn off the upper right bridge arm Q3; the EPWM controller resumes PID closed-loop regulation and continues to drive the upper left bridge arm Q1 and the lower left bridge arm Q2 to achieve complementary conduction with a set dead zone. The polarity of the output current is reversed by adjusting the reverse duty cycle to complete the generation of the negative half-cycle of the AC output waveform; the filter module adjusts its parameters synchronously to maintain the high-frequency ripple filtering effect.

[0062] (5) Hierarchical dead zone protection and abnormal shutdown mechanism To completely avoid power device burnout caused by bridge arm shoot-through, a two-stage dead-time protection system is designed, and abnormal signal detection and shutdown logic are added: 1) EPWM fast transistor basic dead time: During the switching process of the upper left bridge arm Q1 and the lower left bridge arm Q2 complementary conduction, a dead time of 50-200ns is set to ensure that the other switch is driven to conduct after the previous switch is completely turned off, so as to avoid the common conduction of the left bridge arm. 2) GPIO slow transistor switching coordination dead zone: During the entire polarity switching process of the upper right bridge arm Q3 and the lower right bridge arm Q4, the EPWM controller locks the upper left bridge arm Q1 and the lower left bridge arm Q2 to the no-load duty cycle state. If an abnormal signal is detected in the upper right bridge arm Q3 / lower right bridge arm Q4, the upper left bridge arm Q1 and the lower left bridge arm Q2 are immediately and synchronously turned off. After the slow transistor switching is completed and the signal is stable, the normal drive of the fast transistor is restored to avoid shoot-through between bridge arms. 3) Overload abnormal shutdown: When the load current sampling feedback unit detects that the current exceeds 1.2 times the rated value, the EPWM controller immediately reduces the duty cycle to 0, and the GPIO controller shuts down the upper right bridge arm Q3 / lower right bridge arm Q4 to realize circuit overload protection.

[0063] It should be noted that in this embodiment, the load current is collected and the overload judgment threshold is set based on the inverter output rated current. After the current exceeds the limit, the PWM modulation output is shut down to achieve overload protection, which is a conventional protection operation in the field of power electronic control of inverter circuits. Based on this conventional protection logic, this application makes a special design: when overload is triggered, not only is the output duty cycle of the EPWM controller set to zero, but the upper right bridge arm and the lower right bridge arm are also shut down simultaneously through the GPIO controller to achieve synchronous blocking protection of high-frequency fast transistors and power frequency slow transistors, which is compatible with the hybrid control H-bridge circuit architecture of the present invention that combines high-frequency fast transistors with power frequency slow transistors.

[0064] This embodiment uses the inverter output rated current as a reference to set the overload judgment condition, which can accurately identify abnormal overcurrent conditions. After overload is triggered, the PWM modulation output is simultaneously shut down and the two power frequency slow transistors are locked, which can quickly cut off the energy transmission path of the circuit and avoid the overload current from continuously impacting the power switching transistors and downstream load devices, effectively preventing faults such as device overheating and breakdown. Relying on the protection method of synchronous locking of fast and slow transistors, it fits the working characteristics of the hybrid control circuit of this invention, improves the response speed and protection comprehensiveness of overload protection, and further enhances the safety and fault tolerance of the overall circuit operation.

[0065] In some embodiments of the present invention Figure 4 This is a schematic diagram of an embodiment of the operating timing of the hybrid control type H-bridge inverter circuit provided by the present invention. It includes the level drive signals (including the prediction switching timing) of the GPIO controller for the upper right bridge arm Q3 / lower right bridge arm Q4, the PWM pulse signals (including the PID adjustment duty cycle waveform) of the EPWM controller for the upper left bridge arm Q1 / lower left bridge arm Q2, the output current waveform (without zero-crossing impact), and the graded dead time window, clearly showing the correspondence between the on and off timing of each switch and the output current.

[0066] like Figure 4As shown, the GPIO controller 302 drives the upper right bridge arm Q3 / lower right bridge arm Q4 of the power frequency slow transistor with a 50Hz square wave, which is consistent with the frequency of the power frequency AC power output from the inverter. The high and low levels of the waveform correspond to the switching of the conduction state of the two sets of power frequency slow transistors (e.g., high level corresponds to the upper right bridge arm Q3 being on and the lower right bridge arm Q4 being off, and low level corresponds to the lower right bridge arm Q4 being on and the upper right bridge arm Q3 being off). The period is completely synchronized with the power frequency period of the output current, which intuitively reflects the control logic of the slow transistor's "power frequency polarity switching". Moreover, the waveform contains a predicted switching sequence, which reserves a safety window for the subsequent stop and restart of the high-frequency fast transistor. The EPWM controller drives the upper left bridge arm Q1 and lower left bridge arm Q2 of the high-frequency fast transistor with a 20kHz high-frequency PWM pulse sequence, which falls within the 10-50kHz operating frequency range of the fast transistor. The pulse duty cycle changes dynamically over time, demonstrating the role of the PID closed-loop control algorithm—adjusting the PWM duty cycle based on real-time feedback of the load current to modulate a voltage envelope that matches the output current waveform. Especially before and after GPIO level switching, the EPWM signal exhibits a sustained low level (duty cycle of 0, labeled "-0kHz"), indicating that the high-frequency fast transistor stops outputting PWM pulses. This is the key timing sequence for zero-crossing prediction switching: when the load current approaches the zero-crossing point (preset small current threshold), the fast transistor output is shut down, providing a safe interval for the state switching of the mains frequency slow transistor and preventing bridge arm shoot-through or current surges during the switching process. Output current i out The waveform is a smooth, undistorted sine wave, synchronized with the 50Hz drive signal period of the power frequency slow transistor, and without spikes or surges at the zero-crossing point. This directly verifies the control effect of the present invention—the high-frequency modulation of the fast transistor ensures the accuracy of the current waveform, while the stop-wave before the zero-crossing point and the smooth switching of the slow transistor eliminate the current distortion and surges at the zero-crossing point in traditional inverter circuits. In addition, the timing diagram includes a two-stage dead-time design: one is the conventional dead-time when the high-frequency fast transistors Q1 / Q2 are complementaryly turned on (implied in the high-low level switching of the EPWM pulse to prevent same-side bridge arm shoot-through), and the other is the "stop-wave dead-time" during the zero-crossing switching (i.e., the stage when the EPWM signal is continuously low, providing a safe interval for the switching of the power frequency slow transistor and preventing the fast and slow transistors from conducting simultaneously), forming a hierarchical safety protection mechanism that is compatible with the architecture of the fast and slow transistor hybrid control of the present invention.

[0067] The hybrid control H-bridge inverter circuit of this application forms an inverter architecture that combines high efficiency, high reliability, and low cost through the coordinated operation of the DC bus module, H-bridge power module, drive control module, and load current sampling feedback unit. It adopts a hybrid bridge arm structure of high-frequency fast transistors and power-frequency slow transistors, ensuring output waveform accuracy through high-frequency modulation of the fast transistors and significantly reducing switching losses through power-frequency switching of the slow transistors. Relying on load current sampling feedback and PID closed-loop regulation of the EPWM controller, it achieves load adaptive control, improving output stability and load adaptability. Through direct driving of the power-frequency slow transistors and zero-crossing prediction timing control by the GPIO controller, it eliminates zero-crossing current surges and avoids bridge arm shoot-through risks. At the same time, it simplifies the drive circuit design, eliminating the need for dedicated drive chips for the power-frequency slow transistors, effectively reducing hardware costs, and comprehensively meeting the performance, efficiency, reliability, and economic requirements of the inverter circuit.

[0068] The hybrid control type H-bridge inverter circuit and control method provided by the present invention have been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A hybrid control type H-bridge inverter circuit, characterized in that, include: DC bus module, H-bridge power module, drive control module, GPIO level matching unit, load current sampling feedback unit; The DC bus module is electrically connected to the H-bridge power module and is used to provide DC power. The H-bridge power module includes four power switching transistors: upper left bridge arm, lower left bridge arm, upper right bridge arm, and lower right bridge arm, which are used to realize DC to AC power conversion; the upper left bridge arm and lower left bridge arm are high-frequency fast transistors, and the upper right bridge arm and lower right bridge arm are power frequency slow transistors. The drive control module includes an EPWM controller and a GPIO controller; the EPWM controller is electrically connected to the upper left bridge arm and the lower left bridge arm, and is used to output complementary high-frequency PWM drive signals with dead time to the high-frequency fast transistor; the GPIO controller is electrically connected to the GPIO level matching unit, and is used to output low-voltage logic control signals. The GPIO level matching unit is electrically connected to the upper right bridge arm and the lower right bridge arm, and is used to convert the low-voltage logic control signal into a level drive signal and then output the level drive signal to the power frequency slow tube; The load current sampling feedback unit is electrically connected to the EPWM controller and is used to collect the load current and feed it back to the EPWM controller to form a closed-loop control.

2. The hybrid control type H-bridge inverter circuit according to claim 1, characterized in that, The DC bus module includes a first bus capacitor connected in parallel across the DC power supply to filter out DC bus voltage ripple.

3. The hybrid control type H-bridge inverter circuit according to claim 1, characterized in that, The upper left and lower left bridge arms of the high-frequency fast transistor are fast recovery MOSFETs or IGBTs with built-in freewheeling diodes, and the operating frequency is 10-50kHz. The upper right and lower right bridge arms of the power frequency slow tube are MOSFETs, and their operating frequency is consistent with the frequency of the inverter output AC power.

4. The hybrid control type H-bridge inverter circuit according to claim 1, characterized in that, The GPIO level matching unit consists of a current-limiting resistor and a Zener diode connected in series, and is used to convert the low-voltage signal of the GPIO controller into the level drive signal required by the power frequency slow tube.

5. The hybrid control type H-bridge inverter circuit according to claim 1, characterized in that, The load current sampling feedback unit consists of a precision sampling resistor and a current conditioning chip, which are connected in series between the midpoint A of the bridge arm and the load. The sampled signal is conditioned and then sent to the EPWM controller.

6. The hybrid control type H-bridge inverter circuit according to claim 1, characterized in that, The hybrid control type H-bridge inverter circuit also includes a frequency adaptive LC filter module; The frequency adaptive LC filter module is connected in series between the H-bridge power module and the midpoint B of the bridge arm, and is used to accurately filter out high-frequency ripples in the inverter output process and optimize the sinusoidality of the output AC waveform. The frequency adaptive LC filter module consists of a magnetic core adjustable inductor and a second capacitor.

7. A control method for a hybrid control type H-bridge inverter circuit, based on the hybrid control type H-bridge inverter circuit according to any one of claims 1 to 6, characterized in that, include: The DC bus module is charged by a DC power supply; the upper right bridge arm is turned on and the lower right bridge arm is turned off by a GPIO controller; the dead time is set by an EPWM controller, and the load current sampling feedback unit is started to sample the load current in real time. The upper right bridge arm is kept on and the lower right bridge arm is kept off by the GPIO controller; the upper left bridge arm and the lower left bridge arm are controlled to conduct in a complementary manner by the EPWM controller according to the load current. When the load current is detected to drop to a preset low current threshold, the EPWM controller stops outputting the PWM signal; when the current crosses zero, the GPIO controller completes a shockless switching of the upper right bridge arm off and the lower right bridge arm on; after the switching is completed, the EPWM controller output is restarted. The upper right bridge arm is kept off and the lower right bridge arm is kept on by the GPIO controller; the closed-loop regulation is restored by the EPWM controller to control the upper left bridge arm and the lower left bridge arm to conduct in a complementary manner, thereby achieving the reversal of the output current polarity.

8. The hybrid control type H-bridge inverter circuit control method according to claim 7, characterized in that, The EPWM controller uses a PID closed-loop control algorithm to adjust the PWM duty cycle in real time according to the load current.

9. The hybrid control type H-bridge inverter circuit control method according to claim 7, characterized in that, When the upper left bridge arm and the lower left bridge arm are complementary and conducting, a dead time is set. When the lower right bridge arm and the upper right bridge arm switch conduction, the EPWM controller sets the output duty cycle of the fast transistor to 0 to prevent the high-frequency fast transistor and the power frequency slow transistor from conducting at the same time. Furthermore, when an abnormal power frequency slow transistor level is detected, the high frequency fast transistor is synchronously turned off through the EPWM controller.

10. The hybrid control type H-bridge inverter circuit control method according to claim 7, characterized in that, When the load current exceeds a preset multiple of the inverter output rated current, the duty cycle of the EPWM controller is set to 0, and the upper right bridge arm and the lower right bridge arm are turned off through the GPIO controller to achieve overload protection.

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