A meteorological stationary satellite DCP transmitting baseband chip and a control method thereof

Abstract

The application discloses a kind of weather stationary satellite DCP sending baseband chip and its control method, its chip includes data receiving module, coding processing module, baseband modulation module, GNSS time service frequency calibration module, monitoring management module, DCP special unique code chip interface, built-in RTC module, power amplifier monitoring module, power management module, reset control module, IO extension control module and mixer control interface.The application adopts single-chip highly integrated architecture, integrates data transceiving, four-stage cascade coding, baseband modulation, double-redundancy time-frequency calibration, equipment identity recognition, power amplifier open-loop monitoring protection and intelligent power consumption management and other functions, solves the defects of traditional DCP terminal, such as low integration, large power consumption, weak channel anti-interference, poor clock stability, lack of power amplifier protection and non-uniform interface, effectively improves the equipment time slot transmission accuracy, data transmission reliability and operation safety, reduces the difficulty of integrated operation and maintenance.

Description

Technical Field

[0001] This invention relates to the field of satellite communication technology, and in particular to a DCP transmitting baseband chip for a meteorological geostationary satellite and its control method. Background Technology

[0002] Geostationary satellite data collection systems (DCS) are crucial infrastructure for meteorological, hydrological, oceanographic, and environmental monitoring. They are used to relay data from dispersed ground collection stations to ground data centers via geostationary satellites. DCP terminals, as ground-based acquisition and transmission equipment, require miniaturization, low power consumption, high reliability, and long-term unattended operation. Existing DCP terminals are generally built using discrete components, consisting of multiple chips such as MCU, FPGA, RF front-end, clock circuit, and power management, which presents the following technical shortcomings:

[0003] (1) Low integration and high size and power consumption: The existing DCP terminal adopts a discrete device solution, which has a large circuit board area and high power consumption, which is not conducive to long-term deployment in unattended outdoor environments.

[0004] (2) Single channel coding scheme: Existing DCP terminals usually only use simple convolutional coding or transmit directly without coding, which has limited anti-interference ability and a high data loss rate under poor channel conditions;

[0005] (3) Insufficient frequency stability: DCP terminals usually use ordinary crystal oscillators, which have limited frequency stability. After long-term operation, the frequency offset accumulates, affecting the correct demodulation of the receiver, and does not support high-precision time synchronization.

[0006] (4) Lack of power amplifier status monitoring: The existing DCP terminal lacks real-time monitoring of the power and temperature of the RF power amplifier, which makes it impossible to detect power amplifier abnormalities in time and poses a risk of transmission failure.

[0007] (5) Non-standard external interfaces: The control interfaces and status indication methods of DCP terminals from different manufacturers are different, which is not conducive to system integration and unified management;

[0008] Based on the above, this application proposes a DCP transmitting baseband chip for meteorological geostationary satellites and its control method. Summary of the Invention

[0009] Based on the technical problems existing in the background technology, this invention proposes a meteorological geostationary satellite DCP transmission baseband chip and its control method.

[0010] This invention proposes a DCP (Digital Catalytic Converter) baseband chip for meteorological geostationary satellites, comprising a data receiving module, an encoding and processing module, a baseband modulation module, a GNSS timing and frequency calibration module, a monitoring and management module, a DCP-specific unique code chip interface, a built-in RTC module, a power amplifier monitoring module, a power management module, a reset control module, an I / O expansion control module, and a mixer control interface, all integrated within the same chip. The power management module is electrically connected to all modules within the chip, providing appropriate operating voltages for each module. The reset control module is connected to all modules within the chip, enabling unified reset across the entire chip. The monitoring and management module is integrated with the data receiving module, encoding and processing module, and baseband modulation module... The module, GNSS timing and frequency calibration module, power amplifier monitoring module, and IO expansion control module are electrically connected. The monitoring and management module is used to collect the operating status of each module and issue configuration parameters. The DCP dedicated unique code chip interface is connected to the encoding processing module for transmitting the read device unique identification code to the encoding processing module to embed data frames. The IO expansion control module is electrically connected to the power amplifier monitoring module and the mixer control interface respectively for receiving power amplifier abnormal signals and linking the output of front-end device control signals. The data receiving module is electrically connected to the encoding processing module, the baseband modulation module is connected to the encoding processing module, and the built-in RTC module is connected to the GNSS timing and frequency calibration module.

[0011] The data receiving module is equipped with a serial port and an Ethernet port for receiving data to be sent;

[0012] The encoding processing module is used to sequentially perform BCH encoding, scrambling, RS encoding, and convolutional encoding on the data to be transmitted to form encoded data.

[0013] The baseband modulation module is used to perform QPSK modulation and shaping filtering on the encoded data to generate a baseband IQ signal;

[0014] The GNSS timing and frequency calibration module is equipped with a GNSS chip interface for receiving GNSS second pulse signals, disciplining and calibrating the local clock through a digital phase-locked loop, and outputting a high-precision clock signal to the encoding processing module and the baseband modulation module.

[0015] The monitoring and management module includes a monitoring port and a configuration interface, which are used to monitor the chip's working status and configure its working parameters.

[0016] The DCP dedicated unique code chip interface is used to connect to the DCP dedicated unique code chip and read the device's unique identification code;

[0017] The built-in RTC module is used to provide a timekeeping function when GNSS signals are lost;

[0018] The power amplifier monitoring module includes an RF power acquisition interface and a temperature acquisition interface, which are used to acquire the power amplifier's transmit power and temperature, respectively.

[0019] The power management module has multiple built-in voltage regulators and supports switching between working mode and sleep mode.

[0020] The reset control module is equipped with a reset pin for receiving external reset signals and performing chip reset.

[0021] The IO expansion control module is equipped with multiple general-purpose IO interfaces for controlling the output of external LED indicators and the operating status control of the RF power amplifier. The LED indicators include operating status indicator, data reception indicator, second pulse indicator, transmission status indicator and mixer carrier frequency lock indicator.

[0022] The mixer control interface is used to output control signals to control the reset and startup of the mixer chip.

[0023] Preferably, the GNSS timing and frequency calibration module supports one or more of the following satellite navigation systems: GPS, GLONASS, Galileo, and BeiDou.

[0024] The built-in RTC module uses a low-power real-time clock circuit. When the GNSS signal is lost, it keeps time based on the frequency calibration information before the GNSS signal is lost and outputs a replacement second pulse signal.

[0025] The logic for the coordinated operation of the GNSS timing and frequency calibration module and the built-in RTC module is as follows:

[0026] (1) The external GNSS receiver chip outputs a 1PPS pulse per second and an NMEA message, which are sent to the TDC through the GNSS chip interface;

[0027] (2) The TDC simultaneously acquires the clock signals of GNSS1PPS and the local crystal oscillator, measures the time difference between the two, and sends it to the DPLL;

[0028] (3) The DPLL generates the frequency control word, high-precision clock, timekeeping 1PPS and frequency calibration parameters based on the time difference;

[0029] (4) The frequency control word is converted into a voltage-controlled voltage by a DAC, which controls the local crystal oscillator to adjust the frequency, forming a closed-loop discipline;

[0030] (5) The high-precision clock output by DPLL is sent to the encoding and modulation module, and the timekeeping 1PPS and frequency calibration parameters are sent to the RTC module.

[0031] (6) When GNSS is normal, the built-in RTC module synchronously calibrates its own clock according to the timekeeping 1PPS and frequency calibration parameters. When GNSS is lost, the built-in RTC module outputs a backup time / 1PPS second pulse to provide a timekeeping base for the system.

[0032] Preferably, the BCH encoding, scrambling, RS encoding and convolutional encoding in the encoding processing module are performed according to the CCSDS standard, wherein the RS encoding adopts RS(255,223) code;

[0033] The power management module includes at least one low-dropout linear regulator for generating different voltages required by various modules within the chip. The power management module includes a sleep control unit and a wake-up control unit. The sleep control unit shuts down the power supply to a specified module in response to an external sleep command or an internal timing signal. The wake-up control unit restores the power supply to a specified module in response to an external wake-up command or an internal timing signal.

[0034] Preferably, the general-purpose I / O interface of the I / O expansion control module includes at least: an RF power amplifier start control interface, an RF power amplifier stop control interface, a mixer chip reset interface, a mixer chip start interface, a working status indicator interface, a data receiving indicator interface, a second pulse indicator interface, a transmit status indicator interface, and a mixer carrier frequency lock indicator interface.

[0035] Preferably, the power amplifier monitoring module is used to convert the collected analog signals of transmission power and temperature into digital signals, which are read by the monitoring and management module. When the power or temperature exceeds the threshold, the linkage IO extended control module automatically shuts down the radio frequency power amplifier.

[0036] The power amplifier monitoring module includes an RF power acquisition interface and a temperature acquisition interface. The RF power acquisition interface is used to connect to an external power detection circuit, receive an analog voltage signal representing the transmission power and convert it into a digital quantity. The temperature acquisition interface is used to connect to an external temperature sensor, receive an analog voltage signal representing the power amplifier temperature and convert it into a digital quantity.

[0037] This invention also proposes a control method for the DCP transmitting baseband chip of a meteorological geostationary satellite, comprising the following steps:

[0038] S1: Power-on Reset and Initialization: After the chip is powered on, the reset control module performs a chip reset, and the power management module enters the working mode to supply power to each module;

[0039] S2: GNSS time synchronization and RTC synchronization: The GNSS time synchronization module receives the GNSS second pulse signal through the GNSS chip interface, uses a digital phase-locked loop to discipline and synchronize the local clock, and outputs the synchronized high-precision clock to the encoding processing module and the baseband modulation module. At the same time, the built-in RTC module continuously synchronizes the frequency when the GNSS signal is normal and stores the synchronization parameters.

[0040] S3: Read Unique Identifier Code: The DCP dedicated unique identifier chip interface reads the device's unique identifier code as the identity identifier for data transmission;

[0041] S4: Data reception: The data reception module receives the data to be sent through the serial port or Ethernet port and stores it in the FIFO buffer. The data reception process is completed by interrupt or DMA. After the reception is completed, the encoding processing module is triggered to start encoding.

[0042] S5: Concatenated coding: The coding processing module sequentially performs BCH coding, scrambling, RS coding, and convolutional coding on the data to be transmitted to form coded data;

[0043] S6: QPSK modulation and IQ output: The baseband modulation module performs QPSK modulation and shaping filtering on the encoded data to generate baseband IQ signals and output them to the external RF circuit.

[0044] S7: Power Amplifier and Mixer Startup: The IO expansion control module outputs the RF power amplifier startup control signal through the corresponding IO interface according to the transmission command, and starts the RF power amplifier to transmit;

[0045] S8: Transmission monitoring: The power amplifier monitoring module continuously collects the power amplifier's transmission power and temperature during the transmission process and reports them through the monitoring port;

[0046] S9: Transmission Complete and Sleep: Transmission ends, power amplifier and mixer are turned off, and low-power sleep mode is entered;

[0047] S10: Status Indicator: LED displays real-time status of operation, reception, 1PPS, transmission, and carrier lock.

[0048] Preferably, the specific logical steps of S2 are as follows:

[0049] S201: The GNSS time synchronization and frequency calibration module receives the standard GNSS second pulse signal through an external GNSS chip interface, which is defined as the standard time reference. Simultaneously, the local second pulse time generated by the local crystal oscillator frequency division is collected. The time deviation between two second pulses is calculated with high precision using the chip's internal time-to-digital converter. The formula used is: ;

[0050] in The time deviation between the local clock and the GNSS standard clock. This is the time when the local crystal oscillator outputs the second pulse. For the GNSS standard second pulse time, if =0 indicates that the local clock is precisely synchronized. If a phase and frequency deviation is detected in the local clock, the clock discipline and correction process will begin.

[0051] S202: Based on the time deviation of two consecutive sampling periods, calculate the relative deviation of the local crystal oscillator's real-time frequency. The formula for calculating the frequency deviation is:

[0052] ;

[0053] in This refers to the relative frequency deviation of the crystal oscillator. This represents the time deviation at the current sampling moment. This represents the time deviation from the previous sampling time. The continuous sampling interval period;

[0054] S203: The digital phase-locked loop uses a proportional-integral control algorithm to generate the frequency control word, completing the closed-loop discipline of the local crystal oscillator. The formula for calculating the frequency control word is as follows:

[0055] ;

[0056] in For DAC frequency control word, This is a proportionality coefficient used to quickly correct instantaneous phase deviations. These are integral coefficients used to eliminate static residual frequency offset. For real-time time deviation, This represents the cumulative historical time deviation.

[0057] The frequency control word is input to the digital-to-analog converter, which converts it into a voltage-controlled voltage to regulate the local crystal oscillator output frequency. The corrected formula for the local crystal oscillator output frequency is:

[0058] ;

[0059] in The corrected crystal oscillator output frequency, This refers to the nominal frequency of the crystal oscillator. For crystal oscillator voltage-controlled sensitivity, This is the DAC frequency control word;

[0060] S204: After closed-loop discipline correction, the local clock frequency accuracy is better than 2×10. The GNSS timing and frequency correction module synchronously outputs the corrected unified high-precision clock signal to the encoding processing module and the baseband modulation module to ensure the precise unification of data encoding rate, baseband modulation symbol rate and transmission time slot, and eliminate system clock asynchronous error. S205: Under normal operating conditions with continuous GNSS signal lock, the built-in RTC module receives the second pulse calibration signal and frequency compensation parameters output by the GNSS time synchronization and frequency calibration module in real time, and completes its own clock phase and frequency alignment. The RTC calibration formula is: ,in This refers to the RTC second pulse timing after calibration. The original second pulse time of the RTC before calibration. The RTC module stores the time deviation ΔT, frequency deviation δf, frequency control word W, and compensation amount ΔTcomp of this calibration in its internal non-volatile register, continuously iteratively updating the calibration parameters. When the GNSS signal is lost in the future, this set of historical parameters can be called to complete high-precision timekeeping and achieve uninterrupted output of the time and frequency reference.

[0061] Preferably, the specific logical steps of S3 are as follows:

[0062] S301: After the chip power-on initialization is complete, the DCP dedicated unique code chip interface uses a single-bus protocol to send a wake-up timing signal to the peripheral OTP unique code chip to complete bus initialization. The interface continuously monitors the single-bus level status to determine whether the external unique code chip is online and whether the communication link is normal. The online device determination formula is defined as follows: ;

[0063] in For the online status indicator of the equipment, It is a single-bus real-time level. For single-bus device response threshold level, when Once it is determined that the external DCP unique code chip is in place and the link is normal, the data reading process begins. The monitoring and management module determines that the equipment is abnormal and records the equipment missing and abnormal log.

[0064] S302: The DCP dedicated unique code chip interface reads the N-bit original device unique code embedded in the external OTP chip via a single-bus timing sequence. The original code is a one-time factory-embedded, non-erasable hardware identification code, denoted as the original code sequence. ,in It is a single-bit binary encoded data, where n is the total number of bits in the unique code;

[0065] S303: The chip performs CRC cyclic redundancy check on the read original unique code, using the CRC-8 check algorithm. The check formula is as follows: ;

[0066] in Output the verification value for a single iteration. To verify the initial value in the previous iteration, This is the original encoded bit data to be verified. Generate polynomial constants for the CRC-8 standard;

[0067] After iterating through all the bits of data to complete the calculation, the final check value is obtained. Compare it with the factory verification value built into the unique code chip. The formula for determining valid data is as follows: ;

[0068] in This serves as a unique identifier for data validity. Determine if the read unique code data is valid. If a read error is detected, the read operation will be re-initiated, repeating a maximum of three times. If the read operation fails three times, a hardware error will be reported.

[0069] S304: Verified valid unique code The frame format is encapsulated and embedded in the uplink data frame header as a device identification identifier. The formula for generating the identification identifier field is as follows: ;

[0070] in For the device identification field that is ultimately embedded in the data frame, The number of bits for frame alignment padding. Fixed frame header identifier constants for DCP terminals;

[0071] S305: Packaged The data is stored in the chip's internal register cache and continuously output to the encoding processing module. The encoding processing module splices the device's unique identifier with the sensor-collected business data and participates in the subsequent BCH encoding, scrambling, RS encoding, and convolutional encoding processes, so that each frame of uplink data carries a device-specific watermark.

[0072] Preferably, the specific logical steps of S5 are as follows:

[0073] S501: The encoding processing module receives the original service data frame to be sent, assuming the original information data sequence is... First, the code enters the BCH encoder to complete error detection and correction encoding. Redundancy check bits are calculated using a generator polynomial, with the following formula: ;

[0074] in The generator polynomial for BCH encoding, where t is the number of BCH error correction bits. It is a primitive element of the finite field GF(2^m);

[0075] The original information polynomial After shifting the parity bits left by a certain number of bits, the generator polynomial is moduloed to obtain the BCH parity polynomial. The calculation formula is as follows: ;

[0076] Where n is the code length after BCH encoding, and K is the original information bit length. For quotient polynomial, For redundancy check polynomials;

[0077] The check digit is appended to the end of the original data to obtain the BCH-encoded output data. Complete random error detection and error correction preprocessing;

[0078] S502: The BCH-encoded data undergoes pseudo-random scrambling. To avoid continuous long 0 or long 1 code streams in satellite channel transmission causing clock loss at the receiver, scrambling uses a linear feedback shift register to generate a pseudo-random sequence. The scrambling operation formula is as follows: ;

[0079] in For the scrambled i-th bit of data, This is the original i-th bit data after BCH encoding. It is a CCSDS standard pseudo-random scrambling sequence. This is an XOR operation;

[0080] Scrambling randomizes the fixed bitstream, smooths out the spectral characteristics, ensures stable clock recovery at the receiver, and improves adaptability to weak channels.

[0081] S503: The scrambled data is subjected to RS block coding using standard RS(255,223) coding. The finite field is: A single frame contains 223 information symbols and 32 check symbols, and can correct up to 16 symbol errors. The RS encoding generator polynomial formula is as follows: ;

[0082] in Generate a polynomial for RS encoding. for Finite field primitive element;

[0083] The information symbol polynomial is: The RS check redundancy symbol is obtained by polynomial division, and the formula is as follows: ,in For RS encoding quotient polynomial, The RS redundancy check polynomial is used to append the check symbols to the end of the information symbols, generating an RS-encoded output data frame. To achieve the ability to correct sudden bit errors;

[0084] S504: The RS-encoded data is fed into a convolutional encoder, using standard CCSDS convolutional encoding with a constraint length K=7 and a bit rate of 1 / 2. It outputs a dual-stream bitrate through two generator polynomials. The convolutional encoding output formula is: ,in , These are the two output bits for convolutional coding. , These are the CCSDS standard convolution generation coefficients. Input data bits for current and historical shifts;

[0085] Data redundancy is increased by convolutional coding, and a four-level cascaded error correction system is formed by combining front-end BCH and RS coding. Finally, the baseband coded data that completes the full-link coding is output and sent to the baseband modulation module.

[0086] Compared with existing technologies, the beneficial effects of this invention are:

[0087] 1. All functions such as data reception, encoding and modulation, timing and frequency calibration, power amplifier monitoring, power management, and peripheral control are highly integrated into a single baseband chip, which greatly reduces the terminal PCB board area and the number of peripheral discrete components. At the same time, the chip supports fine switching between working mode and sleep mode, and can independently power off non-core modules, significantly reducing the static power consumption and average power consumption of the device. It effectively solves the problems of large size, high power consumption and weak battery life of traditional devices, and is suitable for long-term deployment scenarios such as unattended operation in the field and solar power supply.

[0088] 2. The chip hardware internally incorporates a four-level concatenated coding architecture conforming to the CCSDS standard: BCH coding, data scrambling, RS (255,223) coding, and convolutional coding. BCH coding corrects random errors, RS coding suppresses burst errors, scrambling optimizes the code stream's spectral characteristics, and convolutional coding further increases link redundancy. This multi-level error correction mechanism complements and adapts to the complex and variable wireless channels of meteorological satellites, significantly reducing data packet loss under fading and interference conditions, and greatly improving the stability and accuracy of uplink transmission of meteorological monitoring data.

[0089] 3. The local crystal oscillator is precisely disciplined using a GNSS digital phase-locked loop to achieve ultra-high precision clock output. It is also equipped with a built-in RTC module to achieve parameter memory and timekeeping. When the GNSS signal is normal, dynamic frequency calibration and parameter storage are completed. When the GNSS signal is blocked or lost due to interference, the historical calibration parameters are used to maintain timekeeping. This avoids frequency drift and time slot offset caused by long-term operation of the terminal, ensuring stable transmission frequency and accurate satellite time slot alignment. It completely solves the problem of demodulation failure at the ground receiver due to excessive frequency offset.

[0090] 4. The chip has a built-in power amplifier monitoring module, which can collect the RF power amplifier's transmission power and operating temperature in real time, and link with the IO expansion control module to form a closed-loop hardware protection logic. When faults such as power amplifier overheating or abnormal output power are detected, the RF transmission link can be quickly cut off to avoid power amplifier burnout, abnormal RF transmission, and other faults. This enables the device to self-diagnose and self-protect in unattended scenarios, effectively reducing the probability of terminal transmission failure and improving the device's working life and environmental adaptability.

[0091] 5. The chip standardizes the data transceiver interface, device unique code interface, radio frequency control interface, mixer control interface, multi-dimensional LED status indicator interface, and monitoring configuration interface. The unified hardware interface and control logic realize the standardization of DCP terminal peripheral adaptation, eliminating the need to modify drivers and hardware circuits for different devices, greatly reducing the difficulty of system integration, facilitating the batch deployment of meteorological DCS systems, unified operation and maintenance, and standardized equipment management, and significantly improving scalability and compatibility.

[0092] This invention adopts a highly integrated monolithic architecture, integrating functions such as data transmission and reception, four-level cascaded coding, baseband modulation, dual-redundant time-frequency calibration, device identification, power amplifier open-loop monitoring and protection, and intelligent power consumption management. It solves the defects of traditional DCP terminals, such as low integration, large power consumption and size, weak channel anti-interference, poor clock stability, lack of power amplifier protection, and inconsistent interfaces. It effectively improves the device's time slot transmission accuracy, data transmission reliability, and operational security, reduces the difficulty of integration and maintenance, and significantly improves the environmental adaptability and overall performance of meteorological DCP terminals, making it suitable for long-term unattended meteorological satellite data transmission scenarios in the field. Attached Figure Description

[0093] Figure 1 This is a block diagram of a meteorological geostationary satellite DCP transmission baseband chip proposed in this invention;

[0094] Figure 2 This is a schematic diagram of the internal structure of the encoding and processing module in the DCP transmission baseband chip of a meteorological geostationary satellite proposed in this invention;

[0095] Figure 3 This is a logic diagram of the GNSS timing and frequency calibration module and the built-in RTC module working together in a DCP transmitting baseband chip for a meteorological geostationary satellite, as proposed in this invention.

[0096] Figure 4 This is a schematic diagram of power allocation and mode switching in the power management module of a DCP transmitting baseband chip for a meteorological geostationary satellite, as proposed in this invention.

[0097] Figure 5 This is a flowchart of a control method for a DCP (Digital Cavity Portal) baseband chip for meteorological geostationary satellites proposed in this invention. Detailed Implementation

[0098] The present invention will be further explained below with reference to specific embodiments.

[0099] Example

[0100] Reference Figure 1-4This embodiment proposes a DCP (Digital Catalytic Converter) baseband chip for meteorological geostationary satellites. The chip includes a data receiving module, an encoding processing module, a baseband modulation module, a GNSS timing and frequency calibration module, a monitoring and management module, a DCP-specific unique code chip interface, a built-in RTC module, a power amplifier monitoring module, a power management module, a reset control module, an I / O expansion control module, and a mixer control interface. The power management module is electrically connected to all modules within the chip, providing appropriate operating voltages for each module. The reset control module is connected to all modules within the chip, enabling unified reset across the entire chip. The monitoring and management module is integrated with the data receiving module, encoding processing module, baseband modulation module, and baseband modulation module. The system is electrically connected to the control module, GNSS timing and frequency calibration module, power amplifier monitoring module, and IO expansion control module. The monitoring and management module is used to collect the operating status of each module and issue configuration parameters. The DCP dedicated unique code chip interface is connected to the encoding processing module to transmit the read device unique identification code to the encoding processing module to embed data frames. The IO expansion control module is electrically connected to the power amplifier monitoring module and the mixer control interface respectively to receive power amplifier abnormal signals and link to output front-end device control signals. The data receiving module is electrically connected to the encoding processing module, the baseband modulation module is connected to the encoding processing module, and the built-in RTC module is connected to the GNSS timing and frequency calibration module.

[0101] The data receiving module is equipped with a serial port and an Ethernet port for receiving data to be sent.

[0102] The encoding processing module is used to sequentially perform BCH encoding, scrambling, RS encoding, and convolutional encoding on the data to be transmitted to form encoded data;

[0103] The BCH encoding, scrambling, RS encoding, and convolutional encoding in the encoding processing module are performed according to the CCSDS standard, with RS encoding using RS(255,223) code.

[0104] The baseband modulation module is used to perform QPSK modulation and shaping filtering on the encoded data to generate baseband IQ signals;

[0105] The GNSS timing and frequency calibration module is equipped with a GNSS chip interface to receive GNSS second pulse signals, perform disciplining and frequency calibration of the local clock through a digital phase-locked loop, and output a high-precision clock signal to the encoding processing module and the baseband modulation module.

[0106] The GNSS timing and frequency calibration module supports one or more of the following satellite navigation systems: GPS, GLONASS, Galileo, and BeiDou.

[0107] The monitoring and management module includes a monitoring port and a configuration interface, which are used to monitor the chip's operating status and configure its operating parameters.

[0108] The DCP dedicated unique code chip interface is used to connect to the DCP dedicated unique code chip and read the device's unique identification code;

[0109] The built-in RTC module provides timekeeping functionality in the event of GNSS signal loss.

[0110] The built-in RTC module uses a low-power real-time clock circuit. When the GNSS signal is lost, it keeps time based on the frequency calibration information before the GNSS signal was lost and outputs a replacement second pulse signal.

[0111] The logic for the GNSS timing and frequency calibration module and the built-in RTC module to work together is as follows:

[0112] (1) The external GNSS receiver chip outputs a 1PPS pulse per second and an NMEA message, which are sent to the TDC through the GNSS chip interface;

[0113] (2) The TDC simultaneously acquires the clock signals of GNSS1PPS and the local crystal oscillator, measures the time difference between the two, and sends it to the DPLL;

[0114] (3) The DPLL generates the frequency control word, high-precision clock, timekeeping 1PPS and frequency calibration parameters based on the time difference;

[0115] (4) The frequency control word is converted into a voltage-controlled voltage by a DAC, which controls the local crystal oscillator to adjust the frequency, forming a closed-loop discipline;

[0116] (5) The high-precision clock output by DPLL is sent to the encoding and modulation module, and the timekeeping 1PPS and frequency calibration parameters are sent to the RTC module.

[0117] (6) When GNSS is normal, the built-in RTC module synchronously calibrates its own clock according to the timekeeping 1PPS and frequency calibration parameters. When GNSS is lost, the built-in RTC module outputs backup time / 1PPS pulse to provide the system with a timekeeping base.

[0118] The power amplifier monitoring module includes an RF power acquisition interface and a temperature acquisition interface, which are used to acquire the power amplifier's transmit power and temperature, respectively.

[0119] The power amplifier monitoring module converts the collected analog signals of transmit power and temperature into digital signals, which are then read by the monitoring and management module. When the power or temperature exceeds the threshold, the linkage IO expansion control module automatically shuts down the RF power amplifier. The power amplifier monitoring module includes an RF power acquisition interface and a temperature acquisition interface. The RF power acquisition interface is used to connect to an external power detection circuit, receive the analog voltage signal representing the transmit power, and convert it into a digital quantity. The temperature acquisition interface is used to connect to an external temperature sensor, receive the analog voltage signal representing the power amplifier temperature, and convert it into a digital quantity.

[0120] The power management module has multiple built-in voltage regulators and supports switching between working mode and sleep mode;

[0121] The power management module includes at least one low-dropout linear regulator for generating different voltages required by various modules inside the chip. The power management module includes a sleep control unit and a wake-up control unit. The sleep control unit shuts down the power supply to a specified module in response to an external sleep command or an internal timing signal. The wake-up control unit restores the power supply to a specified module in response to an external wake-up command or an internal timing signal.

[0122] The reset control module is equipped with a reset pin, which is used to receive external reset signals and perform chip reset;

[0123] The IO expansion control module is equipped with multiple general-purpose IO interfaces for controlling the output of external LED indicators and the operating status control of the RF power amplifier. The LED indicators include operating status indicator, data reception indicator, second pulse indicator, transmission status indicator and mixer carrier frequency lock indicator.

[0124] The general-purpose I / O interfaces of the I / O expansion control module include at least the following: RF power amplifier start control interface, RF power amplifier stop control interface, mixer chip reset interface, mixer chip start interface, working status indicator interface, data receiving indicator interface, second pulse indicator interface, transmit status indicator interface, and mixer carrier frequency lock indicator interface;

[0125] The mixer control interface is used to output control signals to control the reset and startup of the mixer chip.

[0126] Reference Figure 5 This embodiment proposes a control method for the DCP transmitting baseband chip of a meteorological geostationary satellite, including the following steps:

[0127] S1: Power-on Reset and Initialization: After the chip is powered on, the reset control module performs a chip reset, and the power management module enters the working mode to supply power to each module. The power supply sequence is: first the digital core logic (1.8V), then the IO interface and analog circuit (3.3V) to avoid latch-up effect.

[0128] S2: GNSS time synchronization and RTC synchronization: The GNSS time synchronization module receives the GNSS second pulse signal through the GNSS chip interface, uses a digital phase-locked loop to discipline and synchronize the local clock, and outputs the synchronized high-precision clock to the encoding processing module and the baseband modulation module. At the same time, the built-in RTC module continuously synchronizes the frequency when the GNSS signal is normal and stores the synchronization parameters.

[0129] The frequency calibration process is divided into a coarse adjustment stage and a fine adjustment stage. The coarse adjustment stage uses a digital phase-locked loop to quickly capture the frequency deviation, while the fine adjustment stage uses a proportional-integral (PI) control loop for fine adjustment, ultimately synchronizing the local clock with the GNSS clock. The frequency accuracy is better than 2e-9. The high-precision clock after calibration is output to the encoding processing module and the baseband modulation module. At the same time, the built-in RTC module continuously receives the frequency calibration information and uses GNSS pulses to correct the frequency and phase of the RTC pulses, so that the RTC time is synchronized with the GNSS time. The built-in RTC module stores the current frequency calibration parameters in a non-volatile register for use in case of GNSS signal loss.

[0130] S3: Read Unique Identifier Code: The DCP dedicated unique identifier chip interface reads the device's unique identifier code as the identity identifier for data transmission;

[0131] S4: Data reception: The data reception module receives the data to be sent through the serial port or Ethernet port and stores it in the FIFO buffer. The data reception process is completed by interrupt or DMA. After the reception is completed, the encoding processing module is triggered to start encoding.

[0132] S5: Concatenated coding: The coding processing module sequentially performs BCH coding, scrambling, RS coding, and convolutional coding on the data to be transmitted to form coded data;

[0133] S6: QPSK modulation and IQ output: The baseband modulation module performs QPSK modulation and shaping filtering on the encoded data to generate baseband IQ signals and output them to the external RF circuit.

[0134] Its standard QPSK quadrature modulation formula is: ;

[0135] Where I is the baseband signal amplitude of the in-phase path, Q is the baseband signal amplitude of the quadrature path, and A is the baseband modulation reference amplitude. , These are the input modulation bits after grouping, and their values ​​are either 0 or 1.

[0136] S7: Power Amplifier and Mixer Startup: The IO expansion control module outputs the RF power amplifier startup control signal through the corresponding IO interface according to the transmission command, and starts the RF power amplifier to transmit;

[0137] The IO extension control module enables the RF front-end timing based on the system transmit time slot command. It employs a timing enable determination formula to ensure the mixer stabilizes first, followed by the power amplifier, thus preventing spurious radiation. The formula is as follows: ;in This is the power amplifier enable signal. This is the mixer enable signal. To provide a stable delay for the mixer,

[0138] S8: Transmission monitoring: The power amplifier monitoring module continuously collects the power amplifier's transmission power and temperature during the transmission process and reports them through the monitoring port;

[0139] The sampling frequency can be configured from 1Hz to 100Hz. The collected power and temperature data are stored in the internal register in real time. The monitoring and management module can read these data through the monitoring port. The power amplifier monitoring module has a built-in comparator. When the power is detected to be lower than the set threshold or the temperature exceeds the set threshold, it automatically outputs a power amplifier stop signal through the IO expansion control module to shut down the RF power amplifier and prevent damage to the power amplifier.

[0140] The formula for the sampling time interval is:

[0141] ;

[0142] in The sampling period is Configurable sampling frequency;

[0143] S9: Transmission Complete and Hibernation: Transmission ends, power amplifier and mixer are turned off, and low-power hibernation is entered. In hibernation mode, only the GNSS timing and frequency calibration module, RTC module and reset detection circuit are powered. The power consumption of the entire chip is reduced to the microamp level. Wake-up can be achieved by external wake-up command or internal timer.

[0144] The formula for determining the power supply switch of the module is:

[0145] ;

[0146] S10: Status Indicator: LED displays real-time status of working, receiving, 1PPS, transmitting, and carrier lock-in.

[0147] IO4 outputs periodic pulses to indicate that the chip is operating normally;

[0148] When the data receiving module receives data, IO5 outputs a brief pulse to light up the LED;

[0149] When the GNSS 1PPS signal is valid, IO6 outputs a pulse with each second pulse;

[0150] During transmission, IO7 outputs a high level to illuminate the transmitter LED;

[0151] When the mixer carrier is locked, IO8 outputs a low level to light up the lock LED.

[0152] In this embodiment, the specific logical steps of S2 are as follows:

[0153] S201: The GNSS time synchronization and frequency calibration module receives the standard GNSS second pulse signal through an external GNSS chip interface, which is defined as the standard time reference. Simultaneously, the local second pulse time generated by the local crystal oscillator frequency division is collected. The time deviation between two second pulses is calculated with high precision using the chip's internal time-to-digital converter. The formula used is: ;

[0154] in The time deviation between the local clock and the GNSS standard clock. This is the time when the local crystal oscillator outputs the second pulse. For the GNSS standard second pulse time, if =0 indicates that the local clock is precisely synchronized. If a phase and frequency deviation is detected in the local clock, the clock discipline and correction process will begin.

[0155] S202: Based on the time deviation of two consecutive sampling periods, calculate the relative deviation of the local crystal oscillator's real-time frequency. The formula for calculating the frequency deviation is:

[0156] ;

[0157] in This refers to the relative frequency deviation of the crystal oscillator. This represents the time deviation at the current sampling moment. This represents the time deviation from the previous sampling time. The continuous sampling interval period;

[0158] S203: The digital phase-locked loop uses a proportional-integral control algorithm to generate the frequency control word, completing the closed-loop discipline of the local crystal oscillator. The formula for calculating the frequency control word is as follows:

[0159] ;

[0160] in For DAC frequency control word, This is a proportionality coefficient used to quickly correct instantaneous phase deviations. These are integral coefficients used to eliminate static residual frequency offset. For real-time time deviation, This represents the cumulative historical time deviation.

[0161] The frequency control word is input to the digital-to-analog converter, which converts it into a voltage-controlled voltage to regulate the local crystal oscillator output frequency. The corrected formula for the local crystal oscillator output frequency is:

[0162] ;

[0163] in The corrected crystal oscillator output frequency, This refers to the nominal frequency of the crystal oscillator. For crystal oscillator voltage-controlled sensitivity, This is the DAC frequency control word;

[0164] S204: After closed-loop discipline correction, the local clock frequency accuracy is better than 2×10. The GNSS timing and frequency correction module synchronously outputs the corrected unified high-precision clock signal to the encoding processing module and the baseband modulation module to ensure the precise unification of data encoding rate, baseband modulation symbol rate and transmission time slot, and eliminate system clock asynchronous error. S205: Under normal operating conditions with continuous GNSS signal lock, the built-in RTC module receives the second pulse calibration signal and frequency compensation parameters output by the GNSS time synchronization and frequency calibration module in real time, and completes its own clock phase and frequency alignment. The RTC calibration formula is: ,in This refers to the RTC second pulse timing after calibration. The original second pulse time of the RTC before calibration. The RTC module stores the time deviation ΔT, frequency deviation δf, frequency control word W, and compensation amount ΔTcomp of this calibration in its internal non-volatile register, continuously iteratively updating the calibration parameters. When the GNSS signal is lost in the future, this set of historical parameters can be called to complete high-precision timekeeping and achieve uninterrupted output of the time and frequency reference.

[0165] In this embodiment, the specific logical steps of S3 are as follows:

[0166] S301: After the chip power-on initialization is complete, the DCP dedicated unique code chip interface uses a single-bus protocol to send a wake-up timing signal to the peripheral OTP unique code chip to complete bus initialization. The interface continuously monitors the single-bus level status to determine whether the external unique code chip is online and whether the communication link is normal. The online device determination formula is defined as follows: ;

[0167] in For the online status indicator of the equipment, It is a single-bus real-time level. For single-bus device response threshold level, when Once it is determined that the external DCP unique code chip is in place and the link is normal, the data reading process begins. The monitoring and management module determines that the equipment is abnormal and records the equipment missing and abnormal log.

[0168] S302: The DCP dedicated unique code chip interface reads the N-bit original device unique code embedded in the external OTP chip via a single-bus timing sequence. The original code is a one-time factory-embedded, non-erasable hardware identification code, denoted as the original code sequence. ,in It is a single-bit binary encoded data, where n is the total number of bits in the unique code;

[0169] S303: The chip performs CRC cyclic redundancy check on the read original unique code, using the CRC-8 check algorithm. The check formula is as follows: ;

[0170] in Output the verification value for a single iteration. To verify the initial value in the previous iteration, This is the original encoded bit data to be verified. Generate polynomial constants for the CRC-8 standard;

[0171] After iterating through all the bits of data to complete the calculation, the final check value is obtained. Compare it with the factory verification value built into the unique code chip. The formula for determining valid data is as follows: ;

[0172] in This serves as a unique identifier for data validity. Determine if the read unique code data is valid. If a read error is detected, the read operation will be re-initiated, repeating a maximum of three times. If the read operation fails three times, a hardware error will be reported.

[0173] S304: Verified valid unique code The frame format is encapsulated and embedded in the uplink data frame header as a device identification identifier. The formula for generating the identification identifier field is as follows: ;

[0174] in For the device identification field that is ultimately embedded in the data frame, The number of bits for frame alignment padding. Fixed frame header identifier constants for DCP terminals;

[0175] S305: Packaged The data is stored in the chip's internal register cache and continuously output to the encoding processing module. The encoding processing module splices the device's unique identifier with the sensor-collected business data and participates in the subsequent BCH encoding, scrambling, RS encoding, and convolutional encoding processes, so that each frame of uplink data carries a device-specific watermark.

[0176] In this embodiment, the specific logical steps of S5 are as follows:

[0177] S501: The encoding processing module receives the original service data frame to be sent, assuming the original information data sequence is... First, the code enters the BCH encoder to complete error detection and correction encoding. Redundancy check bits are calculated using a generator polynomial, with the following formula: ;

[0178] in The generator polynomial for BCH encoding, where t is the number of BCH error correction bits. It is a primitive element of the finite field GF(2^m);

[0179] The original information polynomial After shifting the parity bits left by a certain number of bits, the generator polynomial is moduloed to obtain the BCH parity polynomial. The calculation formula is as follows: ;

[0180] Where n is the code length after BCH encoding, and K is the original information bit length. For quotient polynomial, For redundancy check polynomials;

[0181] The check digit is appended to the end of the original data to obtain the BCH-encoded output data. Complete random error detection and error correction preprocessing;

[0182] S502: The BCH-encoded data undergoes pseudo-random scrambling. To avoid continuous long 0 or long 1 code streams in satellite channel transmission causing clock loss at the receiver, scrambling uses a linear feedback shift register to generate a pseudo-random sequence. The scrambling operation formula is as follows: ;

[0183] in For the scrambled i-th bit of data, This is the original i-th bit data after BCH encoding. It is a CCSDS standard pseudo-random scrambling sequence. This is an XOR operation;

[0184] Scrambling randomizes the fixed bitstream, smooths out the spectral characteristics, ensures stable clock recovery at the receiver, and improves adaptability to weak channels.

[0185] S503: The scrambled data is subjected to RS block coding using standard RS(255,223) coding. The finite field is: A single frame contains 223 information symbols and 32 check symbols, and can correct up to 16 symbol errors. The RS encoding generator polynomial formula is as follows: ;

[0186] in Generate a polynomial for RS encoding. for Finite field primitive element;

[0187] The information symbol polynomial is: The RS check redundancy symbol is obtained by polynomial division, and the formula is as follows: ,in For RS encoding quotient polynomial, The RS redundancy check polynomial is used to append the check symbols to the end of the information symbols, generating an RS-encoded output data frame. To achieve the ability to correct sudden bit errors;

[0188] S504: The RS-encoded data is fed into a convolutional encoder, using standard CCSDS convolutional encoding with a constraint length K=7 and a bit rate of 1 / 2. It outputs a dual-stream bitrate through two generator polynomials. The convolutional encoding output formula is: ,in , These are the two output bits for convolutional coding. , These are the CCSDS standard convolution generation coefficients. Input data bits for current and historical shifts;

[0189] Data redundancy is increased by convolutional coding, and a four-level cascaded error correction system is formed by combining front-end BCH and RS coding. Finally, the baseband coded data that completes the full-link coding is output and sent to the baseband modulation module.

[0190] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A DCP (Digital Capacitor Packet) baseband chip for meteorological geostationary satellites, characterized in that, This includes a data receiving module, encoding processing module, baseband modulation module, GNSS timing and frequency calibration module, monitoring and management module, DCP dedicated unique code chip interface, built-in RTC module, power amplifier monitoring module, power management module, reset control module, IO expansion control module, and mixer control interface integrated within the same chip. The power management module is electrically connected to all modules within the chip, providing adaptive operating voltages for each module. The reset control module is connected to all modules within the chip, enabling unified reset across the entire chip. The monitoring and management module is integrated with the data receiving module, encoding processing module, baseband modulation module, GNSS timing and frequency calibration module... The module, power amplifier monitoring module, and IO expansion control module are electrically connected. The monitoring and management module is used to collect the operating status of each module and issue configuration parameters. The DCP dedicated unique code chip interface is connected to the encoding processing module for transmitting the read device unique identifier code to the encoding processing module to embed data frames. The IO expansion control module is electrically connected to the power amplifier monitoring module and the mixer control interface respectively for receiving power amplifier abnormal signals and linking the output of front-end device control signals. The data receiving module is electrically connected to the encoding processing module, the baseband modulation module is connected to the encoding processing module, and the built-in RTC module is connected to the GNSS time synchronization and frequency calibration module. The data receiving module is equipped with a serial port and an Ethernet port for receiving data to be sent; The encoding processing module is used to sequentially perform BCH encoding, scrambling, RS encoding, and convolutional encoding on the data to be transmitted to form encoded data. The baseband modulation module is used to perform QPSK modulation and shaping filtering on the encoded data to generate a baseband IQ signal; The GNSS timing and frequency calibration module is equipped with a GNSS chip interface for receiving GNSS second pulse signals, disciplining and calibrating the local clock through a digital phase-locked loop, and outputting a high-precision clock signal to the encoding processing module and the baseband modulation module. The monitoring and management module includes a monitoring port and a configuration interface, which are used to monitor the chip's working status and configure its working parameters. The DCP dedicated unique code chip interface is used to connect to the DCP dedicated unique code chip and read the device's unique identification code; The built-in RTC module is used to provide a timekeeping function when GNSS signals are lost; The power amplifier monitoring module includes an RF power acquisition interface and a temperature acquisition interface, which are used to acquire the power amplifier's transmit power and temperature, respectively. The power management module has multiple built-in voltage regulators and supports switching between working mode and sleep mode. The reset control module is equipped with a reset pin for receiving external reset signals and performing chip reset. The IO expansion control module is equipped with multiple general-purpose IO interfaces for controlling the output of external LED indicators and the operating status control of the RF power amplifier. The LED indicators include operating status indicator, data reception indicator, second pulse indicator, transmission status indicator and mixer carrier frequency lock indicator. The mixer control interface is used to output control signals to control the reset and startup of the mixer chip.

2. The meteorological geostationary satellite DCP transmission baseband chip according to claim 1, characterized in that, The GNSS timing and frequency calibration module supports one or more of the following satellite navigation systems: GPS, GLONASS, Galileo, and BeiDou. The built-in RTC module uses a low-power real-time clock circuit. When the GNSS signal is lost, it keeps time based on the frequency calibration information before the GNSS signal is lost and outputs a replacement second pulse signal. The logic for the coordinated operation of the GNSS timing and frequency calibration module and the built-in RTC module is as follows: (1) The external GNSS receiver chip outputs a 1PPS pulse per second and an NMEA message, which are sent to the TDC through the GNSS chip interface; (2) The TDC simultaneously acquires the clock signals of GNSS1PPS and the local crystal oscillator, measures the time difference between the two, and sends it to the DPLL; (3) The DPLL generates the frequency control word, high-precision clock, timekeeping 1PPS and frequency calibration parameters based on the time difference; (4) The frequency control word is converted into a voltage-controlled voltage by a DAC, which controls the local crystal oscillator to adjust the frequency, forming a closed-loop discipline; (5) The high-precision clock output by DPLL is sent to the encoding and modulation module, and the timekeeping 1PPS and frequency calibration parameters are sent to the RTC module. (6) When GNSS is normal, the built-in RTC module synchronously calibrates its own clock according to the timekeeping 1PPS and frequency calibration parameters. When GNSS is lost, the built-in RTC module outputs a backup time / 1PPS second pulse to provide a timekeeping base for the system.

3. The meteorological geostationary satellite DCP transmission baseband chip according to claim 2, characterized in that, The BCH encoding, scrambling, RS encoding and convolutional encoding in the encoding processing module are performed in accordance with the CCSDS standard, wherein the RS encoding adopts RS (255,223) code; The power management module includes at least one low-dropout linear regulator for generating different voltages required by various modules within the chip. The power management module includes a sleep control unit and a wake-up control unit. The sleep control unit shuts down the power supply to a specified module in response to an external sleep command or an internal timing signal. The wake-up control unit restores the power supply to a specified module in response to an external wake-up command or an internal timing signal.

4. A meteorological geostationary satellite DCP transmission baseband chip according to claim 3, characterized in that, The general-purpose I / O interfaces of the I / O expansion control module include at least: RF power amplifier start control interface, RF power amplifier stop control interface, mixer chip reset interface, mixer chip start interface, working status indicator interface, data receiving indicator interface, second pulse indicator interface, transmit status indicator interface, and mixer carrier frequency lock indicator interface.

5. A meteorological geostationary satellite DCP transmission baseband chip according to claim 4, characterized in that, The power amplifier monitoring module is used to convert the collected analog signals of transmission power and temperature into digital signals, which are read by the monitoring and management module. When the power or temperature exceeds the threshold, the linkage IO extended control module automatically shuts down the RF power amplifier. The power amplifier monitoring module includes an RF power acquisition interface and a temperature acquisition interface. The RF power acquisition interface is used to connect to an external power detection circuit, receive an analog voltage signal representing the transmission power and convert it into a digital quantity. The temperature acquisition interface is used to connect to an external temperature sensor, receive an analog voltage signal representing the power amplifier temperature and convert it into a digital quantity.

6. A control method for a baseband chip for a meteorological geostationary satellite DCP transmission, based on the chip described in any one of claims 1-5, characterized in that, Includes the following steps: S1: Power-on Reset and Initialization: After the chip is powered on, the reset control module performs a chip reset, and the power management module enters the working mode to supply power to each module; S2: GNSS time synchronization and RTC synchronization: The GNSS time synchronization module receives the GNSS second pulse signal through the GNSS chip interface, uses a digital phase-locked loop to discipline and synchronize the local clock, and outputs the synchronized high-precision clock to the encoding processing module and the baseband modulation module. At the same time, the built-in RTC module continuously synchronizes the frequency when the GNSS signal is normal and stores the synchronization parameters. S3: Read Unique Identifier Code: The DCP dedicated unique identifier chip interface reads the device's unique identifier code as the identity identifier for data transmission; S4: Data reception: The data reception module receives the data to be sent through the serial port or Ethernet port and stores it in the FIFO buffer. The data reception process is completed by interrupt or DMA. After the reception is completed, the encoding processing module is triggered to start encoding. S5: Concatenated coding: The coding processing module sequentially performs BCH coding, scrambling, RS coding, and convolutional coding on the data to be transmitted to form coded data; S6: QPSK modulation and IQ output: The baseband modulation module performs QPSK modulation and shaping filtering on the encoded data to generate baseband IQ signals and output them to the external RF circuit. S7: Power Amplifier and Mixer Startup: The IO expansion control module outputs the RF power amplifier startup control signal through the corresponding IO interface according to the transmission command, and starts the RF power amplifier to transmit; S8: Transmission monitoring: The power amplifier monitoring module continuously collects the power amplifier's transmission power and temperature during the transmission process and reports them through the monitoring port; S9: Transmission Complete and Sleep: Transmission ends, power amplifier and mixer are turned off, and low-power sleep mode is entered; S10: Status Indicator: LED displays real-time status of operation, reception, 1PPS, transmission, and carrier lock.

7. The control method for a meteorological geostationary satellite DCP transmitting baseband chip according to claim 6, characterized in that, The specific logical steps of S2 are as follows: S201: The GNSS time synchronization and frequency calibration module receives the standard GNSS second pulse signal through an external GNSS chip interface, which is defined as the standard time reference. Simultaneously, the local second pulse time generated by the local crystal oscillator frequency division is collected. The time deviation between two second pulses is calculated with high precision using the chip's internal time-to-digital converter. The formula used is: ; in The time deviation between the local clock and the GNSS standard clock. This is the time when the local crystal oscillator outputs the second pulse. For the GNSS standard second pulse time, if =0 indicates that the local clock is precisely synchronized. If a phase and frequency deviation is detected in the local clock, the clock discipline and correction process will begin. S202: Based on the time deviation of two consecutive sampling periods, calculate the relative deviation of the local crystal oscillator's real-time frequency. The formula for calculating the frequency deviation is: ； in This refers to the relative frequency deviation of the crystal oscillator. This represents the time deviation at the current sampling moment. This represents the time deviation from the previous sampling time. The continuous sampling interval period; S203: The digital phase-locked loop uses a proportional-integral control algorithm to generate the frequency control word, completing the closed-loop discipline of the local crystal oscillator. The formula for calculating the frequency control word is as follows: ； in For DAC frequency control word, This is a proportionality coefficient used to quickly correct instantaneous phase deviations. These are integral coefficients used to eliminate static residual frequency offset. For real-time time deviation, This represents the cumulative historical time deviation. The frequency control word is input to the digital-to-analog converter, which converts it into a voltage-controlled voltage to regulate the local crystal oscillator output frequency. The corrected formula for the local crystal oscillator output frequency is: ； in The corrected crystal oscillator output frequency, This refers to the nominal frequency of the crystal oscillator. For crystal oscillator voltage-controlled sensitivity, This is the DAC frequency control word; S204: After closed-loop discipline correction, the local clock frequency accuracy is better than 2×10. The GNSS timing and frequency correction module synchronously outputs the corrected unified high-precision clock signal to the encoding processing module and the baseband modulation module to ensure the precise unification of data encoding rate, baseband modulation symbol rate and transmission time slot, and eliminate system clock asynchronous error. S205: Under normal operating conditions with continuous GNSS signal lock, the built-in RTC module receives the second pulse calibration signal and frequency compensation parameters output by the GNSS time synchronization and frequency calibration module in real time, and completes its own clock phase and frequency alignment. The RTC calibration formula is: ,in This refers to the RTC second pulse timing after calibration. The original second pulse time of the RTC before calibration. The RTC module stores the time deviation ΔT, frequency deviation δf, frequency control word W, and compensation amount ΔTcomp of this calibration in its internal non-volatile register, continuously iteratively updating the calibration parameters. When the GNSS signal is lost in the future, this set of historical parameters can be called to complete high-precision timekeeping and achieve uninterrupted output of the time and frequency reference.

8. The control method for a meteorological geostationary satellite DCP transmission baseband chip according to claim 7, characterized in that, The specific logical steps of S3 are as follows: S301: After the chip power-on initialization is complete, the DCP dedicated unique code chip interface uses a single-bus protocol to send a wake-up timing signal to the peripheral OTP unique code chip to complete bus initialization. The interface continuously monitors the single-bus level status to determine whether the external unique code chip is online and whether the communication link is normal. The online device determination formula is defined as follows: ; in For the online status indicator of the equipment, It is a single-bus real-time level. For single-bus device response threshold level, when Once it is determined that the external DCP unique code chip is in place and the link is normal, the data reading process begins. The monitoring and management module determines that the equipment is abnormal and records the equipment missing and abnormal log. S302: The DCP dedicated unique code chip interface reads the N-bit original device unique code embedded in the external OTP chip via a single-bus timing sequence. The original code is a one-time factory-embedded, non-erasable hardware identification code, denoted as the original code sequence. ,in It is a single-bit binary encoded data, where n is the total number of bits in the unique code; S303: The chip performs CRC cyclic redundancy check on the read original unique code, using the CRC-8 check algorithm. The check formula is as follows: ; in Output the verification value for a single iteration. To verify the initial value in the previous iteration, This is the original encoded bit data to be verified. Generate polynomial constants for the CRC-8 standard; After iterating through all the bits of data to complete the calculation, the final check value is obtained. Compare it with the factory verification value built into the unique code chip. The formula for determining valid data is as follows: ; in This serves as a unique identifier for data validity. Determine if the read unique code data is valid. If a read error is detected, the read operation will be re-initiated, repeating a maximum of three times. If the read operation fails three times, a hardware error will be reported. S304: Verified valid unique code The frame format is encapsulated and embedded in the uplink data frame header as a device identification identifier. The formula for generating the identification identifier field is as follows: ; in For the device identification field that is ultimately embedded in the data frame, The number of bits for frame alignment padding. Fixed frame header identifier constants for DCP terminals; S305: Packaged The data is stored in the chip's internal register cache and continuously output to the encoding processing module. The encoding processing module splices the device's unique identifier with the sensor-collected business data and participates in the subsequent BCH encoding, scrambling, RS encoding, and convolutional encoding processes, so that each frame of uplink data carries a device-specific watermark.

9. The control method for a meteorological geostationary satellite DCP transmission baseband chip according to claim 8, characterized in that, The specific logical steps of S5 are as follows: S501: The encoding processing module receives the original service data frame to be sent, assuming the original information data sequence is... First, the code enters the BCH encoder to complete error detection and correction encoding. Redundancy check bits are calculated using a generator polynomial, with the following formula: ; in The generator polynomial for BCH encoding, where t is the number of BCH error correction bits. It is a primitive element of the finite field GF(2^m); The original information polynomial After shifting the parity bits left by a certain number of bits, the generator polynomial is moduloed to obtain the BCH parity polynomial. The calculation formula is as follows: ; Where n is the code length after BCH encoding, and K is the original information bit length. For quotient polynomial, For redundancy check polynomials; The check digit is appended to the end of the original data to obtain the BCH-encoded output data. Complete random error detection and error correction preprocessing; S502: The BCH-encoded data undergoes pseudo-random scrambling. To avoid continuous long 0 or long 1 code streams in satellite channel transmission causing clock loss at the receiver, scrambling uses a linear feedback shift register to generate a pseudo-random sequence. The scrambling operation formula is as follows: ; in For the scrambled i-th bit of data, This is the original i-th bit data after BCH encoding. It is a CCSDS standard pseudo-random scrambling sequence. This is an XOR operation; Scrambling randomizes the fixed bitstream, smooths out the spectral characteristics, ensures stable clock recovery at the receiver, and improves adaptability to weak channels. S503: The scrambled data is subjected to RS block coding using standard RS(255,223) coding. The finite field is: A single frame contains 223 information symbols and 32 check symbols, and can correct up to 16 symbol errors. The RS encoding generator polynomial formula is as follows: ; in Generate a polynomial for RS encoding. for Finite field primitive element; The information symbol polynomial is: The RS check redundancy symbol is obtained by polynomial division, and the formula is as follows: ,in For RS encoding quotient polynomial, The RS redundancy check polynomial is used to append the check symbols to the end of the information symbols, generating an RS-encoded output data frame. To achieve the ability to correct sudden bit errors; S504: The RS-encoded data is fed into a convolutional encoder, using standard CCSDS convolutional encoding with a constraint length K=7 and a bit rate of 1 / 2. It outputs a dual-stream bitrate through two generator polynomials. The convolutional encoding output formula is: ,in , These are the two output bits for convolutional coding. , These are the CCSDS standard convolution generation coefficients. Input data bits for current and historical shifts; Data redundancy is increased by convolutional coding, and a four-level cascaded error correction system is formed by combining front-end BCH and RS coding. Finally, the baseband coded data that completes the full-link coding is output and sent to the baseband modulation module.

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