Data transmission method, system and device, electronic equipment and storage medium

Abstract

The present disclosure provides a data transmission method, system, device, electronic equipment and storage medium, which relates to the field of cloud service and can be applied to a cloud platform. The method comprises the following steps: determining to-be-transmitted data, and writing the to-be-transmitted data into a data cache area; generating a target DTD according to attribute information of the to-be-transmitted data, and writing the target DTD into a DTD cache area; in response to detecting that new data is written into the DTD cache area, reading the target DTD, and constructing a target WQE according to the target DTD; reading the to-be-transmitted data from the data cache area according to the target WQE, and writing the to-be-transmitted data into a memory of a remote node. The present disclosure realizes the offloading of computing and transmission load, and reduces the transmission delay of message data.

Description

Technical Field

[0001] This disclosure relates to the field of cloud services, specifically to a data transmission method, system, apparatus, electronic device, and storage medium. Background Technology

[0002] As the parameter size of deep learning models (especially large-scale language models) continues to grow, distributed training and inference have become the mainstream technical paradigm in the field of artificial intelligence. In distributed computing systems, the performance of collective communication between cluster nodes directly affects the overall computational efficiency and response speed. Typical collective communication operations include all-reduce, broadcast, and all-gather, which are widely used in core processes such as gradient synchronization, parameter distribution, and activation value transfer. Currently, high-performance computing clusters commonly use Remote Direct Memory Access (RDMA) technology to achieve data exchange between nodes. Summary of the Invention

[0003] This disclosure presents a data transmission method, system, apparatus, electronic device, and storage medium.

[0004] According to a first aspect of this disclosure, a data transmission method is provided, comprising: determining data to be transmitted and writing the data to be transmitted into a data buffer; generating a target data transmission descriptor (DTD) based on attribute information of the data to be transmitted and writing the target DTD into a DTD buffer; in response to detecting that new data has been written into the DTD buffer, reading the target DTD and constructing a target work queue element (WQE) based on the target DTD; reading the data to be transmitted from the data buffer based on the target WQE and writing the data to be transmitted into the memory of a remote node.

[0005] According to a second aspect of this disclosure, a data transmission system is provided, comprising: a graphics processing unit (GPU) and a data processing unit (DPU), the DPU including a proxy module and a remote direct memory access engine; the GPU is configured to: determine data to be transmitted and write the data to be transmitted into a data buffer; generate a target data transmission descriptor (DTD) based on attribute information of the data to be transmitted and write the target DTD into a DTD buffer; the proxy module is configured to, in response to detecting that new data has been written to the DTD buffer, read the target DTD and construct a target work queue element (WQE) based on the target DTD; the remote direct memory access engine is configured to read the data to be transmitted from the data buffer based on the target WQE and write the data to be transmitted into the memory of a remote node.

[0006] According to a third aspect of this disclosure, a data transmission apparatus is provided, comprising: a data writing unit configured to determine data to be transmitted and write the data to be transmitted into a data buffer; a DTD writing unit configured to generate a target data transmission descriptor DTD based on attribute information of the data to be transmitted and write the target DTD into a DTD buffer; a WQE generation unit configured to, in response to detecting new data written to the DTD buffer, read the target DTD and construct a target work queue element WQE based on the target DTD; and a data transmission unit configured to read the data to be transmitted from the data buffer based on the target WQE and write the data to be transmitted into the memory of a remote node.

[0007] According to a fourth aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a method as described in any implementation of the first aspect.

[0008] According to a fifth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions for causing a computer to perform a method as described in any implementation of the first aspect.

[0009] According to a sixth aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method as described in any implementation of the first aspect.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 This is an exemplary system architecture diagram to which this disclosure can be applied; Figure 2 This is a flowchart of a first embodiment of the data transmission method according to the present disclosure; Figure 3 This is a flowchart of a second embodiment of the data transmission method according to the present disclosure; Figure 4 This is a flowchart of a third embodiment of the data transmission method according to the present disclosure; Figure 5 This is a flowchart of the fourth embodiment of the data transmission method according to the present disclosure; Figure 6This is a flowchart of the fifth embodiment of the data transmission method according to the present disclosure; Figure 7 This is a flowchart of the sixth embodiment of the data transmission method according to the present disclosure; Figure 8 This is a flowchart of the seventh embodiment of the data transmission method according to the present disclosure; Figure 9 This is a schematic diagram of the structure of a data transmission system according to an embodiment of the present disclosure; Figure 10 This is a schematic diagram of a structure of a data transmission apparatus according to an embodiment of the present disclosure; Figure 11 This is a block diagram of an electronic device used to implement the data transmission method of the embodiments of this disclosure. Detailed Implementation

[0012] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0013] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0014] Figure 1 An exemplary system frame 100 is shown, to which embodiments of the data transmission method or data transmission apparatus of this disclosure may be applied.

[0015] like Figure 1 As shown, system architecture 100 may include terminal devices 101, 102, and 103, a network 104, and a server 105. Network 104 serves as the medium for providing communication links between terminal devices 101, 102, and 103 and server 105. Network 104 may include various connection types, such as wired or wireless communication links, or fiber optic cables, etc.

[0016] Users can use terminal devices 101, 102, and 103 to interact with server 105 via network 104 to receive or send messages, etc. Various applications for enabling information communication between the terminal devices 101, 102, and 103 and server 105 can be installed. These applications include cloud storage applications and instant messaging applications.

[0017] Terminal devices 101, 102, and 103 and server 105 can be either hardware or software. When terminal devices 101, 102, and 103 are hardware, they can be various electronic devices with displays, including but not limited to smartphones, tablets, laptops, and desktop computers. When terminal devices 101, 102, and 103 are software, they can be installed in the aforementioned electronic devices, and can be implemented as multiple software programs or software modules, or as a single software program or software module; no specific limitation is made here. When server 105 is hardware, it can be implemented as a distributed server cluster composed of multiple servers, or as a single server. When server 105 is software, it can be implemented as multiple software programs or software modules, or as a single software program or software module; no specific limitation is made here.

[0018] Server 105 can provide various services through its built-in applications. For example, users can operate the server through applications on terminal devices 101, 102, and 103 and send data transmission requests to server 105. Server 105 can receive and process these data transmission requests, performing the following steps: determining the data to be transmitted and writing it to a data buffer; generating a target DTD (Data Transfer Descriptor) based on the attribute information of the data to be transmitted and writing it to a DTD buffer; in response to detecting new data written to the DTD buffer, reading the target DTD and constructing a target WQE (Work Queue Element) based on the target DTD; and reading the data to be transmitted from the data buffer based on the target WQE and writing it to the memory of the remote node.

[0019] It should be noted that the data transmission method provided in this embodiment is generally executed by server 105, and correspondingly, the data transmission device is generally located in server 105.

[0020] It should be understood that Figure 1 The number of terminal devices, networks, and servers shown is merely illustrative. Depending on implementation needs, any number of terminal devices, networks, and servers can be included.

[0021] Continue to refer to Figure 2 The diagram illustrates a flow 200 of a first embodiment of a data transmission method according to the present disclosure. This data transmission method includes the following steps: Step 201: Determine the data to be transmitted and write it into the data buffer.

[0022] In this embodiment, the execution subject of the data transmission method (e.g.) Figure 1The server 105 shown will determine the data to be transmitted and write it to the data buffer. The local GPU (Graphics Processing Unit) executes preset business computing tasks such as deep learning model training and parallel computing. After a single round of computing tasks is completed, the GPU will traverse the business data such as calculation results, intermediate feature data, and model parameters in its local video memory. Based on the data interaction rules between cluster nodes, business routing configuration, and data request instructions from remote nodes, the server will select the data content that needs to be transmitted across nodes via RDMA (remote direct memory access) and determine this part of the data as the data to be transmitted in this transmission.

[0023] Then, the GPU reads the data buffer parameters configured during system initialization, including the total buffer capacity, starting address, address space range, and maximum length of a single data segment. It verifies the total amount of data to be transferred, the data format, and the storage alignment rules to ensure that the size and format of the data to be transferred match the storage specifications of the data buffer. Following a preset address increment order and data alignment rules, the GPU continuously writes the verified data to be transferred into its own pre-defined data buffer within video memory. The writing process uses a direct memory write mode, eliminating the need for CPU involvement in data copying and transfer, thus ensuring efficient data writing. After the data write operation is completed, the GPU locks the storage area of ​​that data segment in the data buffer, stopping any read, write, or modification of that area to prevent data tampering during transmission.

[0024] Step 202: Generate a target data transmission descriptor (DTD) based on the attribute information of the data to be transmitted, and write the target DTD into the DTD buffer.

[0025] In this embodiment, the aforementioned execution entity generates a target DTD based on the attribute information of the data to be transmitted and writes the target DTD into the DTD cache. The GPU retrieves the attribute information of the data to be transmitted stored in the previous process, specifically including: the data cache handle, the offset address of the data relative to the cache, and the total length of the data to be transmitted. Here, the handle is an identifier used to identify an object or item.

[0026] The GPU uses a predefined DTD standard data structure to fill and encapsulate various attribute information fields to generate a target DTD. The target DTD may include, but is not limited to, the following core fields: Operation Type field: filled with the identifier of the RDMA read / write operation being performed; Transfer Length field: filled with the total length of the data to be transferred in bytes; Remote Data Buffer Handle: remote offset address; Local Data Buffer Handle; Local Offset Address. After filling, the GPU performs format verification according to bit width and byte alignment rules to generate the target DTD.

[0027] This embodiment uses a DTD circular buffer as an instruction cache. The buffer is managed for reading and writing by the Producer Index (PI) and Consumer Index (CI). The GPU reads the pointer status of the current circular buffer in real time: comparing the positions of the producer and consumer pointers to determine if there are free storage units in the buffer. If the buffer is not full, the DTD write operation is performed directly; if the buffer is full, the GPU pauses the new DTD generation and enters a waiting state until the DPU agent module finishes processing the existing DTD, updates the consumer pointer to release free space, and then continues to execute the write operation. The GPU will notify the DPU of the updated PI pointer value.

[0028] The GPU locates the free memory position pointed to by the production pointer in the circular buffer and writes the assembled target DTD completely into the corresponding memory unit. The writing process is a direct write to video memory, without CPU forwarding, ensuring instruction issuance efficiency. After a single target DTD is written, the GPU, according to the traversal rules of the circular buffer, steps the production pointer PI one unit forward, pointing to the next free memory position, preparing for the writing of the next DTD.

[0029] This embodiment defines a generalized, hardware-independent RDMA data transfer task description format for communication between the DPU and computing units (CPU / GPU). This protocol allows the CPU and GPU to issue only high-level task instructions without directly constructing and submitting complex low-level WQE, thereby achieving transparency to the backend network interface card hardware specifications.

[0030] Step 203: In response to the detection of new data being written to the DTD buffer, the target DTD is read and the target work queue element WQE is constructed based on the target DTD.

[0031] In this embodiment, the agent module inside the DPU determines changes in the buffer data by comparing the values ​​of the production pointer (PI) and consumption pointer (CI) in the DTD circular buffer in real time. When a step in the production pointer (PI) is detected and PI and CI do not overlap, it is determined that a new target DTD has been written to the DTD circular buffer, and the subsequent reading and parsing process is triggered. The entire monitoring process is completed independently by the DPU hardware without the need for CPU scheduling.

[0032] Then, based on the current consumer pointer CI, the agent module locates the memory unit to be processed in the DTD circular buffer and reads the newly added target DTD completely from the GPU memory's DTD circular buffer. The read operation is implemented through the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) bus, using a hardware direct read method to ensure real-time instruction reading. After the read is completed, the agent module performs format verification on the target DTD, checking the integrity of each field and the validity of the data, eliminating abnormal instructions, and proceeding to the parsing stage after the verification is passed.

[0033] Subsequently, the proxy module parses the target DTD according to the preset instruction format, extracting the internal dynamic field information one by one. These mainly include: Operation Type field: filled with the RDMA read / write operation identifier executed this time; Transmission Length field: filled with the total length of data to be transmitted in bytes; Remote Data Buffer Handle: remote offset address; Local Data Buffer Handle; Local Offset Address, etc. These parameters are dynamic service information specific to this transmission, used to define the behavior of a single RDMA transmission.

[0034] Finally, the proxy module, based on the RDMA protocol specification and the WQE standard structure, maps and encapsulates the static resources configured during the initialization phase and the dynamic parameters parsed from the DTD, thereby generating a hardware-recognizable target WQE. The specific assembly logic may include: converting the RDMA operation type in the DTD to the standard opcode corresponding to the WQE; combining the local memory base address configured during initialization with the address offset in the DTD to obtain the complete local memory address required by the WQE, and filling it with the local key lkey; combining the remote memory base address configured during initialization with the address offset in the DTD to obtain the complete remote memory address, and filling it with the remote key rkey; writing the length of the data to be transmitted in the DTD into the WQE length field; selecting the physical network interface and corresponding QP according to the preset scheduling strategy, and writing the QP pointer / number into the WQE channel identifier field.

[0035] After the target WQE is constructed, the proxy module performs format, bit width, and byte alignment checks according to the RDMA engine's interface specifications. Once confirmed to be correct, the WQE is temporarily stored in the DPU's internal cache, waiting to be submitted to the corresponding queue for the QP's send queue, preparing for subsequent data transmission by the RDMA engine.

[0036] Step 204: Read the data to be transmitted from the data buffer according to the target WQE, and write the data to be transmitted into the memory of the remote node.

[0037] In this embodiment, the RDMA engine retrieves the target WQE from the transmit queue of the corresponding queue pair and parses it. It then uses the data handle to query the local memory address, data priority information, and local key lkey, verifying local memory access permissions. After successful permission verification, the engine directly reads the data to be transmitted from the corresponding range of the GPU's video memory data buffer via a hardware direct connection channel. The entire reading process does not involve CPU forwarding.

[0038] The RDMA engine extracts the remote memory address and remote key rkey carried by the WQE to complete the remote memory access permission verification. After successful verification, it sends data packets via the designated physical network interface according to the preset scheduling result; the RDMA hardware of the remote device receives the packets and writes the data into the designated memory area. Once the transmission task corresponding to the current WQE is completed, the RDMA engine generates a CQE with complete status information and writes it to the completion queue.

[0039] In addition, the proxy module obtains the CQE (Completion Queue Element) corresponding to the WQE, and then updates the consumption pointer ci in the DTD cache of the GPU, thereby notifying the GPU that the data transfer has been completed.

[0040] The data transmission method provided by this disclosure first determines the data to be transmitted and writes it into a data buffer. Then, it generates a target data transmission descriptor (DTD) based on the attribute information of the data to be transmitted and writes the target DTD into a DTD buffer. Next, in response to detecting new data being written to the DTD buffer, it reads the target DTD and constructs a target work queue element (WQE) based on the target DTD. Finally, it reads the data to be transmitted from the data buffer based on the target WQE and writes it into the memory of the remote node. This method relies on GPU and DPU collaboration and an RDMA transmission architecture, with data and instruction flow handled entirely by hardware, eliminating the need for CPU intervention. Through hierarchical caching, instruction standardization, hardware task parsing, and remote direct write mechanisms, it offloads computational and transmission loads, reduces message data transmission latency, lowers host computing power overhead, and improves cluster data transmission efficiency and system stability.

[0041] Furthermore, the collection, storage, use, processing, transmission, provision, and disclosure of any type of information, such as user personal information, involved in the technical solutions disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0042] Continue to refer to Figure 3 , Figure 3 A flow 300 of a second embodiment of the data transmission method according to the present disclosure is shown. The data transmission method includes the following steps: Step 301: In response to determining that the current computing task has been completed, determine the data to be transmitted.

[0043] In this embodiment, the GPU runs deep learning training, parallel computing, and other business tasks, and monitors the task running status in real time. If the execution body of the data transmission method (e.g., Figure 1 The server 105 shown detects that the current round of computation has been completed and all computation results have been generated, thus determining that the computation task is complete. At this time, the GPU's CUDA kernel (CUDA kernel function) needs to transfer data. The GPU will filter out the computation results, intermediate features, model parameters, and other data that need to be shared across nodes according to preset data interaction rules, define them as the data to be transferred in this RDMA transfer, and record the corresponding storage location, data length, and other attribute information.

[0044] Step 302: Determine the data buffer area for writing data from the pre-allocated buffer pool according to the data length of the data to be transmitted.

[0045] In this embodiment, the aforementioned execution entity has divided the GPU memory into multiple levels of data cache areas during initialization, forming a dedicated cache pool. Each cache area is classified according to its capacity and its range is marked. After the GPU obtains the total length of the data to be transmitted, it traverses the capacity parameters of each cache area in the cache pool to match a free cache area that can completely accommodate the data. After selecting the target area, its occupancy status is marked to prevent conflicts caused by concurrent occupancy by multiple tasks, thereby determining the corresponding dedicated data cache area for this data writing.

[0046] Step 303: Copy the data to be transferred to the data buffer area according to the source address of the data to be transferred in the video memory.

[0047] In this embodiment, after the GPU obtains the source address, data length, and determined target data cache address of the data to be transferred in video memory, it calls the CUDA kernel function to perform a data copy operation within the video memory. Specifically, it locates the physical storage location of the data to be transferred based on the source address and copies all data directly from the native storage area to the pre-allocated data cache according to byte alignment rules. The copying process is completed independently by the GPU hardware, using a zero-intermediate method, without consuming CPU resources. After the copy is completed, the data cache is marked as ready.

[0048] Step 304: Generate a target DTD based on the attribute information of the data to be transmitted, and write the target DTD into the DTD buffer.

[0049] Step 305: In response to the detection of new data being written to the DTD buffer, the target DTD is read and the target WQE is constructed based on the target DTD.

[0050] Step 306: Read the data to be transmitted from the data buffer according to the target WQE, and write the data to be transmitted into the memory of the remote node.

[0051] Steps 304-306 are basically the same as steps 202-204 in the aforementioned embodiments. For specific implementation methods, please refer to the aforementioned description of steps 202-204, which will not be repeated here.

[0052] from Figure 3 It can be seen from this that, with Figure 2 Compared to the corresponding embodiments, the data transmission method in this embodiment emphasizes the step of writing the data to be transmitted into the data cache area. Data filtering, cache matching, and data copying are completed inside the GPU. Hardware-level data transfer is achieved by relying on CUDA kernel functions, without occupying CPU resources throughout the process. In addition, combined with the on-demand allocation mechanism of the cache pool, the video memory space is rationally utilized, ensuring the stability and efficiency of data flow and improving the overall business processing efficiency.

[0053] Continue to refer to Figure 4 , Figure 4 A flow 400 of a third embodiment of the data transmission method according to this disclosure is shown. The data transmission method includes the following steps: Step 401: In response to determining that the current computing task has been completed, determine the data to be transmitted.

[0054] Step 402: Determine the data buffer area for writing data from the pre-allocated buffer pool according to the data length of the data to be transmitted.

[0055] Step 403: Copy the data to be transferred to the data buffer area according to the source address of the data to be transferred in the video memory.

[0056] Steps 401-403 are basically the same as steps 301-303 in the aforementioned embodiments. For specific implementation methods, please refer to the aforementioned description of steps 301-303, which will not be repeated here.

[0057] Step 404: Obtain the local storage information and remote storage information of the data to be transmitted.

[0058] In this embodiment, after the GPU completes copying the data to be transferred to the data buffer, the execution body of the data transfer method (e.g., Figure 1 The server 105 shown reads and obtains local storage information from the local memory address mapping table, including the starting physical address of the data buffer, the data length, and the memory access key lkey. At the same time, it obtains remote storage information based on the communication configuration and the negotiation results with the node, including the remote node's memory target address, the remote access key rkey, and the target node identifier.

[0059] Step 405: Fill the local storage information, remote storage information, and data length into the corresponding fields according to the preset DTD template format to obtain the target DTD.

[0060] In this embodiment, the GPU, based on the system-defined DTD template structure, fills in the acquired local storage information, remote storage information, data length, and other parameters according to the corresponding field specifications. Specifically, the local address and lkey are filled into the local storage field, the remote address and rkey are filled into the remote storage field, and the data length is filled into the transmission length field. After encapsulation, the target DTD is obtained.

[0061] Step 406: Write the target DTD to the DTD cache and update the value of the production pointer in the DTD cache.

[0062] In this embodiment, the GPU writes the generated target DTD to the free memory unit currently pointed to by the production pointer in the DTD circular cache according to the address index. After writing, the GPU will step the production pointer forward by one valid position, i.e., point to the new free unit, according to the management rules of the circular cache, and complete the instruction submission.

[0063] Step 407: In response to the detection of new data being written to the DTD buffer, the target DTD is read and the target WQE is constructed based on the target DTD.

[0064] Step 408: Read the data to be transmitted from the data buffer according to the target WQE, and write the data to be transmitted into the memory of the remote node.

[0065] Steps 407-408 are basically the same as steps 203-204 in the aforementioned embodiments. For specific implementation methods, please refer to the aforementioned description of steps 203-204, which will not be repeated here.

[0066] from Figure 4 It can be seen from this that, with Figure 3 Compared to the corresponding embodiments, the data transmission method in this embodiment emphasizes the steps of constructing the target DTD and writing the target DTD into the DTD cache. By automatically collecting local and remote storage parameters, relying on standardized templates to encapsulate and generate DTD instructions, and then writing them into the cache and updating the production pointer, this process is completed autonomously by the GPU without CPU intervention, thereby ensuring the efficiency and orderliness of instruction flow.

[0067] Continue to refer to Figure 5 , Figure 5 A flowchart 500 of a fourth embodiment of the data transmission method according to the present disclosure is shown. The data transmission method includes the following steps: Step 501: In response to determining that the current computing task has been completed, determine the data to be transmitted.

[0068] Step 502: Determine the data buffer area for writing data from the pre-allocated buffer pool according to the data length of the data to be transmitted.

[0069] Step 503: Copy the data to be transferred to the data buffer area according to the source address of the data to be transferred in the video memory.

[0070] Step 504: Obtain the local storage information and remote storage information of the data to be transmitted.

[0071] Step 505: Fill the local storage information, remote storage information, and data length into the corresponding fields according to the preset DTD template format to obtain the target DTD.

[0072] Steps 501-505 are basically the same as steps 401-405 in the previous embodiment. For specific implementation methods, please refer to the above description of steps 401-405, which will not be repeated here.

[0073] Step 506: Read the first current value of the producer pointer and the second current value of the consumer pointer from the DTD buffer.

[0074] In this embodiment, the instruction parsing module of the DPU reads the control field of the DTD ring buffer in real time through hardware addressing to obtain the first current value of the production pointer (recording the latest instruction write position) and the second current value of the consumption pointer (recording the position of the next instruction to be read).

[0075] Step 507: Determine whether there are any free slots in the DTD cache based on the first current value and the second current value.

[0076] In this embodiment, the DPU will compare the current value of the read production pointer (first current value) with the current value of the consumption pointer (second current value) and perform boundary judgment. Based on the rules for determining whether the circular buffer is empty or full, the remaining storage capacity of the buffer is calculated.

[0077] Specifically, the relative positions of the producer and consumer pointers are used to determine the idle status. The calculation rule is: (producer pointer + total cache capacity - consumer pointer) % total cache capacity < total cache capacity - 1. It can be seen that as long as the two pointers do not overlap, or a full queue state of "producer pointer catching up with consumer pointer" has not been formed, it means that there is an idle slot. In other words, as long as the cache is not full, it is determined that there is an idle slot, and a new target DTD can be written.

[0078] Step 508: In response to determining that there is a free slot in the DTD cache, the target DTD is written into the free slot, and the value of the production pointer in the DTD cache is updated.

[0079] If a free slot is found in the DTD cache, the DPU will write the target DTD to be processed into the corresponding free storage unit. After the write operation is completed, the producer pointer will be updated forward to point to the next free location according to the circular cache management rules.

[0080] Step 509: In response to the detection of new data being written to the DTD buffer, the target DTD is read and the target WQE is constructed based on the target DTD.

[0081] Step 510: Read the data to be transmitted from the data buffer according to the target WQE, and write the data to be transmitted into the memory of the remote node.

[0082] Steps 509-510 are basically the same as steps 203-204 in the aforementioned embodiments. For specific implementation methods, please refer to the aforementioned description of steps 203-204, which will not be repeated here.

[0083] Step 511: In response to determining that the data to be transmitted has been successfully written into the memory of the remote node, update the value of the consumer pointer.

[0084] After receiving a successful data write status from the remote node, the DPU confirms that the transmission task corresponding to the current DTD has been completed. Following the circular buffer management rules, it advances the consumption pointer of the DTD buffer by one position, updates its current value, and marks the instruction as completed, allowing it to continue reading and processing the remaining DTDs to be consumed in the buffer.

[0085] This updates the consumption pointer after successful remote data writing, marks the completion of instruction processing, and releases cache slots in an orderly manner, ensuring the continuous operation of the circular cache and improving the efficiency of instruction scheduling and transmission.

[0086] from Figure 5 It can be seen from this that, with Figure 4 Compared with the corresponding embodiments, the data transmission method in this embodiment emphasizes the steps of determining the free slots in the DTD buffer and writing the target DTD into the free slots. By comparing the values ​​of the two pointers, the free state of the buffer is determined, and DTD instructions are written as needed. This can avoid data overflow, ensure the orderly storage of instructions, and thus improve the stability of instruction flow and overall processing efficiency.

[0087] Continue to refer to Figure 6 , Figure 6 A flow 600 of a fifth embodiment of the data transmission method according to the present disclosure is shown. The data transmission method includes the following steps: Step 601: In response to determining that the current computing task has been completed, determine the data to be transmitted.

[0088] Step 602: Determine the data buffer area for writing data from the pre-allocated buffer pool according to the data length of the data to be transmitted.

[0089] Step 603: Copy the data to be transferred to the data buffer area according to the source address of the data to be transferred in the video memory.

[0090] Step 604: Obtain the local storage information and remote storage information of the data to be transmitted.

[0091] Step 605: Fill the local storage information, remote storage information and data length into the corresponding fields according to the preset DTD template format to obtain the target DTD.

[0092] Step 606: Write the target DTD to the DTD cache and update the value of the production pointer in the DTD cache.

[0093] Steps 601-606 are basically the same as steps 401-406 in the previous embodiment. For specific implementation methods, please refer to the above description of steps 401-406, which will not be repeated here.

[0094] Step 607: In response to the detection that the value of the production pointer has been updated, determine that new data is written to the DTD cache.

[0095] In this embodiment, the DPU polls the production pointer of the DTD cache in real time. When it detects that the pointer value has been updated, it determines that the cache has been written with a new target DTD and then triggers the instruction reading process.

[0096] Step 608: Read the target DTD and construct the target WQE based on the resource information configured in the initialization phase and the target DTD.

[0097] After the DPU detects a new DTD write, it reads the target DTD from the buffer. It then retrieves the hardware, link, and other resource information from the system initialization configuration, and combines this information with parameters such as the local address, remote address, data length, and key from the DTD to assemble and generate the target WQE according to the specified format.

[0098] In some optional implementations of this embodiment, step 608 includes: reading the resource information configured during the initialization phase, wherein the resource information includes: queue pairs, key information, and hardware configuration information; parsing the target DTD and extracting dynamic instruction fields based on the parsing results, wherein the dynamic instruction fields include: operation type, address offset, and control identifier; and filling the resource information and dynamic instruction fields into the corresponding data fields according to the WQE data structure defined in the Remote Direct Memory Access Protocol to obtain the constructed target WQE.

[0099] In this implementation, the DPU first reads the fixed resource information preloaded during the system initialization phase from the local hardware registers and configuration cache. This information includes hardware configuration parameters such as communication queue pair number, data encryption key, hardware port, transmission bandwidth, and working mode. This type of information is globally valid and does not need to be generated repeatedly.

[0100] Then, the DPU will retrieve the target DTD to be processed in the cache, parse the content segment by segment according to the preset instruction format, and extract the real-time dynamic instruction fields: identify the operation type of this transmission, the offset between local and remote memory addresses, transmission start / stop, verification, retransmission and other control flags, and clarify the specific execution requirements of the current data transmission.

[0101] Afterwards, the DPU strictly follows the WQE standard data structure specified by the RDMA protocol and divides the corresponding storage field areas. Fixed resource information such as queue pairs, keys, and hardware configurations are filled into the static fields of the WQE. Then, dynamic instruction fields such as operation type, address offset, and control identifiers are matched and filled one by one. After the fields are verified to be correct, a target WQE with a complete structure and conforming to the protocol requirements is finally generated for issuing and executing data transmission tasks.

[0102] By reusing static resources for initialization, parsing and extracting dynamic instruction fields, and assembling WQE according to the RDMA protocol specification, the overhead of redundant configuration is reduced, and the efficiency of transmission task construction and operational reliability are improved.

[0103] Step 609: Read the data to be transmitted from the data buffer according to the target WQE, and write the data to be transmitted into the memory of the remote node.

[0104] Step 609 is basically the same as step 204 in the aforementioned embodiment. For the specific implementation method, please refer to the aforementioned description of step 204, which will not be repeated here.

[0105] from Figure 6 It can be seen from this that, with Figure 4 Compared to the corresponding embodiments, the data transmission method in this embodiment emphasizes the step of constructing the target WQE. This allows for the rapid identification of new instructions by monitoring changes in the production pointer, timely reading of the DTD, and generation of the WQE in conjunction with preset resources, ensuring the efficient startup of the transmission task and smooth and stable overall scheduling.

[0106] Continue to refer to Figure 7 , Figure 7 A flow 700 of a sixth embodiment of the data transmission method according to the present disclosure is shown. The data transmission method includes the following steps: Step 701: Determine the data to be transmitted and write the data to be transmitted into the data buffer.

[0107] Step 702: Generate a target data transmission descriptor (DTD) based on the attribute information of the data to be transmitted, and write the target DTD into the DTD buffer.

[0108] Step 703: In response to the detection of new data being written to the DTD buffer, the target DTD is read and the target WQE is constructed based on the target DTD.

[0109] Steps 701-703 are basically the same as steps 201-203 in the aforementioned embodiments. For specific implementation methods, please refer to the aforementioned description of steps 201-203, which will not be repeated here.

[0110] Step 704: Determine the target network interface from multiple physical network interfaces according to the preset scheduling strategy.

[0111] In this embodiment, the DPU invokes preset scheduling policies such as load balancing and link priority, and simultaneously collects real-time bandwidth, link status, and traffic load data for each physical network interface. Based on the policy rules, it compares and filters the data, selecting the target physical network interface suitable for this transmission task as the data forwarding exit.

[0112] Step 705: Read the data to be transmitted from the data buffer according to the target WQE, and write the data to be transmitted into the memory of the remote node through the target network interface.

[0113] The DPU reads complete data to be transmitted segment by segment from the data buffer according to the data length and address offset specified in the WQE. It then forwards the read data to the previously selected target physical network interface, encapsulates the data packet according to the RDMA protocol, and sends it outward through the physical link. After the packet reaches the remote node, it directly writes the data to the designated memory area of ​​the remote node based on parameters such as the remote address and control identifier in the WQE, without requiring the involvement of the CPUs at both ends.

[0114] from Figure 7 It can be seen from this that, with Figure 2 Compared to the corresponding embodiments, the data transmission method in this embodiment emphasizes the steps of determining the target network port and transmitting data through the target network port. This method intelligently selects the network port based on a preset strategy, rationally allocates the transmission link, and completes RDMA data direct transmission in combination with the selected network port, ensuring stable, efficient and low-latency data transmission.

[0115] Continue to refer to Figure 8 , Figure 8 A flow 800 of a seventh embodiment of the data transmission method according to the present disclosure is shown. The data transmission method includes the following steps: Step 801: Determine the data to be transmitted and write the data to be transmitted into the data buffer.

[0116] Step 802: Generate a target data transmission descriptor (DTD) based on the attribute information of the data to be transmitted, and write the target DTD into the DTD buffer.

[0117] Step 803: In response to the detection of new data being written to the DTD buffer, the target DTD is read and the target work queue element WQE is constructed based on the target DTD.

[0118] Step 804: Determine the target network interface from multiple physical network interfaces according to the preset scheduling strategy.

[0119] Steps 801-804 are basically the same as steps 701-704 in the previous embodiment. For specific implementation methods, please refer to the above description of steps 701-704, which will not be repeated here.

[0120] Step 805: Determine the target queue pair from multiple queue pairs corresponding to the target network interface according to the preset transmission strategy, and use the target queue pair as the target transmission channel.

[0121] In this embodiment, the DPU invokes preset transmission policies such as traffic priority, bandwidth allocation, and service isolation. Simultaneously, it reads the status of all queue pairs under the target network interface, including queue number, current load, connection status, permission attributes, and corresponding service type. Combining the attributes, data volume, and priority of this transmission task, it compares each pair according to the policy rules: high-priority services are matched with dedicated priority queue pairs, high-traffic tasks use high-bandwidth queue pairs, and different services are assigned independent queue pairs for isolation. Finally, the queue pairs that meet the requirements are selected as target queue pairs and bound to a dedicated channel for this RDMA transmission. Subsequent data transmission and task scheduling are then performed using this channel.

[0122] Step 806: Read the data to be transmitted from the data buffer according to the target WQE, and write the data to be transmitted into the memory of the remote node through the target transmission channel.

[0123] The DPU reads the complete data to be transmitted segment by segment from the data buffer according to the data length and address offset specified by WQE. It then encapsulates the data into a protocol-compliant message and sends it to the selected target queue for transmission. After the message reaches the remote node via the link, the data is directly written to the designated remote memory area according to the remote memory address and control instructions in WQE, without occupying the CPU of either host for data copying.

[0124] from Figure 8 It can be seen from this that, with Figure 7 Compared to the corresponding embodiments, the data transmission method in this embodiment emphasizes the step of determining the target transmission channel from the target network interface, thereby preferentially allocating queue pairs according to the transmission strategy, realizing service isolation and reasonable traffic scheduling; relying on the selected channel to complete RDMA direct transmission, the resource allocation is accurate, the transmission is orderly, congestion is reduced, and data transmission is guaranteed to be efficient, stable and low-latency.

[0125] In some optional implementations of this embodiment, the above data transmission method further includes: splitting the target DTD into multiple sub-DTDs according to a preset fragmentation strategy, and generating sub-WQEs corresponding to the sub-DTDs; and reading the data to be transmitted from the data buffer according to the target WQE and writing the data to be transmitted into the memory of the remote node, including: reading the data corresponding to the sub-WQE from the data buffer respectively, and writing the read data into the memory of the remote node.

[0126] In this implementation, the DPU loads a preset data fragmentation strategy and, based on rules such as the maximum transmission length of a single frame and message specifications, splits the complete target DTD into multiple independent sub-DTDs. Then, referring to resource configuration and sub-DTD parameters, it constructs matching sub-WQEs one by one. Next, it parses each sub-WQE sequentially, reading the corresponding fragmented data from the local data cache according to the address and data length recorded within it, and performing data verification. Finally, it transmits each fragmented data in sequence, writing it piece by piece to the specified memory area on the remote node according to the sub-WQE instructions, ultimately completing the final storage of the entire data.

[0127] By splitting instructions and tasks according to a fragmentation strategy, corresponding sub-WQEs are generated and transmitted in segments. This adapts to the single-frame transmission limit, avoids congestion caused by excessively large packets, results in smoother transmission, and ensures complete and orderly data writing, thereby improving overall transmission reliability.

[0128] Continue to refer to Figure 9 The document illustrates an embodiment of a data transmission system 900 according to the present disclosure, which includes a graphics processing unit (GPU) 901 and a data processing unit (DPU) 902, the DPU 902 including a proxy module 9021 and a remote direct memory access engine 9022.

[0129] The GPU901 is used to determine the data to be transmitted and write it to the data buffer; it also generates a target data transfer descriptor (DTD) based on the attribute information of the data to be transmitted and writes the target DTD to the DTD buffer. Multiple streaming multiprocessors (SMs) of the GPU execute CUDA kernel functions to generate the data transfer instruction (DTD) and the data to be transmitted.

[0130] Shared memory consists of two core modules: (1) DTD buffer: adopts a circular queue structure to receive and buffer the DTD generated by the CUDA Kernel as an intermediate buffer for instruction transmission; (2) Data buffer: stores the raw data to be transmitted for subsequent reading by the RDMA engine.

[0131] The proxy module 9021 is used to read the target DTD in response to the detection of new data being written to the DTD buffer, and to construct a target work queue element (WQE) based on the target DTD. In other words, the proxy module receives the DTD instructions from the GPU, parses them, generates a work queue entry (WQE) conforming to the RDMA protocol specification, and sends it to the remote direct memory access engine (RDMAEngine); simultaneously, it receives the completion queue entry (CQE) returned by the RDMA Engine, providing feedback on the transmission status.

[0132] The Remote Direct Memory Access Engine 9022 is used to read data to be transferred from the data buffer according to the target WQE and write the data to be transferred into the memory of the remote node. The RDMA Engine receives the WQE issued by the Proxy module, reads the data to be transferred from the Data Buffer of the GPU shared memory, and writes the data directly into the memory of the remote node through the remote network interface card (remote NIC), without the CPU participating in the data copying process.

[0133] It should be noted that the aforementioned DPU can also be implemented by a smart network card, and this embodiment does not specifically limit this.

[0134] In some optional implementations of this embodiment, the data transmission system 900 further includes a central processing unit (CPU) 903, which is used to initiate the execution of kernel functions on the GPU 901 so that the GPU can perform computing tasks.

[0135] The CPU can send initialization instructions (init) to the DPU and GPU respectively, enabling the DPU and GPU to complete hardware configuration and resource initialization, thus establishing the basic environment for subsequent data transfer. The CPU will then notify the GPU to start executing computational tasks, that is, to have multiple SMs of the GPU execute the CUDA Kernel, thereby generating data transfer instructions (DTD) and data to be transferred.

[0136] The initialization operations performed by the CPU may include: (1) The CPU requests data buffer and corresponding DTD buffer space in the GPU memory and registers the space address with the DPU so that the DPU's RDMA engine and Proxy module can access the data buffer and DTD buffer in the GPU memory respectively. (2) The CPU creates the corresponding Proxy instance in the DPU and configures the Proxy instance; (3) The CPU creates RDMA resources such as QP and CQ on the DPU; (4) The rank CPUs participating in the set communication communicate with each other (through traditional socket communication, as long as information can be exchanged), collect the data buffers of all nodes and the rkey (remote key) registered to RDMA, and other information required for node RDMA communication, and configure it to the DPU proxy. (5) The CPU launches the CUDA kernel on the GPU and begins data processing and transmission.

[0137] Further reference Figure 10 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of a data transmission device, which is similar to... Figure 2 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0138] like Figure 10As shown, the data transmission device 1000 of this embodiment includes: a data writing unit 1001, a DTD writing unit 1002, a WQE generation unit 1003, and a data transmission unit 1004. The data writing unit 1001 is configured to determine the data to be transmitted and write it into a data buffer; the DTD writing unit 1002 is configured to generate a target data transmission descriptor (DTD) based on the attribute information of the data to be transmitted and write the target DTD into a DTD buffer; the WQE generation unit 1003 is configured to read the target DTD in response to detecting new data written to the DTD buffer and construct a target work queue element (WQE) based on the target DTD; the data transmission unit 1004 is configured to read the data to be transmitted from the data buffer based on the target WQE and write it into the memory of a remote node.

[0139] In this embodiment, the specific processing of the data writing unit 1001, DTD writing unit 1002, WQE generation unit 1003, and data transmission unit 1004 in the data transmission device 1000, and the resulting technical effects, can be found in references to [reference needed]. Figure 2 The relevant descriptions of steps 201-204 in the corresponding embodiments will not be repeated here.

[0140] In some optional implementations of this embodiment, the data writing unit 1001 is further configured to: determine the data to be transmitted in response to determining that the current computing task has been completed; determine the data buffer area for writing data from the pre-allocated cache pool according to the data length of the data to be transmitted; and copy the data to be transmitted to the data buffer area according to the source address of the data to be transmitted in the video memory.

[0141] In some optional implementations of this embodiment, the DTD writing unit 1002 is further configured to: obtain local storage information and remote storage information of the data to be transmitted; fill the local storage information, remote storage information and data length into the corresponding fields according to the preset DTD template format to obtain the target DTD; write the target DTD into the DTD cache and update the value of the production pointer in the DTD cache.

[0142] In some optional implementations of this embodiment, the data transmission device 1000 further includes: a reading unit configured to read a first current value of the production pointer and a second current value of the consumption pointer in the DTD cache; a determining unit configured to determine whether there is a free slot in the DTD cache based on the first current value and the second current value; and a DTD writing unit 1002 further configured to: write the target DTD into the free slot in response to determining that there is a free slot in the DTD cache.

[0143] In some optional implementations of this embodiment, the WQE generation unit 1003 includes: a determination subunit configured to determine that new data is written to the DTD cache in response to detecting that the value of the production pointer has been updated; and a construction subunit configured to read the target DTD and construct the target WQE according to the resource information configured in the initialization phase and the target DTD.

[0144] In some optional implementations of this embodiment, the construction subunit is further configured to: read the resource information configured during the initialization phase, wherein the resource information includes: queue pairs, key information, and hardware configuration information; parse the target DTD, extract the dynamic instruction field based on the parsing result, wherein the dynamic instruction field includes: operation type, address offset, and control identifier; and fill the resource information and dynamic instruction field into the corresponding data fields according to the WQE data structure defined in the Remote Direct Memory Access Protocol to obtain the constructed target WQE.

[0145] In some optional implementations of this embodiment, the data transmission device 1000 further includes: a network port determination unit, configured to determine a target network port from multiple physical network ports according to a preset scheduling strategy; and the data transmission unit 1004 includes: a data writing subunit, configured to write the data to be transmitted into the memory of a remote node through the target network port.

[0146] In some optional implementations of this embodiment, the data transmission device 1000 further includes: a channel determination unit configured to determine a target queue pair from multiple queue pairs corresponding to the target network port according to a preset transmission strategy, and to use the target queue pair as the target transmission channel; and a data writing subunit further configured to write the data to be transmitted into the memory of the remote node through the target transmission channel.

[0147] In some optional implementations of this embodiment, the data transmission device 1000 further includes: a sharding unit configured to split the target DTD into multiple sub-DTDs according to a preset sharding strategy and generate sub-WQEs corresponding to the sub-DTDs; and the data transmission unit 1004 further configured to: read the data corresponding to the sub-WQEs from the data buffer respectively and write the read data into the memory of the remote node.

[0148] In some optional implementations of this embodiment, the data transmission device 1000 further includes a pointer update unit configured to update the value of the consumer pointer in response to determining that the data to be transmitted has been successfully written into the memory of the remote node.

[0149] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0150] Figure 11A schematic block diagram of an example electronic device 1100 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0151] Figure 11 A schematic block diagram of an example electronic device 1100 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0152] like Figure 11 As shown, device 1100 includes a computing unit 1101, which can perform various appropriate actions and processes according to a computer program stored in read-only memory (ROM) 1102 or a computer program loaded into random access memory (RAM) 1103 from storage unit 1108. The RAM 1103 may also store various programs and data required for the operation of device 1100. The computing unit 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Input / output (I / O) interface 1105 is also connected to bus 1104.

[0153] Multiple components in device 1100 are connected to I / O interface 1105, including: input unit 1106, such as keyboard, mouse, etc.; output unit 1107, such as various types of monitors, speakers, etc.; storage unit 1108, such as disk, optical disk, etc.; and communication unit 1109, such as network card, modem, wireless transceiver, etc. Communication unit 1109 allows device 1100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0154] The computing unit 1101 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1101 performs the various methods and processes described above, such as data transfer methods. For example, in some embodiments, the data transfer method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1108. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1100 via ROM 1102 and / or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by the computing unit 1101, one or more steps of the data transfer method described above may be performed. Alternatively, in other embodiments, the computing unit 1101 may be configured to perform the data transfer method by any other suitable means (e.g., by means of firmware).

[0155] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0156] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0157] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0158] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0159] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0160] Cloud computing refers to a technological system that enables access to elastic and scalable shared physical or virtual resources via a network. These resources can include servers, operating systems, networks, software, and storage devices, and can be deployed and managed in an on-demand, self-service manner. Cloud computing technology can provide efficient and powerful data processing capabilities for applications such as artificial intelligence and blockchain, as well as for model training.

[0161] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0162] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0163] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data transmission method, comprising: Determine the data to be transmitted and write the data to be transmitted into the data buffer area; A target data transmission descriptor (DTD) is generated based on the attribute information of the data to be transmitted, and the target DTD is written into the DTD buffer. In response to detecting that new data has been written to the DTD buffer, the target DTD is read, and a target work queue element (WQE) is constructed based on the target DTD; According to the target WQE, the data to be transmitted is read from the data buffer and written into the memory of the remote node.

2. The method according to claim 1, wherein, The step of determining the data to be transmitted and writing the data to be transmitted into the data buffer includes: In response to determining that the current computation task has been completed, determine the data to be transmitted; The data buffer area for writing data is determined from the pre-allocated buffer pool based on the data length of the data to be transmitted; The data to be transferred is copied to the data cache area according to the source address of the data to be transferred in the video memory.

3. The method according to claim 2, wherein, The step of generating a target data transmission descriptor (DTD) based on the attribute information of the data to be transmitted, and writing the target DTD into the DTD buffer, includes: Obtain the local storage information and remote storage information of the data to be transmitted; The target DTD is obtained by filling the local storage information, the remote storage information, and the data length into the corresponding fields according to the preset DTD template format. Write the target DTD into the DTD cache and update the value of the production pointer in the DTD cache.

4. The method according to claim 3, wherein, Also includes: Read the first current value of the producer pointer and the second current value of the consumer pointer from the DTD buffer; Determine whether there are any free slots in the DTD cache area based on the first current value and the second current value; and The step of writing the target DTD into the DTD cache includes: In response to determining that there is a free slot in the DTD cache, the target DTD is written into the free slot.

5. The method according to claim 3, wherein, The step of responding to the detection of new data being written to the DTD buffer, reading the target DTD, and constructing a target work queue element (WQE) based on the target DTD includes: In response to the detection that the value of the production pointer has been updated, it is determined that new data is written to the DTD cache; Read the target DTD and construct the target WQE based on the resource information configured in the initialization phase and the target DTD.

6. The method according to claim 5, wherein, The step of constructing the target WQE based on the resource information configured during the initialization phase and the target DTD includes: Read the resource information configured during the initialization phase, wherein the resource information includes: queue pairs, key information, and hardware configuration information; The target DTD is parsed, and dynamic instruction fields are extracted based on the parsing results. The dynamic instruction fields include: operation type, address offset, and control identifier. According to the WQE data structure defined in the Remote Direct Memory Access Protocol, the resource information and the dynamic instruction field are filled into the corresponding data fields to obtain the constructed target WQE.

7. The method according to claim 1, wherein, Also includes: The target network interface is determined from multiple physical network interfaces according to the preset scheduling strategy; as well as The step of writing the data to be transmitted into the memory of the remote node includes: The data to be transmitted is written into the memory of the remote node through the target network port.

8. The method according to claim 7, wherein, Also includes: According to the preset transmission strategy, a target queue pair is determined from multiple queue pairs corresponding to the target network interface, and the target queue pair is used as the target transmission channel; as well as The step of writing the data to be transmitted into the memory of the remote node through the target network port includes: The data to be transmitted is written into the memory of the remote node through the target transmission channel.

9. The method according to claim 1, wherein, Also includes: The target DTD is split into multiple sub-DTDs according to a preset sharding strategy, and sub-WQEs corresponding to the sub-DTDs are generated. as well as The step of reading the data to be transmitted from the data buffer according to the target WQE and writing the data to be transmitted into the memory of the remote node includes: The data corresponding to the sub-WQE is read from the data cache area respectively, and the read data is written into the memory of the remote node.

10. The method according to claim 4, wherein, Also includes: In response to determining that the data to be transmitted has been successfully written into the memory of the remote node, the value of the consumer pointer is updated.

11. A data transmission system, comprising: Graphics Processing Unit (GPU) and Data Processing Unit (DPU), wherein the DPU includes: an agent module and a remote direct memory access engine. The GPU is used to: determine the data to be transmitted and write the data to be transmitted into a data buffer; generate a target data transmission descriptor (DTD) based on the attribute information of the data to be transmitted and write the target DTD into a DTD buffer; The proxy module is used to read the target DTD and construct a target work queue element (WQE) based on the target DTD in response to detecting that new data has been written to the DTD buffer. The remote direct memory access engine is used to read the data to be transmitted from the data cache according to the target WQE, and write the data to be transmitted into the memory of the remote node.

12. The system according to claim 11, wherein, It also includes: Central Processing Unit (CPU), The CPU is used to initiate and execute kernel functions on the GPU, so that the GPU performs computational tasks.

13. A data transmission apparatus, comprising: The data writing unit is configured to determine the data to be transmitted and write the data to be transmitted into the data buffer. The DTD writing unit is configured to generate a target data transmission descriptor DTD based on the attribute information of the data to be transmitted, and write the target DTD into the DTD buffer. The WQE generation unit is configured to read the target DTD and construct a target work queue element WQE based on the target DTD in response to detecting that new data has been written to the DTD buffer. The data transmission unit is configured to read the data to be transmitted from the data buffer according to the target WQE and write the data to be transmitted into the memory of the remote node.

14. An electronic device comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method of any one of claims 1-10.

15. A non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-10.

16. A computer program product comprising a computer program that, when executed by a processor, implements the method according to any one of claims 1-10.

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