Integrated circuit and method of manufacturing the same

Abstract

An integrated circuit includes a trench isolation structure between two semiconductor fins. A first source / drain region of a first transistor is formed in a first semiconductor fin. A second source / drain region of a second transistor is formed in a second semiconductor fin adjacent to the first source / drain region. A first source / drain contact is formed over the first source / drain region including a single metal layer. A second source / drain contact is formed over the second source / drain region and includes a stack of two metal layers. An upper metal layer of the second source / drain contact extends laterally beyond an edge of a lower metal layer of the second source / drain contact and is located over the trench isolation structure. Embodiments of the present application also relate to methods of manufacturing an integrated circuit.

Description

Technical Field

[0001] This application provides an integrated circuit and a method for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advancements in integrated circuit materials and design have yielded several generations of integrated circuits, each with smaller and more complex circuits than the previous one. In the development of integrated circuits, functional density (i.e., the number of interconnect devices per chip region) has typically increased, while geometry (i.e., the smallest component (or wire) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. This shrinkage also increases the complexity of handling and manufacturing integrated circuits. Summary of the Invention

[0003] One aspect of this application provides a method for manufacturing an integrated circuit, comprising: forming a first semiconductor fin extending along a first lateral direction; forming a second semiconductor fin extending along the first lateral direction; depositing a trench isolation structure between the first semiconductor fin and the second semiconductor fin; depositing a gate metal extending along a second lateral direction intersecting the first lateral direction across the first semiconductor fin, the second semiconductor fin, and the trench isolation structure; growing a first source / drain region of a first transistor located on the first semiconductor fin and extending partially above the first trench isolation structure; growing a second source / drain region of a second transistor located on the second semiconductor fin and extending partially above the trench isolation structure; forming a first portion of a first source / drain contact on the first source / drain region and a second source / drain contact on the second source / drain region by depositing a first metal layer; and forming a second portion of the first source / drain contact located on the top surface of the first portion and extending laterally above the trench isolation structure beyond the edge of the first portion by depositing a second metal layer.

[0004] Another aspect of this application provides a method for manufacturing an integrated circuit, comprising: depositing a trench isolation structure between a first semiconductor fin and a second semiconductor fin; growing a first source / drain region of a first transistor in a first trench in the first semiconductor fin; growing a second source / drain region of the first transistor in a second trench in the first semiconductor fin; depositing a first source / drain contact on the first source / drain region of the first transistor; depositing a second source / drain contact on the second source / drain region of the first transistor, wherein the first source / drain contact has a greater height than the second source / drain contact; depositing an interlayer dielectric layer above the first transistor; forming a first conductive via located in the interlayer dielectric region and contacting the top surface of the first source / drain contact; and forming a second conductive via located in the interlayer dielectric region and contacting the top surface of the second source / drain contact, wherein the height of the first conductive via is less than the height of the second conductive via.

[0005] Another aspect of this application provides an integrated circuit, including:

[0006] The first active region extends along the first lateral direction;

[0007] The second active region extends along the first lateral direction;

[0008] The trench isolation structure is located between the first active region and the second active region;

[0009] A first transistor, the first transistor comprising: a first source / drain region located in a first active region and partially suspended above the trench isolation structure; and a first source / drain contact located on the first source / drain region and comprising a first metal structure and a second metal structure, the second metal structure covering at least a portion of the top surface of the first metal structure and extending beyond the lateral edge of the first portion;

[0010] The second transistor includes: a second source / drain region located in the second active region and partially suspended above the trench isolation structure adjacent to the first source / drain region; and a second source / drain contact located on the second source / drain region.

[0011] An interlayer dielectric layer is located on the first source / drain contact and the second source / drain contact;

[0012] The first conductive via is located in the interlayer dielectric layer and contacts the top surface of the second metal structure of the first source / drain contact.

[0013] The second conductive via is located in the interlayer dielectric layer and contacts the top surface of the second source / drain contact, wherein the height of the second conductive via is greater than the height of the first conductive via. Attached Figure Description

[0014] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0015] Figures 1-20 These are cross-sectional views, perspective views, and top views of integrated circuits at various processing stages according to some embodiments;

[0016] Figure 21 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments;

[0017] Figure 22 This is a flowchart of a method for manufacturing an integrated circuit according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0020] Terms indicating relative degree, such as “about” or “basically”, should be interpreted in accordance with the understanding of a person skilled in the art based on current technical specifications.

[0021] This disclosure generally relates to semiconductor devices, and more specifically, to field-effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured devices. Examples of nanostructured devices include gate-all-around (GAA) devices, nanosheet FETs (NSFETs), nanowire FETs (NWFETs), and the like. In advanced technology nodes, the active region spacing between nanostructured devices is typically uniform, the source / drain epitaxial structure is symmetrical, and a metal gate surrounds all four sides of the nanostructure (e.g., a nanosheet).

[0022] GAA transistor structures can be patterned using any suitable method. For example, one or more photolithography processes, including dual-patterning or multi-patterning processes, can be used to pattern these structures. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches compared to those achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0023] According to some embodiments, the active region is implemented in conjunction with a semiconductor fin extending along a first lateral direction (e.g., the X direction). A trench isolation structure extends along the first lateral direction, beside adjacent semiconductor fins, and between adjacent semiconductor fins. A gate region extends along a second lateral direction (e.g., the Y direction) across the semiconductor fins and the trench isolation structure. Source / drain regions of transistors are formed in the semiconductor fins, wherein channels of the stacked transistors extend along the X direction between adjacent source / drain regions. The stacked channels are formed by the semiconductor fins and are located at the intersection of the gate region and the active region. At the layout level, source / drain contact metal elements extend along the second lateral direction. Source / drain contact dividers extend above the trench isolation structure along the first lateral direction. At the intersection of the source / drain contact dividers and the source / drain contact regions, source / drain contact metal elements are removed or not formed, so that the source / drain contacts of adjacent transistors can be electrically isolated from each other.

[0024] Embodiments of this disclosure provide source / drain contacts capable of continuously reducing active region spacing and trench isolation structure dimensions. In some embodiments, the source / drain contact partition does not overlap with the semiconductor fins but is located entirely above the trench isolation structure. Embodiments of this disclosure can use a stack of two source / drain contact metals to form the selected source / drain contact. More specifically, when adjacent source / drain regions of two transistors formed in different semiconductor fins need to be electrically isolated from each other and both need to be contacted through their respective conductive vias, one source / drain contact includes a stack of two metals, while the other includes only one source / drain contact metal. In the stack of two source / drain contact metals, the edge of the higher metal overlaps with that of the lower metal, such that the higher metal is closer to the source / drain contact of the adjacent transistor on the other side of the trench isolation structure. This layout and structure can further reduce the active region spacing, increase the density of transistor formation, better cover the source / drain silicide through the source / drain contact regions, reduce time-varying dielectric breakdown, and improve overall device performance. Embodiments of this disclosure also provide integrated circuits with better functionality and higher wafer yield.

[0025] While the accompanying drawings and description primarily focus on examples of nanostructured transistors in which the transistors are stacked components including channels, the principles of this disclosure extend to other types of transistors. The principles of this disclosure extend to MOS transistors, FinFET transistors, and other types of transistors.

[0026] Figures 1-17 These are cross-sectional views, perspective views, and top views of an integrated circuit 100 manufactured according to some embodiments of the present disclosure. The manufacturing process produces multiple transistors 101, which will be described in more detail below.

[0027] Figure 1 This is a cross-sectional view of integrated circuit 100 in an intermediate stage of processing. Integrated circuit 100 includes a substrate 102. Substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., doped with P-type or N-type dopants) or undoped. The semiconductor material of substrate 102 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide indium phosphide; or combinations thereof. Other substrates may be used, such as single-layer substrates, multilayer substrates, or gradient substrates.

[0028] Integrated circuit 100 includes a semiconductor stack 103, which includes a plurality of alternating semiconductor layers 104 and sacrificial semiconductor layers 106. Figure 1In the example, stack 103 includes three semiconductor layers 104 and three sacrificial semiconductor layers 106. However, in practice, different numbers of semiconductor layers 104 and sacrificial semiconductor layers 106 may be used without departing from the scope of this disclosure.

[0029] As will be further elaborated below, semiconductor layer 104 will be patterned to form channels for the stacking of multiple transistors. As will be elaborated further below, sacrificial semiconductor layer 106 will eventually be completely removed and used to form gate metal and other structures around the semiconductor nanostructure.

[0030] In some embodiments, the semiconductor layer 104 can be formed using a first semiconductor material, such as silicon or silicon carbide, and the sacrificial semiconductor layer 106 can be formed using a second semiconductor material, such as silicon or germanium. Each layer of the multilayer stack 103 can be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), and molecular beam epitaxy (MBE).

[0031] Due to the high etch selectivity between the materials of semiconductor layer 104 and sacrificial semiconductor layer 106, the sacrificial semiconductor layer 106 of the second semiconductor material can be removed without significantly etching the semiconductor layer 104 of the first semiconductor material, thereby allowing the semiconductor layer 104 to be released to form the channel region of the stack of transistors, as will be explained in more detail below.

[0032] In one example, semiconductor layer 104 is silicon, and sacrificial semiconductor layer 106 is silicon-germanium. In some embodiments, sacrificial semiconductor layer 106 has a germanium concentration between 10% and 50%, although other concentrations may be used without exceeding the scope of this disclosure. This allows sacrificial semiconductor layer 106 to have selective etchability relative to semiconductor layer 104. Other materials and concentrations may be used without exceeding the scope of this disclosure.

[0033] Figure 2A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 2B It is based on some embodiments of the state Figure 2A The image shows a top view of the integrated circuit 100 in the processing stage. Figure 2A The cross-sectional view is along Figure 2B It was cut by the cutting line 2A.

[0034] exist Figure 2AIn this context, multiple semiconductor fins 108a-108c have been formed from the stack 103. In the following discussion, some reference numerals include the suffixes "a", "b", or "c". The suffixes may be omitted when the reference is not specific to a particular individual structure. For example, when referring to each of the semiconductor fins in general, semiconductor fins 108a-108c may be simply referred to as semiconductor fin 108.

[0035] Semiconductor fins 108 are formed by forming trenches 110 in the stack 103 and the substrate 102. Although Figure 1 Not shown, but first a hard mask layer is formed on stack 103 and patterned thereon. Trench 110 is formed by an anisotropic etching process, which etches downwards in the presence of the patterned hard mask. The etching process defines semiconductor fins 108 by forming trench 110 through sacrificial semiconductor layer 106, semiconductor layer 104, and substrate 102. Semiconductor fins 108 extend along the X direction and are spaced apart from each other along the Y direction by the trench 110.

[0036] Each semiconductor fin 108 corresponds to an active region or an active region of the integrated circuit 100. Each active region corresponds to the location of the source / drain and channel regions of a transistor. Semiconductor fin 108a corresponds to a first active region. Semiconductor fin 108b corresponds to a second active region. Semiconductor fin 108c corresponds to a third active region. In some embodiments, the substrate 102 of each semiconductor fin corresponds to a doped well region.

[0037] exist Figure 2A and Figure 2B In this process, a shallow trench isolation structure 112 is formed by depositing dielectric material in the trenches 110 located between the fins 108. Figure 2A The shallow trench isolation structure 112 is shown as a single layer of dielectric material. However, in practice, multiple dielectric layers can be used to form the trench isolation structure 112. The dielectric layers can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable deposition processes. In an exemplary embodiment, the dielectric material of the trench isolation structure 112 includes silicon oxide. However, the dielectric material may include SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure.

[0038] After the dielectric material of the trench isolation structure 112 is deposited, an etch-back process is performed to recess the top of the shallow trench isolation structure 112 below the lowest sacrificial semiconductor layer 106. This results in the top surface of the shallow trench isolation structure 112 being lower than the bottom surface of the lowest sacrificial semiconductor layer 106 of each fin. Other processes can be used to form the shallow trench isolation structure 112 without departing from the scope of this disclosure. Each trench isolation structure 112 extends along the X direction, adjacent to and between two adjacent semiconductor fins 108.

[0039] In some embodiments, the trench isolation structure 112 comprises SiO2, an oxide formed from tetraethyl orthosilicate, or other suitable dielectric material. In some embodiments, the trench isolation structure 112 has a depth between 50 nm and 100 nm.

[0040] Figure 3A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 3B Is in Figure 3A The image shows a top view of the integrated circuit 100 in the processing stage. Figure 3A The cross-sectional view is along Figure 3B It was cut by the cutting line 3A.

[0041] exist Figure 3A and Figure 3B In this circuit, a sacrificial gate structure 114 is formed above the fin 108. Each sacrificial gate structure 114 extends along the Y direction, spanning the semiconductor fin 108 and the trench isolation structure 112. The layout of the sacrificial gate structure 114 corresponds to the layout of the gate metal or gate structure of the transistor. Specifically, the sacrificial gate structure 114 will eventually be replaced by the gate metal. As will be explained in more detail below, according to the circuit layout of the integrated circuit 100, the gate metal will be segmented at selected locations between the semiconductor fins 108 using an efficient process to electrically isolate the gate metals of adjacent transistors. The sacrificial gate structure 114 corresponds to its respective gate metal layout location G1-G3.

[0042] The sacrificial gate structure 114 includes a dielectric layer 116. In an exemplary embodiment, the dielectric layer 116 comprises silicon oxide. However, alternatively, the dielectric layer 116 may comprise SiN, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure. In some embodiments, the dielectric layer 116 has a low-k dielectric material. The dielectric layer 116 may be deposited by CVD, ALD, or PVD.

[0043] The sacrificial gate structure includes a sacrificial gate layer 118 located on the dielectric layer 116. The sacrificial gate layer 118 may include a material with high etch selectivity relative to the trench isolation structure 112. In an exemplary embodiment, the sacrificial gate layer 118 includes polysilicon. However, the sacrificial gate layer 118 may be a conductive, semi-conductive, or non-conductive material, and may be or include amorphous silicon, polysilicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The sacrificial gate layer 118 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material.

[0044] In some embodiments, the sacrificial gate structure 114 includes a dielectric layer on the sacrificial gate layer 118. In an exemplary embodiment, the dielectric layer includes SiN. However, alternatively, the dielectric layer may include SiO, SiCN, SiOC, SiOCN, or other dielectric materials without departing from the scope of this disclosure. The dielectric layer may be deposited by CVD, ALD, or PVD.

[0045] exist Figure 3A and Figure 3B In this embodiment, a gate spacer layer 120 is formed on the sidewalls of the sacrificial gate structure 114. Specifically, the gate spacer layer 120 is formed on the sidewalls of the dielectric layer 116 and the sacrificial gate layer 118. The gate spacer layer 120 is also formed on the top surface of the sacrificial gate structure 114, the top semiconductor layer 104 of each semiconductor fin 108, and other exposed surfaces. The gate spacer layer 120 can be formed by PVD, CVD, ALD, or other suitable deposition processes. In the specific example shown herein, the gate spacer layer 120 comprises SiOCN. Alternatively, the gate spacer layer 120 may comprise one or more of SiO, SiN, SiON, SiCN, SiOC, or other suitable dielectric materials. In some embodiments, the gate spacer layer 120 has a width between 2 nm and 8 nm, although other thicknesses may be used without departing from the scope of this disclosure.

[0046] exist Figure 3A and Figure 3B In this process, an etching process is performed to pattern the gate spacer layer 120. The etching process includes an anisotropic etching process that etches in a downward direction. The anisotropic etching process removes the gate spacer layer 120 from the horizontal surface of the gate spacer 120 with a smaller vertical thickness. After the gate spacer layer is patterned, the vertically thicker portion of the gate spacer layer 120 remains on the sidewall of the sacrificial gate structure 114.

[0047] like Figure 3BAs can be seen in the top view, after the gate spacer layer 120 is patterned, the dielectric structure 121 remains on the top surface of the trench isolation structure 112 as a residue of the gate spacer layer 120. As will be explained in more detail below, these dielectric structures 121 will suppress the lateral growth of the lower portion of the source / drain regions.

[0048] Figure 4A This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 4B Is in Figure 4A The image shows a top view of the integrated circuit 100 in the processing stage. Figure 4A The cross-sectional view is along Figure 4B It was cut by the cutting line 4A.

[0049] exist Figure 4A and Figure 4B In some embodiments, source / drain trenches 124 are formed. After patterning the gate spacer layer 120, one or more etching processes are performed to form the source / drain trenches 124 in the fin 108. Forming the source / drain trenches 124 includes etching through each of the semiconductor layers 104, each of the sacrificial semiconductor layers 106, and a portion of the substrate 102. Therefore, the removal operation includes suitable etching operations to remove material from the semiconductor layers 104, the sacrificial semiconductor layers 106, and the substrate 102. Etching processes may include reactive ion etching (RIE), neutral beam etching (NBE), atomic layer etching (ALE), etc.

[0050] The formation of the source / drain trench 124 results in the formation of a stack 126 of channel 105. Specifically, after the formation of the source / drain trench 124, the remaining portion of the semiconductor layer 104 now corresponds to the channel 105 of the transistor stack. The formation of the source / drain trench 124 results in the formation of a plurality of sacrificial semiconductor nanostructures 107 by a sacrificial semiconductor layer 106. The substrate 102 is exposed at the bottom of each source / drain trench 124. The stack 126 of each channel 105 corresponds to the channel of the stack of a single transistor, as will be explained in more detail below.

[0051] Semiconductor fin 108a includes stacked channels 105a and sacrificial semiconductor nanostructures 107a. Semiconductor fin 108b includes stacked channels 105b (not shown) and sacrificial semiconductor nanostructures 107b (not shown). Semiconductor fin 108c includes stacked channels 105c (not shown) and sacrificial semiconductor nanostructures 107c (not shown).

[0052] Figure 5 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 5In this process, a selective etching process is performed to recess the exposed ends of the sacrificial semiconductor nanostructure 107 while substantially leaving the channel 105 unetched. More specifically, recesses are formed in the ends of the sacrificial semiconductor nanostructure 107 relative to adjacent channels 105. These recesses can be formed by performing an etching process that selectively etches the material of the sacrificial semiconductor nanostructure 107 relative to the materials of the channel 105 and the substrate 102.

[0053] exist Figure 5 An internal spacer 130 is formed in the recess. The internal spacer 130 is formed by depositing a dielectric layer in a conformal deposition process on the exposed surfaces of the channel 105, the gate spacer layer 120, the sacrificial semiconductor nanostructure 107, and the substrate 102. Most notably, the dielectric layer fills the recess. The dielectric layer may include SiCN, SiOCN, SiON, SiN, or other suitable dielectric materials. The dielectric layer can be formed by suitable deposition methods, such as CVD, ALD, PVD, or other deposition processes.

[0054] The internal spacer 130 is formed by performing an anisotropic etching process that etches downwards. During the anisotropic etching process, the gate spacer layer 120 and the sacrificial gate structure 114 are used as a mask. The dielectric layer is removed from all locations exposed through the mask. As a result, the dielectric layer is removed from the trench 124. The portion of the dielectric layer remaining in the recess corresponds to the internal spacer 130. The internal spacer 130 contacts the ends of the sacrificial semiconductor nanostructure 107 and the channel 105. As will be explained in more detail below, the internal spacer 130 separates the gate metal from the source / drain.

[0055] Figure 6A and Figure 6B This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 6C Is in Figure 6A and Figure 6B The image shows a top view of the integrated circuit 100 in the processing stage. Figure 6A and Figure 6B The cross-sectional views are taken along cut lines 6A and 6B, respectively. Cut line 6A cuts through a portion of semiconductor fin 108a. Cut line 6B cuts along the Y direction through each of semiconductor fins 108a-108c, and more specifically, through the gate metal 148 of the gate layout G2, as will be described in more detail below. The source / drain region layout along the Y direction is... Figure 7 This is shown more clearly in the perspective view, as described further below.

[0056] exist Figures 6A-6CIn this embodiment, a bottom semiconductor layer 132 is formed on the substrate 102 and each source / drain trench 124. In some embodiments, the bottom semiconductor layer 132 comprises an intrinsic semiconductor material. In some embodiments, the semiconductor material of the semiconductor layer 132 is the same as the semiconductor material of the substrate 102.

[0057] exist Figures 6A-6C In this embodiment, an interposer 131 is formed at the bottom of each source / drain trench 124. The interposer 131 is formed on the semiconductor substrate 102 exposed at the bottom of each source / drain trench 124. In some embodiments, the interposer comprises an intrinsic (undoped) semiconductor material, such as undoped silicon, undoped silicon germanium, or other undoped semiconductor materials. In some embodiments, the interposer comprises a dielectric material, such as SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. In some embodiments, the interposer 131 comprises a combination of an intrinsic semiconductor layer and a dielectric layer situated on the intrinsic semiconductor layer.

[0058] exist Figure 6A In some embodiments, the interposer 131 includes a bottom semiconductor layer 132 and a bottom dielectric layer 134 situated on the bottom semiconductor layer 132. The bottom semiconductor layer 132 includes an intrinsic (undoped) semiconductor material, such as undoped silicon, undoped silicon germanium, or other undoped semiconductor materials. The bottom dielectric structure 134 may include SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The bottom dielectric structure 134 can be formed by ALD, CVD, or PVD, followed by a selected patterning process. The bottom dielectric structure 134 helps prevent leakage current between the source / drain regions 136 and the bottom semiconductor layer 132. In some embodiments, the bottom dielectric structure 134 has a thickness between 2 nm and 8 nm.

[0059] exist Figures 6A-6C In some embodiments, source / drain regions 136 are formed in the source / drain trench 124. The source / drain regions 136 are epitaxially grown from the channel 105. The source / drain regions 136 grow on the exposed portion of the fin 108 and contact the channel 105. For each stack 126 of the channel 105, there are two source / drain regions 136. Some stacks 126 of the channel 105 may share source / drain regions 136 with stacks 126 of adjacent channels 105 along the X direction.

[0060] Source / drain regions 136a are formed in semiconductor fin 108a. A channel 105a of each stack extends along the X direction between two adjacent source / drain regions 136a, as shown below. Figure 6AThe most easily visible part is the semiconductor fin 108b. Source / drain regions 136b are formed in semiconductor fin 108b. A channel 105b of each stack extends along the X-direction between two adjacent source / drain regions 136b. Source / drain regions 136c are formed in semiconductor fin 108c. A channel 105c of each stack extends along the X-direction between two adjacent source / drain regions 136c. Source / drain regions 136d are formed in semiconductor fin 108d. A channel 105d of each stack extends along the X-direction between two adjacent source / drain regions 136d.

[0061] The source / drain region 136 may comprise any acceptable semiconductor material, such as materials suitable for N-type or P-type devices. For N-type regions, in some embodiments, the source / drain region 136 comprises a material that induces tensile strain in the channel region, such as silicon, SiC, SiCP, SiP, etc. For P-type transistors, according to some embodiments, the source / drain region 136 comprises a material that induces compressive strain in the channel region, such as SiGe, SiGeB, Ge, GeSn, etc. The source / drain region 136 may have a surface that protrudes from the corresponding surface of the fin and may have facets. In some embodiments, adjacent source / drain regions 136 may be merged, thereby forming a single source / drain region 136 over two adjacent fins 108.

[0062] In some embodiments, during the formation of the source / drain region 136, an in-situ doping process can be performed to implant N-type or P-type dopant into the source / drain region 136, depending on the conductivity type of the formed transistor or region. The N-type dopant may include phosphorus, arsenic, antimony, or other suitable N-type dopant types. The P-type dopant may include boron, gallium, indium, or other suitable P-type dopant types. The source / drain region 136 may undergo an annealing process after dopant implantation. The source / drain region 136 may have a conductivity of approximately 10... 19 cm -3 With about 10 21 cm -3 The concentration of impurities between them.

[0063] Although Figure 6A and Figure 6B Each source / drain region 136 is shown as a single epitaxial layer, but in practice, in some embodiments, each source / drain region 136 includes multiple epitaxial layers. A first epitaxial layer of the source / drain region 136 is grown at the end of the channel 105. A second epitaxial layer of the source / drain region 136 is grown on the first epitaxial layer, covering the sides of the internal spacer 130. A final epitaxial layer of the source / drain region 136 is grown on a third epitaxial layer and fills the source / drain trench 124. The individual epitaxial layers of the source / drain region 136 can have different material and doping distributions.

[0064] exist Figures 6A-6C In some embodiments, a dielectric pad layer 138, a contact etch stop layer (CESL) 140, and an interlayer dielectric layer (ILD) 142 are formed. In some embodiments, the dielectric pad layer 140 is a thin dielectric layer conformally deposited on the exposed surfaces of the source / drain regions 136, the exposed surfaces of the dielectric structure 121, the exposed surfaces of the trench isolation structure 112, the exposed surfaces of the dielectric structure 138, and the exposed surfaces of the gate spacer layer 120. The dielectric pad layer 138 may include SiO, SiN, SiOC, SiOCN, SiON, or other suitable dielectric materials. The dielectric pad layer 138 may be deposited by ALD, CVD, PVD, or other suitable deposition processes. In some embodiments, the dielectric layer 138 is not present.

[0065] CESL 140 may include a thin dielectric layer conformally deposited on dielectric pad layer 138. CESL 140 may include SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. CESL 140 may be deposited by CVD, ALD, PVD, or other suitable deposition processes. In a particular example, dielectric pad layer 138 includes silicon oxide, while CESL 140 includes silicon nitride. Dielectric pad layer 138 and CESL 140 together correspond to CESL bilayer 141. In some embodiments, CESL bilayer 141 is between 3 nm and 6 nm, although other thicknesses may be used without departing from the scope of this disclosure.

[0066] Interlayer dielectric layer 142 covers CESL 140. Interlayer dielectric layer 142 fills the remaining space between adjacent sacrificial gate structures 114. Interlayer dielectric layer 142 may correspond to the lowest interlayer dielectric layer of integrated circuit 100. In some embodiments, interlayer dielectric layer 142 may be referred to as ILD0. Although not shown herein, another interlayer dielectric layer may be formed above interlayer dielectric layer 142. Conductive vias and metal wire networks may be formed in the upper interlayer dielectric layer. Interlayer dielectric layer 142 may include SiO, SiON, SiN, SiC, SiOC, SiOCN, SiON, or other suitable dielectric materials. Interlayer dielectric layer 142 may be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0067] In some embodiments, a chemical mechanical polishing (CMP) process is performed after depositing the interlayer dielectric layer 142. As a result of the CMP process, the top surfaces of the interlayer dielectric layer 142, CESL 140, gate spacer layer 120, and sacrificial gate layer 118 are coplanar. The CMP process can also reduce the height of the sacrificial gate structure 114 and the gate spacer layer 120.

[0068] Although Figures 6A-6C It is not obvious in the middle, but the source / drain region 136 extends laterally above the trench isolation structure 112. This is in Figure 7 It is more obvious in the view.

[0069] exist Figures 6A-6C In some embodiments, the sacrificial gate layer 118 is removed. The sacrificial gate layer 118 can be removed by an etching process that selectively etches the material of the sacrificial gate layer 118 relative to adjacent materials, such as the dielectric layer 116 and the gate spacer layer 124. Removal of the sacrificial gate layer 118 forms gate trenches between the gate spacer layers 124.

[0070] exist Figures 6A-6C In some embodiments, an etching process is performed to remove the sacrificial semiconductor nanostructure 107. The sacrificial semiconductor nanostructure 107 can be removed by a selective etching process using an etchant selective to the material of the channel 105, thereby removing the sacrificial semiconductor nanostructure 107 without significantly etching the channel 105. The removal of the sacrificial semiconductor nanostructure 107 is referred to as “releasing” the channel 105. In some embodiments, the etching process is an isotropic etching process using an etching gas and optionally a carrier gas, wherein the etching gas includes F2 and HF, and the carrier gas can be an inert gas such as Ar, He, N2, or combinations thereof. In some embodiments, the etching process causes the sides of the channel 105 to become rounded. The etching process also results in gaps being created between the channels 105.

[0071] exist Figures 6A-6C In some embodiments, a gate dielectric is formed. The gate dielectric includes an interface gate dielectric layer 144 and a high-k gate dielectric layer 146. In some embodiments, the interface gate dielectric layer 144 is deposited on an exposed portion of the channel 105. The interface gate dielectric layer 144 is formed directly on the exposed portion of the channel 105. The high-k gate dielectric layer 146 is formed on the interface gate dielectric layer 144 and other exposed surfaces, such as the exposed sidewalls of the gate spacer layer 120 and the internal spacer 130.

[0072] An interface gate dielectric layer 144 surrounds the channel 105. The interface gate dielectric layer 144 may include a dielectric material, such as silicon oxide, silicon nitride, or other suitable dielectric materials. Compared to high-k dielectrics such as hafnium oxide or other high-k dielectrics that can be used as transistor gate dielectrics, the interface gate dielectric layer 144 may include a dielectric with a relatively low k value. High-k dielectrics may include dielectric materials having a dielectric constant higher than that of silicon oxide. The interface gate dielectric layer 144 may be formed by thermal oxidation, chemical vapor deposition (CVD), or atomic layer deposition (ALD). The interface gate dielectric layer 144 may have a thickness between 0.5 nm and 2 nm. Other materials, deposition processes, and thicknesses may be used for the interface gate dielectric layer 144 without departing from the scope of this disclosure. The interface gate dielectric layer 144 in Figure 6A It is displayed in the middle. Although Figure 6B Although not shown, the interface gate dielectric layer 144 is also present on the surface of the channel 105 between the channel 105 and the high-K gate dielectric layer 146.

[0073] A high-k gate dielectric layer 146 is deposited in a conformal deposition process. The conformal deposition process deposits the high-k gate dielectric layer 146 on the interface gate dielectric layer 144, on the substrate 102, and on the gate spacer layer 120. The high-k gate dielectric layer 146 surrounds the channel 105. The high-k gate dielectric layer 146 has a thickness between 1 nm and 3 nm. The high-k dielectric layer comprises one or more dielectric materials, such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and / or combinations thereof. The high-k gate dielectric layer 146 can be formed by CVD, ALD, or any suitable method. Other thicknesses, deposition processes, and materials can be used for the high-k gate dielectric layer 146 without departing from the scope of this disclosure.

[0074] exist Figures 6A-6C In some embodiments, gate metal 148 is deposited. Gate metal 148 is deposited at the location of the sacrificial gate layer 118 and the sacrificial semiconductor nanostructure 107. Therefore, gate metal 148 is located in a gate trench above hard mask layer 124 and above hard mask layer 150. Gate metal 148 also surrounds channel 105.

[0075] like Figure 6BAs can be seen, the gate metal 148 of the gate layout G2 is shorted together around all channels 105. Each stack of channels 105a, 105b, and 105c represents a separate transistor 101a, 101b, and 101c, respectively. More specifically, each location of the gate metal 148 crossing the semiconductor fin 108 corresponds to a location of a separate transistor 101. Figures 6A-6C As shown in the processing stage, the gate electrodes of all transistors 101a-101c in gate region G2 are shorted together. The same applies to the other gate regions G1 and G3. Although not described herein, depending on the circuit layout, a gate metal partitioning process is used to electrically isolate the gate electrodes of adjacent transistors by removing gate metal at selected locations.

[0076] Figure 6C As shown, the gate metal 148 of each gate region G1-G3 extends uninterruptedly across fins 108a-108c. Figure 6C The dashed lines in the diagram indicate the locations of the semiconductor fins 108a-108c below the gate regions G1-G3, the gate spacer layer 120, a portion of the high-K gate dielectric layer 146 on the sidewall of the gate spacer layer 120, the interlayer dielectric layer 142, and the CESL double layer 141.

[0077] exist Figures 6A-6C In the diagram, a single gate metal 148 is shown as the gate electrode of transistor 101. However, in practice, gate metal 148 may include multiple gate metals. For example, gate metal 148 may include one or more pad layers, one or more work function layers, and gate fill material to fill the remaining space between gate spacer layers 120. Gate metal 148 may include one or more of Ti, TiN, Ta, TaN, Al, Cu, Co, Ru, W, Au, or other suitable conductive materials. Gate metal 148 may be deposited by PVD, ALD, or CVD.

[0078] After the gate metal 148 is formed, a CMP process is performed to reduce the height of the gate metal 148 and to obtain a flat top surface for the remaining structure.

[0079] According to some embodiments, the critical dimension of the semiconductor fin 108 along the Y direction is between 10 nm and 90 nm. Other dimensions may be used without departing from the scope of this disclosure.

[0080] Figure 7 This is a perspective view of an integrated circuit 100 according to one embodiment. Figure 7 The XZ plane of the perspective view is cut along the semiconductor fin 108a. Figure 7The perspective view shows the YZ plane cut through the source / drain regions 136a, 136b, and 136c of transistors 101a, 101b, and 101c.

[0081] Figure 7 The view shows that interlayer dielectric layer 143 fills the space between adjacent source / drain regions 136. In some embodiments, interlayer dielectric layer 143 and interlayer dielectric layer 142 are the same material and are deposited in the same process. In some embodiments, interlayer dielectric layer 143 is a different material and is deposited in a different deposition process. For example, in some embodiments, interlayer dielectric layer 143 comprises silicon oxide, while interlayer dielectric layer 142 comprises silicon nitride. In some embodiments, both dielectric layers 142 and 143 comprise silicon oxide. Other combinations of materials may be used without departing from the scope of this disclosure.

[0082] Figure 7 The view shows that the source / drain region 136 protrudes along the Y direction above the trench isolation structure 112. This is the result of forming the source / drain region 136 through an epitaxial growth process.

[0083] exist Figure 7 In this embodiment, a dielectric layer 152 is formed on the top surface of the integrated circuit 100. Specifically, the dielectric layer 152 is located on the top surface of the gate metal 148, the interlayer dielectric layer 142, and the top surfaces of other exposed structures. In some embodiments, the dielectric layer 152 comprises SiN, SiON, SiOCN, SiOC, or other suitable materials. According to some embodiments, the dielectric layer 152 helps prevent oxidation of the underlying structures.

[0084] exist Figure 7 In this embodiment, a dielectric layer 154 is formed on the dielectric layer 152. In some embodiments, the dielectric layer 154 comprises SiO, SiN, SiON, SiOCN, SiOC, or other suitable materials. Other materials may be used without departing from the scope of this disclosure. The dielectric layer 154 may be deposited by ALD, CVD, PVD, or other suitable deposition processes.

[0085] exist Figure 7 In this embodiment, layer 156 is formed on dielectric layer 154. In some embodiments, layer 156 is a tungsten-doped carbide layer. In some embodiments, layer 156 comprises SiC, SiOC, or SiOCN having tungsten. Other materials may be used without departing from the scope of this disclosure. Layer 156 may be deposited by ALD, CVD, PVD, or other suitable deposition processes.

[0086] exist Figure 7In this embodiment, a dielectric layer 158 is formed on layer 156. In some embodiments, dielectric layer 158 comprises SiO, SiN, SiON, SiOCN, SiOC, or other suitable materials. Other materials may be used without departing from the scope of this disclosure. Dielectric layer 158 may be deposited by ALD, CVD, PVD, or other suitable deposition processes. In some embodiments, dielectric layers 154 and 158 are formed using the same material, such as silicon oxide, or other suitable dielectric materials.

[0087] exist Figure 7 In this embodiment, layer 160 is formed on dielectric layer 158. In some embodiments, layer 160 is amorphous silicon. Other materials may be used without departing from the scope of this disclosure. Layer 160 may be deposited by ALD, CVD, PVD, or other suitable deposition processes.

[0088] Figure 8 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 8 In this process, a photolithography process was performed to define the pattern for the deposition of source / drain contacts in layer 160. Specifically, multiple trenches 162 were formed in layer 160. Figure 8 In the middle, the groove 162 extends continuously along the Y direction.

[0089] Figure 9A This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 9A In this process, a second photolithography process is implemented to define the pattern for the source / drain contact segmentation region. Specifically, multiple trenches 162 are incorporated into layers 158 and 156, and their patterns are relative to... Figure 8 The pattern shown has been changed. Specifically, trench 162 is divided by region 163 of dielectric layer 158. Region 163 corresponds to the pattern of the source / drain partition region. Figure 8 and Figure 9A The photolithography process will collectively define the actual layout of the first layer of the source / drain contact metals, as will be explained in more detail below.

[0090] exist Figure 9A In the middle, after patterning layer 158, layer 160 is removed. Now, layer 158 is used as a hard mask.

[0091] Figure 9B Is in Figure 9AThe layout 900 of the integrated circuit 100 shown in the figure is representative of the processing stage. Layout 900 is not a view of the integrated circuit 100 or any structure of the integrated circuit 100. Layout 900 shows active regions A1, A2, and A3 corresponding to the locations of semiconductor fins 108a-108c. The widths of the active regions A1-A3 represent the width along the Y direction corresponding to the width of the source / drain region 136 along the Y direction. As previously established, the source / drain region 136 is suspended above the trench isolation structure 112 and is therefore slightly wider along the Y direction than the semiconductor fin 108 in which it is grown.

[0092] Layout 900 shows gate regions G1-G3 corresponding to the locations of gate metal 148 as previously described. Layout 900 shows source / drain contact lines SDC1 and SDC2. Source / drain contact lines SDC1 and SDC2 represent the... Figure 8 The location of trench 162 in the processing stage is shown in the diagram. Layout 900 shows source / drain contact dividing lines SDCC1 and SDCC2. These dividing lines represent areas where source / drain contact metal is absent. Therefore, Figure 9A Region 163 corresponds to the location where the source / drain contact line SDC crosses the source / drain contact dividing line SDCC. For example... Figure 9B As can be seen, the SDCC2 has two different widths along the Y direction. As will be explained in more detail below, the smaller width corresponds to the position adjacent to the source / drain contact that will form two stacked metal pieces.

[0093] Figure 10 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 10 In this process, one or more etching processes are performed to further extend the recess 162 into the integrated circuit 100. Specifically, one or more etching processes etch through dielectric layers 154, 152, and 142 to expose the top surface of the source / drain region 136. One or more etching processes also expose dielectric layer 143. The removed portion of dielectric layer 142 corresponds to the location where metal will be deposited for the source / drain contacts. The etching process can include anisotropic etching processes that selectively etch in a downward direction. Anisotropic etching processes can include reactive ion etching or other types of etching. One or more etching processes can recess the top surface of the source / drain region 136.

[0094] Figure 11 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 11In this process, a dielectric liner layer 166 is deposited on the sidewalls of trench 162. The dielectric liner layer 166 liner the exposed sides of dielectric layers 142 and 154. The dielectric liner layer 166 may include SiN, SiON, SiOCN, SiCN, or other suitable dielectric materials. The dielectric liner layer 166 may be deposited by ALD, CVD, PVD, or other suitable deposition processes. In some embodiments, after depositing the dielectric liner layer 166, the dielectric layer 166 is etched to expose the source / drain regions 136.

[0095] Figure 12 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 12 In this process, a silicide layer 168 is formed, preparing for the formation of source / drain contacts. The formation of the silicide layer 168 may include: depositing a thin layer of metal Ti, Ni, Al, Ta, or other suitable metal, followed by a thermal annealing process to form the silicide layer 168 from the metal layer. Therefore, the silicide layer 168 may include titanium silicide, nickel silicide, aluminum silicide, tantalum silicide, or other suitable silicides.

[0096] Figure 13 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 13 In this process, a metal layer 170 is deposited. The metal layer 170 fills the trench 162. As will be described in more detail below, the metal layer 170 is used to form source / drain contacts. In some embodiments, the metal layer 170 comprises tungsten. Alternatively, the metal layer 170 may comprise Ta, Ti, Al, Ru, Co, Au, or other suitable materials. In some embodiments, a pad layer of titanium nitride or tantalum nitride is formed on the silicide and dielectric pad layer 166 prior to the formation of the metal layer 170. In some embodiments, the metal layer 170 is formed directly on the silicide 168. The metal layer 170 can be deposited by PVD, ALD, CVD, or other suitable deposition processes. In some embodiments, the metal layer 170 may be formed in a bottom-up manner. In some embodiments, the metal layer 170 comprises tungsten formed in a bottom-up manner. In some embodiments, a TiN pad layer is deposited prior to the deposition of the metal layer 170.

[0097] Figure 14 This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 14In some embodiments, a CMP process is implemented. The CMP process removes dielectric layer 154, removes dielectric layer 152, and reduces the height of metal layer 170. The reduction in the height of metal layer 170 results in the formation of individual source / drain contacts 171a, 171b, and 171c for transistors 101a-101c, a combined source / drain contact 171ab for transistors 101a and 101b, and a first portion 173c of the source / drain contact 171c. The function of the CMP process is to electrically isolate the source / drain contacts 171 from each other according to the pattern of the source / drain contact divider lines SDCC. As will be explained in more detail below, one of the source / drain contacts 171c will include a second portion formed on the top surface of the first portion 173c.

[0098] In some embodiments, the top surface of the gate metal 148 is coplanar with the top surface of the source / drain contact 171. In some embodiments, the gate metal 148 serves as an etch stop layer for a CMP process.

[0099] Figure 15A This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 15A In this configuration, a dielectric layer 174 is deposited on the top surface of the source / drain contact 171, the first portion 173c, the gate metal 148, and other exposed surfaces. In some embodiments, the dielectric layer 174 serves as an etch stop layer. The dielectric layer 174 comprises one or more of SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials. The dielectric layer 174 can be deposited using CVD, ALD, PVD, or other suitable deposition processes.

[0100] exist Figure 15A In some embodiments, a dielectric layer 176 is deposited on the dielectric layer 174. The dielectric layer 176 is an interlayer dielectric layer, including SiO, SiN, or other suitable dielectric materials. The dielectric layer 176 can be deposited by CVD, ALD, PVD, or other suitable deposition processes.

[0101] exist Figure 15A In this process, a photolithography process is performed to form openings in dielectric layers 176 and 174 to expose a portion of the top surface of the first portion 173c of the source / drain contact 171c, and a portion of the dielectric layer 142 located above the trench isolation region 112 between semiconductor fins 108b and 108c.

[0102] exist Figure 15AIn this process, metal layers are deposited in the openings of dielectric layers 176 and 174. A CMP process is performed to remove excess metal material from the top surface of dielectric layer 176. This results in the formation of a second portion 175c of the source / drain contact 171c on the top surface of the first portion 173c of the source / drain contact 171c. Therefore, Figure 15A The source / drain contact 171c visible in the image includes a first portion 173c and a second portion 175c. The first portion 173c can be referred to as the first source / drain metal part of the source / drain contact 171c. The second portion 175c can be referred to as the second source / drain metal part of the source / drain contact 171c.

[0103] The first portion 173c has a side edge or side surface 177 adjacent to the source / drain contact 171ab. The second portion 175c has a side edge or side surface 179 positioned further toward the source / drain contact 171ab along the Y direction. Therefore, the second portion 175c overlaps with the side surface 177 of the first portion 173c. Compared to the first portion 173c, the second portion 175c extends further above the trench isolation structure 112. The total width of the first portion 173c along the Y direction is greater than the total width of the second portion 175c along the Y direction. Further details regarding the dimensions will be provided below.

[0104] Figure 15B It is based on some embodiments of the state Figure 15A The layout 1500 related to integrated circuit 100 in the processing stage shown is illustrated. Layout 1500 and... Figure 9B The layout is basically similar to that of 900, except that layout 1500 shows the location of the second part 175c. The second part 175c overlaps with the active region A3 (and the semiconductor fin 108c) and the trench isolation structure 112.

[0105] Figure 16A This is a perspective view of an integrated circuit 100 according to some embodiments. Figure 16A In this process, an interlayer dielectric layer 176 is regrown. This can also be viewed as growing a second sublayer of the interlayer dielectric layer 176 on the top surface of the first sublayer. The second sublayer can have the same material as the first sublayer.

[0106] exist Figure 16AIn this process, source / drain conductive vias 182 and gate conductive vias 184 are formed in the interlayer dielectric layer 176. The source / drain conductive via 182 contacts the top surface of the source / drain contact 171. The gate conductive via 184 contacts the top surface of the gate metal 148. Openings are formed in the interlayer dielectric layer 176 through photolithography and corresponding etching processes to form the conductive vias 182 / 184. A deposition process is then performed to deposit metal into the openings of the conductive vias 182 / 184. The metal of the conductive vias may include W, Ta, Ti, Co, Au, Ru, Al, or other suitable conductive materials. The metal can be deposited using PVD, ALD, CVD, or other suitable deposition processes.

[0107] Source / drain conductive via 182ab contacts the top surface of source / drain contact 171ab. Source / drain conductive via 182c contacts the top surface of the second portion 175c of source / drain contact 171c. Source / drain conductive via 182b contacts the top surface of source / drain contact 171b. Gate conductive via 184a contacts a portion of the gate metal 148 corresponding to the gate electrode of transistor 101a. Gate conductive via 184c contacts a portion of the gate metal 148 corresponding to the gate electrode of transistor 101c.

[0108] In some embodiments, the conductive via 182c overlaps with the edge 177 of the first portion 173c of the source / drain contact 171c. The conductive via 182c also overlaps with the trench isolation structure 112.

[0109] Figure 16B It is based on some embodiments of the state Figure 16A The image shows a cross-sectional view of the integrated circuit 100 in the processing stage. Figure 16B The cross-sectional view corresponds to Figure 16A The perspective view of the YZ plane. An advantage of the process used to form the source / drain contact 171, which includes a stack of source / drain contact metals (e.g., in source / drain contact 171c), is that the silicide 168 of each of the source / drain regions 136 completely covers the top surface of the source / drain region 136. Therefore, there is no exposed source / drain material near the source / drain contact 171. This allows the source / drain regions to be formed closer to adjacent source / drain contacts. As a result, reliability (time-varying dielectric breakdown) is improved. Leakage current and short-circuit phenomena are reduced. Additionally, as will be explained in more detail below, the second portion 175c of the source / drain contact can be used as a power rail supplying VDD or VSS (ground). In some embodiments, the source / drain contact 171c covers the sidewalls of the silicide.

[0110] Figure 16C Based on some embodiments and Figure 16A and Figure 16B The layout 1600 shown is related to the processing stage of the integrated circuit 100. Layout 1600 is basically similar to layout 1500, except that the positions of conductive vias 182 / 184 are shown.

[0111] Figure 16D Based on some embodiments and Figure 16A and 16B The layout 1602 shown is related to the processing stage of the integrated circuit 100. The layout 1602 is basically similar to the layout 1600, except that the boundaries of the source / drain contacts 171ab and 171c are outlined, and the dimensions D1-D12 are shown.

[0112] In some embodiments, D1 is between 8 nm and 100 nm. In some embodiments, D2 is between 8 nm and 100 nm. In some embodiments, the ratio of D1 / D2 is between 1 and 13. In some embodiments, the size of the overlap portion D3 between 175c and 173c is between 13 nm and 20 nm. In some embodiments, the distance (D4) by which 175c extends beyond 173c is between 6 nm and 13 nm. In some embodiments, the ratio of D3 / D4 is between 1 and 4. In some embodiments, D4 may be greater than D3. In some embodiments, the width D6 of the source / drain contact along the Y dimension is between 8 nm and 12 nm. In some embodiments, the distance D7 between 182c and active region A3 is less than the distance D7' between 182c and A2. In some embodiments, the width D8 of active regions A1-A3 is between 10 nm and 60 nm. In some embodiments, the narrow portion D9 of SDCC2 is between 10 nm and 15 nm. In some embodiments, the distance D10 between active regions is between 15 nm and 28 nm. In some embodiments, the distance D11 between SDCC2 and A1 is between 0.5 nm and 6 nm. In some embodiments, the distance D11' is between 0.5 nm and 6 nm. In some embodiments, D11 and D11' are the same. In some embodiments, D11 and D11' are different. In some embodiments, the dimension D12 is between 0 nm and 8 nm. In some embodiments, the ratio of D11 / D10 is between 0.02 and 0.4. In some embodiments, the ratio of D9 / D10 is between 0.3 and 1. In some embodiments, D11 is less than D9. In some embodiments, D9 is less than D11. In some embodiments, D11 is less than D6. In some embodiments, D6 is less than D11. In some embodiments, D11 is less than D7'. In some embodiments, D7' is less than D11. In some embodiments, the width of 175c along the X direction is less than or equal to the width of 173c.

[0113] Figures 16A-16D The integrated circuit 100 and its corresponding layout, and the combination Figures 1-16C The process shown and described offers several benefits. Each active region corresponds to a logic cell. The cell boundary lies above the SDCC between the active regions. In some embodiments, the layout rules for the first metal layer cannot be moved into the logic cell corresponding to A3, as this could reduce the critical dimensions of the metal lines. This necessitates that the conductive via 182c be positioned near the cell boundary (midway between A3 and A2). Advantageously, the use of a stack of source / drain contact metals allows the conductive via 182c to be placed near the cell boundary.

[0114] In some embodiments, the source / drain conductive via 182ab is not directly connected to the VDD / VSS power rail located above the active region A2. The source / drain contact 171ab completely covers the silicide 168 and the source / drain regions 136a / b, thereby improving time-varying dielectric breakdown performance.

[0115] In some embodiments, the SDCC is moved toward the cell boundary while maintaining the same size, thereby avoiding shrinkage that could cause short circuits between adjacent source / drain contacts. Additionally, the SDCC is moved toward the cell boundary while maintaining the same size.

[0116] In some embodiments, although the second portion 175c of the source / drain contact 171c is close to the source / drain contact 171ab, the distance between them can be well controlled by a photolithography process that can pattern the second portion 175c of the source / drain contact 171c. This contrasts with the difficulty in reducing the distance between 173c and 171ab, as controlling the lateral growth of the source / drain regions is more challenging.

[0117] In some embodiments, the top surfaces of the first portion 173c and other source / drain contacts 171 are at the same height or coplanar with the top surface of the gate metal 148. In some embodiments, the top surface of the second portion 175c is higher than the top surface of the gate metal 148 by a height between 6 nm and 10 nm. In some embodiments, due to an etching process, the second source / drain contact metal has a recess below the top surface of the gate metal 148. In some embodiments, the recess depth is between 0 nm and 10 nm.

[0118] In some embodiments, the source / drain contact 171 (and the first portion 173c) has a width between 9 nm and 20 nm along the X direction and a width between 8 nm and 100 nm along the Y direction. In some embodiments, the second portion 175c has a width between 6 nm and 10 nm along the X direction and a width between 8 nm and 100 nm along the Y direction. In some embodiments, the ratio of the width of the first portion 173c along the Y direction to the width of the second portion 175c along the Y direction is between 1 and 13. In some embodiments, the overlap between 175c and 173c along the Y direction is between 13 nm and 20 nm. In some embodiments, the distance by which 175c extends beyond the edge 177 of 173c is between 6 nm and 13 nm. Other dimensions may be used without departing from the scope of the invention.

[0119] In some embodiments, the conductive via 182 located on the second portion 175c of the source / drain contact 171 may be of the power rail type. In some embodiments, the source / drain conductive vias may have different heights. For example, the source / drain conductive via 182ab may have a height between 12 nm and 30 nm, while the source / drain contact 182c may have a height between 6 nm and 18 nm. In some embodiments, the overlap between the edges 177 of the second portion 175c and the first portion 173c is between 2 nm and 3 nm. In some embodiments, the ratio of the height of 175c to the height of 173c is between 0.2 and 0.8. Other dimensions may be used without departing from the scope of this disclosure.

[0120] Figure 17 This refers to layout 1700 related to integrated circuit 100 according to some embodiments. Layout 1700 and... Figure 16C The layout is basically similar to 1600, except that the position of the conductive via 182c is replaced by a power rail 186 that provides VDD or VSS (ground). The width of the power rail 186 along the X direction is approximately equal to the distance between G1 and G2 along the X direction, or between 20nm and 100nm.

[0121] Figure 18 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 18 Integrated circuit 100 and Figure 16B The integrated circuit 100 is substantially similar, except that the source / drain via 182c is wider and shorter than the source / drain via 182ab. In some embodiments, this provides reduced resistance in the source / drain via 182c.

[0122] Figure 19This refers to layout 1900 related to integrated circuit 100 according to some embodiments. Layout 1900 and... Figure 16C The layout is basically similar to 1600, except that SDCC2 has a uniform width along the Y direction. Additionally, D4 is greater than or equal to D3.

[0123] Figure 20 This is a cross-sectional view of an integrated circuit 100 according to some embodiments. Figure 20 Integrated circuit 100 and Figure 16B The integrated circuit 100 is substantially similar, except that the top surface of the source / drain contact 171 (and the first portion 173) is higher than the top surface of the gate metal 148. The height of the top surface of the gate metal 148 is represented by a dashed line. In some embodiments, the height of the top surface of 171ab above the top surface of the gate metal 148 is between 5 nm and 20 nm, although other dimensions may be used without departing from the scope of this disclosure.

[0124] The integrated circuit 100 also includes a dielectric layer 186 and a dielectric layer 188. The dielectric layer 188 is an interlayer dielectric layer and may include SiO, SiN, or other suitable dielectric materials. The dielectric layer 186 is an etch stop layer and includes SiN, SiCN, SiOCN, SiOC, or other suitable dielectric materials.

[0125] Figure 21 This is a flowchart of a method 2100 for forming an integrated circuit according to some embodiments. Method 2100 may use... Figures 1 to 20 The described structure, process, and system. At 2102, method 2100 includes forming a first semiconductor fin extending along a first lateral direction. An example of the first semiconductor fin is... Figure 2A Semiconductor fin 108c. At 2104, method 2100 includes forming a second semiconductor fin extending along a first lateral direction. An example of the second semiconductor fin is... Figure 2A Semiconductor fin 108b. At 2106, method 2100 includes depositing a trench isolation structure between the first and second semiconductor fins. An example of the trench isolation structure is... Figure 2B The trench isolation structure 112. At 2108, method 2100 includes depositing gate metal extending along a second lateral direction perpendicular to the first lateral direction, across the first semiconductor fin, the second semiconductor fin, and the trench isolation structure. An example of the gate metal is... Figure 6C The gate metal 148 / G2. At 2110, method 2100 includes growing a first source / drain region of a first transistor located on a first semiconductor fin and extending partially over a first trench isolation structure. An example of the first transistor is... Figure 7The transistor 101c. An example of the first source / drain region is... Figure 7 The source / drain region 136c. At 2112, method 2100 includes growing a second source / drain region of a second transistor located on a second semiconductor fin and extending partially above the trench isolation structure. An example of the second transistor is... Figure 7 Transistor 101b. An example of the second source / drain region is source / drain region 136b. At 2114, method 2100 includes forming a first portion of a first source / drain contact on the first source / drain region by depositing a first metal layer, and forming a second source / drain contact on the second source / drain region. An example of the first source / drain metal layer is... Figure 13 Metal layer 170. An example of the first portion of the first source / drain contact is... Figure 14 Part 173c. An example of the second source / drain contact is... Figure 14 The source / drain contact 171ab. At 2116, method 2100 includes forming a second portion of the first source / drain contact located on the top surface of the first portion and extending laterally beyond the edge of the first portion above the trench isolation structure by depositing a second metal layer. An example of the second portion of the first source / drain contact is the second portion 175c of the source / drain contact 171c of FIG. 15.

[0126] Figure 22 This is a flowchart of a method 2200 for forming an integrated circuit according to some embodiments. Method 2200 can use... Figures 1-20 The described structure, process, and system. At 2202, method 2200 includes depositing a trench isolation structure between a first semiconductor fin and a second semiconductor fin. An example of a trench isolation structure is... Figure 2B The trench isolation structure 112. An example of the first semiconductor fin is... Figure 2B The semiconductor fin 108b. An example of a second semiconductor fin is... Figure 2B Semiconductor fin 108b. At 2204, method 2200 includes growing a first source / drain region of a first transistor in a first trench within the first semiconductor fin. An example of the first transistor is... Figure 7 Transistor 101c. At 2206, method 2200 includes growing a second source / drain region of the first transistor in a second trench within a first semiconductor fin. An example of the first source / drain region and the second source / drain region is... Figure 7The source / drain region 136c. At 2208, method 2200 includes forming a first source / drain contact on the first source / drain region of the first transistor. At 2210, method 2200 includes forming a second source / drain contact on the second source / drain region of the first transistor, wherein the first source / drain contact has a greater height than the second source / drain contact. An example of the second source / drain contact is the source / drain contact 171c of FIG. 15. At 2212, method 2200 includes forming an interlayer dielectric layer over the first transistor. An example of the interlayer dielectric layer is... Figure 16A The interlayer dielectric layer 176. At 2214, method 2200 includes forming a first conductive via located in the interlayer dielectric region and contacting the top surface of the first source / drain contact. At 2216, method 2200 includes forming a second conductive via located in the interlayer dielectric region and contacting the top surface of the second source / drain contact, wherein the height of the first conductive via is less than the height of the second conductive via. An example of the first and second conductive vias is... Figure 16C Conductive via 182c.

[0127] According to some embodiments, the active region is implemented in conjunction with a semiconductor fin extending along a first lateral direction (e.g., the X direction). A trench isolation structure extends along the first lateral direction, adjacent to and between adjacent semiconductor fins. A gate region extends along a second lateral direction (e.g., the Y direction) across the semiconductor fin and the trench isolation structure. Source / drain regions of the transistor are formed in the semiconductor fin, with stacked channels located where the gate region intersects with the semiconductor fin. At the layout level, source / drain contact metal elements extend along the second lateral direction. Source / drain contact dividers extend along the first lateral direction above the trench isolation structure. At the intersections of the source / drain contact dividers and the source / drain contact regions, source / drain contact metal elements are removed or not formed to electrically isolate the source / drain contacts of adjacent transistors from each other.

[0128] Embodiments of this disclosure provide source / drain contacts capable of continuously reducing active region spacing and trench isolation structure dimensions. In some embodiments, the source / drain contact partition does not overlap with the semiconductor fins but is located entirely above the trench isolation structure. Embodiments of this disclosure can use a stack of two source / drain contact metals to form the selected source / drain contact. More specifically, when adjacent source / drain regions of two transistors formed in different semiconductor fins need to be electrically isolated from each other and both need to be contacted through their respective conductive vias, one source / drain contact includes a stack of two metals, while the other includes only one source / drain contact metal. In the stack of two source / drain contact metals, the edge of the higher metal overlaps with that of the lower metal, such that the higher metal is closer to the source / drain contact of the adjacent transistor on the other side of the trench isolation structure. This layout and structure can further reduce the active region spacing, increase the density of transistor formation, better cover the source / drain silicide through the source / drain contact regions, reduce time-varying dielectric breakdown, and improve overall device performance. Embodiments of this disclosure also provide integrated circuits with better functionality and higher wafer yield.

[0129] In some embodiments, a method includes: forming a first semiconductor fin extending along a first lateral direction; forming a second semiconductor fin extending along the first lateral direction; depositing a trench isolation structure between the first semiconductor fin and the second semiconductor fin; and depositing a gate metal extending along a second lateral direction perpendicular to the first lateral direction across the first semiconductor fin, the second semiconductor fin, and the trench isolation structure. The method further includes: growing a first source / drain region of a first transistor located on the first semiconductor fin and extending partially above the first trench isolation structure; growing a second source / drain region of a second transistor located on the second semiconductor fin and extending partially above the trench isolation structure; forming a first portion of a first source / drain contact on the first source / drain region by depositing a first metal layer; forming a second source / drain contact on the second source / drain region; and forming a second portion of the first source / drain contact located on the top surface of the first portion and extending laterally above the trench isolation structure beyond the edge of the first portion by depositing a second metal layer. In some embodiments, the method further includes: forming an interlayer dielectric layer over the first source / drain contact and the second source / drain contact; and forming, by a deposition process, a first conductive via extending through the interlayer dielectric layer and contacting the top surface of the second portion of the first source / drain contact; and forming, by the deposition process, a second conductive via extending through the interlayer dielectric layer and contacting the top surface of the second source / drain contact, wherein the top surface of the first portion of the source / drain contact is coplanar with the top surface of the second source / drain contact. In some embodiments, the method further includes: forming, by the deposition process, a third conductive via contact extending through the interlayer dielectric layer and contacting the top surface of the gate metal. In some embodiments, the first conductive via is located above the edge of the first portion of the first source / drain contact. In some embodiments, the top surface of the first portion of the first source / drain contact is higher than the top surface of the gate metal. In some embodiments, the method further includes: electrically isolating the first portion of the first source / drain contact from the second source / drain contact by performing a CMP process. In some embodiments, the method further includes: forming an interlayer dielectric layer over the first portion of the first source / drain contact and the second source / drain contact before forming the second portion of the first source / drain contact. In some embodiments, forming the second portion of the first source / drain contact includes: exposing the top surface of the first portion of the first source / drain contact by forming a trench through the interlayer dielectric layer; and depositing the second portion of the first source / drain contact in the trench. In some embodiments, the second portion of the first source / drain contact includes a power voltage rail.In some embodiments, the first transistor includes: a plurality of stacked channels; a plurality of internal spacers interleaved with the stacked channels, wherein the gate metal surrounds the channels.

[0130] In some embodiments, a method includes: depositing a trench isolation structure between a first semiconductor fin and a second semiconductor fin; growing a first source / drain region of a first transistor in a first trench in the first semiconductor fin; growing a second source / drain region of the first transistor in a second trench in the first semiconductor fin; and depositing a first source / drain contact on the first source / drain region of the first transistor. The method includes depositing a second source / drain contact on the second source / drain region of the first transistor. The first source / drain contact has a greater height than the second source / drain contact. The method includes depositing an interlayer dielectric layer over the first transistor; forming a first conductive via located in the interlayer dielectric region and contacting the top surface of the first source / drain contact; and forming a second conductive via located in the interlayer dielectric region and contacting the top surface of the second source / drain contact. The height of the first conductive via is less than the height of the second conductive via. In some embodiments, forming the first source / drain contact includes: forming a third source / drain region of the second transistor and a fourth source / drain region of the second transistor on the second semiconductor fin, wherein the third source / drain region is spaced apart from the first source / drain region along a second lateral direction across the trench isolation structure, wherein the fourth source / drain region is spaced apart from the second source / drain region along the second lateral direction across the trench isolation structure; forming a third source / drain contact on the third source / drain region of the second transistor; and forming a fourth source / drain contact on the fourth source / drain region of the second transistor, wherein the first source / drain contact has a greater height than the second source / drain contact, wherein the first source / drain contact is closer to the second source / drain contact along the second direction than the second source / drain region is closer to the fourth source / drain region along the second direction. In some embodiments, the method further includes forming the first source / drain contact with a metal layer that is more than the second source / drain contact.

[0131] In some embodiments, an integrated circuit includes: a first active region extending along a first lateral direction; a second active region extending along the first lateral direction; a trench isolation structure located between the first active region and the second active region; and a first transistor. The first transistor includes: a first source / drain region located in a first semiconductor fin and partially suspended above the trench isolation structure; a first source / drain contact located on the first source / drain region, the first source / drain contact including a first metal structure and a second structure covering at least a portion of the top surface of the first metal structure and extending beyond a lateral edge of the first portion. The integrated circuit includes a second transistor, the second transistor including: a second source / drain region located in a second semiconductor fin and partially covering the trench isolation structure adjacent to the first source / drain region; and a second source / drain contact located on the second source / drain region. The integrated circuit includes: an interlayer dielectric layer located on a first source / drain contact and a second source / drain contact; a first conductive via located in the interlayer dielectric layer, the first conductive via contacting the top surface of a second metal structure of the first source / drain contact; and a second conductive via located in the interlayer dielectric layer, the second conductive via contacting the top surface of the second source / drain contact. The height of the second conductive via is greater than the height of the first conductive via.

[0132] This application provides an integrated circuit, comprising: a first active region extending along a first lateral direction; a second active region extending along the first lateral direction; a trench isolation structure located between the first active region and the second active region; a first transistor, the first transistor comprising: a first source / drain region and a first source / drain contact, the first source / drain region being located in the first active region and partially suspended above the trench isolation structure, the first source / drain contact being located on the first source / drain region and comprising a first metal structure and a second metal structure, the second metal structure covering at least a portion of the top surface of the first metal structure and extending beyond the lateral edge of the first portion; and a second transistor. The second transistor includes: a second source / drain region and a second source / drain contact, the second source / drain region being located in the second active region and partially suspended above the trench isolation structure adjacent to the first source / drain region, the second source / drain contact being located on the second source / drain region; an interlayer dielectric layer located on the first source / drain contact and the second source / drain contact; a first conductive via located in the interlayer dielectric layer and contacting the top surface of the second metal structure of the first source / drain contact; and a second conductive via located in the interlayer dielectric layer and contacting the top surface of the second source / drain contact, wherein the height of the second conductive via is greater than the height of the first conductive via.

[0133] In some embodiments, the first transistor includes a plurality of stacked channels in contact with the first source / drain region. In some embodiments, the first transistor includes gate metal surrounding the stacked channels. In some embodiments, the top surface of the gate metal is lower than the top surface of the second source / drain contact. In some embodiments, the integrated circuit further includes a silicide covering the entire top surface of both the first and second source / drain regions. In some embodiments, a second portion of the first source / drain contact includes a power supply voltage rail. In some embodiments, the second source / drain contact is closer to the second metal structure than the first metal structure.

[0134] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing an integrated circuit, comprising: Forming a first semiconductor fin extending along a first lateral direction; A second semiconductor fin extending along the first lateral direction is formed; A trench isolation structure is deposited between the first semiconductor fin and the second semiconductor fin; A gate metal is deposited along a second lateral direction that extends transversely to the first lateral direction, spanning the first semiconductor fin, the second semiconductor fin, and the trench isolation structure. A first source / drain region of a first transistor is grown on the first semiconductor fin and extends partially above the first trench isolation structure; A second source / drain region of a second transistor is grown on the second semiconductor fin and extends partially above the trench isolation structure; By depositing a first metal layer, a first portion of a first source / drain contact is formed on the first source / drain region, and a second source / drain contact is formed on the second source / drain region; as well as A second portion of the first source / drain contact is formed by depositing a second metal layer, which is located on the top surface of the first portion and extends laterally over the trench isolation structure beyond the edge of the first portion.

2. The method according to claim 1, further comprising: An interlayer dielectric layer is formed above the first source / drain contact and the second source / drain contact; and A first conductive via is formed by a deposition process, extending through the interlayer dielectric layer and contacting the top surface of the second portion of the first source / drain contact. and The deposition process forms a second conductive via that extends through the interlayer dielectric layer and contacts the top surface of the second source / drain contact, wherein the top surface of the first portion of the source / drain contact is coplanar with the top surface of the second source / drain contact.

3. The method according to claim 2, further comprising: The deposition process forms a third conductive via contact that extends through the interlayer dielectric layer and contacts the top surface of the gate metal.

4. The method according to claim 2, wherein, The first conductive via is located above the edge of the first portion of the first source / drain contact.

5. The method according to claim 1, wherein, The top surface of the first portion of the first source / drain contact is higher than the top surface of the gate metal.

6. The method according to claim 1, further comprising: By implementing a chemical mechanical polishing process, the first portion of the first source / drain contact is electrically isolated from the second source / drain contact.

7. The method according to claim 1, further comprising: Before forming the second portion of the first source / drain contact, an interlayer dielectric layer is formed over the first portion of the first source / drain contact and the second source / drain contact.

8. The method according to claim 7, wherein, The second portion forming the first source / drain contact includes: By forming trenches through the interlayer dielectric layer, the top surface of the first portion of the first source / drain contact is exposed; and The second portion of the first source / drain contact is deposited in the trench.

9. A method for manufacturing an integrated circuit, comprising: A trench isolation structure is deposited between the first semiconductor fin and the second semiconductor fin; A first source / drain region of a first transistor is grown in a first trench in the first semiconductor fin; The second source / drain region of the first transistor is grown in the second trench within the first semiconductor fin; First source / drain contacts are deposited on the first source / drain regions of the first transistor; A second source / drain contact is deposited on the second source / drain region of the first transistor, wherein the first source / drain contact has a greater height than the second source / drain contact; An interlayer dielectric layer is deposited above the first transistor; Forming a first conductive via located in the interlayer dielectric region, contacting the top surface of the first source / drain contact; and A second conductive via is formed in the interlayer dielectric region, which contacts the top surface of the second source / drain contact, wherein the height of the first conductive via is less than the height of the second conductive via.

10. An integrated circuit, comprising: The first active region extends along the first lateral direction; The second active region extends along the first lateral direction; The trench isolation structure is located between the first active region and the second active region; A first transistor, the first transistor comprising: a first source / drain region located in a first active region and partially suspended above the trench isolation structure; and a first source / drain contact located on the first source / drain region and comprising a first metal structure and a second metal structure, the second metal structure covering at least a portion of the top surface of the first metal structure and extending beyond the lateral edge of the first portion; The second transistor includes: a second source / drain region located in the second active region and partially suspended above the trench isolation structure adjacent to the first source / drain region; and a second source / drain contact located on the second source / drain region. An interlayer dielectric layer is located on the first source / drain contact and the second source / drain contact; The first conductive via is located in the interlayer dielectric layer and contacts the top surface of the second metal structure of the first source / drain contact. The second conductive via is located in the interlayer dielectric layer and contacts the top surface of the second source / drain contact, wherein the height of the second conductive via is greater than the height of the first conductive via.

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