A complementary field effect transistor and a manufacturing method thereof, a memory device
By forming a protective layer and a capping layer in the CFET structure and using an etching process to achieve epitaxial growth of the seed layer, the manufacturing problem of independent transmission transistors in CFET memory cells is solved, and the device integration density is improved.
Patent Information
- Application Number
- CN202610818958.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-08
- Publication Date
- 2026-08-25
AI Technical Summary
Existing technologies cannot manufacture independent N-type and P-type transistors as transmission transistors in a CFET structure, which limits the development of memory cells based on the CFET structure.
By forming a protective layer, a capping layer, and etching processes in the CFET structure, different or the same types of source and drain can be epitaxially grown in the seed layer of the vertically stacked structure to form independent N-type and P-type transistors.
This invention enables independent transmission transistors in memory cells based on CFET structure, effectively doubling the device width and improving device integration.
Smart Images
Figure CN122641074A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a complementary field-effect transistor, its manufacturing method, and a memory device. Background Technology
[0002] Static Random-Access Memory (SRAM) is a semiconductor memory based on bistable flip-flops. It can stably store data as long as it is powered on, without the need for periodic refresh, and has nanosecond-level access speed and low latency.
[0003] SRAM memory cells consist of a bistable circuit composed of six transistors (6T, including two memory bit transistors and four feedback loop transistors), with data stability maintained by cross-coupled inverters. When memory cells are manufactured based on planar MOSFET (Metal Oxide Semiconductor Field Effect Transistor), FinFET (Fin Field Effect Transistor), or GAAFET (Gate-All-Around Field Effect Transistor) structures, the layout design offers greater freedom because the transistors (including N-type and P-type transistors) are horizontally distributed, but this also results in a larger chip area.
[0004] To improve device integration and reduce chip footprint, memory cells can be fabricated based on the CFET (Complementary FET) structure. In a CFET device structure, N-type transistors and P-type transistors are naturally paired by vertically stacking in the same channel region, and their numbers are equal. However, for memory circuits such as 6T SRAM, independent N-type and P-type transistors are required as transport transistors. With current technology, independent transport transistors cannot be implemented in a vertically stacked CFET structure, thus limiting the development of CFET-based memory cells. Summary of the Invention
[0005] The purpose of this invention is to provide a complementary field-effect transistor and its manufacturing method, as well as a memory device, to solve the problem of how to manufacture memory cells with independent transmission transistors based on a CFET structure.
[0006] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing a complementary field-effect transistor, comprising: A basic device structure is provided, the basic device structure comprising at least two vertically stacked structures formed on a substrate, each of the vertically stacked structures comprising two seed layers formed sequentially from bottom to top; A protective layer is formed, the protective layer covering at least one seed layer; A first cover layer is formed, which covers the sidewalls of the vertically stacked structure; Remove the protective layer; The seed layer exposed after removing the protective layer is epitaxially grown to produce a source / drain transistor, thus obtaining the first transistor. A second capping layer is formed, which covers the first transistor; The exposed seed layer is epitaxially grown to produce a source-drain transistor, thus obtaining a second transistor. Remove the second overlay.
[0007] Optionally, in the manufacturing method of the complementary field-effect transistor, the protective layer is made of SOC.
[0008] Optionally, in the method for manufacturing the complementary field-effect transistor, the method for forming the protective layer includes: Deposit protective materials to cover the underlying device structure; Etching removes part of the protective material to obtain a protective layer that covers the seed layer at the bottom of at least one vertically stacked structure.
[0009] Optionally, in the method for manufacturing the complementary field-effect transistor, the method for forming the protective layer includes: Deposit protective materials to cover the underlying device structure; Etching removes part of the protective material to obtain a protective layer that covers the bottom seed layer and two seed layers in at least one vertical stacked structure.
[0010] Optionally, in the manufacturing method of the complementary field-effect transistor, the first capping layer has a different etching selectivity than the protective layer and the vertical stacked structure; the second capping layer has a different etching selectivity than the vertical stacked structure.
[0011] Optionally, in the manufacturing method of the complementary field-effect transistor, the material of the first capping layer is the same as the material of the second capping layer.
[0012] Optionally, in the method for manufacturing the complementary field-effect transistor, the method for forming the first capping layer includes: A full-coverage layer is formed, which covers the surface of the basic device structure and the protective layer; The full overlay is vertically etched to obtain a first overlay that covers the sidewalls of the vertically stacked structure.
[0013] Optionally, in the method for manufacturing the complementary field-effect transistor, the method for forming the second capping layer includes: Deposit a cover material to cover the underlying device structure; Etching removes part of the cover material to obtain a second cover layer, which covers the first transistor.
[0014] To address the aforementioned technical problems, the present invention also provides a complementary field-effect transistor (CFPT), manufactured using the CFPT manufacturing method described in any of the preceding claims. The CFPT includes a substrate and at least two vertically stacked structures formed on the substrate. Each of the vertically stacked structures includes two seed layers formed sequentially from bottom to top. At least one of the two seed layers in the vertically stacked structure has source and drain of the same type epitaxially grown, and at least one of the two seed layers in the vertically stacked structure has source and drain of different types epitaxially grown.
[0015] To address the aforementioned technical problems, the present invention also provides a storage device, including a complementary field-effect transistor as described in any of the preceding claims.
[0016] The present invention provides a complementary field-effect transistor (CFET) and its manufacturing method, as well as a memory device, comprising: providing a basic device structure, the basic device structure including at least two vertically stacked structures formed on a substrate, each of the vertically stacked structures including two seed layers formed sequentially from bottom to top; forming a protective layer covering at least one seed layer; forming a first capping layer covering the sidewalls of the vertically stacked structures; removing the protective layer; epitaxially growing a source / drain on the seed layer exposed after removing the protective layer to obtain a first transistor; forming a second capping layer covering the first transistor; epitaxially growing a source / drain on the exposed seed layer to obtain a second transistor; and removing the second capping layer. In this way, the two seed layers in at least one of the vertically stacked structures are epitaxially grown with different types of source / drain, while simultaneously ensuring that the two seed layers in at least one of the vertically stacked structures are epitaxially grown with the same type of source / drain, forming a single-transistor transmission transistor, and doubling the equivalent width of the device, thus solving the problem of how to manufacture memory cells with independent transmission transistors based on a CFET structure. Attached Figure Description
[0017] Figure 1 A flowchart illustrating the manufacturing method of the complementary field-effect transistor provided in this embodiment; Figures 2(A) to 2(O) are schematic diagrams of the device structure at each step in the manufacturing method of the complementary field-effect transistor provided in this embodiment; Figure 3 This is a schematic diagram of the structure of the first complementary field-effect transistor provided in this embodiment; Figure 4 This is a schematic diagram of the structure of the second complementary field-effect transistor provided in this embodiment; The labels in the attached figures are explained as follows: 100 - Substrate; 200 - Vertical stacked structure; 201 - Bottom seed layer; 202 - Top seed layer; 210 - Protective layer; 220 - First capping layer; 230 - First transistor; 240 - Second capping layer; 250 - Second transistor. Detailed Implementation
[0018] The complementary field-effect transistor, its manufacturing method, and memory device proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales.
[0019] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0020] This embodiment provides a method for manufacturing a complementary field-effect transistor, such as... Figure 1 As shown, it includes: S1, providing a basic device structure, the basic device structure including at least two vertically stacked structures formed on a substrate, each of the vertically stacked structures including two seed layers formed sequentially from bottom to top; S2, forming a protective layer that covers at least one seed layer; S3, forming a first covering layer that covers the sidewalls of the vertically stacked structure; S4, Remove the protective layer; S5, epitaxially grow source and drain on the seed layer exposed after removing the protective layer to obtain the first transistor; S6, forming a second cover layer, the second cover layer covering the first transistor; S7, epitaxially grow source and drain on the exposed seed layer to obtain the second transistor; S8, remove the second overlay.
[0021] The complementary field-effect transistor manufacturing method provided in this embodiment creatively sets up process steps, using a protective layer, a first capping layer and a second capping layer to epitaxially grow different types of source and drain in two seed layers in at least one vertical stacked structure, while simultaneously allowing the two seed layers in at least one vertical stacked structure to epitaxially grow the same type of source and drain, forming a single transistor transmission tube, and doubling the device's equivalent width, thus solving the problem of how to manufacture memory cells with independent transmission tubes based on CFET structures.
[0022] Specifically, in this embodiment, step S1 provides a basic device structure. As shown in FIG2(A), the basic device structure includes at least two vertically stacked structures 200 formed on a substrate 100, each of the vertically stacked structures 200 including a bottom seed layer 201 and a top seed layer 202 formed sequentially from bottom to top.
[0023] In practical applications, the substrate 100 can be a silicon substrate, and the substrate 100 may also contain other device structures, such as metal interconnect layers, which will not be elaborated further in this application. Furthermore, the bottom seed layer 201 and the top seed layer 202 may specifically include multiple silicon layers and silicon-germanium layers stacked sequentially from bottom to top, with the silicon layers subsequently used as seed layers for epitaxial growth of source and drain layers. Additionally, the sidewalls and top of the bottom seed layer 201 and the top seed layer 202 may also be covered with silicon nitride to obtain a complete vertically stacked structure.
[0024] The specific formation method of the basic device structure can be obtained by those skilled in the art in the existing manufacturing methods of complementary field-effect transistors, and will not be described in detail here.
[0025] This embodiment illustrates the manufacturing process using the example of two horizontally placed vertically stacked structures 200 formed on a substrate. Those skilled in the art will be able to learn, based on this embodiment, how to form complementary field-effect transistors when there are four or more vertically stacked structures 200.
[0026] Furthermore, in this embodiment, step S2 involves forming a protective layer 210, which covers at least one seed layer.
[0027] Specifically, in this embodiment, the protective layer 210 is made of spin-coated organic carbon SOC, which can completely fill the gaps in each vertical stacked structure 200 and has good surface flatness.
[0028] This embodiment provides two specific implementation schemes for forming the protective layer 210, so as to enable the subsequent formation of two complementary field-effect transistors with different device structures: In the first implementation scheme, as shown in FIG2(B), the method for forming the protective layer 210 mainly includes: firstly, depositing a protective material to cover the basic device structure, including the surface of the substrate 100, the surface of the vertical stacked structure 200, and the gap between the vertical stacked structures 200; then, etching away part of the protective material to obtain the protective layer 210, the protective layer 210 covering at least one seed layer 201 at the bottom of the vertical stacked structure, wherein part of the protective material can be removed by photolithography etching process to obtain the protective layer 210.
[0029] In the second implementation scheme, as shown in FIG2(C), the method for forming the protective layer 210 mainly includes: firstly, depositing a protective material to cover the basic device structure, including the surface of the substrate 100, the surface of the vertical stacked structure 200, and the gap between the vertical stacked structures 200; then, etching away part of the protective material to obtain the protective layer 210, which covers at least one bottom seed layer 201 in the vertical stacked structure 200 and at least two seed layers (including the bottom seed layer 201 and the top seed layer 202) in the vertical stacked structure 200.
[0030] In this embodiment, since the protective layer 210 is made of SOC, while the vertical stacked structure 200 is mainly made of materials such as SiO2, SiN, Si and SiGe, the protective layer 210 and the vertical stacked structure 200 have different etching selectivity ratios. Therefore, when etching away part of the protective material, the integrity of the vertical stacked structure 200 can be guaranteed.
[0031] Furthermore, in this embodiment, in step S3, a first cover layer 220 is formed, which covers the sidewalls of the vertically stacked structure 200.
[0032] Specifically, in this embodiment, the first capping layer 220 can be made of materials such as SiON, SiOC, or SiOCN, thus having a different etching selectivity ratio than both the protective layer 210 and the vertical stacked structure 200. This ensures that the first capping layer 220 is intact when the protective layer 210 is removed. Of course, in practical applications, other materials with different etching selectivity ratios than both the protective layer 210 and the vertical stacked structure 200 can also be selected, which will not be elaborated upon in this application.
[0033] In this embodiment, the method for forming the first cover layer 220 mainly includes: first, forming a full cover layer that covers the surface of the basic device structure (including the substrate 100 and the vertical stacked structure 200) and the protective layer 210; then, vertically etching the full cover layer to obtain the first cover layer 220, which covers the sidewall of the vertical stacked structure 200.
[0034] Corresponding to the two specific implementation schemes for forming the protective layer 210 in step S2, the specific implementation schemes for forming the first covering layer 220 in step S3 are as follows: Corresponding to the first implementation scheme, as shown in FIG2(D), since the protective layer 210 covers at least one bottom seed layer 201 in the vertical stacked structure 200, the first cover layer 220 covers the bottom seed layer 201 and top seed layer 202 in the vertical stacked structure 200 that are not covered by the protective layer 210.
[0035] Corresponding to the second implementation scheme, as shown in Figure 2(E), since the protective layer 210 covers the bottom seed layer 201 and the two seed layers (bottom seed layer 201 and top seed layer 202) in at least one vertical stacked structure 200, the first cover layer 220 covers the top seed layer 202 in the vertical stacked structure 200 that is not covered by the protective layer 210.
[0036] Furthermore, in this embodiment, step S4 involves removing the protective layer 210.
[0037] In practical applications, the protective layer 210 can be completely removed using an etching process. At this point, the seed layer that was originally covered by the protective layer 210 is exposed, while the remaining seed layers are still covered by the first capping layer 220.
[0038] Corresponding to the two specific implementation schemes for forming the first cover layer 220 in step S3, the specific implementation schemes for removing the protective layer 210 in step S4 are as follows: Corresponding to the first implementation scheme, as shown in Figure 2(F), after removing the protective layer 210, the bottom seed layer 201 in at least one vertical stacked structure 200 that was originally covered by the protective layer 210 is exposed, while the other seed layers are still covered by the first cover layer 220.
[0039] Corresponding to the second implementation scheme, as shown in Figure 2(G), after the protective layer 210 is removed, the bottom seed layer 201 and two seed layers (bottom seed layer 201 and top seed layer 202) in at least one vertical stacked structure 200 that were originally covered by the protective layer 210 are exposed, while the other seed layers (the top seed layer 202 in at least one vertical stacked structure 200) are still covered by the first cover layer 220.
[0040] Furthermore, in this embodiment, in step S5, the seed layer exposed after removing the protective layer 210 is epitaxially grown to obtain the first transistor 230.
[0041] Specifically, in this embodiment, all exposed seed layers in this step are epitaxially grown with the same type of source / drain. For example, SiGe source / drain are grown to make the first transistor 230 a P-type transistor; or, Si:P (phosphorus-doped silicon) source / drain are grown to make the first transistor 230 an N-type transistor.
[0042] Corresponding to the two specific implementation schemes for removing the protective layer 210 in step S4, the specific implementation schemes for obtaining the first transistor 230 in step S5 are as follows: Corresponding to the first implementation scheme, as shown in Figure 2(H), at least one bottom seed layer 201 in the vertical stacked structure 200 epitaxially grows a source drain to form a first transistor 230.
[0043] Corresponding to the second implementation scheme, as shown in Figure 2(I), at least one bottom seed layer 201 in the vertical stacked structure 200 and at least one two seed layers (bottom seed layer 201 and top seed layer 202) in the vertical stacked structure 200 are epitaxially grown to form the first transistor 230.
[0044] The specific implementation of epitaxial source and drain is something that those skilled in the art can obtain from existing complementary field-effect transistor manufacturing methods, and will not be elaborated further in this application.
[0045] Furthermore, in this embodiment, in step S6, a second cover layer 240 is formed, which covers the first transistor 230.
[0046] Specifically, in this embodiment, the material of the second capping layer 240 can be SiON, SiOC, SiOCN, etc., so that it has a different etching selectivity ratio than the vertical stacked structure 200, so that the vertical stacked structure 200 can be well preserved when the second capping layer 240 is removed. Of course, in practical applications, other materials with different etching selectivity ratios than the vertical stacked structure 200 can also be selected, which will not be elaborated on in this application.
[0047] Preferably, in order to simplify the process, a one-step etching process is used to expose the seed layer that was originally covered by the first cover layer 220 in order to form a source / drain. In this embodiment, the material of the first cover layer 220 is the same as the material of the second cover layer 240.
[0048] In this embodiment, the method for forming the second cover layer 240 mainly includes: first, depositing a cover material to cover the basic device structure, including the substrate 100, the surface of the vertical stacked structure 200, and the gap between the vertical stacked structure 200; then, etching away part of the cover material to obtain the second cover layer 240, which covers the first transistor 230. The second cover layer 240 can be obtained by photolithography etching process to remove part of the cover material.
[0049] Corresponding to the two specific implementation schemes for obtaining the first transistor 230 in step S5, the specific implementation schemes for forming the second cover layer 240 in step S6 are as follows: Corresponding to the first implementation scheme, as shown in Figure 2(J), the bottom seed layer 201 and the top seed layer 202, which were originally covered by the first cover layer 220, are exposed due to the etching process. At the same time, the first transistor 230 formed is covered by the second cover layer 240.
[0050] Corresponding to the second implementation scheme, as shown in Figure 2(K), the top seed layer 202, which was originally covered by the first capping layer 220, is exposed due to the etching process. At the same time, the first transistor 230 formed is covered by the second capping layer 240.
[0051] Furthermore, in this embodiment, step S7 involves epitaxially growing a source drain on the exposed seed layer to obtain a second transistor 250.
[0052] Specifically, in this embodiment, all exposed seed layers in this step are epitaxially grown with the same type of source / drain, and this type is different from the source / drain type epitaxially grown in step S5. For example, if step S5 grows SiGe source / drain to make the first transistor 230 a P-type transistor, then this step grows Si:P (phosphorus-doped silicon) source / drain to make the second transistor 250 an N-type transistor; or, if step S5 grows Si:P (phosphorus-doped silicon) source / drain to make the first transistor 230 an N-type transistor, then this step grows SiGe source / drain to make the second transistor 250 a P-type transistor.
[0053] Corresponding to the two specific implementation schemes for forming the second cover layer 240 in step S6, the specific implementation schemes for obtaining the second transistor 250 in step S7 are as follows: Corresponding to the first implementation scheme, as shown in Figure 2(L), the exposed bottom seed layer 201 and top seed layer 202 epitaxially grow source drains to form the second transistor 250, while the first transistor 230 formed is still covered by the second capping layer 240.
[0054] Corresponding to the second implementation scheme, as shown in Figure 2(M), the exposed top seed layer 202 epitaxially grows source and drain to form the second transistor 250, while the first transistor 230 formed is still covered by the second capping layer 240.
[0055] The specific implementation of epitaxial source and drain is something that those skilled in the art can obtain from existing complementary field-effect transistor manufacturing methods, and will not be elaborated further in this application.
[0056] Furthermore, in this embodiment, step S8 involves removing the second cover layer 240.
[0057] Specifically, the second capping layer 240 can be removed using an etching process to expose the first transistor 230. Since the second capping layer 240 and the vertical stacked structure 200 have different etching selectivity, the morphology of the vertical stacked structure 200 can be kept intact and the integrity of the device structure can be guaranteed when the second capping layer 240 is completely removed.
[0058] Corresponding to the two specific implementation schemes for the second transistor 250 in step S7, the specific implementation schemes for removing the second cover layer 240 in step S8 are as follows: Corresponding to the first implementation scheme, as shown in Figure 2(N), after removing the second cover layer 240, a first transistor 230 is formed at the bottom seed layer of at least one vertical stacked structure 200, and a second transistor 250 is formed at the remaining seed layers. Taking the device structure shown in Figure 2(N) as an example, the two seed layers of the vertical stacked structure 200 on the left side both form the second transistor 250, so that the gate-source-drain connections of the two second transistors are the same, forming a single-transistor transmission transistor, and realizing a doubling of the device's equivalent width; the two seed layers of the vertical stacked structure 200 on the right side form the first transistor 230 and the second transistor 250 respectively, which is the same as the existing vertical stacked structure of field-effect transistors, forming two transistors.
[0059] Corresponding to the second implementation scheme, as shown in Figure 2(O), after removing the second cover layer 240, a second transistor 250 is formed at the top seed layer of at least one vertical stacked structure 200, and a first transistor 230 is formed at the remaining seed layers. Taking the device structure shown in Figure 2(O) as an example, the first transistor 230 is formed in both the upper and lower seed layers of the vertical stacked structure 200 on the left, so that the gate-source-drain connections of the upper and lower first transistors are the same, forming a single-transistor transmission transistor, and realizing a doubling of the device's equivalent width; the first transistor 230 and the second transistor 250 are formed in the upper and lower seed layers of the vertical stacked structure 200 on the right, which is the same as the existing vertical stacked structure of field-effect transistors, forming two transistors.
[0060] In practical applications, after step S8, there may also be RMG (Replacement Metal Gate) process, metal interconnect layer process, etc. The specific process steps are well known to those skilled in the art, and this application will not elaborate on them.
[0061] It should be noted that the protective layer 210 and the first cover layer 220 in this embodiment should be made of different materials to give them different etching selectivity ratios, which facilitates the implementation of each process step. Furthermore, the materials of the protective layer 210, the first cover layer 220, and the second cover layer 240 should be different from the materials used in the vertical stacked structure 200, so that the vertical stacked structure 200 can be completely preserved when the protective layer 210, the first cover layer 220, and the second cover layer 240 are etched away, ensuring the integrity and effectiveness of the device structure.
[0062] Corresponding to the manufacturing method of the complementary field-effect transistor provided in this embodiment, this embodiment also provides a complementary field-effect transistor, the complementary field-effect transistor including a substrate 100 and at least two vertically stacked structures 200 formed on the substrate 100; each of the vertically stacked structures 200 includes two seed layers formed sequentially from bottom to top; at least two seed layers in at least one of the vertically stacked structures 200 are epitaxially grown with the same type of source and drain, and at least two seed layers in at least one of the vertically stacked structures 200 are epitaxially grown with different types of source and drain.
[0063] Specifically, corresponding to the first implementation scheme mentioned above, such as Figure 3 As shown, in at least one vertical stacked structure 200 of the complementary field-effect transistor, the upper and lower seed layers both form a second transistor 250, so that the gate-source-drain connections of the upper and lower second transistors are the same, forming a single-transistor transmission tube, and realizing a doubling of the device's equivalent width; in other vertical stacked structures 200, the upper and lower seed layers respectively form a first transistor 230 and a second transistor 250, which is the same as the vertical stacked structure of existing field-effect transistors, forming two transistors.
[0064] Corresponding to the second implementation scheme above, such as Figure 4 As shown, in at least one vertical stacked structure 200 of the complementary field-effect transistor, the upper and lower seed layers both form the first transistor 230, so that the gate-source-drain connections of the upper and lower first transistors are the same, forming a single-transistor transmission tube, and realizing the doubling of the device's equivalent width; in other vertical stacked structures 200, the upper and lower seed layers respectively form the first transistor 230 and the second transistor 250, which is the same as the vertical stacked structure of existing field-effect transistors, forming two transistors.
[0065] In practical applications, when the complementary field-effect transistors provided in this embodiment are used as storage cells of 6T SRAM, the number of vertical stacking structures 200 is 4; the two seed layers in the two vertical stacking structures 200 form transistors of the same type (both are first transistors 230 or both are second transistors 250) to obtain a single-transistor transmission tube, thereby making the 4 vertical stacking structures 200 of the complementary field-effect transistors have 6 equivalent transistors, that is, to obtain a 6T device structure.
[0066] Furthermore, this embodiment also provides a memory device including the complementary field-effect transistor described above.
[0067] Specifically, for a 6T SRAM, its memory cell can have four vertically stacked structures 200, where two vertically stacked structures 200 are arranged in a horizontal group, and another two vertically stacked structures 200 are also arranged in a horizontal group, with the two groups of vertically stacked structures 200 arranged centrally symmetrically. In each group, two seed layers in one of the vertically stacked structures 200 form transistors of the same type to form a single-transistor transmission transistor PG.
[0068] Of course, for other memory devices, the number of vertical stacked structures 200 and the number and distribution of transmission transistors PG forming a single transistor can be reasonably set according to actual needs, which will not be elaborated in this application.
[0069] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, different parts between embodiments can also be combined with each other, and this invention does not limit this.
[0070] This embodiment provides a complementary field-effect transistor (CFET) and its manufacturing method, as well as a memory device, comprising: providing a basic device structure, the basic device structure including at least two vertically stacked structures formed on a substrate, each of the vertically stacked structures including two seed layers formed sequentially from bottom to top; forming a protective layer covering at least one seed layer; forming a first capping layer covering the sidewalls of the vertically stacked structures; removing the protective layer; epitaxially growing a source / drain on the seed layer exposed after removing the protective layer to obtain a first transistor; forming a second capping layer covering the first transistor; epitaxially growing a source / drain on the exposed seed layer to obtain a second transistor; and removing the second capping layer. In this way, the two seed layers in at least one vertically stacked structure are epitaxially grown with different types of source / drain, while simultaneously ensuring that the two seed layers in at least one vertically stacked structure are epitaxially grown with the same type of source / drain, forming a single-transistor transport transistor, and doubling the device's equivalent width, thus solving the problem of how to manufacture memory cells with independent transport transistors based on a CFET structure.
[0071] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A method for manufacturing a complementary field-effect transistor, characterized in that, include: A basic device structure is provided, the basic device structure comprising at least two vertically stacked structures formed on a substrate, each of the vertically stacked structures comprising two seed layers formed sequentially from bottom to top; A protective layer is formed, the protective layer covering at least one seed layer; A first cover layer is formed, which covers the sidewalls of the vertically stacked structure; Remove the protective layer; The seed layer exposed after removing the protective layer is epitaxially grown to produce a source / drain transistor, thus obtaining the first transistor. A second capping layer is formed, which covers the first transistor; The exposed seed layer is epitaxially grown to produce a source-drain transistor, thus obtaining a second transistor. Remove the second overlay.
2. The method for manufacturing a complementary field-effect transistor according to claim 1, characterized in that, The protective layer is made of SOC material.
3. The method for manufacturing a complementary field-effect transistor according to claim 1, characterized in that, The method for forming the protective layer includes: Deposit protective materials to cover the underlying device structure; Etching removes part of the protective material to obtain a protective layer that covers the seed layer at the bottom of at least one vertically stacked structure.
4. The method for manufacturing a complementary field-effect transistor according to claim 1, characterized in that, The method for forming the protective layer includes: Deposit protective materials to cover the underlying device structure; Etching removes part of the protective material to obtain a protective layer that covers the bottom seed layer and two seed layers in at least one vertical stacked structure.
5. The method for manufacturing a complementary field-effect transistor according to claim 1, characterized in that, The first capping layer has a different etching selectivity than the protective layer and the vertical stacked structure; the second capping layer has a different etching selectivity than the vertical stacked structure.
6. The method for manufacturing a complementary field-effect transistor according to claim 1, characterized in that, The material of the first cover layer is the same as that of the second cover layer.
7. The method for manufacturing a complementary field-effect transistor according to claim 1, characterized in that, The method for forming the first covering layer includes: A full-coverage layer is formed, which covers the surface of the basic device structure and the protective layer; The full overlay is vertically etched to obtain a first overlay that covers the sidewalls of the vertically stacked structure.
8. The method for manufacturing a complementary field-effect transistor according to claim 1, characterized in that, The method for forming the second covering layer includes: Deposit a cover material to cover the underlying device structure; Etching removes part of the cover material to obtain a second cover layer, which covers the first transistor.
9. A complementary field-effect transistor, manufactured using the method for manufacturing a complementary field-effect transistor as described in any one of claims 1 to 8, characterized in that, The complementary field-effect transistor includes a substrate and at least two vertically stacked structures formed on the substrate; each of the vertically stacked structures includes two seed layers formed sequentially from bottom to top; at least one of the two seed layers in the vertically stacked structure has source and drain of the same type epitaxially grown, and at least one of the two seed layers in the vertically stacked structure has source and drain of different types epitaxially grown.
10. A storage device, characterized in that, Including the complementary field-effect transistor as described in claim 9.