Array substrate, display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate, an active layer and a multilayer conductive layer which are arranged on one side of the substrate in a laminated manner, the active layer and the multilayer conductive layer form a plurality of pixel circuits, the plurality of pixel circuits are configured to be sequentially scanned along a second direction in order, the pixel circuit comprises a driving transistor, a data writing transistor, a first leakage suppression transistor and a first capacitor, a first end of the first capacitor is electrically connected with a first electrode of the first leakage suppression transistor, the multilayer conductive layer forms a plurality of first preset signal lines and a plurality of first scan lines, a control electrode of the data writing transistor is electrically connected with one of the first scan lines, and a second end of the first capacitor is electrically connected with one of the first preset signal lines, wherein the first preset signal line corresponding to the pixel circuit is electrically connected with the first scan line corresponding to a pixel circuit in a next scanning order. The application can reduce the frame of the array substrate.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the advancement of display technology, the application of array substrates is becoming more and more widespread, and the requirements for array substrates are correspondingly becoming more and more stringent.

[0003] However, the array substrates in related technologies have issues that need further improvement, such as large bezels. Summary of the Invention

[0004] The present invention provides an array substrate and a display substrate to reduce the bezel of the array substrate.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate comprising a substrate; an active layer and multiple conductive layers stacked on one side of the substrate; The active layer and the multilayer conductive layer form a plurality of pixel circuits, which are arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; the plurality of pixel circuits are configured to scan sequentially along the second direction; each pixel circuit includes a driving transistor, a data writing transistor, a first leakage current suppression transistor, and a first capacitor; the first terminal of the first capacitor is electrically connected to the first electrode of the first leakage current suppression transistor, and the second electrode of the first leakage current suppression transistor is electrically connected to the control electrode of the driving transistor; The multilayer conductive layer is formed with a plurality of first preset signal lines arranged along the second direction and a plurality of first scan lines arranged along the second direction; the control electrode of the data writing transistor is electrically connected to one of the first scan lines, and the second end of the first capacitor is electrically connected to one of the first preset signal lines; wherein, the first preset signal line corresponding to the pixel circuit is electrically connected to the first scan line corresponding to the pixel circuit in the next scanning sequence.

[0006] Optionally, the array substrate includes a display area and a non-display area at least partially surrounding the display area, the pixel circuit being located in the display area; the first scan line extending from the display area to the non-display area, and the first preset signal line extending from the display area to the non-display area; the connection point between the first preset signal line and the first scan line is located in the non-display area. Preferably, the array substrate includes a gate driving circuit located in the non-display area, and the gate driving circuit is electrically connected to the first scan line and the first preset signal line.

[0007] Optionally, the pixel circuit further includes a first initialization transistor, the first terminal of which is electrically connected to the first terminal of the driving transistor; the first terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor. The multilayer conductive layer is further formed with a plurality of second preset signal lines arranged along the second direction and a plurality of first enable signal lines arranged along the second direction; the control electrode of the first leakage current suppression transistor is electrically connected to one of the first enable signal lines, and the second electrode of the first initialization transistor is electrically connected to one of the second preset signal lines. Any two of the first preset signal line, the second preset signal line, and the first enable signal line are configured in different layers; Preferably, the multilayer conductive layer includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked on the side of the active layer away from the substrate; the first enable signal line is located in the first conductive layer, the first preset signal line is located in the second conductive layer, and the second preset signal line is located in the third conductive layer; Preferably, the first preset signal line includes a first capacitor plate and a first trace connected to the first capacitor plate, wherein the first capacitor plate overlaps with the active layer to form the first capacitor; along the second direction, the size of the first capacitor plate is larger than the size of the first trace. Preferably, the second preset signal line includes a second trace and a third trace connected to the second trace; along the second direction, the second trace corresponding to the pixel circuit in the previous scanning sequence is located between the first trace corresponding to the pixel circuit in the current scanning sequence and the first enable signal line; along the thickness direction of the array substrate, the orthographic projection of the third trace on the substrate is located outside the orthographic projection of the first capacitor plate on the substrate, and overlaps with the orthographic projection portion of the first enable signal line on the substrate.

[0008] Optionally, two adjacent pixel circuits along the first direction are mirror-symmetrical; Preferably, the pixel circuit further includes a second initialization transistor, which is used to initialize the control electrode of the driving transistor; the multilayer conductive layer also forms a plurality of first initialization lines arranged along the first direction; the first initialization lines are located at the center of the overall structure formed by two adjacent pixel circuits and are electrically connected to the second initialization transistors in the two adjacent pixel circuits. Preferably, the multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the side of the active layer away from the substrate; the first initialization line is located in the fourth conductive layer.

[0009] Optionally, the pixel circuit further includes a second leakage current suppression transistor, wherein the first terminal of the second leakage current suppression transistor is electrically connected to the first terminal of the first leakage current suppression transistor, and the control terminal of the second leakage current suppression transistor is electrically connected to the control terminal of the first leakage current suppression transistor; the channel length of the first leakage current suppression transistor is greater than the channel length of the second leakage current suppression transistor, and the channel width of the first leakage current suppression transistor is greater than the channel width of the second leakage current suppression transistor. Preferably, the difference between the channel length of the first leakage current suppression transistor and the channel length of the second leakage current suppression transistor is in the range of 2.5 micrometers to 3 micrometers; and / or, the difference between the channel width of the first leakage current suppression transistor and the channel length width of the second leakage current suppression transistor is in the range of 1.5 micrometers to 2 micrometers.

[0010] Optionally, the multilayer conductive layer further forms a plurality of first power sub-lines arranged along the first direction, and the first electrode of the driving transistor is electrically connected to the first power sub-lines; the multilayer conductive layer further forms a first interconnect line, the control electrode of the driving transistor is connected to one end of the first interconnect line, and the second electrode of the first leakage current suppression transistor is connected to the other end of the first interconnect line. Along the thickness direction of the array substrate, the orthographic projection of the first interconnect line on the substrate lies within the orthographic projection of the first power sub-line on the substrate; Preferably, the minimum distance between the boundary of the orthographic projection of the first interconnect line on the substrate and the boundary of the orthographic projection of the first power sub-line on the substrate is greater than or equal to 0.5 micrometers.

[0011] Optionally, the pixel circuit further includes a second capacitor, the first end of which is electrically connected to the first power supply sub-line, and the second end of which is electrically connected to the control electrode of the driving transistor. The multilayer conductive layer further forms multiple second capacitor plates and multiple second power sub-lines arranged along the second direction; the second power sub-lines are electrically connected to the first power sub-lines; any two of the second capacitor plates, the second power sub-lines, and the first power sub-lines are disposed in different layers; along the thickness direction of the array substrate, the orthographic projection of the channel of the driving transistor on the substrate is located within the orthographic projection of the second capacitor plate on the substrate; the second power sub-lines and the second capacitor plates overlap to form the second capacitor; The first interconnect includes a first sub-section and a second sub-section; along the thickness direction of the array substrate, the orthographic projection of the first sub-section on the substrate is located within the outer contour of the orthographic projection of the second power sub-line on the substrate, and the orthographic projection of the second sub-section on the substrate is located outside the outer contour of the orthographic projection of the second power sub-line on the substrate; the dimension of the first sub-section in the first direction is greater than the dimension of the second sub-section in the first direction. Preferably, the difference between the dimension of the first sub-part in the first direction and the dimension of the second sub-part in the first direction is in the range of 0.2 micrometers to 0.5 micrometers; Preferably, the multilayer conductive layer further forms a plurality of data lines arranged along the first direction, and the first electrode of the data writing transistor is electrically connected to one of the data lines; the portion of the driving transistor located in the active layer includes a conductive channel, a first electrode contact portion, and a first electrode lead-out portion, the first electrode contact portion being connected to the data line, and the first electrode lead-out portion being connected to the first electrode contact portion and the conductive channel; along the thickness direction of the array substrate, the orthographic projection of the first electrode lead-out portion on the substrate is located outside the orthographic projection of the data line on the substrate; and / or, along the thickness direction of the array substrate, the orthographic projection of the first electrode lead-out portion on the substrate at least partially overlaps with the orthographic projection of the second power sub-line on the substrate.

[0012] Optionally, the pixel circuit further includes a third initialization transistor, which is used to initialize the light-emitting unit corresponding to the pixel circuit; the multilayer conductive layer also forms a plurality of second initialization lines arranged along the second direction; The multilayer conductive layer is further formed with a second interconnect line extending along the second direction. One end of the second interconnect line is connected to the second initialization line through an interconnect hole, and the other end of the second interconnect line is connected to the third initialization transistor. Along the thickness direction of the array substrate, the orthographic projection of the second interconnect line on the substrate at least partially overlaps with the orthographic projection of the first initialization line on the substrate. The second initialization line includes a connection portion connected to the interconnect hole. Along the thickness direction of the array substrate, the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection portion of the active layer on the substrate.

[0013] Optionally, the pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor, wherein the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor; the multilayer conductive layer further forms a plurality of second enable signal lines arranged along the second direction, and the control electrodes of the first light-emitting control transistor and the second light-emitting control transistor are electrically connected to one of the second enable signal lines. The multilayer conductive layer also forms a third interconnect line extending along the second direction; along the thickness direction of the array substrate, the orthographic projection of the third interconnect line on the substrate intersects the orthographic projection of the second enable signal line on the substrate; the first electrode of the driving transistor is connected to one end of the third interconnect line, and the first electrode of the first light-emitting control transistor is connected to the second end of the third interconnect line.

[0014] According to another aspect of the present invention, a display panel is provided, the display panel comprising an array substrate as described in any of the preceding claims.

[0015] The technical solution of this invention uses an array substrate comprising a substrate; an active layer and multiple conductive layers stacked on one side of the substrate; multiple pixel circuits formed in the active layer and multiple conductive layers, the multiple pixel circuits being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; the multiple pixel circuits being configured to scan sequentially along the second direction; each pixel circuit comprising a driving transistor, a data writing transistor, a first leakage current suppression transistor, and a first capacitor; a first terminal of the first capacitor being electrically connected to a first electrode of the first leakage current suppression transistor, and a second electrode of the first leakage current suppression transistor being electrically connected to a control electrode of the driving transistor; multiple first preset signal lines arranged along the second direction and multiple first scan lines arranged along the second direction formed in the multiple conductive layers; a control electrode of the data writing transistor being electrically connected to a first scan line, and a second terminal of the first capacitor being electrically connected to a first preset signal line; wherein, the first preset signal line corresponding to a pixel circuit is electrically connected to the first scan line corresponding to a pixel circuit in the next scanning sequence. Since the first preset signal line is electrically connected to the first scan line of the next scan sequence, the first preset signal line can share a set of gate driving circuits with the first scan line, thereby reducing the gate driving circuit required by the array substrate and reducing the bezel of the array substrate.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention; Figure 2 A schematic diagram of a pixel circuit structure provided in an embodiment of the present invention; Figure 3 A timing diagram of a pixel circuit provided in an embodiment of the present invention; Figure 4 A top view of a repeating cell in an array substrate provided in an embodiment of the present invention; Figure 5 A bottom view of a repeating cell in an array substrate provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of an active layer structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure of a first conductive layer provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a second conductive layer provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a third conductive layer provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a fourth conductive layer provided in an embodiment of the present invention; Figure 11 for Figure 1 A magnified view of a portion of the image. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] Figure 1 This is a schematic diagram of an array substrate provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel circuit structure provided in an embodiment of the present invention. Figure 3 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention. Figure 4 This is a top view of a repeating cell in an array substrate provided in an embodiment of the present invention. Figure 5 This is a bottom view of a repeating cell in an array substrate provided in an embodiment of the present invention, with reference to... Figures 1 to 5 . The array substrate includes a substrate, an active layer Psi stacked on one side of the substrate, and multiple conductive layers. The active layer Psi and the multiple conductive layers form multiple pixel circuits Px, which are arranged in an array along a first direction X and a second direction Y, with the first direction X intersecting the second direction Y. The multiple pixel circuits Px are configured to be scanned sequentially along the second direction Y. Each pixel circuit includes a driving transistor T1, a data writing transistor T2, a first leakage current suppression transistor T8, and a first capacitor C1. The first terminal of the first capacitor C1 is electrically connected to the first electrode of the first leakage current suppression transistor T8, and the second electrode of the first leakage current suppression transistor T8 is electrically connected to the control electrode of the driving transistor T1. The multiple conductive layers form multiple first preset signal lines Vx arranged along the second direction Y, and multiple first scan lines S2 arranged along the second direction Y. The control electrode of the data writing transistor T2 is electrically connected to one of the first scan lines S2, and the second terminal of the first capacitor C1 is electrically connected to one of the first preset signal lines Vx. The first preset signal line Vx corresponding to a pixel circuit is electrically connected to the first scan line S2 corresponding to the pixel circuit in the next scanning sequence.

[0022] Specifically, the array substrate can be used to fabricate a display panel. For example, after fabricating corresponding light-emitting units on the array substrate, a display panel can be formed. It is understood that the display panel may also include structures such as an encapsulation layer. The substrate in the array substrate can be a rigid substrate or a flexible substrate. Rigid substrates are, for example, silicon, diamond, or sapphire substrates, while flexible substrates are, for example, polyimide substrates. The active layer Psi is disposed on one side of the substrate and can be used to form the conductive channels of each transistor in the pixel circuit. The conductive layer has conductive structures that form at least one of the following: gate, source, drain, capacitor, internal interconnects in the pixel circuit, and various signal lines required to drive the pixel circuit.

[0023] Pixel circuits Px are formed within an active layer Psi and multiple conductive layers. Each pixel circuit Px can drive at least one light-emitting unit, which can be an OLED (Organic Light Emitting Diode), Micro LED (Micro Light Emitting Diode), or Mini LED (Mini Light Emitting Diode), etc. Multiple pixel circuits Px are arranged in an array along a first direction X and a second direction Y, where X is, for example, a row direction and Y is, for example, a column direction. Within one frame, the pixel circuits Px are scanned sequentially along the second direction Y; that is, within the same frame, pixel circuits Px scanned earlier in the scan sequence are scanned first, and those scanned later are scanned later. In some embodiments, the scan order can be understood as the order in which data is written, or it can be understood as the order in which light emission begins, etc. The scan order of pixel circuits Px in the same row is the same, meaning the array substrate is driven in a row-scan manner.

[0024] like Figure 2 and Figure 3 As shown, in the pixel circuit Px, the driving transistor T1 generates a corresponding driving current based on the voltage of its control electrode, and the light-emitting unit can emit light in response to this driving current. The data writing transistor T2 is used to write data voltage to the driving transistor. Different data voltages can control the driving transistor T1 to generate different driving currents, thereby causing the light-emitting unit to emit light of different brightness. The pixel circuit Px also includes a first capacitor C1 and a first leakage suppression transistor T8. The first capacitor C1 can maintain the first electrode of the first leakage suppression transistor T8 at a stable potential during the light-emitting phase, thereby preventing the control electrode potential of the driving transistor T1 from being unable to be maintained due to leakage. In other words, by setting the first capacitor C1 and the first leakage suppression transistor T8, the leakage problem of the control electrode of the driving transistor T1 can be improved, resulting in better display performance of the light-emitting unit at low frequencies.

[0025] The second terminal of the first capacitor C1 is connected to a first preset signal line Vx. The first preset signal line Vx is used to provide the required signal to the first capacitor C1, such as providing an AC signal after the data writing stage and before the light emission stage, to ensure that a stable potential can be coupled to the first electrode of the first leakage current suppression transistor T8 before the light emission stage, so that the potential of the first electrode of the first leakage current suppression transistor T8 is stable during the light emission stage.

[0026] The first preset signal line Vx extends along the first direction X, and multiple first preset signal lines Vx are arranged along the second direction Y. Furthermore, a first scan line S2 extending along the first direction X is formed in the multilayer conductive layer. The data writing transistor T2 can be turned on under the control of the scan signal on the first scan line S2, thereby writing the data voltage to the driving transistor. In this embodiment, the first preset signal line Vx corresponding to the pixel circuit in the current row is electrically connected to the first scan line corresponding to the pixel circuit in the next scan sequence; in other words, the signal on the first preset signal line Vx is the same as the signal on the first scan line S2 corresponding to the pixel circuit in the next scan sequence. In this embodiment, since the pixel circuits are scanned row by row, the first preset signal line Vx corresponding to the pixel circuit in the current row is electrically connected to the first scan line S2 corresponding to the pixel circuit in the next row. The "previous row" and "next row" mentioned in this embodiment refer to the previous row and the next row in the scanning sequence. Since the data writing stage of the next row pixel circuit Px is after the data writing stage of the current row pixel circuit Px and before the light emission stage of the current row pixel circuit Px, the first scan line S2 corresponding to the next row pixel circuit Px can provide an AC signal after the data writing stage and before the light emission stage of the current row, that is, it can be electrically connected to the first preset signal line Vx.

[0027] Furthermore, in this embodiment, the first preset signal line Vx and the first scan line S2 are different signal lines, which is more conducive to the electrical connection between the first preset signal line Vx and the corresponding first capacitor, and thus more conducive to the wiring of the pixel circuit. Moreover, the first preset signal line Vx is electrically connected to the first scan line S2 of the next scanning sequence. Therefore, the first preset signal line Vx can share a set of gate driving circuits for providing scanning signals with the first scan line S2. In other words, one less set of gate driving circuits can be provided on the array substrate, thereby greatly reducing the bezel of the array substrate.

[0028] The technical solution of this embodiment uses an array substrate including a substrate; an active layer and multiple conductive layers stacked on one side of the substrate; multiple pixel circuits formed in the active layer and multiple conductive layers, the multiple pixel circuits being arranged in an array along a first direction and a second direction, the first direction intersecting the second direction; the multiple pixel circuits being configured to scan sequentially along the second direction; each pixel circuit including a driving transistor, a data writing transistor, a first leakage suppression transistor, and a first capacitor; the first terminal of the first capacitor being electrically connected to the first electrode of the first leakage suppression transistor, and the second electrode of the first leakage suppression transistor being electrically connected to the control electrode of the driving transistor; multiple first preset signal lines arranged along the second direction and multiple first scan lines arranged along the second direction being formed in the multiple conductive layers; the control electrode of the data writing transistor being electrically connected to a first scan line, and the second terminal of the first capacitor being electrically connected to a first preset signal line; wherein, the first preset signal line corresponding to the pixel circuit is electrically connected to the first scan line corresponding to the pixel circuit in the next scanning sequence. Since the first preset signal line is electrically connected to the first scan line of the next scan sequence, the first preset signal line can share a set of gate driving circuits with the first scan line, thereby reducing the gate driving circuit required by the array substrate and reducing the bezel of the array substrate.

[0029] Optionally, such as Figure 2 As shown, the pixel circuit may specifically include a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a second initialization transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a third initialization transistor T7, a first leakage current suppression transistor T8, a second leakage current suppression transistor T9, a third leakage current suppression transistor T10, a first initialization transistor T11, a first capacitor C1, and a second capacitor Cst.

[0030] The first terminal of the data writing transistor T2 is electrically connected to the first terminal of the driving transistor T1, the second terminal of the data writing transistor T2 is electrically connected to the data line Vdata, and the control terminal of the data writing transistor T2 is electrically connected to the first scan line S2. The first terminal of the threshold compensation transistor T3 is electrically connected to the second terminal of the driving transistor T1, the second terminal of the threshold compensation transistor T3 is electrically connected to the first terminal of the second leakage current suppression transistor, and the control terminal of the threshold compensation transistor T3 is electrically connected to the first scan line S2. The first terminal of the second initialization transistor T4 is electrically connected to the first initialization line Vref1, the second terminal of the second initialization transistor T4 is electrically connected to the first terminal of the third leakage current suppression transistor T10, and the control terminal of the second initialization transistor T4 is electrically connected to the second scan line S1. The first terminal of the first light-emitting control transistor T5 is electrically connected to the first power supply line VDD, the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the driving transistor T1, and the control terminal of the first light-emitting control transistor T5 is electrically connected to the second enable signal line EM. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T1, the second terminal of the second light-emitting control transistor T6 is electrically connected to the first terminal of the light-emitting unit, and the control terminal of the second light-emitting control transistor T6 is electrically connected to the second enable signal line EM. The first terminal of the third initialization transistor T7 is electrically connected to the second initialization line Vref2, the second terminal of the third initialization transistor T7 is electrically connected to the first terminal of the light-emitting unit, and the control terminal of the third initialization transistor T7 is electrically connected to the third scan line S3.

[0031] The first terminal of the first leakage current suppression transistor T8 is also electrically connected to the second terminal of the second leakage current suppression transistor T9 and the second terminal of the third leakage current suppression transistor T10; the control terminals of the first leakage current suppression transistor T8, the second leakage current suppression transistor T9, and the third leakage current suppression transistor T10 are all electrically connected to the first enable signal line EMB.

[0032] The second terminal of the first initialization transistor T11 is electrically connected to the second preset signal line VEH, the first terminal of the first initialization transistor T11 is electrically connected to the first terminal of the driving transistor T1, and the control terminal of the first initialization transistor T11 is electrically connected to the third scan line S3.

[0033] The first terminal of the second capacitor Cst is electrically connected to the first power supply line VDD, and the second terminal of the second capacitor Cst is electrically connected to the control electrode of the driving transistor T1. The second terminal of the light-emitting unit is electrically connected to the second power supply line VSS.

[0034] In each of the above transistors, one of the first and second terminals is the source, and the other is the drain; the control terminal of each transistor is the gate.

[0035] The operation of the pixel circuit includes a first reset stage t1, a data writing stage t2, a leakage current suppression writing stage t3, a second reset stage t5, and a light emission stage t6.

[0036] In the first reset phase t1, the signal on the first enable signal line EMB controls the first leakage current suppression transistor T8 and the third leakage current suppression transistor T10 to turn on, and the second scan line S2 controls the second initialization transistor T4 to turn on. At this time, the signal on the first initialization line Vref1 is written to the control terminal of the driving transistor T1, and the signal of the control terminal of the driving transistor T1 is reset.

[0037] During the data writing phase t2, the signal on the first enable signal line EMB controls the first leakage current suppression transistor T8 and the second leakage current suppression transistor T9 to turn on, while the signal on the first scan line S2 controls the data writing transistor T2 and the threshold compensation transistor T3 to turn on. At this time, the data voltage on the data line Vdata is written to the control electrode of the driving transistor T1 after passing through the data writing transistor T2, the driving transistor T1, the threshold compensation transistor T3, the second leakage current suppression transistor T9, and the first leakage current suppression transistor T8. When the potential difference between the control electrode of the driving transistor T1 and the first electrode of the driving transistor T1 is equal to the threshold voltage of the driving transistor T1, the driving transistor T1 is turned off. At this time, the potential of the control electrode of the driving transistor T1 contains the threshold voltage information of the driving transistor T1.

[0038] During the leakage current suppression writing stage t3, the first preset signal line Vx provides an AC signal to the first capacitor C1, so that the first electrode potential of the first leakage current suppression transistor T8 remains stable after the leakage current suppression writing stage t3 ends.

[0039] During the second reset phase t4, the signal on the third scan line S3 controls the first initialization transistor T11 and the third initialization transistor T7 to turn on, completing the reset of the first terminal of the driving transistor T1 and the first terminal of the light-emitting unit.

[0040] During the light-emitting stage t5, the second enable signal line EM controls the first light-emitting control transistor T5 and the second light-emitting control transistor T6 to turn on, driving transistor T1 to generate a driving current, and the light-emitting unit responds to the driving current to emit light.

[0041] Optionally, in the above embodiment, the signal provided by the first scan line S2 within one frame time can be a multi-pulse signal, and there are multiple pulses in the leakage current suppression writing stage t3, so that the signal can be better written to the first electrode of the first leakage current suppression transistor T8, and the potential of the first electrode of the first leakage current suppression transistor T8 is stable during the light emission stage.

[0042] Optionally, the array substrate includes a display area and a non-display area that at least partially surrounds the display area, and the pixel circuit Px is located in the display area; the first scan line S2 extends from the display area to the non-display area, and the first preset signal line Vx extends from the display area to the non-display area; the connection position between the first preset signal line Vx and the first scan line S2 is located in the non-display area.

[0043] Specifically, a gate driving circuit for providing scanning signals is disposed in the non-display area of ​​the array substrate. The gate driving circuit is electrically connected to the first scan line S2 and the first preset signal line Vx. In other words, the first scan line S2 and the first preset signal line Vx can be driven using the same set of gate driving circuits, thereby saving one set of gate driving circuits and reducing the bezel size. At the same time, the connection position of the first scan line S2 and the first preset signal line Vx is located in the non-display area, which avoids occupying space in the display area, thus facilitating wiring in the display area and increasing pixel density.

[0044] It should be noted that in this embodiment, the third scan line S3 corresponding to the current row pixel circuit is multiplexed as the second scan line S1 corresponding to the next row pixel circuit. The array substrate can be understood as being arranged in an array based on the repeating unit CF. In the repeating unit CF, the first initialization transistor T11 and the third initialization transistor T7 belong to the previous row pixel circuit.

[0045] Optionally, refer to Figure 1 The multilayer conductive layer also forms multiple second preset signal lines VEH arranged along the second direction Y and multiple first enable signal lines EMB arranged along the second direction Y; the second preset signal lines VEH extend along the first direction X, and the first enable signal lines EMB extend along the first direction; any two of the first preset signal lines Vx, the second preset signal lines VEH and the first enable signal lines EMB are arranged in different layers.

[0046] Specifically, any two of the first preset signal line Vx, the second preset signal line VEH, and the first enable signal line EMB are located on different conductive layers. In this embodiment, the multilayer conductive layer includes at least three conductive layers to respectively house the above three types of signal lines. Since the first preset signal line Vx, the second preset signal line VEH, and the first enable signal line EMB all extend in the same direction, if signal lines are arranged on the same layer, winding is required and a larger spacing is needed in the second direction. By setting any two on different layers, winding can be reduced to lower the wiring difficulty; and the spacing between any two can be reduced in the second direction Y, thereby saving space in the second direction, i.e., the column direction, and further increasing the pixel density of the array substrate.

[0047] Optionally, continue to refer to Figure 1 , Figure 4 and Figure 5 The multilayer conductive layer includes a first conductive layer M1, a second conductive layer M2, and a third conductive layer M3 sequentially stacked on the side of the active layer Psi away from the substrate; the first enable signal line EMB is located in the first conductive layer, the first preset signal line Vx is located in the second conductive layer M2, and the second preset signal line VEH is located in the third conductive layer M3.

[0048] Specifically, the material of the first conductive layer M1 can be metallic Mo, the material of the second conductive layer M2 can be metallic Mo, and the material of the third conductive layer M3 can be a Ti / Al / Ti stacked structure. The first enable signal line EMB can overlap with the active layer Psi to form the control electrode of the first leakage current suppression transistor T8, the control electrode of the second leakage current suppression transistor T9, and the control electrode of the third leakage current suppression transistor T10. Setting the first enable signal line EMB in the first conductive layer M1 can improve the control capability of each transistor. Setting the first preset signal line Vx in the second conductive layer M2 can, on the one hand, make the distance between the first preset signal line Vx and the active layer Psi closer, which is beneficial to increasing the capacitance value of the first capacitor C1; on the other hand, the second conductive layer M2 has more space to set the first preset signal line Vx, so that the first preset signal line Vx can have a larger size, which can also increase the capacitance value of the first capacitor C1. In this embodiment, the first scan line S2, the second scan line S1, and the third scan line S3 are all disposed in the first conductive layer M1. Each scan line needs to form the control electrode of the corresponding transistor. Disposing of them in the first conductive layer M1 can improve the control capability of the conductive channel of the transistor. In this embodiment, the first preset signal line Vx is disposed in the second conductive layer M2, that is, the first preset signal line Vx and the first scan line S2 are disposed in different layers.

[0049] Optionally, Figure 6 This is a schematic diagram of an active layer structure provided in an embodiment of the present invention. Figure 7 This is a schematic diagram of the structure of a first conductive layer provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of a second conductive layer provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of the structure of a third conductive layer provided in an embodiment of the present invention. Figure 10 This is a schematic diagram of a fourth conductive layer provided in an embodiment of the present invention. (Reference) Figures 4 to 10 The first preset signal line Vx includes a first capacitor plate Vx1 and a first trace Vx2 connected to the first capacitor plate Vx1. The first capacitor plate Vx1 overlaps with the active layer Psi to form a first capacitor C1. Along the second direction Y, the size of the first capacitor plate Vx1 is larger than the size of the first trace Vx2.

[0050] Specifically, in this embodiment, the first preset signal line Vx1 comprises two parts: a first capacitor plate Vx1 and a first trace Vx2. The first trace Vx2 and the first capacitor plate Vx1 are connected in series to form the first preset signal line Vx1. The first capacitor plate Vx1 is the part that needs to overlap with the active layer Psi to form the first capacitor C1. In this embodiment, it is disposed in the second direction Y. The size of the first capacitor plate Vx1 is larger than the size of the first trace Vx1, that is, the width of the first capacitor plate Vx1 is larger, which is beneficial to increasing the capacitance value of the first capacitor C1, thereby increasing the ability of the first capacitor C1 to maintain a stable potential. In addition, the width of the first trace Vx2 is smaller, which is also beneficial to reducing the space required for the first preset signal line Vx1 as a whole, thereby increasing the pixel density of the array substrate. It can be understood that the part of the active layer Psi that overlaps with the first capacitor plate Vx2 can also be provided with a larger width to form the first capacitor C1 with a larger capacitance value.

[0051] Optionally, refer to Figure 4 and Figure 9 The second preset signal line VEH includes a second trace VEH1 and a third trace VEH2 connected to the second trace VEH1; along the second direction Y, the second trace VEH1 corresponding to the pixel circuit Px of the previous scanning sequence is located between the first trace Vx2 corresponding to the pixel circuit Px of the current scanning sequence and the first enable signal line EMB; along the thickness direction of the array substrate, the orthographic projection of the third trace VEH2 on the substrate is located outside the orthographic projection of the first capacitor plate Vx1 on the substrate, and overlaps with the orthographic projection of the first enable signal line EMB on the substrate.

[0052] Specifically, in this embodiment, the second preset signal line VEH is wound around the corresponding position of the first capacitor plate Vx1 and partially overlaps with the first enable signal line EMB; that is, the third trace VEH2 is wound around to the outside of the first capacitor plate Vx1, and the third trace VEH2 is set to partially overlap with the first enable signal line EMB. With this arrangement, in the second direction Y, the arrangement of the first preset signal line Vx, the second preset signal line VEH, and the first enable signal line EMB can be relatively compact, that is, the whole of the three occupies less space in the second direction Y, which can save space of the array substrate in the second direction Y to increase pixel density; furthermore, it can avoid the second preset signal line VEH from overlapping with the first capacitor C1 while increasing pixel density, thus avoiding affecting the stability of the signal on the first capacitor C1. Or in other words, the effect of adding a new first preset signal line Vx can be achieved without increasing the space of the array substrate in the second direction Y. Furthermore, since the potential on the second preset signal line VEH is fixed, and the second preset signal line VEH is located between the first enable signal line EMB and the first terminal of the second leakage current suppression transistor T9, and also between the first enable signal line EMB and the second leakage current suppression transistor T9, the parasitic capacitance between the first enable signal line EMB and the first terminal of the second leakage current suppression transistor T9, as well as the parasitic capacitance between the first enable signal line EMB and the second terminal of the second leakage current suppression transistor T9, can be reduced, thereby improving problems such as crosstalk in the first direction X.

[0053] Optionally, refer to Figure 1 The two adjacent pixel circuits Px along the first direction X are mirror symmetrical.

[0054] Specifically, along the first direction X, any two adjacent pixel circuits Px are mirror-symmetrical about the center line between them; at this time, the parts of two adjacent pixel circuits that need to access the same signal on the first direction X can be set adjacently, and thus can share a signal line (such as sharing a first initialization line Vref1), which can reduce the number of signal lines required and save the space required by the array substrate on the first direction X, that is, it can increase the pixel density.

[0055] Optionally, in some embodiments, in two adjacent columns of pixel circuits Px, one column of driven light-emitting units includes red light-emitting units and blue light-emitting units; the other column of driven light-emitting units includes green light-emitting units.

[0056] Optionally, refer to Figure 1The pixel circuit also includes a second initialization transistor T4; a first initialization line Vref1 extends along the second direction Y, and multiple first initialization lines Vref1 are arranged along the first direction X; the first initialization line Vref1 is located at the center of the overall structure formed by two adjacent pixel circuits and is electrically connected to the second initialization transistors in the two adjacent pixel circuits.

[0057] Specifically, the repeating units CF in the array substrate are arranged in an array, and two adjacent repeating units CF in the first direction X are also mirror-symmetrical. Two adjacent repeating units CF in the first direction X can form a repeating module, and the array substrate is arranged in an array with repeating modules CF as units. Each column of repeating modules corresponds to a first initialization line Vref1, and in the first direction X, the first initialization line Vref1 is located at the center of the repeating module. The second initialization transistor T7 in two adjacent pixel circuits Px is electrically connected to the same first initialization line Vref1, which can reduce the number of first initialization lines Vref1 required, thereby increasing the pixel density.

[0058] Furthermore, such as Figure 1 As shown, in the same repeating module, two second initialization transistors T7 are connected to the first initialization line Vref1 through the same via, which can reduce the number of vias, reduce process costs, and increase pixel density.

[0059] Optionally, refer to Figure 1 and Figure 10 The first initialization line Vref1 is located in the fourth conductive layer M4. The first initialization line Vref1 extends along the second direction Y and is located in the fourth conductive layer M4, which can avoid overlapping with the signal line extending along the first direction X, thus making it more convenient for the routing of the first initialization line Vref1.

[0060] Optionally, refer to Figure 4 , Figure 5 and Figure 6 The channel length of the first leakage current suppression transistor T8 is greater than the channel length of the second leakage current suppression transistor T9; the channel width of the first leakage current suppression transistor T8 is greater than the channel width of the second leakage current suppression transistor T9. In some embodiments, optionally, the difference between the channel length of the first leakage current suppression transistor T8 and the channel length of the second leakage current suppression transistor T9 is in the range of 2.5 micrometers to 3 micrometers; and / or, the difference between the channel width of the first leakage current suppression transistor T8 and the channel width of the second leakage current suppression transistor T9 is in the range of 1.5 micrometers to 2 micrometers.

[0061] Specifically, the first leakage current suppression transistor T8 is directly connected to the control electrode of the driving transistor T1. By setting the first leakage current suppression transistor T8 to have a larger channel length and a larger channel width, the leakage current of the first leakage current suppression transistor T8 can be reduced. This prevents the problem of leakage current from the control electrode of the driving transistor T1 to the first electrode of the first leakage current suppression transistor T8 after the potential of the first electrode of the first preset signal line Vx is coupled downwards, thus preventing the light-emitting unit from producing a bright spot.

[0062] Optionally, such as Figure 4 As shown, the channel length direction of the first leakage current suppression transistor T8 and the channel length direction of the second leakage current suppression transistor T9 can be set to the second direction. The portion of the first capacitor C1 located in the active layer Psi extends along the first direction X. The channel of the first leakage current suppression transistor T8, the portion of the first capacitor C1 located in the active layer Psi, and the channel of the second leakage current suppression transistor T9 are generally shaped like a "π".

[0063] Optionally, refer to Figure 4 , Figure 9 and Figure 10 The multilayer conductive layer also forms multiple first power sub-lines VDD1 arranged along the first direction X. The first electrode of the driving transistor T1 is electrically connected to the first power sub-line VDD1 through the first light-emitting control transistor T5. The multilayer conductive layer also forms a first interconnect line 31. The control electrode of the driving transistor T1 is connected to one end of the first interconnect line 31, and the second electrode of the first leakage current suppression transistor T8 is connected to the other end of the first interconnect line 31. Along the thickness direction of the array substrate, the orthographic projection of the first interconnect line 31 on the substrate is located within the orthographic projection of the first power sub-line VDD1 on the substrate.

[0064] Specifically, in this embodiment, the first power line VDD includes a first power sub-line VDD1 and a second power sub-line VDD2. The first power sub-lines VDD1 and VDD2 are interwoven across different layers to form a mesh structure, which reduces the resistance of the first power line VDD and thus improves the problem of uneven brightness. The first power sub-line VDD1 can be disposed on the fourth conductive layer and extends along the first direction X; the first interconnect 31 is disposed on the third conductive layer and is used to connect the gate of the first leakage current suppression transistor T8 and the gate of the driving transistor T1. In other words, since the first interconnect 31 is metal, it can also be understood as the gate of the driving transistor T1. By placing the first interconnect 31 below the first power sub-line VDD1, the first power sub-line VDD1 can shield the first interconnect 31; for example, after the AC signal on the data line Vdata is coupled to the first power sub-line VDD1, it will not continue to be coupled to the first interconnect 31, which means that the parasitic capacitance generated between the data line Vdata and the gate of the driving transistor T1 can be shielded, thereby improving the problem of crosstalk in the column direction.

[0065] Optionally, in some embodiments, the minimum distance between the boundary of the orthographic projection of the first interconnect 31 on the substrate and the boundary of the orthographic projection of the first power sub-line VDD1 on the substrate is greater than or equal to 0.5 micrometers. The first interconnect 31 is completely within the orthographic projection of the first power sub-line VDD1, ensuring good shielding performance.

[0066] Optionally, refer to Figure 4 , Figure 6 and Figure 7 The multilayer conductive layer also forms multiple second capacitor plates 41 and second power sub-lines VDD2 arranged along the second direction Y; any two of the second capacitor plates 41, second power sub-lines VDD2 and first power sub-lines VDD1 are disposed in different layers; along the thickness direction of the array substrate, the orthographic projection of the channel of the driving transistor T1 on the substrate is located within the orthographic projection of the second capacitor plate 41 on the substrate; the second power sub-line VDD2 and the second capacitor plate 41 overlap (i.e., their orthographic projections on the substrate overlap) to form the second capacitor Cst; the first interconnect line 31 includes a first sub-part 311 and a second sub-part 312; along the thickness direction of the array substrate, the orthographic projection of the first sub-part 311 on the substrate is located within the outer contour of the orthographic projection of the second power sub-line VDD2 on the substrate, and the orthographic projection of the second sub-part 312 on the substrate is located outside the outer contour of the orthographic projection of the second power sub-line VDD2 on the substrate; the size of the first sub-part 311 in the first direction X is larger than the size of the second sub-part 312 in the first direction X.

[0067] Specifically, the first interconnect 31 is divided into two parts: the first sub-part 311 overlaps with the second power sub-line VDD2, while the second sub-part 312 does not overlap with the second power sub-line VDD2. Therefore, at the junction of the first sub-part 311 and the second sub-part 312, the first interconnect 31 has a sloping section. In actual fabrication, the first interconnect 31 at this sloping section will experience some loss. In this embodiment, the size of the first sub-part 311 is set larger than the size of the second sub-part 312. This ensures that, after actual process losses, the sizes of the first sub-part 311 and the second sub-part 312 are close in the actual product, preventing the first sub-part 311 from becoming thinner after overexposure and causing abnormal problems such as aluminum corrosion. It should also be noted that the first sub-part 311 and the second sub-part 312 only refer to the traces and do not represent the parts that contact vias.

[0068] Optionally, in some embodiments, the difference between the dimension of the first sub-part 311 in the first direction X and the dimension of the second sub-part 312 in the first direction X ranges from 0.2 micrometers to 0.5 micrometers.

[0069] Optionally, refer to Figure 4 and Figure 11 The multilayer conductive layer also forms multiple data lines Vdata arranged along the first direction X. The portion of the driving transistor T1 located in the active layer Psi includes a conductive channel, a first electrode contact, and a first electrode lead-out. The first electrode contact is connected to the data line Vdata, overlaps with the data line Vdata, and is connected through a via. The first electrode lead-out is connected between the conductive channel and the first electrode contact. Along the thickness direction of the array substrate, the orthographic projection of the first electrode lead-out on the substrate is outside the orthographic projection of the data line on the substrate. This reduces the parasitic capacitance between the data line Vdata and the first electrode lead-out, which in turn reduces the parasitic capacitance between the data line Vdata and the first electrode of the driving transistor T1, thereby reducing the load on the data line Vdata and improving crosstalk issues.

[0070] Optionally, the orthographic projection of the first lead-out onto the substrate at least partially overlaps with the orthographic projection of the second power sub-line VDD2 onto the substrate. This configuration utilizes the second power sub-line VDD2 to shield the parasitic capacitance between the data line Vdata and the first lead-out, preventing signals on the data line Vdata from coupling to the first lead-out. This further reduces the load on the data line Vdata and improves crosstalk issues.

[0071] Optionally, Figure 11 for Figure 1 A magnified view of a specific area, specifically Figure 1 A magnified view of a portion of region Z1 in the middle area, for reference. Figure 1 , Figure 10 and Figure 11The multilayer conductive layer forms multiple second initialization lines Vref2, which extend along a first direction X; the multiple second initialization lines Vref2 are arranged along a second direction Y. The multilayer conductive layer also forms a second interconnect line 32 extending along the second direction Y. One end of the second interconnect line 32 is connected to the second initialization line Vref2 through an interconnect hole 52, and the other end of the second interconnect line 32 is connected to a third initialization transistor T7. Along the thickness direction of the array substrate, the orthographic projection of the second interconnect line 32 on the substrate at least partially overlaps with the orthographic projection of the first initialization line Vref1 on the substrate. The second initialization line Vref2 includes a connection portion 51 connected to the interconnect hole 52. Along the thickness direction of the array substrate, the orthographic projection of the connection portion 51 on the substrate partially overlaps with the orthographic projection of the active layer on the substrate.

[0072] Specifically, the second interconnect 32 is disposed in the third conductive layer M3, and the second initialization line Vref2 is disposed in the second conductive layer M2. The second initialization line Vref2 is connected to the second interconnect 32 through an interconnect via 51, and the second interconnect 32 is electrically connected to the second initialization transistor T7 through a corresponding via. The connection portion 51 contacts the interconnect via 52, and the orthographic projection of the connection portion 51 on the substrate covers the orthographic projection of the interconnect via 52 on the substrate. The connection portion 51 can be understood as the portion of the second initialization line Vref2 located in the interconnect via 52 and its surrounding area. In this embodiment, since the interconnect via 52 is disposed between the second and third conductive layers, when fabricating the interconnect via 52, if the overlay offset of the overlay process is large, the interconnect via 52 may connect to the active layer, thereby causing a short circuit between the second initialization line Vref2 and the light-emitting unit. In this embodiment, the size of the connection portion 51 is set to be large and partially covers the active layer. Even if the overlay offset is large when fabricating the interconnect via 52, the interconnect via 52 will not exceed the area of ​​the connection portion 51, thus avoiding the problem of a short circuit between the second initialization line Vref2 and the light-emitting unit.

[0073] Optionally, refer to Figure 1 and Figure 4 The multilayer conductive layer also forms multiple second enable signal lines EM arranged along the second direction Y, and the multilayer conductive layer also forms a third interconnect line 33 extending along the second direction Y; along the thickness direction of the array substrate, the orthographic projection of the third interconnect line 33 on the substrate intersects with the orthographic projection of the second enable signal line EM on the substrate; the first electrode of the driving transistor T1 is connected to one end of the third interconnect line 33, and the first electrode of the first light-emitting control transistor T5 is connected to the second end of the third interconnect line 33.

[0074] Specifically, the third interconnect 33 is also connected to the first terminal of the first initialization transistor T11. In other words, the first terminal of the driving transistor T1 is led to the first initialization transistor T11 through the third interconnect 33, and further receives the signal of the second preset signal line VEH through the first initialization transistor T11. This configuration can reduce the length of the active layer, the winding length of the second preset signal line VEH, and the number of vias required by the array substrate, thereby further saving space in the array substrate in the second direction and increasing the pixel density.

[0075] Optionally, continue to refer to Figure 1 Two adjacent repeating modules can share the via between the second preset signal line VEH and the first initialization transistor T11, thereby further reducing the space required by the array substrate in the first direction X and increasing the pixel density.

[0076] Optionally, such as Figure 1 , Figure 4 and Figure 9 As shown, the multilayer conductive layer also forms multiple fourth interconnect lines 34 extending along the second direction Y, and the fourth interconnect lines 34 are located in the third conductive layer. The fourth interconnect lines 34 are connected to the first power sub-line VDD1 and the second power sub-line VDD2, so that the first power sub-line VDD1 and the second power sub-line VDD2 form a mesh structure.

[0077] Based on the same inventive concept, the present invention also provides a display panel, which includes the array substrate provided in any embodiment of the present invention and has the same beneficial effects, which will not be described in detail here.

[0078] Based on the same inventive concept, the present invention also provides a display device, which includes the display panel provided in any embodiment of the present invention. The display device can be a mobile phone, tablet computer, MP3 player, MP4 player, smartwatch, smart helmet, or other wearable device, etc. The display device has the same beneficial effects as the display panel described in this embodiment, and will not be repeated here.

[0079] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0080] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, The array substrate includes a substrate; an active layer and multiple conductive layers stacked on one side of the substrate; The active layer and the multilayer conductive layer form a plurality of pixel circuits, and the plurality of pixel circuits are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect. The plurality of pixel circuits are configured to scan sequentially along the second direction; the pixel circuit includes a driving transistor, a data writing transistor, a first leakage current suppression transistor, and a first capacitor; a first terminal of the first capacitor is electrically connected to a first electrode of the first leakage current suppression transistor, and a second electrode of the first leakage current suppression transistor is electrically connected to the control electrode of the driving transistor; The multilayer conductive layer is formed with a plurality of first preset signal lines arranged along the second direction and a plurality of first scan lines arranged along the second direction; the control electrode of the data writing transistor is electrically connected to one of the first scan lines, and the second end of the first capacitor is electrically connected to one of the first preset signal lines; wherein, the first preset signal line corresponding to the pixel circuit is electrically connected to the first scan line corresponding to the pixel circuit in the next scanning sequence.

2. The array substrate according to claim 1, characterized in that, The array substrate includes a display area and a non-display area that at least partially surrounds the display area, and the pixel circuit is located in the display area; the first scan line extends from the display area to the non-display area, and the first preset signal line extends from the display area to the non-display area; the connection point between the first preset signal line and the first scan line is located in the non-display area; Preferably, the array substrate includes a gate driving circuit located in the non-display area, and the gate driving circuit is electrically connected to the first scan line and the first preset signal line.

3. The array substrate according to claim 1, characterized in that, The pixel circuit further includes a first initialization transistor, the first terminal of which is electrically connected to the first terminal of the driving transistor; the first terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor. The multilayer conductive layer is further formed with a plurality of second preset signal lines arranged along the second direction and a plurality of first enable signal lines arranged along the second direction; the control electrode of the first leakage current suppression transistor is electrically connected to one of the first enable signal lines, and the second electrode of the first initialization transistor is electrically connected to one of the second preset signal lines. Any two of the first preset signal line, the second preset signal line, and the first enable signal line are configured in different layers; Preferably, the multilayer conductive layer includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked on the side of the active layer away from the substrate; the first enable signal line is located in the first conductive layer, the first preset signal line is located in the second conductive layer, and the second preset signal line is located in the third conductive layer; Preferably, the first preset signal line includes a first capacitor plate and a first trace connected to the first capacitor plate, wherein the first capacitor plate overlaps with the active layer to form the first capacitor; along the second direction, the size of the first capacitor plate is larger than the size of the first trace. Preferably, the second preset signal line includes a second trace and a third trace connected to the second trace; along the second direction, the second trace corresponding to the pixel circuit in the previous scanning sequence is located between the first trace corresponding to the pixel circuit in the current scanning sequence and the first enable signal line; along the thickness direction of the array substrate, the orthographic projection of the third trace on the substrate is located outside the orthographic projection of the first capacitor plate on the substrate, and overlaps with the orthographic projection portion of the first enable signal line on the substrate.

4. The array substrate according to claim 1, characterized in that, The two adjacent pixel circuits along the first direction are mirror-symmetrical; Preferably, the pixel circuit further includes a second initialization transistor, which is used to initialize the control electrode of the driving transistor; the multilayer conductive layer also forms a plurality of first initialization lines arranged along the first direction; the first initialization lines are located at the center of the overall structure formed by two adjacent pixel circuits and are electrically connected to the second initialization transistors in the two adjacent pixel circuits. Preferably, the multilayer conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the side of the active layer away from the substrate; the first initialization line is located in the fourth conductive layer.

5. The array substrate according to claim 1, characterized in that, The pixel circuit further includes a second leakage current suppression transistor, the first terminal of the second leakage current suppression transistor is electrically connected to the first terminal of the first leakage current suppression transistor, and the control terminal of the second leakage current suppression transistor is electrically connected to the control terminal of the first leakage current suppression transistor; the channel length of the first leakage current suppression transistor is greater than the channel length of the second leakage current suppression transistor, and the channel width of the first leakage current suppression transistor is greater than the channel width of the second leakage current suppression transistor. Preferably, the difference between the channel length of the first leakage current suppression transistor and the channel length of the second leakage current suppression transistor is in the range of 2.5 micrometers to 3 micrometers; and / or, the difference between the channel width of the first leakage current suppression transistor and the channel length width of the second leakage current suppression transistor is in the range of 1.5 micrometers to 2 micrometers.

6. The array substrate according to claim 1, characterized in that, The multilayer conductive layer also forms a plurality of first power sub-lines arranged along the first direction, and the first electrode of the driving transistor is electrically connected to the first power sub-lines; the multilayer conductive layer also forms a first interconnect line, the control electrode of the driving transistor is connected to one end of the first interconnect line, and the second electrode of the first leakage current suppression transistor is connected to the other end of the first interconnect line. Along the thickness direction of the array substrate, the orthographic projection of the first interconnect line on the substrate lies within the orthographic projection of the first power sub-line on the substrate; Preferably, the minimum distance between the boundary of the orthographic projection of the first interconnect line on the substrate and the boundary of the orthographic projection of the first power sub-line on the substrate is greater than or equal to 0.5 micrometers.

7. The array substrate according to claim 6, characterized in that, The pixel circuit further includes a second capacitor, the first end of which is electrically connected to the first power supply sub-line, and the second end of which is electrically connected to the control electrode of the driving transistor. The multilayer conductive layer further forms multiple second capacitor plates and multiple second power sub-lines arranged along the second direction; the second power sub-lines are electrically connected to the first power sub-lines; any two of the second capacitor plates, the second power sub-lines, and the first power sub-lines are disposed in different layers; along the thickness direction of the array substrate, the orthographic projection of the channel of the driving transistor on the substrate is located within the orthographic projection of the second capacitor plate on the substrate; the second power sub-lines and the second capacitor plates overlap to form the second capacitor; The first interconnect includes a first sub-section and a second sub-section; along the thickness direction of the array substrate, the orthographic projection of the first sub-section on the substrate is located within the outer contour of the orthographic projection of the second power sub-line on the substrate, and the orthographic projection of the second sub-section on the substrate is located outside the outer contour of the orthographic projection of the second power sub-line on the substrate. The dimension of the first sub-part in the first direction is greater than the dimension of the second sub-part in the first direction; Preferably, the difference between the dimension of the first sub-part in the first direction and the dimension of the second sub-part in the first direction is in the range of 0.2 micrometers to 0.5 micrometers; Preferably, the multilayer conductive layer further forms a plurality of data lines arranged along the first direction, and the first electrode of the data writing transistor is electrically connected to one of the data lines; the portion of the driving transistor located in the active layer includes a conductive channel, a first electrode contact portion, and a first electrode lead-out portion, the first electrode contact portion being connected to the data line, and the first electrode lead-out portion being connected to the conductive channel; along the thickness direction of the array substrate, the orthographic projection of the first electrode lead-out portion on the substrate is located outside the orthographic projection of the data line on the substrate; And / or, along the thickness direction of the array substrate, the orthographic projection of the first electrode lead on the substrate at least partially overlaps with the orthographic projection of the second power sub-line on the substrate.

8. The array substrate according to claim 4, characterized in that, The pixel circuit further includes a third initialization transistor, which is used to initialize the light-emitting unit corresponding to the pixel circuit; the multilayer conductive layer also forms a plurality of second initialization lines arranged along the second direction. The multilayer conductive layer also forms a second interconnect line extending along the second direction, one end of the second interconnect line being connected to the second initialization line through an interconnect hole, and the other end of the second interconnect line being connected to the third initialization transistor; Along the thickness direction of the array substrate, the orthographic projection of the second interconnect line on the substrate at least partially overlaps with the orthographic projection of the first initialization line on the substrate; The second initialization line includes a connection portion connected to the interconnect hole. Along the thickness direction of the array substrate, the orthographic projection of the connection portion on the substrate overlaps with the orthographic projection portion of the active layer on the substrate.

9. The array substrate according to claim 1, characterized in that, The pixel circuit further includes a first light-emitting control transistor and a second light-emitting control transistor. The first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor. The multilayer conductive layer also forms a plurality of second enable signal lines arranged along the second direction. The control electrodes of the first light-emitting control transistor and the control electrodes of the second light-emitting control transistor are electrically connected to one of the second enable signal lines. The multilayer conductive layer is further formed with a third interconnect line extending along the second direction; along the thickness direction of the array substrate, the orthographic projection of the third interconnect line on the substrate intersects with the orthographic projection of the second enable signal line on the substrate. The first terminal of the driving transistor is connected to one end of the third interconnect, and the first terminal of the first light-emitting control transistor is connected to the second end of the third interconnect.

10. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-9.

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