Rerouting layer and its circuit repair method

Abstract

A rewiring layer and a circuit repairing method thereof, wherein the rewiring layer comprises: a plurality of circuit layers arranged in sequence, and the plurality of circuit layers are distributed with main functional traces and auxiliary traces; the main functional traces are used to realize the electrical interconnection between the internal circuit of a chip and external pins; the auxiliary traces are used to bridge and repair when the main functional traces are broken; and the auxiliary traces are physically isolated and electrically disconnected from the main functional traces when the main functional traces are not broken. In the state that the main functional traces are not broken, the auxiliary traces are in an electrically silent state and do not participate in signal transmission. When the main functional traces are broken, a bridge path can be established at the broken position of the main functional traces by selectively activating the auxiliary traces. Compared with the traditional scrap processing method, the in-situ functional recovery of the failed circuit is realized by adding auxiliary traces, the fault tolerance and yield level of the advanced packaging process are improved, and the overall failure risk of the package caused by microcircuit defects is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a redistribution layer and a method for repairing its circuitry. Background Technology

[0002] The redistribution layer (RDL) is a core interconnect structure in advanced packaging technologies, primarily functioning to rearrange chip I / O ports and extend electrical connections. In flip-chip and wafer-level packaging processes, when the original chip's pad spacing is too small or its placement doesn't meet the connection requirements of the packaging substrate, the redistribution layer, by depositing a metal wiring layer on the wafer surface, reroutes the signal pins on the chip to more suitable areas, thus matching the pin layout of the packaging substrate. This layer typically uses low-resistance metal materials such as copper or aluminum, combined with a polymer dielectric layer (such as polyimide or benzocyclobutene) for insulation, forming a multi-layer interconnect structure that significantly improves wiring density and signal transmission efficiency.

[0003] The core value of redistribution layer technology lies in breaking through the physical limitations of traditional packaging, supporting multi-chip integration and 3D stacking. In fan-out and 2.5D / 3D packaging, the redistribution layer not only realizes the redistribution of ports on a single chip, but also plays a crucial role in lateral interconnection between chips, enabling high-speed communication between different functional chips (such as logic chips and memory chips) within the same package. As linewidth / spacing evolves towards sub-10 micrometers, redistribution layer technology is deeply integrated with technologies such as through-silicon vias (TSVs) and micro-bumps, becoming an important support for improving the integration and performance of system-in-package (SIP) systems, and driving the transformation of packaging technology from a simple protection function to a high-performance interconnect platform.

[0004] However, there are still many problems with the redistribution layer in the existing technology. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a redistribution layer and a method for repairing its circuits, so as to achieve in-situ repair of open circuits in the redistribution layer and improve packaging yield.

[0006] To address the aforementioned problems, this invention provides a redistribution layer, comprising: a plurality of line layers stacked sequentially, wherein main functional traces and auxiliary traces are distributed within the plurality of line layers; wherein the main functional traces are used to realize electrical interconnection between internal circuits of the chip and external pins; the auxiliary traces are used to bridge and repair when the main functional traces are open-circuited; and in the state where the main functional traces are not open-circuited, the auxiliary traces are physically isolated and electrically disconnected from the main functional traces.

[0007] Optionally, the plurality of line layers include: an adjacent first line layer and a second line layer.

[0008] Optionally, the main functional routing includes: a plurality of first functional routings distributed within the first circuit layer, the plurality of first functional routings being arranged along a first direction and extending along a second direction, the first direction being perpendicular to the second direction; and a plurality of second functional routings distributed within the second circuit layer, the plurality of second functional routings being arranged along the first direction and extending along the second direction, each second functional routing being electrically connected to a corresponding first functional routing.

[0009] Optionally, the auxiliary routing includes: a first auxiliary routing, a second auxiliary routing, a third auxiliary routing, and a fourth auxiliary routing distributed within the first line layer; wherein the first auxiliary routing, the second auxiliary routing, and the plurality of first functional routings are arranged along the first direction, the first auxiliary routing and the second auxiliary routing extend along the second direction, and are respectively arranged on opposite sides of the plurality of first functional routings; the third auxiliary routing and the fourth auxiliary routing are arranged along the second direction, and the projections of the third auxiliary routing and the fourth auxiliary routing overlap with the projections of the plurality of second functional routings, and the third auxiliary routing and the fourth auxiliary routing are disconnected at positions corresponding to the interval regions of any adjacent second functional routings; a fifth auxiliary routing, a sixth auxiliary routing, a seventh auxiliary routing, and an eighth auxiliary routing distributed within the second line layer; wherein the fifth auxiliary routing, the sixth auxiliary routing, the seventh auxiliary routing, and the eighth auxiliary routing are distributed within the second line layer; wherein the fifth auxiliary routing, the sixth auxiliary routing, the seventh auxiliary routing, the eighth ... The auxiliary routing lines and the plurality of second functional routing lines are arranged along the first direction. The fifth auxiliary routing line and the sixth auxiliary routing line extend along the second direction and are respectively arranged on opposite sides of the plurality of second functional routing lines. The seventh auxiliary routing line and the eighth auxiliary routing line are arranged along the second direction, and the projections of the seventh auxiliary routing line and the eighth auxiliary routing line overlap with the projections of the plurality of first functional routing lines. The seventh auxiliary routing line and the eighth auxiliary routing line are disconnected at the interval region of any adjacent first functional routing line. The first auxiliary routing line is electrically connected to the seventh auxiliary routing line and the eighth auxiliary routing line respectively. The second auxiliary routing line is electrically connected to the seventh auxiliary routing line and the eighth auxiliary routing line respectively. The fifth auxiliary routing line is electrically connected to the third auxiliary routing line and the fourth auxiliary routing line respectively. The sixth auxiliary routing line is electrically connected to the third auxiliary routing line and the fourth auxiliary routing line respectively.

[0010] Optionally, the auxiliary routing includes: a first auxiliary routing and a second auxiliary routing distributed within the first line layer, wherein the first auxiliary routing and the second auxiliary routing are physically isolated and electrically disconnected at positions corresponding to the intervals between any adjacent second functional routings; wherein, the first auxiliary routing includes a first part, a second part, and a third part, the first part and the third part are arranged along the second direction, and the projections of the first part and the third part overlap with the projections of the plurality of second functional routings, the second part and the plurality of second functional routings are arranged along the first direction, and the second part is electrically connected to the first part and the third part respectively; the second auxiliary routing includes a fourth part, a fifth part, and a sixth part, the fourth part and the sixth part are arranged along the second direction, and the projections of the fourth part and the sixth part overlap with the projections of the plurality of second functional routings, the fifth part and the plurality of second functional routings are arranged along the first direction, and the fifth part is electrically connected to the fourth part and the sixth part respectively. The system includes: a third auxiliary trace and a fourth auxiliary trace distributed within the second circuit layer, wherein the third auxiliary trace and the fourth auxiliary trace are physically isolated and electrically disconnected at positions corresponding to the intervals between any adjacent first functional traces; wherein the third auxiliary trace includes a seventh part, an eighth part, and a ninth part, the seventh part and the ninth part are arranged along the second direction, and the projections of the seventh part and the ninth part overlap with the projections of the plurality of first functional traces; the eighth part and the plurality of first functional traces are arranged along the first direction, and the eighth part is electrically connected to the seventh part and the ninth part respectively; the fourth auxiliary trace includes a tenth part, an eleventh part, and a twelfth part, the tenth part and the twelfth part are arranged along the second direction, and the projections of the tenth part and the twelfth part overlap with the projections of the plurality of first functional traces; the eleventh part and the plurality of first functional traces are arranged along the first direction, and the eleventh part is electrically connected to the tenth part and the twelfth part respectively.

[0011] Optionally, the auxiliary routing includes: a first auxiliary routing and a second auxiliary routing distributed within the first line layer, the first auxiliary routing and the second auxiliary routing being located around the plurality of first functional routings, and the first auxiliary routing and the second auxiliary routing forming a semi-enclosure of the plurality of first functional routings, the first auxiliary routing and the second auxiliary routing maintaining physical isolation and electrical disconnection; a third auxiliary routing and a fourth auxiliary routing distributed within the second line layer, the third auxiliary routing and the fourth auxiliary routing being located around the plurality of second functional routings, and the third auxiliary routing and the fourth auxiliary routing forming a semi-enclosure of the plurality of second functional routings, the third auxiliary routing and the fourth auxiliary routing maintaining physical isolation and electrical disconnection, the first auxiliary routing, the second auxiliary routing, the third auxiliary routing and the fourth auxiliary routing forming a full enclosure of the plurality of first functional routings and the plurality of second functional routings; the first auxiliary routing and the third auxiliary routing are electrically connected, and the second auxiliary routing and the fourth auxiliary routing are electrically connected.

[0012] Optionally, the auxiliary routing includes: a first auxiliary routing and a second auxiliary routing distributed within the first line layer, the first auxiliary routing and the second auxiliary routing being located around the plurality of first functional routings, and the first auxiliary routing and the second auxiliary routing forming a complete enclosure of the plurality of first functional routings, the first auxiliary routing and the second auxiliary routing maintaining physical isolation and electrical disconnection; a third auxiliary routing and a fourth auxiliary routing distributed within the second line layer, the third auxiliary routing and the fourth auxiliary routing being located around the plurality of second functional routings, and the third auxiliary routing and the fourth auxiliary routing forming a complete enclosure of the plurality of second functional routings, the third auxiliary routing and the fourth auxiliary routing maintaining physical isolation and electrical disconnection, the projections of the first auxiliary routing and the third auxiliary routing overlapping, the projections of the second auxiliary routing and the fourth auxiliary routing overlapping; the first auxiliary routing and the third auxiliary routing being electrically connected, the second auxiliary routing and the fourth auxiliary routing being electrically connected.

[0013] Optionally, each of the circuit layers also has a dielectric material used to cover the main functional traces and the auxiliary traces within the circuit layer.

[0014] Accordingly, the present invention also provides a method for repairing the redistribution layer, comprising: forming a redistribution layer as described in any of the above technical solutions; performing electrical tests after forming each of the redistribution layers; and when an open circuit is detected in the main functional trace of the redistribution layer, performing an open circuit bridging repair process to restore the main functional trace to its original path.

[0015] Optionally, the method for repairing the main functional circuit by bridging the circuit includes: when the gap at the break point is smaller than a preset size, irradiating the main functional circuit with a laser, and fusing the metal material of the main functional circuit based on the laser energy, so that the break point is reconnected.

[0016] Optionally, the method for repairing the main functional line by bridging the circuit break includes: when the gap at the circuit break position is greater than or equal to a preset size, bridging the circuit break position of the main functional line through the auxiliary routing, so that the current or signal transmitted by the main functional line bypasses the circuit break position and is transmitted through the auxiliary routing.

[0017] Optionally, the method for bridging the location of the main functional wiring break by the auxiliary wiring includes: forming a first connection point at one end of the auxiliary wiring and a repair point upstream of the break point of the main functional wiring; and forming a second connection point at the other end of the auxiliary wiring and a repair point downstream of the break point of the main functional wiring.

[0018] Optionally, the method for forming the first connection point and the second connection point includes: exposing the location of the repair point based on laser drilling; filling the drilling with conductive material to form the first connection point and the second connection point.

[0019] Optionally, the method for forming the first connection point and the second connection point includes: fusing the metal materials of the auxiliary trace and the main functional trace at the repair point location based on laser energy to form the first connection point and the second connection point.

[0020] Optionally, the test equipment can be used to locate the break point of the main function wiring.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages: In the redistribution layer of this invention, by configuring the main functional traces and the auxiliary traces in parallel within the circuit layer and establishing a physical isolation and electrical disconnection mechanism between them, a collaborative design of functional redundancy and fault repair is achieved. When the main functional trace is not open-circuited, the auxiliary traces are in an electrically silent state and do not participate in signal transmission, thereby completely avoiding parasitic interference on the electrical characteristics of the main functional traces and ensuring signal integrity and power integrity. Simultaneously, based on a pre-designed architecture, the auxiliary traces used for repair are embedded within the wiring layer, eliminating the need for additional planar space or interlayer resources in the package. When the main functional trace is open-circuited, the auxiliary traces can be selectively activated to establish a bridging path between the upstream and downstream of the open-circuit point of the main functional trace, allowing current or signals to bypass the open-circuit section and continue transmission. Compared to traditional scrapping methods, adding the auxiliary traces enables in-situ functional recovery of failed circuits, significantly improving the fault tolerance and yield of advanced packaging processes and effectively reducing the risk of overall failure of high-value packages due to microscopic circuit defects.

[0022] Furthermore, the auxiliary routing includes: a first auxiliary routing and a second auxiliary routing distributed within the first line layer, the first auxiliary routing and the second auxiliary routing being located around the plurality of first functional routings, and the first auxiliary routing and the second auxiliary routing forming a complete enclosure of the plurality of first functional routings, the first auxiliary routing and the second auxiliary routing maintaining physical isolation and electrical disconnection; a third auxiliary routing and a fourth auxiliary routing distributed within the second line layer, the third auxiliary routing and the fourth auxiliary routing being located around the plurality of second functional routings, and the third auxiliary routing and the fourth auxiliary routing forming a complete enclosure of the plurality of second functional routings, the third auxiliary routing and the fourth auxiliary routing maintaining physical isolation and electrical disconnection, the projections of the first auxiliary routing and the third auxiliary routing overlapping, the projections of the second auxiliary routing and the fourth auxiliary routing overlapping; the first auxiliary routing and the third auxiliary routing being electrically connected, the second auxiliary routing and the fourth auxiliary routing being electrically connected. The auxiliary routing adopts a same-layer, fully enclosed routing method. When the main functional routing is broken, it can be directly bridged and repaired using the auxiliary routing on the same layer. This structure places the repair point and the auxiliary routing on the same circuit layer, and laser drilling only needs to penetrate a single layer of dielectric material to reach the target location, significantly reducing the drilling depth and process difficulty.

[0023] The rewiring layer circuit repair method of this invention constructs a closed-loop quality control system of "preparation-detection-repair" during the formation of the rewiring layer. Electrical testing is embedded in the layer-by-layer preparation process to achieve precise location and early interception of failure nodes. For detected open circuit defects in the main functional traces, the auxiliary traces are used for open circuit bridging repair to restore the circuit, thus saving defective products that would otherwise be scrapped. This significantly reduces material waste and production costs in advanced packaging processes, and improves overall manufacturing yield and capacity utilization.

[0024] Furthermore, the method for repairing the open circuit bridging of the main functional circuit includes: when the gap at the open circuit location is smaller than a preset size, irradiating the main functional circuit with a laser, and fusing the metal material of the main functional trace based on laser energy, thereby reconnecting the open circuit location. This repair method uses laser fusion to address micro-gap open circuit defects, utilizing a high-energy laser beam to directly irradiate the open circuit location, causing the metal trace material to partially melt and reconnect. This method does not require the introduction of external conductive materials or auxiliary traces, the repair process is simple and efficient, avoids the additional parasitic parameters caused by the activation of auxiliary traces, and maintains the electrical characteristics of the original circuit to the greatest extent.

[0025] Furthermore, the method for repairing open circuits in the main functional circuit includes: when the gap at the open circuit location is greater than or equal to a preset size, bridging the open circuit location of the main functional circuit using the auxiliary trace, so that the current or signal transmitted by the main functional circuit bypasses the open circuit location and is transmitted via the auxiliary trace. This repair method uses the auxiliary trace bridging method to address large gap open circuit defects, establishing an alternative path by using the preset auxiliary trace to bypass the open circuit section. This method can overcome the limitations of laser fusion on gap size, expand the range of repairable defects, and make even severe open circuit failures salvageable, significantly improving the applicability of the repair technology and the overall reliability of the package.

[0026] Furthermore, the method for forming the first connection point and the second connection point includes: exposing the location of the repair point based on laser drilling; and filling the drilling with conductive material to form the first connection point and the second connection point. The method for forming the first connection point and the second connection point employs a combined process of laser drilling and conductive material filling. After precisely exposing the repair point location with a laser, the conductive material is filled to establish an electrical connection. This method has high process maturity, good connection reliability, is applicable to various metal trace material systems, and possesses good process compatibility.

[0027] Furthermore, the method for forming the first connection point and the second connection point includes: fusing the metal materials of the auxiliary trace and the main functional trace at the repair point location based on laser energy to form the first connection point and the second connection point. This method directly utilizes laser energy to fuse the metal materials of the auxiliary trace and the main functional trace, eliminating the need for additional material filling steps. This method simplifies the process flow, reduces the interface reliability risks caused by introducing heterogeneous materials, and achieves metallurgical-grade bonding between homogeneous metals.

[0028] Furthermore, the break point of the main functional wiring is located using the testing equipment. By accurately locating the break point of the main functional wiring using the testing equipment, spatial coordinates are provided for subsequent repair operations. This collaborative mechanism of location and repair ensures accurate identification and rapid positioning of the repair point, thereby improving repair efficiency and success rate, and reducing the risk of misoperation. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of a rewiring layer; Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA; Figure 3 This is a schematic diagram of the rewiring layer in an embodiment of the present invention; Figure 4 yes Figure 3 Schematic diagram of the cross section along line BB; Figure 5 This is a schematic diagram of the rewiring layer according to another embodiment of the present invention; Figure 6 yes Figure 5 Schematic diagram of the cross-section along the CC line; Figure 7 This is a schematic diagram of the rewiring layer according to another embodiment of the present invention; Figure 8 yes Figure 7 Schematic diagram of the cross-section along the DD line; Figure 9 This is a schematic diagram of the rewiring layer according to another embodiment of the present invention; Figure 10 yes Figure 9 Schematic diagram of the cross-section along the EE line; Figure 11 Yes Figure 4 The diagram shows the structure of the rewiring layer after line repair. Figure 12 Yes Figure 6 The diagram shows the structure of the rewiring layer after line repair. Figure 13Yes Figure 8 The diagram shows the structure of the rewiring layer after line repair. Figure 14 Yes Figure 10 The diagram shows the structure after the rewiring layer has been repaired. Detailed Implementation

[0030] As described in the background section, the high copper pillars in existing panel-level packaging structures still present numerous problems. These will be explained in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic diagram of a rewiring layer; Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA.

[0032] As semiconductor technology evolves towards smaller sizes and higher integration, advanced packaging technology has become a key path to continuing Moore's Law. In new architectures such as 2.5D / 3D packaging and fan-out packaging, the redistribution layer, as the core structure for achieving inter-chip interconnection, is experiencing continuous increases in wiring density, with increasingly narrower line widths and spacings. While this miniaturization trend effectively alleviates I / O port bottlenecks, it also presents severe reliability challenges to the metal traces of the redistribution layer. Process fluctuations, material inhomogeneities, and thermomechanical stress can all induce microscopic-level circuit defects, with open circuits in metal traces being particularly fatal. Since the redistribution layer typically carries the dual functions of power distribution and high-speed signal transmission, a single point of open circuit can lead to the complete failure of related electrical nodes, thereby causing systemic functional collapse.

[0033] Please refer to Figure 1 and Figure 2 Currently, the industry lacks effective repair methods for this type of failure. Once a redistribution layer open circuit defect is discovered during the post-packaging testing phase (such as...), the failure becomes critical. Figure 2 As shown in Part A, the entire chip or package often has to be scrapped. This "one failure, all failure" dilemma not only causes significant economic losses but also severely restricts production yield and capacity ramp-up. Especially in complex packaging scenarios such as high-end processors and artificial intelligence chips, the cost of a single failed product is extremely high, and the repair window is extremely narrow.

[0034] Based on this, the present invention provides a redistribution layer and its circuit repair method. By configuring the main functional traces and the auxiliary traces in parallel within the circuit layer and establishing a physical isolation and electrical disconnection mechanism between them, a collaborative design of functional redundancy and fault repair is achieved. When the main functional trace is not open-circuited, the auxiliary traces are in an electrically silent state and do not participate in signal transmission, thereby completely avoiding parasitic interference on the electrical characteristics of the main functional traces and ensuring signal integrity and power integrity. Simultaneously, based on a pre-designed architecture, the auxiliary traces used for repair are embedded within the wiring layer, without requiring additional planar space or interlayer resources of the package. When the main functional trace is open-circuited, the auxiliary traces can be selectively activated to establish a bridging path between the upstream and downstream of the open-circuit point of the main functional trace, allowing current or signals to bypass the open-circuit section and continue transmission. Compared to traditional scrapping methods, adding the auxiliary traces enables in-situ functional recovery of failed circuits, significantly improving the fault tolerance and yield of advanced packaging processes, and effectively reducing the risk of overall failure of high-value packages due to microscopic circuit defects.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figure 3 This is a schematic diagram of the rewiring layer in an embodiment of the present invention; Figure 4 yes Figure 3 Schematic diagram of the cross section along line BB.

[0037] Please refer to Figure 3 and Figure 4 A redistribution layer includes: a plurality of line layers stacked sequentially, wherein main functional traces and auxiliary traces are distributed within the plurality of line layers; wherein the main functional traces are used to realize electrical interconnection between internal circuits of a chip and external pins; the auxiliary traces are used to bridge and repair when the main functional traces are open-circuited; and in the state where the main functional traces are not open-circuited, the auxiliary traces are physically isolated and electrically disconnected from the main functional traces.

[0038] By configuring the main functional traces and auxiliary traces in parallel within the circuit layer and establishing a physical isolation and electrical disconnection mechanism between them, a collaborative design for functional redundancy and fault repair is achieved. When the main functional trace is not open-circuited, the auxiliary traces are electrically silent and do not participate in signal transmission, thus completely avoiding parasitic interference on the electrical characteristics of the main functional traces and ensuring signal and power integrity. Simultaneously, based on a pre-designed architecture, the auxiliary traces used for repair are embedded within the wiring layer, eliminating the need for additional planar space or interlayer resources within the package. When the main functional trace is open-circuited, the auxiliary traces can be selectively activated to establish a bridging path between the upstream and downstream of the open-circuit point, allowing current or signals to bypass the open section and continue transmission. Compared to traditional scrapping methods, adding auxiliary traces enables in-situ functional recovery of failed circuits, significantly improving the fault tolerance and yield of advanced packaging processes and effectively reducing the risk of overall failure of high-value packages due to microscopic circuit defects.

[0039] It should be noted that, in this embodiment, during the layout design phase of the rewiring layer, the main functional traces need to be systematically evaluated and classified to identify critical signal lines, high-current carrying lines, thermal stress concentration sections, and traces with high repair cost-effectiveness as key protection targets. For these target traces, a parallel routing strategy is adopted to pre-position auxiliary traces in their adjacent areas to build redundant repair resources. The path planning of the auxiliary traces should follow the principle of full coverage, arranging them along the entire length of the main functional traces or at least covering the critical sections with a high probability of failure, ensuring that there are nearby repair resources available in the event of a circuit break at any location. Geometrically, the auxiliary traces and the main functional traces must maintain a strict insulation distance. This distance needs to balance electrical isolation reliability and the operability of the laser repair process. That is, too small a distance can easily lead to interlayer dielectric breakdown or parasitic coupling during normal operation, while too large a distance will increase the laser aperture range and alignment difficulty during bridging repair. In addition, the trace width design of the auxiliary traces should also match or be slightly wider than that of the main functional traces to ensure that they have sufficient current carrying capacity after activation and to avoid introducing new reliability bottlenecks due to repairs.

[0040] In this embodiment, the main functional traces include: signal traces, power traces, and ground traces.

[0041] In this embodiment, the plurality of wiring layers include: an adjacent first wiring layer and a second wiring layer; each wiring layer also has a dielectric material (not shown), which is used to cover the main functional traces and the auxiliary traces within the wiring layer. By covering and protecting the main functional traces and the auxiliary traces within each wiring layer with the dielectric material, reliable dielectric isolation and physical support are formed, effectively blocking the corrosion of metal traces by moisture, pollutants and mechanical stress, and improving the long-term reliability and environmental adaptability of the rewiring layer.

[0042] Please continue to refer to this. Figure 3 and Figure 4In this embodiment, the main functional routing includes: a plurality of first functional routings 100 distributed within the first circuit layer, the plurality of first functional routings 100 being arranged along a first direction X and extending along a second direction Y, the first direction X being perpendicular to the second direction Y; a plurality of second functional routings 101 distributed within the second circuit layer, the plurality of second functional routings 101 being arranged along the first direction X and extending along the second direction Y, each second functional routing 101 being electrically connected to a corresponding first functional routing 100; the auxiliary routing includes: a first auxiliary routing 200, a second auxiliary routing 201, a third auxiliary routing 202, and a fourth auxiliary routing 201 distributed within the first circuit layer. Line 203; wherein, the first auxiliary routing line 200, the second auxiliary routing line 201, and the plurality of first functional routing lines 100 are arranged along the first direction X, the first auxiliary routing line 200 and the second auxiliary routing line 201 extend along the second direction Y, and are respectively arranged on opposite sides of the plurality of first functional routing lines 100; the third auxiliary routing line 202 and the fourth auxiliary routing line 203 are arranged along the second direction Y, and the projections of the third auxiliary routing line 202 and the fourth auxiliary routing line 203 overlap with the projections of the plurality of second functional routing lines 101, and the third auxiliary routing line 202 and the fourth auxiliary routing line 203 correspond to any adjacent second functional routing line. The interval region of 101 is broken; the fifth auxiliary trace 204, the sixth auxiliary trace 205, the seventh auxiliary trace 206, and the eighth auxiliary trace 207 are distributed in the second line layer; wherein, the fifth auxiliary trace 204, the sixth auxiliary trace 205, and the plurality of second functional traces 101 are arranged along the first direction X, the fifth auxiliary trace 204 and the sixth auxiliary trace 205 extend along the second direction Y, and are respectively arranged on opposite sides of the plurality of second functional traces 101; the seventh auxiliary trace 206 and the eighth auxiliary trace 207 are arranged along the second direction Y, and the projections of the seventh auxiliary trace 206 and the eighth auxiliary trace 207 are... The projections of the plurality of first functional traces 100 overlap, and the seventh auxiliary trace 206 and the eighth auxiliary trace 207 are disconnected at positions corresponding to the interval regions of any adjacent first functional traces 100; the first auxiliary trace 200 is electrically connected to the seventh auxiliary trace 206 and the eighth auxiliary trace 207 respectively, the second auxiliary trace 201 is electrically connected to the seventh auxiliary trace 206 and the eighth auxiliary trace 207 respectively, the fifth auxiliary trace 204 is electrically connected to the third auxiliary trace 202 and the fourth auxiliary trace 203 respectively, and the sixth auxiliary trace 205 is electrically connected to the third auxiliary trace 202 and the fourth auxiliary trace 203 respectively.

[0043] The auxiliary routing and the main functional routing are placed on different routing layers, forming a three-dimensional repair network through vertical interlayer stacking. When the main functional routing is broken, the upper and lower layers can be connected at a designated repair point. Laser-driven perforation penetrates the dielectric material between the layers, enabling the auxiliary routing and the main functional routing to achieve electrical connection in the vertical direction. This cross-layer bridging method fully utilizes the multi-layer stacking characteristics of the redistribution layers, achieving redundant design without occupying routing resources on the same layer, and improving the flexibility and density of the planar layout.

[0044] Figure 5 This is a schematic diagram of the rewiring layer according to another embodiment of the present invention; Figure 6 yes Figure 5 Schematic diagram of the cross section along the CC line.

[0045] This embodiment is based on the above embodiment ( Figure 3 and Figure 4 The redistribution layer will be further described based on the previous embodiment, except that the layout of the auxiliary traces is different. The following will provide a detailed description in conjunction with the accompanying drawings.

[0046] Please refer to Figure 5 and Figure 6The auxiliary routing includes: a first auxiliary routing 300 and a second auxiliary routing 301 distributed within the first line layer. The first auxiliary routing 300 and the second auxiliary routing 301 are physically isolated and electrically disconnected at positions corresponding to the intervals between any adjacent second functional routings 101. The first auxiliary routing 300 includes a first portion 3001, a second portion 3002, and a third portion 3003. The first portion 3001 and the third portion 3003 are arranged along the second direction Y, and the projections of the first portion 3001 and the third portion 3003 overlap with the projections of the plurality of second functional routings 101. The second portion 3002 and the plurality of second functional routings 101 overlap with the projections of the second auxiliary routings 101. The trace 101 is arranged along the first direction X, and the second portion 3002 is electrically connected to the first portion 3001 and the third portion 3003 respectively; the second auxiliary trace 301 includes a fourth portion 3011, a fifth portion 3012 and a sixth portion 3013, the fourth portion 3011 and the sixth portion 3013 are arranged along the second direction Y, and the projections of the fourth portion 3011 and the sixth portion 3013 overlap with the projections of the plurality of second functional traces 101, the fifth portion 3012 and the plurality of second functional traces 101 are arranged along the first direction X, and the fifth portion 3012 is electrically connected to the fourth portion 3011 and the sixth portion 3013 respectively. The third auxiliary trace 302 and the fourth auxiliary trace 303 are distributed within the second circuit layer. The third auxiliary trace 302 and the fourth auxiliary trace 303 are physically isolated and electrically disconnected at positions corresponding to the intervals between any adjacent first functional traces 100. The third auxiliary trace 302 includes a seventh portion 3021, an eighth portion 3022, and a ninth portion 3023. The seventh portion 3021 and the ninth portion 3023 are arranged along the second direction Y, and the projections of the seventh portion 3021 and the ninth portion 3023 overlap with the projections of the plurality of first functional traces 100. The eighth portion 3022 and the plurality of first functional traces 100 are arranged along the second direction Y. The first functional traces 100 are arranged in a direction X, and the eighth part 3022 is electrically connected to the seventh part 3021 and the ninth part 3023 respectively; the fourth auxiliary trace 303 includes a tenth part 3031, an eleventh part 3032 and a twelfth part 3033, the tenth part 3031 and the twelfth part 3033 are arranged in the second direction Y, and the projections of the tenth part 3031 and the twelfth part 3033 overlap with the projections of the plurality of first functional traces 100, the eleventh part 3032 and the plurality of first functional traces 100 are arranged in the first direction X, and the eleventh part 3032 is electrically connected to the tenth part 3031 and the twelfth part 3033 respectively.

[0047] The auxiliary traces employ a segmented wiring structure within the same layer. All components of the auxiliary traces on one side are distributed within the same circuit layer, eliminating the need for cross-layer connections. This design significantly reduces the number of interlayer vias or connection nodes, lowering the risk of secondary failures due to node failure. Furthermore, the same-layer arrangement allows the auxiliary traces to be formed in a single photolithography and electroplating process, avoiding the multiple alignment, exposure, and etching steps required for multi-layer stacking, thereby improving manufacturing efficiency and pattern accuracy.

[0048] Figure 7 This is a schematic diagram of the rewiring layer according to another embodiment of the present invention; Figure 8 yes Figure 7 Schematic diagram of the cross section along the DD line.

[0049] This embodiment is based on the above embodiment ( Figure 3 and Figure 4 The redistribution layer will be further described based on the previous embodiment, except that the layout of the auxiliary traces is different. The following will provide a detailed description in conjunction with the accompanying drawings.

[0050] Please refer to Figure 7 and Figure 8 The auxiliary routing includes: a first auxiliary routing 400 and a second auxiliary routing 401 distributed within the first circuit layer, wherein the first auxiliary routing 400 and the second auxiliary routing 401 are located around the plurality of first functional routings 100, and the first auxiliary routing 400 and the second auxiliary routing 401 form a semi-encirclement of the plurality of first functional routings 100, and the first auxiliary routing 400 and the second auxiliary routing 401 are physically isolated and electrically disconnected; and a third auxiliary routing 402 and a fourth auxiliary routing 403 distributed within the second circuit layer, wherein the third auxiliary routing 402 and the fourth auxiliary routing 403 are located around the plurality of second functional routings 100. The third auxiliary line 402 and the fourth auxiliary line 403 form a semi-encirclement of the plurality of second functional lines 101, and the third auxiliary line 402 and the fourth auxiliary line 403 are physically isolated and electrically disconnected. The first auxiliary line 400, the second auxiliary line 401, the third auxiliary line 402 and the fourth auxiliary line 403 form a full encirclement of the plurality of first functional lines 100 and the plurality of second functional lines 101. The first auxiliary line 400 and the third auxiliary line 402 are electrically connected, and the second auxiliary line 401 and the fourth auxiliary line 403 are electrically connected.

[0051] By arranging the auxiliary traces and the main functional traces in two opposing wiring layers, the auxiliary traces form an outer frame structure by winding around the outside of the overall wiring area. During normal operation, the outer auxiliary traces maintain electrical isolation from the inner main functional traces. When a main functional trace experiences an open circuit and requires repair, bridging can be performed at pre-set repair points on each layer, allowing current or signals to bypass the faulty section via the outer auxiliary traces. This outer-circuiting layout fully utilizes the unused space at the package edge, reduces the occupation of the core wiring area, and the symmetrical arrangement on both sides provides convenient repair access points for main functional traces at different locations.

[0052] Figure 9 This is a schematic diagram of the rewiring layer according to another embodiment of the present invention; Figure 10 yes Figure 9 Schematic diagram of the cross section along the EE line.

[0053] This embodiment is based on the above embodiment ( Figure 3 and Figure 4 The redistribution layer will be further described based on the previous embodiment, except that the layout of the auxiliary traces is different. The following will provide a detailed description in conjunction with the accompanying drawings.

[0054] Please refer to Figure 9 and Figure 10 The auxiliary routing includes: a first auxiliary routing 500 and a second auxiliary routing 501 distributed within the first circuit layer, wherein the first auxiliary routing 500 and the second auxiliary routing 501 are located around the plurality of first functional routings 100, and the first auxiliary routing 500 and the second auxiliary routing 501 form a complete enclosure of the plurality of first functional routings 100, and the first auxiliary routing 500 and the second auxiliary routing 501 are physically isolated and electrically disconnected; and a third auxiliary routing 502 and a fourth auxiliary routing 503 distributed within the second circuit layer, wherein the third auxiliary routing 502 and the fourth auxiliary routing 503 are physically isolated and electrically disconnected. 3 is located around the plurality of second functional traces 101, and the third auxiliary trace 502 and the fourth auxiliary trace 503 form a complete enclosure of the plurality of second functional traces 101. The third auxiliary trace 502 and the fourth auxiliary trace 503 are physically isolated and electrically disconnected. The projections of the first auxiliary trace 500 and the third auxiliary trace 502 overlap, and the projections of the second auxiliary trace 501 and the fourth auxiliary trace 503 overlap. The first auxiliary trace 500 and the third auxiliary trace 502 are electrically connected, and the second auxiliary trace 501 and the fourth auxiliary trace 503 are electrically connected.

[0055] The auxiliary routing adopts a same-layer, fully enclosed routing method. When the main functional routing is broken, it can be directly bridged and repaired using the auxiliary routing on the same layer. This structure places the repair point and the auxiliary routing on the same circuit layer, and laser drilling only needs to penetrate a single layer of dielectric material to reach the target location, significantly reducing the drilling depth and process difficulty.

[0056] Figure 11 Yes Figure 4 The diagram shows the structure of the rewiring layer after line repair. Figure 12 Yes Figure 6 The diagram shows the structure of the rewiring layer after line repair. Figure 13 Yes Figure 8 The diagram shows the structure of the rewiring layer after line repair. Figure 14 Yes Figure 10 The diagram shows the structure after the rewiring layer has been repaired.

[0057] Accordingly, this invention also provides a method for repairing rewiring layers; please refer to [the relevant documentation]. Figures 3 to 10 and in conjunction with references Figures 11 to 14 This includes: forming a redistribution layer as described in any of the above embodiments; performing electrical tests after forming each of the above-described redistribution layers; and when an open circuit is detected in the main functional trace of the redistribution layer, performing an open circuit bridging repair process to restore the main functional trace to its original path.

[0058] A closed-loop quality control system of "preparation-inspection-repair" is constructed during the formation of the redistribution layer. Electrical testing is embedded in the layer-by-layer fabrication process to achieve precise location and early interception of failure points. For detected open circuit defects in the main functional traces, the auxiliary traces are used for open circuit bridging repair to restore the circuit, thus saving defective products that would otherwise be scrapped. This significantly reduces material waste and production costs in advanced packaging processes, and improves overall manufacturing yield and capacity utilization.

[0059] In this embodiment, the method for repairing the main functional circuit by bridging the open circuit includes: when the gap at the open circuit location is smaller than a preset size, irradiating the main functional circuit with a laser, and using laser energy to fuse the metal material of the main functional circuit, thereby reconnecting the open circuit location.

[0060] This repair method targets micro-gap open circuit defects using laser fusion. A high-energy laser beam directly irradiates the open circuit location, causing the metal trace material to partially melt and reconnect. This method eliminates the need for external conductive materials or auxiliary traces, resulting in a simple and efficient repair process. It avoids the additional parasitic parameters caused by the activation of auxiliary traces, preserving the electrical characteristics of the original circuit to the greatest extent possible.

[0061] In this embodiment, when the gap at the break point is greater than or equal to a preset size, the break point of the main functional line is bridged by the auxiliary routing, so that the current or signal transmitted by the main functional line bypasses the break point and is transmitted via the auxiliary routing.

[0062] This repair method addresses large-gap open-circuit defects by employing an auxiliary wiring bridging approach. Pre-set auxiliary wiring bypasses the open-circuit section to establish an alternative path. This method overcomes the limitations of laser fusion on gap size, expands the range of repairable defects, and makes even severe open-circuit failures salvageable, significantly improving the applicability of the repair technology and the overall reliability of the package.

[0063] In this embodiment, the method for bridging the location of the main functional wiring break by the auxiliary wiring includes: forming a first connection point at one end of the auxiliary wiring and a repair point upstream of the break point of the main functional wiring; and forming a second connection point at the other end of the auxiliary wiring and a repair point downstream of the break point of the main functional wiring.

[0064] It should be noted that, in this embodiment, in the direction of signal or current transmission, upstream of the break point refers to the section before the current flows into the break location (i.e., near the signal / power supply section), and downstream of the break point refers to the section after the current flows out of the break location (i.e., near the failed metal contact). During bridging repair, the two ends of the auxiliary trace are connected to the upstream and downstream sections respectively, so that the transmission path bypasses the break point and restores the path.

[0065] In this embodiment, the method for forming the first connection point and the second connection point includes: exposing the location of the repair point based on laser drilling; filling the drilling with conductive material to form the first connection point and the second connection point.

[0066] The method for forming the first and second connection points employs a combination of laser drilling and conductive material filling. After precisely exposing the repair point location with a laser, the conductive material is filled to establish an electrical connection. This method boasts high process maturity, good connection reliability, and is applicable to various metal trace material systems, exhibiting excellent process compatibility. Alternatively, laser energy can be used to fuse the metal materials of the auxiliary trace and the main functional trace at the repair point location to form the first and second connection points.

[0067] The method for forming the first and second connection points employs a combination of laser drilling and conductive material filling. After precisely exposing the repair point location with a laser, the conductive material is filled to establish an electrical connection. This method boasts high process maturity, good connection reliability, and is applicable to various metal trace material systems, exhibiting excellent process compatibility. Furthermore, the method directly utilizes laser energy to fuse the metal materials of the auxiliary trace and the main functional trace, eliminating the need for additional material filling steps. This method simplifies the process flow, reduces the interface reliability risks caused by introducing heterogeneous materials, and achieves metallurgical-grade connections between homogeneous metals.

[0068] It should be noted that, in this embodiment, the selection of the two connection point formation methods is mainly based on the interlayer distance or lateral spacing between the auxiliary trace and the main functional trace. When the distance between the two is large, a laser-drilled hole and conductive material filling method is used. The laser precisely penetrates the dielectric material to expose the repair point, and then the conductive material is filled into the hole to establish an electrical connection. This method is mature and reliable, and is suitable for cross-layer bridging or scenarios with large spacing. When the distance between the two is small, a laser direct fusion method is used. The laser energy is used to melt and connect the metal materials of the auxiliary trace and the main functional trace in situ, without the need for additional filling material. This simplifies the process and reduces heterogeneous interfaces, and is suitable for rapid bridging between the same layer or adjacent layers.

[0069] Additionally, when it comes to interlayer laser drilling repair scenarios (such as...) Figure 11 and Figure 12 As shown, when the upper-layer main functional wiring has been fabricated and an opening needs to be made in the dielectric material below it, the vertical laser irradiation path will be blocked by the upper-layer metal wiring. In this case, a tilted laser processing method must be used. By precisely controlling the angle between the laser beam and the vertical direction, the light path passes through the lateral gap of the upper-layer main functional wiring, avoiding the metal obstruction area before acting on the target dielectric material. This method requires the laser system to have multi-axis linkage or beam tilting capabilities to achieve coordinated control of the incident angle, focal depth, and lateral position. This ensures that while avoiding damage to the upper structure, the controllable removal of the lower-layer dielectric material is precisely completed, creating a reliable electrical connection channel for cross-layer bridging repair.

[0070] In this embodiment, the break point of the main functional wiring is located using a testing machine. By accurately locating the break point using the testing machine, spatial coordinates are provided for subsequent repair operations. This collaborative mechanism of location and repair ensures accurate identification and rapid positioning of the repair point, thereby improving repair efficiency and success rate, and reducing the risk of misoperation.

[0071] Specifically, the testing equipment can be an automated optical inspection machine. This machine locates defects based on high-resolution imaging and image comparison technology. Its working principle involves scanning the surface of the circuit layer using a precision optical system to acquire the geometric shape data of the actual traces and performing pixel-level difference analysis with standard data from the design layout. When features such as abrupt changes in trace width, discontinuity interruptions, or abnormal reflections are detected, the system automatically marks the defect coordinates. Some advanced models combine infrared or X-ray transmission imaging to penetrate the surface medium and identify hidden breaks in inner layer traces.

[0072] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A redistribution layer, characterized in that, include: Several circuit layers are stacked sequentially, and main functional traces and auxiliary traces are distributed within these circuit layers; wherein... The main functional wiring is used to realize the electrical interconnection between the internal circuitry of the chip and the external pins; The auxiliary wiring is used to bridge and repair the main functional wiring when it is broken. When the main functional wiring is not broken, the auxiliary wiring remains physically isolated from and electrically disconnected from the main functional wiring.

2. The redistribution layer as described in claim 1, characterized in that, The plurality of line layers include: an adjacent first line layer and a second line layer.

3. The redistribution layer as described in claim 2, characterized in that, The main functional routing includes: a plurality of first functional routings distributed within the first circuit layer, the plurality of first functional routings being arranged along a first direction and extending along a second direction, the first direction being perpendicular to the second direction; and a plurality of second functional routings distributed within the second circuit layer, the plurality of second functional routings being arranged along the first direction and extending along the second direction, each second functional routing being electrically connected to a corresponding first functional routing.

4. The redistribution layer as described in claim 3, characterized in that, The auxiliary routing includes: a first auxiliary routing, a second auxiliary routing, a third auxiliary routing, and a fourth auxiliary routing distributed within the first line layer; wherein the first auxiliary routing, the second auxiliary routing, and the plurality of first functional routings are arranged along the first direction, the first auxiliary routing and the second auxiliary routing extend along the second direction, and are respectively arranged on opposite sides of the plurality of first functional routings; the third auxiliary routing and the fourth auxiliary routing are arranged along the second direction, and the projections of the third auxiliary routing and the fourth auxiliary routing overlap with the projections of the plurality of second functional routings, and the third auxiliary routing and the fourth auxiliary routing are disconnected at positions corresponding to the interval regions of any adjacent second functional routings; a fifth auxiliary routing, a sixth auxiliary routing, a seventh auxiliary routing, and an eighth auxiliary routing distributed within the second line layer; wherein the fifth auxiliary routing, the sixth auxiliary routing, the seventh auxiliary routing, the eighth auxiliary routing, the seventh auxiliary routing, the eighth auxiliary routing, the ninth auxiliary routing, the tenth auxiliary routing, the eleven ... The first functional trace and the plurality of second functional traces are arranged along the first direction. The fifth auxiliary trace and the sixth auxiliary trace extend along the second direction and are respectively arranged on opposite sides of the plurality of second functional traces. The seventh auxiliary trace and the eighth auxiliary trace are arranged along the second direction, and the projections of the seventh auxiliary trace and the eighth auxiliary trace overlap with the projections of the plurality of first functional traces. The seventh auxiliary trace and the eighth auxiliary trace are disconnected at the intervals between any adjacent first functional traces. The first auxiliary trace is electrically connected to the seventh auxiliary trace and the eighth auxiliary trace, the second auxiliary trace is electrically connected to the seventh auxiliary trace and the eighth auxiliary trace, the fifth auxiliary trace is electrically connected to the third auxiliary trace and the fourth auxiliary trace, and the sixth auxiliary trace is electrically connected to the third auxiliary trace and the fourth auxiliary trace.

5. The redistribution layer as described in claim 3, characterized in that, The auxiliary routing includes: a first auxiliary routing and a second auxiliary routing distributed within the first line layer. The first auxiliary routing and the second auxiliary routing are physically isolated and electrically disconnected at positions corresponding to the intervals between any adjacent second functional routings. The first auxiliary routing includes a first part, a second part, and a third part. The first part and the third part are arranged along the second direction, and their projections overlap with the projections of the plurality of second functional routings. The second part and the plurality of second functional routings are arranged along the first direction, and the second part is electrically connected to both the first part and the third part. The second auxiliary routing includes a fourth part, a fifth part, and a sixth part. The fourth part and the sixth part are arranged along the second direction, and their projections overlap with the projections of the plurality of second functional routings. The fifth part and the plurality of second functional routings are arranged along the first direction, and the fifth part is electrically connected to both the fourth part and the sixth part. The third and fourth auxiliary traces are distributed within the second circuit layer. The third and fourth auxiliary traces are physically isolated and electrically disconnected from each other at intervals between any adjacent first functional traces. The third auxiliary trace includes a seventh, eighth, and ninth section. The seventh and ninth sections are arranged along the second direction, and their projections overlap with the projections of the plurality of first functional traces. The eighth section and the plurality of first functional traces are arranged along the first direction, and the eighth section is electrically connected to the seventh and ninth sections respectively. The fourth auxiliary trace includes a tenth, eleventh, and twelfth section. The tenth and twelfth sections are arranged along the second direction, and their projections overlap with the projections of the plurality of first functional traces. The eleventh section and the plurality of first functional traces are arranged along the first direction, and the eleventh section is electrically connected to the tenth and twelfth sections respectively.

6. The redistribution layer as described in claim 3, characterized in that, The auxiliary routing includes: a first auxiliary routing and a second auxiliary routing distributed within the first line layer, the first auxiliary routing and the second auxiliary routing being located around the plurality of first functional routings, and the first auxiliary routing and the second auxiliary routing forming a semi-enclosure of the plurality of first functional routings, the first auxiliary routing and the second auxiliary routing maintaining physical isolation and electrical disconnection; a third auxiliary routing and a fourth auxiliary routing distributed within the second line layer, the third auxiliary routing and the fourth auxiliary routing being located around the plurality of second functional routings, and the third auxiliary routing and the fourth auxiliary routing forming a semi-enclosure of the plurality of second functional routings, the third auxiliary routing and the fourth auxiliary routing maintaining physical isolation and electrical disconnection, the first auxiliary routing, the second auxiliary routing, the third auxiliary routing and the fourth auxiliary routing forming a full enclosure of the plurality of first functional routings and the plurality of second functional routings; the first auxiliary routing and the third auxiliary routing are electrically connected, and the second auxiliary routing and the fourth auxiliary routing are electrically connected.

7. The redistribution layer as described in claim 3, characterized in that, The auxiliary routing includes: a first auxiliary routing and a second auxiliary routing distributed within the first line layer, the first auxiliary routing and the second auxiliary routing being located around the plurality of first functional routings and forming a complete enclosure of the plurality of first functional routings, the first auxiliary routing and the second auxiliary routing maintaining physical isolation and electrical disconnection; a third auxiliary routing and a fourth auxiliary routing distributed within the second line layer, the third auxiliary routing and the fourth auxiliary routing being located around the plurality of second functional routings and forming a complete enclosure of the plurality of second functional routings, the third auxiliary routing and the fourth auxiliary routing maintaining physical isolation and electrical disconnection, the projections of the first auxiliary routing and the third auxiliary routing overlapping, the projections of the second auxiliary routing and the fourth auxiliary routing overlapping; the first auxiliary routing and the third auxiliary routing being electrically connected, the second auxiliary routing and the fourth auxiliary routing being electrically connected.

8. The redistribution layer as described in claim 1, characterized in that, Each of the circuit layers also has a dielectric material used to cover the main functional traces and the auxiliary traces within the circuit layer.

9. A method for repairing rewiring layers, characterized in that, include: Form a redistribution layer as described in any one of claims 1 to 8; Electrical testing is performed after each of the aforementioned circuit layers is formed; When an open circuit is detected in the main functional trace of the line layer, an open circuit bridging repair process is performed to restore the main functional trace to its original path.

10. The method for repairing rewiring layers as described in claim 9, characterized in that, The method for repairing the main functional circuit by bridging the circuit breaks includes: when the gap at the break point is smaller than a preset size, irradiating the main functional circuit with a laser, and fusing the metal material of the main functional circuit based on the laser energy, so that the break point is reconnected.

11. The method for repairing rewiring layers as described in claim 9, characterized in that, The method for repairing the main functional line by bridging the circuit break includes: when the gap at the break point is greater than or equal to a preset size, bridging the break point of the main functional line by the auxiliary routing, so that the current or signal transmitted by the main functional line bypasses the break point and is transmitted via the auxiliary routing.

12. The method for repairing rewiring layers as described in claim 10, characterized in that, The method for bridging the location of the main functional line break by the auxiliary wiring includes: forming a first connection point at one end of the auxiliary wiring and a repair point upstream of the main functional line break point; and forming a second connection point at the other end of the auxiliary wiring and a repair point downstream of the main functional line break point.

13. The method for repairing rewiring layers as described in claim 12, characterized in that, The method for forming the first connection point and the second connection point includes: exposing the location of the repair point based on laser drilling; filling the drilling with conductive material to form the first connection point and the second connection point.

14. The method for repairing rewiring layers as described in claim 12, characterized in that, The method for forming the first connection point and the second connection point includes: fusing the metal materials of the auxiliary trace and the main functional trace at the repair point location based on laser energy to form the first connection point and the second connection point.

15. The method for repairing rewiring layers as described in claim 9, characterized in that, The test machine located the break point of the main function wiring.

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