Chip current calibration device

Abstract

The application discloses a kind of chip current calibration device, comprising: micro bias generation module, correction DAC bias module, correction DAC main module;The micro bias generation module is connected with local current mirror bias current source, the input end of the micro bias generation module is connected reference level, and the output end is connected the input end of the correction DAC bias module;The output end of the correction DAC bias module is connected the input end of the correction DAC main module;The output end of the correction DAC main module is connected with local current mirror bias current source.The application can be the current source of DAC and the like circuit micro current injection to correct the current deviation of DAC due to various factors.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a chip current calibration device. Background Technology

[0002] In the field of analog integrated circuit design, current serves as the core physical carrier for circuit bias supply, cross-domain conversion of electrical signals, and generation of reference signals. The accuracy of this current signal is a crucial foundation for ensuring the stability and performance limits of the core functions of analog chips. Whether it's a bandgap reference source providing stable operating bias for various chip modules, a current-controlled DAC for digital-to-analog signal conversion, a high-precision ADC for high-precision analog-to-digital acquisition, or a low-noise operational amplifier pursuing low-distortion amplification, the static characteristics and dynamic performance of these core functional modules are directly determined by the accuracy of the current signal. Even a small deviation in the current can lead to significant degradation in module performance. Therefore, high-precision current calibration technology has become an indispensable key support in analog IC design. In high-end analog applications such as high-speed, high-resolution digital-to-analog conversion, industrial-grade precision sensor signal conditioning, and active biasing in RF communication front-ends, device process mismatches during chip manufacturing, temperature drift effects caused by changes in the operating environment temperature, and batch process deviations in wafer processing can easily cause the core current source output to deviate from the design value, thereby inducing nonlinear errors. Such errors directly cause the deterioration of the integral and differential nonlinearity of the current-controlled DAC, reduce the effective number of bits of the high-precision ADC, and cause a fixed offset in the output of the bandgap reference source, seriously affecting the overall accuracy and reliability of the chip. Summary of the Invention

[0003] In order to solve the problems existing in the prior art, the present invention aims to provide a chip current calibration device, which can inject a small current into the current source of circuits such as DAC to correct the current deviation of DAC caused by various factors.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: A chip current calibration device includes: a micro bias voltage generation module, a calibration DAC bias module, and a calibration DAC main module; The micro bias voltage generation module is connected to the local current mirror bias current source. The input terminal of the micro bias voltage generation module is connected to the reference level, and the output terminal is connected to the input terminal of the correction DAC bias module. The output of the calibration DAC bias module is connected to the input of the calibration DAC main module; The output of the calibration DAC main module is connected to the local current mirror bias current source.

[0005] As a further improvement of the present invention, the micro bias generation module includes: a first operational amplifier, a first resistor, a second resistor, and a first MOSFET; The inverting input of the first operational amplifier is connected to a reference level, the non-inverting input of the first operational amplifier is connected to the drain of the first MOSFET through the second resistor, and the output of the first operational amplifier is connected to the gate of the first MOSFET. The drain of the first MOSFET is connected to the voltage source in sequence through the second resistor, the first resistor, and the local current mirror bias current source, while the source of the first MOSFET is grounded.

[0006] As a further improvement of the present invention, the correction DAC bias module includes: a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a second operational amplifier, and a third resistor; The output terminal of the micro bias generation module is connected to the gate of the second MOS transistor and the third MOS transistor, and the source of the second MOS transistor and the third MOS transistor is connected to a voltage source. The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor, the gate of the fourth MOS transistor, the gate of the fifth MOS transistor, and the inverting input terminal of the second operational amplifier; The drain of the third MOS transistor is connected to the drain of the fifth MOS transistor, the non-inverting input terminal of the second operational amplifier, and the drain of the sixth MOS transistor. The output terminal of the second operational amplifier is connected to the gate of the sixth MOS transistor; The source of the fourth MOS transistor and the source of the fifth MOS transistor are grounded; The source of the sixth MOS transistor is grounded through the third resistor.

[0007] As a further improvement of the present invention, the main module of the calibration DAC includes: a current mirror circuit, a control switch array structure, and a current output circuit; The current mirror circuit is connected to the correction DAC bias module and the control switch array structure; The control switch array structure is connected to the current output circuit and the control port.

[0008] As a further improvement of the present invention, the current mirror circuit includes: a resistor array connected in series and a plurality of current mirror structures arranged in parallel, wherein the current mirror structure includes: a seventh MOS transistor and a fourth resistor; the resistor array includes: a fifth resistor; The gate of the seventh MOS transistor is connected to the correction DAC bias module, the drain of the seventh MOS transistor is connected to the control switch array structure, the source of the seventh MOS transistor is grounded through the fourth resistor, and the source of the seventh MOS transistor is connected to the adjacent current mirror structure through the fourth resistor and the fifth resistor.

[0009] As a further improvement of the present invention, the control switch array structure includes: a pair of terminal fixed switches connected to each other and a plurality of differential switch pairs arranged in parallel; The differential switch pair includes: an eighth MOS transistor and a ninth MOS transistor; The gate of the eighth MOS transistor is connected to the first control port, the source of the eighth MOS transistor is connected to the source of the ninth MOS transistor and the current mirror circuit, and the drain of the eighth MOS transistor is connected to the current output circuit. The gate of the ninth MOS transistor is connected to the second control port, and the drain of the ninth MOS transistor is connected to the current output circuit.

[0010] As a further improvement of the present invention, the end-fixed switch pair includes: a tenth MOS transistor and an eleventh MOS transistor; The gate of the tenth MOS transistor is grounded, the gate of the eleventh MOS transistor is connected to the power supply, the source of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and the current mirror circuit, the drain of the tenth MOS transistor is connected to the current output circuit, and the drain of the eleventh MOS transistor is connected to the current output circuit.

[0011] As a further improvement of the present invention, the logic levels of each bit of the control word output by the first control port and the second control port are opposite.

[0012] As a further improvement of the present invention, the current output circuit includes: a twelfth MOSFET, a thirteenth MOSFET, and a fourteenth MOSFET; The sources of the twelfth MOS transistor, the thirteenth MOS transistor, and the fourteenth MOS transistor are connected to a voltage source; The gate of the thirteenth MOS transistor is connected to the gate of the fourteenth MOS transistor and the control switch array structure; The gate and drain of the twelfth MOS transistor are connected to the control switch array structure; The drain of the thirteenth MOS transistor is connected to the gate of the thirteenth MOS transistor and the control switch array structure; The drain of the fourteenth MOS transistor is connected to the DAC array to be calibrated.

[0013] Compared with existing technologies, the present invention has the following advantages: The present invention incorporates a micro-bias generation module, which is connected to a reference level and a DAC bias correction module. This allows for the injection of a small current into the current source of circuits such as the DAC to correct current deviations caused by various factors. Compared to traditional methods that rely solely on increasing device area to improve matching accuracy, the present invention achieves high-precision current calibration without significantly increasing chip area, ensuring the accuracy of the output current from the local current mirror bias current source. Attached Figure Description

[0014] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0015] Figure 1 This is a schematic diagram of the chip current calibration device described in this invention; Figure 2 This is a schematic diagram of the micro bias voltage generation module described in this invention; Figure 3 This is a schematic diagram of the structure of the DAC bias correction module described in this invention; Figure 4 This is a schematic diagram of the main structure of the calibration DAC module described in this invention; Figure 5 This is a schematic diagram illustrating the results of verifying that the correction range of the corrected DAC can follow the unit current change of the DAC array to be corrected, as shown in this invention. Figure 6 This is a schematic diagram illustrating the linear result of the total current generated by the linear change of the control word in this invention.

[0016] Figure labeling: 1. Minimal bias generation module; 2. DAC bias correction module; 3. DAC main correction module; 31. Current mirror circuit; 32. Control switch array structure; 33. Current output circuit; 4. Local current mirror bias current source; 5. DAC array to be corrected. Detailed Implementation

[0017] To make the technical problems solved by the present invention, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of the present invention will be further described in detail below. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] In deep submicron processes, random mismatches in components (such as transistor threshold voltage fluctuations and uneven oxide layer thickness) can cause the current at each weighted bit to deviate from the ideal value, severely deteriorating static linearity indicators such as INL and DNL. Simply increasing component size to suppress mismatch not only significantly increases chip area and cost but also introduces huge parasitic capacitances, thus dragging down the dynamic response speed of the DAC and reducing SFDR performance. Furthermore, in low-voltage designs, the signal swing can be reduced, making minute currents highly susceptible to environmental noise and temperature drift (such as changes in carrier mobility). Traditional circuits generating nA-level reference currents typically require a large area and struggle to maintain high accuracy under physical mismatches. This invention provides a chip current calibration device designed to compensate for main path deviations by injecting a small compensation current through an auxiliary path, resolving the design contradiction between current matching, low power consumption, and high dynamic accuracy within a small area. Figure 1 As shown, it includes: a micro bias voltage generation module 1, a calibration DAC bias module 2, and a calibration DAC main module 3; the micro bias voltage generation module 1 is connected to the local current mirror bias current source 4, the input terminal of the micro bias voltage generation module 1 is connected to the reference level, and the output terminal is connected to the input terminal of the calibration DAC bias module 2; the output terminal of the calibration DAC bias module 2 is connected to the input terminal of the calibration DAC main module 3; the output terminal of the calibration DAC main module 3 is connected to the local current mirror bias current source 4.

[0019] The local current mirror bias current source 4 is a common current mirror structure, providing I0 and multiple unit currents I. cell According to the basic principle of current mirrors, I0 and I cell There is a proportional relationship. Multiple unit currents I... cell Due to mismatch issues in the circuit layout, there will be slight deviations, requiring correction of the current I. cal Perform corrections.

[0020] The micro bias voltage generation module 1 generates two voltages ΔV with extremely close levels based on I0 from the local current mirror bias current source 4. tiny The output is sent to the calibration DAC bias module 2; the calibration DAC bias module 2 uses the ΔV generated by the micro bias generation module 1. tiny Applying a small difference ΔI to the gate of two MOSFETs with identical current source branches results in a slight difference in the current sources they generate. tiny Using ΔI tiny Generate a bias voltage V to be supplied to the main module 3 of the correction DAC. BN The main module 3 of the DAC performs a weighted current shunting on the reference generated by the bias module 2 of the DAC correction module. The N-bit control word can generate a minimum current of ΔI. tiny / 2 N-1 .

[0021] like Figure 2 As shown, the micro bias generation module 1 includes: a first operational amplifier, a first resistor R1, a second resistor R2, and a first MOSFET M1; the inverting input terminal of the first operational amplifier OP1 is connected to the reference level VREF, the non-inverting input terminal of the first operational amplifier OP1 is connected to the drain of the first MOSFET M1 through the second resistor R2, and the output terminal of the first operational amplifier OP1 is connected to the gate of the first MOSFET M1; the drain of the first MOSFET M1 is connected to the voltage source AVDD in sequence through the second resistor R2, the first resistor R1, and the local current mirror bias current source 4, and the source of the first MOSFET M1 is grounded to AVSS.

[0022] In the micro bias generation module 1, the reference level V REF The input is given to the inverting input of the first operational amplifier OP1, clamping the intermediate node between the first resistor R1 and the second resistor R2 to V. REF The input current source I0 is adjustable; when it flows through a sufficiently small resistor, it will create a tiny voltage difference ΔV. tiny =IR, through port V G1 and V G2 Output.

[0023] like Figure 3 As shown, the DAC bias correction module 2 includes: a second MOSFET M2, a third MOSFET M3, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, a second operational amplifier OP2, and a third resistor R3; the output terminal of the micro bias generation module 1 is connected to the gates of the second MOSFET M2 and the third MOSFET M3, and the sources of the second MOSFET M2 and the third MOSFET M3 are connected to the voltage source AVDD; the drain of the second MOSFET M2 is connected to the drain of the fourth MOSFET M4, the gate of the fourth MOSFET M4, the gate of the fifth MOSFET M5, and the inverting input terminal of the second operational amplifier OP2; the drain of the third MOSFET M3 is connected to the drain of the fifth MOSFET M5, the non-inverting input terminal of the second operational amplifier OP2, and the drain of the sixth MOSFET M6; the output terminal of the second operational amplifier OP2 is connected to the gate of the sixth MOSFET M6; the sources of the fourth MOSFET M4 and the fifth MOSFET M5 are grounded; and the source of the sixth MOSFET M6 is grounded through the third resistor R3.

[0024] The second MOSFET M2 and the third MOSFET M3 are identical in size and are both PMOS transistors. The gates of the second MOSFET M2 and the third MOSFET M3 are respectively connected to V generated by the micro bias generation module 1. G1 and V G2The fourth MOSFET M4 and the fifth MOSFET M5 are identical in size, both being NMOS transistors, and are used for current mirror replication. The second operational amplifier OP2 performs voltage clamping on the drains of the fourth MOSFET M4 and the fifth MOSFET M5 to minimize the deviation in the current mirror replication caused by the channel length modulation effect. Based on the fundamentals of current mirrors, the current flowing through the second MOSFET M2, the fourth MOSFET M4, and the fifth MOSFET M5 is the same, denoted as I1. If the current flowing through the third MOSFET M3 is denoted as I2, then the current flowing through the sixth MOSFET M6 is I2 - I1 = ΔI. tiny The gate of the sixth MOSFET M6 is connected to the output of the second operational amplifier OP2 (i.e., the clamping op-amp), and its potential V BN The output is used as the reference level for the current mirror in the main DAC module 3, thereby reducing ΔI tiny Perform copying and distribution.

[0025] ΔI tiny The derivation process is as follows: According to the square law of MOSFETs:

[0026] Ignoring the channel modulation effect of the second MOSFET M2 and the third MOSFET M3, we can obtain the following from the definition of transconductance:

[0027] Furthermore, we can obtain:

[0028] From the above equation, it can be seen that for a small change in voltage difference ΔV... tiny It is approximately assumed that (V) GS -V TH Since I0 is a constant, the correction scale of the DAC can be scaled almost linearly by adjusting its value. If we let I0 and the unit current I of the DAC array 5 to be corrected be... cell By maintaining the proportional replication relationship, the correction range of this correction DAC can be automatically matched to the unit current I. cell The changes.

[0029] like Figure 5 As shown, the calibration DAC main module 3 includes: a current mirror circuit 31, a control switch array structure 32, and a current output circuit 33; the current mirror circuit 31 is connected to the calibration DAC bias module 2 and the control switch array; the control switch array structure 32 is connected to the current output circuit 33 and the control port.

[0030] In one embodiment, the current mirror circuit 31 includes: a connected resistor array and several current mirror structures arranged in series. The current mirror structure includes: a seventh MOSFET M7 and a fourth resistor R4. The resistor array includes: a fifth resistor R5. The gate of the seventh MOSFET M7 is connected to the correction DAC bias module 2, the drain of the seventh MOSFET M7 is connected to the control switch array structure 32, the source of the seventh MOSFET M7 is grounded through the fourth resistor, and the source of the seventh MOSFET M7 is connected to adjacent current mirror structures through the fourth resistor R4 and the fifth resistor R5. The resistance value of the fourth resistor R4 is twice the resistance value of the fifth resistor R5.

[0031] In one embodiment, the control switch array structure 32 includes: a pair of terminal fixed switches connected to each other and a plurality of differential switch pairs arranged in parallel; the differential switch pairs include: an eighth MOSFET M8 and a ninth MOSFET M9; the gate of the eighth MOSFET M8 is connected to a first control port, the source of the eighth MOSFET M8 is connected to the source of the ninth MOSFET M9 and the current mirror circuit 31, and the drain of the eighth MOSFET M8 is connected to a current output circuit 33; the gate of the ninth MOSFET M9 is connected to a second control port, and the drain of the ninth MOSFET M9 is connected to the current output circuit 33.

[0032] In one embodiment, the end-fixed switch pair includes: a tenth MOSFET M10 and an eleventh MOSFET M11; the gate of the tenth MOSFET M10 is grounded to AVSS, the gate of the eleventh MOSFET M11 is connected to the power supply AVDD, the source of the tenth MOSFET M10 is connected to the source of the eleventh MOSFET M11 and the current mirror circuit 31, the drain of the tenth MOSFET M10 is connected to the current output circuit 33, and the drain of the eleventh MOSFET M11 is connected to the current output circuit 33.

[0033] In one embodiment, the present invention includes seven sets of current mirror structures. The remaining current mirror structures also include: fifteenth MOSFET M15 to twentieth MOSFET M20, sixth resistor R6 to eleventh resistor R11, and the remaining resistor array includes: twelfth resistor R12 to fifteenth resistor R15. The resistance values ​​of the fourth resistor R4 and the sixth to eleventh resistors R11 are the same as the third resistor R3; the resistance values ​​of the fifth resistor R5 and the eleventh to fifteenth resistors R11 are the same, which is half the resistance of the third resistor R3. The present invention includes six sets of differential switch pairs controlled by a control word. The remaining five sets of differential switch pairs include: twenty-first MOSFET M21 to thirtieth MOSFET M30. The end-fixed switch pairs fix the end current branch to the branch containing the twelfth MOSFET M12. Detailed connection methods are described above and will not be repeated here.

[0034] The control words output from the first control port and the second control port have their logic levels reversed for each bit.

[0035] In one embodiment, the current output circuit 33 includes: a twelfth MOSFET M12, a thirteenth MOSFET M13, and a fourteenth MOSFET M14; the sources of the twelfth MOSFET M12, the thirteenth MOSFET M13, and the fourteenth MOSFET M14 are connected to a voltage source; the gate of the thirteenth MOSFET M13 is connected to the gate of the fourteenth MOSFET M12 and the control switch array structure 32; the gate and drain of the twelfth MOSFET M12 are connected to the control switch array structure 32; the drain of the thirteenth MOSFET M13 is connected to the gate of the thirteenth MOSFET M13 and the control switch array structure 32; and the drain of the fourteenth MOSFET is connected to the DAC array 5 to be calibrated.

[0036] The seventh MOSFET M7 and the thirteenth through eighteenth MOSFETs M18 are NMOS transistors. The gates of these MOSFETs are all connected to the potential V of the correction DAC bias module 2. BN Together with the fourth resistor R4, fifth resistor R5, sixth resistor R6~eleventh resistor R11, and twelfth resistor R12~fifteenth resistor R15, the R2R array forms a source-degraded current mirror structure, which corrects the ΔI in the DAC bias module 2. tiny The process involves replication and current splitting. The currents flowing through the fourth resistor R4, the sixth resistor R6, and then through the eleventh resistor R11 from left to right are: ΔI tiny ΔI tiny / 2、ΔI tiny / 4、ΔI tiny / 8、ΔI tiny / 16、ΔI tiny / 32、ΔI tiny / 32. In the traditional structure, to generate this type of current and ensure accurate replication, the source potentials of the seventh MOSFET M7 and the thirteenth to eighteenth MOSFETs M18 need to be basically the same. For branches with smaller currents, the required resistor value will increase exponentially, which will lead to a significant increase in the area required for the current mirror circuit 31. The advantage of using an R2R resistor array is that the fifth resistor R5 and the twelfth to fifteenth resistors R15 can effectively utilize the total current flowing from their right side to raise the potential, saving a significant amount of area.

[0037] Input control word I CAL <5:0> and I CALN<5:0> Each bit has an inverted logic level, applied to the gate of one of the six groups of differential switch pairs controlled by the control word. These six groups include a differential switch pair consisting of the eighth MOSFET M8 and the ninth MOSFET M9, and the remaining five differential switch pairs consisting of the twenty-first MOSFET M21 to the thirtieth MOSFET M30. (The last part, "through I," appears to be an error and is left untranslated.) CAL <5:0> and I CALN The complementary control of <5:0> selects the current flow of each weighted branch to either the branch containing the thirteenth MOSFET M13 or the branch containing the twelfth MOSFET M12. The tenth MOSFET M10 and the eleventh MOSFET M11 form a fixed-end switch pair, where the gate of the tenth MOSFET M10 is grounded to the voltage AVSS, and the gate of the eleventh MOSFET M11 is connected to the power supply voltage AVDD, so that the final weighted current flows fixedly to the branch containing the twelfth MOSFET M12 and does not participate in the correction current output by the fourteenth MOSFET M14.

[0038] The current flowing through the thirteenth MOSFET M13 will be replicated to the fourteenth MOSFET M14 through a current mirror structure for output, generating I... CAL It can be used to calibrate the unit current source of the DAC array 5 to be calibrated by connecting the fourteenth MOSFET M14 and the tail current source transistor of the unit current source of the DAC array 5 to be calibrated in parallel.

[0039] The invention will now be further explained in conjunction with the specific implementation process, as follows: Verify that the correction range of the calibrated DAC can follow the unit current variation of the unit current source of the DAC array 5 to be calibrated: The unit current I of the unit current source of the DAC array 5 to be calibrated cell Since I0 in the micro bias generation module is copied from the same local current mirror bias current source, it can be assumed that it maintains a k-fold relationship, and the value of k remains almost unchanged under process angle changes.

[0040] The I0 in the micro bias generation module 1 is scanned in 2uA increments, starting at 2uA and ending at 20uA, while the control word I in the calibration DAC main module 3 is maintained. CAL <5:0> remains unchanged at 6'b010000, observe the generated correction current I. CAL The result is as follows Figure 5 As shown in the figure. The results show that the two maintain a high degree of linearity. That is, I... CAL The size can follow I cell Make the same proportional change.

[0041] Verify that the total current generated by the linear change of the control word is linear: Fixed I0 as 2uA, control word ICAL <5:0> changes from 6'd1 in steps of 2 to 6'd63. I CAL <5:0> and I CAL The relationship between current magnitudes is as follows: Figure 6 As shown in the figure. The results show that as the control word increases linearly, the output correction current also remains linear.

[0042] The present invention has the following beneficial effects: Voltage-to-current cross-domain conversion mechanism: Unlike the traditional method of directly obtaining a small current through a large resistor, this invention uses a cascaded micro-bias generation module and a correction DAC bias module. This generates a small voltage difference ΔV across a low-resistance resistor. tiny This is then applied to the gate of the matched MOS transistor, thereby converting it into a controlled differential microcurrent ΔI. tiny This architecture effectively avoids the huge area overhead required to generate nanoampere current.

[0043] Global linear scaling capability: The calibration step size of this invention is linearly adjustable. By adjusting the input reference current I0, the minimum resolution current of the subsequent calibration DAC main module 3 can be linearly scaled. This allows the calibration circuit to automatically match changes in the preset unit current value of the DAC array to be calibrated, achieving adaptive compensation for mismatch errors of different magnitudes.

[0044] This invention does not rely solely on increasing the area of ​​the current source device to improve matching. Instead, it constructs a complete calibration current generation chain consisting of a micro-bias generation module, a differential switch for micro-current generation, an R2R source degradation shunt, and a current mirror current output circuit. By converting the local current mirror bias current into a small voltage difference, and then using the matching differential switch to generate a small differential current, the area overhead caused by directly using ultra-large resistors to generate nanoamp-level current is avoided. Since the calibration current reference is from the same source as the unit current source of the DAC array to be calibrated, the output calibration range can also be scaled proportionally with the current source to be calibrated, thereby more accurately matching the current mismatch range under different process and bias conditions, and improving the calibration accuracy and applicability of the current source array.

[0045] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style of the specification is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0046] The technical principles of the present invention have been described above with reference to specific embodiments. These descriptions are merely for explaining the principles of the invention and should not be construed as limiting the scope of protection of the invention in any way. Based on this explanation, those skilled in the art can readily conceive of other specific embodiments of the invention without inventive effort, and these embodiments will all fall within the scope of protection of the present invention.

Claims

1. A chip current calibration device, characterized in that, include: Miniature bias generation module, DAC bias correction module, DAC main body correction module; The micro bias voltage generation module is connected to the local current mirror bias current source. The input terminal of the micro bias voltage generation module is connected to the reference level, and the output terminal is connected to the input terminal of the correction DAC bias module. The output of the calibration DAC bias module is connected to the input of the calibration DAC main module; The output of the correction DAC main module is connected to the local current mirror bias current source. The main module of the calibration DAC includes: a current mirror circuit, a control switch array structure, and a current output circuit; The current mirror circuit is connected to the correction DAC bias module and the control switch array structure; The control switch array structure is connected to the current output circuit and the control port; The current mirror circuit includes: a connected resistor array and several parallel current mirror structures, wherein the current mirror structure includes: a seventh MOSFET and a fourth resistor; the resistor array includes: a fifth resistor; The gate of the seventh MOS transistor is connected to the correction DAC bias module, the drain of the seventh MOS transistor is connected to the control switch array structure, the source of the seventh MOS transistor is grounded through the fourth resistor, and the source of the seventh MOS transistor is connected to the adjacent current mirror structure through the fourth resistor and the fifth resistor.

2. The chip current calibration device according to claim 1, characterized in that, The micro bias generation module includes: a first operational amplifier, a first resistor, a second resistor, and a first MOSFET; The inverting input of the first operational amplifier is connected to a reference level, the non-inverting input of the first operational amplifier is connected to the drain of the first MOSFET through the second resistor, and the output of the first operational amplifier is connected to the gate of the first MOSFET. The drain of the first MOSFET is connected to the voltage source in sequence through the second resistor, the first resistor, and the local current mirror bias current source, while the source of the first MOSFET is grounded.

3. The chip current calibration device according to claim 1, characterized in that, The calibration DAC bias module includes: a second MOSFET, a third MOSFET, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, a second operational amplifier, and a third resistor; The output terminal of the micro bias generation module is connected to the gate of the second MOS transistor and the third MOS transistor, and the source of the second MOS transistor and the third MOS transistor is connected to a voltage source. The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor, the gate of the fourth MOS transistor, the gate of the fifth MOS transistor, and the inverting input terminal of the second operational amplifier; The drain of the third MOS transistor is connected to the drain of the fifth MOS transistor, the non-inverting input terminal of the second operational amplifier, and the drain of the sixth MOS transistor. The output terminal of the second operational amplifier is connected to the gate of the sixth MOS transistor; The source of the fourth MOS transistor and the source of the fifth MOS transistor are grounded; The source of the sixth MOS transistor is grounded through the third resistor.

4. The chip current calibration device according to claim 1, characterized in that, The control switch array structure includes: a pair of fixed end switches connected to each other and a number of differential switch pairs arranged in parallel. The differential switch pair includes: an eighth MOS transistor and a ninth MOS transistor; The gate of the eighth MOS transistor is connected to the first control port, the source of the eighth MOS transistor is connected to the source of the ninth MOS transistor and the current mirror circuit, and the drain of the eighth MOS transistor is connected to the current output circuit. The gate of the ninth MOS transistor is connected to the second control port, and the drain of the ninth MOS transistor is connected to the current output circuit.

5. The chip current calibration device according to claim 4, characterized in that, The end-fixed switch pair includes: a tenth MOS transistor and an eleventh MOS transistor; The gate of the tenth MOS transistor is grounded, the gate of the eleventh MOS transistor is connected to the power supply, the source of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and the current mirror circuit, the drain of the tenth MOS transistor is connected to the current output circuit, and the drain of the eleventh MOS transistor is connected to the current output circuit.

6. The chip current calibration device according to claim 4, characterized in that, The logic levels of each bit in the control words output by the first control port and the second control port are reversed.

7. The chip current calibration device according to claim 1, characterized in that, The current output circuit includes: a twelfth MOSFET, a thirteenth MOSFET, and a fourteenth MOSFET; The sources of the twelfth MOS transistor, the thirteenth MOS transistor, and the fourteenth MOS transistor are connected to a voltage source; The gate of the thirteenth MOS transistor is connected to the gate of the fourteenth MOS transistor and the control switch array structure; The gate and drain of the twelfth MOS transistor are connected to the control switch array structure; The drain of the thirteenth MOS transistor is connected to the gate of the thirteenth MOS transistor and the control switch array structure; The drain of the fourteenth MOS transistor is connected to the DAC array to be calibrated.

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