Register configuration code generation method and device, equipment, storage medium and product

Abstract

The application discloses a register configuration code generation method and device, equipment, a storage medium and a product, relates to the chip design automation technical field, and the register configuration code generation method comprises: obtaining standardized input information, the standardized input information at least includes a system address mapping table describing a system global address space allocation; the system address mapping table is analyzed, mapping relationship information and target node identification of each address segment are extracted, so that the target register to be configured and the corresponding configuration requirement are determined; the configuration requirement is associated with the corresponding register specification information, and a structured configuration data set containing complete configuration parameters is generated; and register configuration code in a target format is generated based on the structured configuration data set. The application realizes the full-process automatic generation from the system architecture design description to the register configuration code, improves the generation efficiency and accuracy of the register configuration code, and improves the automation degree.

Description

Technical Field

[0001] This application relates to the field of chip design automation technology, and in particular to register configuration code generation methods, apparatus, devices, storage media and products. Background Technology

[0002] In chip system design, register configuration is a crucial link between hardware design and software drivers. Each functional node in a chip system typically contains a considerable number of configuration registers. These registers are used to control system bus routing, address space mapping, node attributes, and the enabling and parameter settings of various functions. During project development, developers need to translate the address segment divisions, mapping methods, target nodes, and other information in the system address mapping table into register configuration code for each configuration node, based on the system architecture design document.

[0003] In related technologies, register configuration code generation primarily relies on manual writing. Developers manually extract parameters such as the start and end addresses, target node identifiers, and mapping methods for each address segment, referring to the system address mapping table and register specification documents, and then fill these parameters into the corresponding register configuration fields. When the number of configuration nodes in the chip system is large and the address mapping relationships are complex, the workload of manual writing increases significantly, and the configuration code written by different developers varies in style, making review and verification difficult.

[0004] Related technologies also propose an automatic register configuration code generation method based on the register manual writing format. This method extracts the register manual content into a text file, calls a conversion script to read the text file, and generates register configuration code based on bus interface attributes. This method uses the register manual as an information source for automated processing, reducing the workload of manual writing to some extent. However, the automation level of this method is still insufficient. It cannot parse and utilize the system address mapping table as a core driver information source, has limited adaptability to complex projects with multiple configuration nodes and multiple mapping tables, and struggles to support the automatic derivation and configuration of node identifier mapping conversion relationships between different chips in multi-chip systems. Summary of the Invention

[0005] The main objective of this application is to provide a register configuration code generation method, apparatus, device, storage medium, and product, aiming to solve the technical problem of insufficient automation in register configuration code generation in related technologies.

[0006] To achieve the above objectives, this application proposes a register configuration code generation method, the method comprising: Obtain standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space; The system address mapping table is parsed to generate an initialization configuration file. Based on the initialization configuration file, the mapping relationship information of each address segment and the target node identifier are extracted to determine the target register to be configured and the corresponding configuration requirements. The configuration requirements are associated with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters; Based on the structured configuration dataset, register configuration code in the target format is generated.

[0007] In one embodiment, the step of parsing the system address mapping table to generate an initialization configuration file includes: Perform data validity verification on the system address mapping table. The data validity verification includes format verification and logical verification. The logical verification is used to detect semantic conflicts between different address segments in the system address mapping table. When the verification fails, an error log is generated and output, indicating the specific field that failed the verification and the corresponding reason for the failure; After the verification is passed, according to the mapping method corresponding to each address segment in the system address mapping table, the address segments are classified and summarized into different mapping tables to obtain a set of classified mapping tables. According to the preset allocation logic, a globally unique identity and a locally unique identity are assigned to each type of node involved in the classified mapping table set. The categorized mapping table set is integrated with the assigned globally unique identifier and locally unique identifier to generate an initialization configuration file.

[0008] In one embodiment, the step of generating the initialization configuration file includes: When the step of obtaining standardized input information also obtains project information, and the number of chips defined in the project information is at least two, the number of instantiations of each chip type is extracted from the project information, and the set of nodes to be configured across multiple chips is determined based on the number of instantiations of each chip type. For each node in the set of nodes to be configured, automatically derive the mapping and conversion relationship between the globally unique identifier and the locally unique identifier; The mapping transformation relationship is integrated with the classified mapping table set, the assigned globally unique identity, and the locally unique identity to generate the initialization configuration file.

[0009] In one embodiment, the step of associating the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters includes: Extract the target node type corresponding to the target node identifier, as well as the base address and tail address corresponding to each address segment from the configuration requirements; Based on the target node type, search the register specification information for all registers to be configured that are included in the target node type to obtain a list of registers to be configured; For each register to be configured in the list of registers to be configured, the address-related configuration parameters of the register to be configured are determined based on the base address and the tail address; The address-related configuration parameters are matched with the bit fields defined in the register specification information of the register to be configured to generate the configuration data item of the register to be configured. The configuration data items corresponding to all registers to be configured in the register list are aggregated to obtain the structured configuration dataset.

[0010] In one embodiment, the step of associating the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters includes: Read the initialization configuration file and extract the mapping method, target node identifier, and globally unique identity identifier corresponding to each address segment from the initialization configuration file. By configuring the parser, the mapping method, the target node identifier, and the globally unique identity identifier are used as the association primary key; Based on the associated primary key, locate the register bit field definition in the register specification information that matches the target node identifier; The mapping method and the globally unique identifier are combined with the register bit field definition to generate the structured configuration dataset.

[0011] In one embodiment, after the step of generating the structured configuration dataset, the method further includes: Receive custom configuration parameters input through a special configuration intervention interface, wherein the custom configuration parameters include supplementary configuration data or instructions to override parameters already generated in the structured configuration dataset; According to the overwrite instruction, the supplementary configuration data is written into the structured configuration dataset, replacing the original parameters in the structured configuration dataset corresponding to the overwrite instruction, to obtain an updated structured configuration dataset, which is then used as input for subsequent code generation steps.

[0012] Furthermore, to achieve the above objectives, this application also proposes a register configuration code generation apparatus, which includes: The acquisition module is used to acquire standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space. The parsing module is used to parse the system address mapping table to generate an initialization configuration file. Based on the initialization configuration file, it extracts the mapping relationship information of each address segment and the target node identifier to determine the target register to be configured and the corresponding configuration requirements. The association module is used to associate the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters. The generation module is used to generate register configuration code in the target format based on the structured configuration dataset.

[0013] In addition, to achieve the above objectives, this application also proposes a register configuration code generation device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the register configuration code generation method described above.

[0014] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the register configuration code generation method described above.

[0015] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the register configuration code generation method described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: Compared to related technologies that rely on manually entering configuration parameters item by item by referring to the system address mapping table and register specification documents, this application obtains standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space; parses the system address mapping table to generate an initialization configuration file; based on the initialization configuration file, extracts the mapping relationship information of each address segment and the target node identifier to determine the target register to be configured and the corresponding configuration requirements; associates the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters; and generates register configuration code in the target format based on the structured configuration dataset. Understandably, this application adopts an automated processing paradigm with the system address mapping table as the core driving data source. After obtaining standardized input information containing at least the system address mapping table, the semantic information of each address segment in the mapping table is automatically parsed and the mapping relationship information and target node identifier are extracted. This automatically determines which registers need to be configured and what the corresponding configuration requirements are. Therefore, based on the association operation between the determined configuration requirements and the register specification information, the configuration parameters can be automatically matched and filled, thereby determining a structured configuration dataset containing complete configuration parameters. Finally, the entire process of generating register configuration code from the system address mapping table is automated, solving the technical problem of insufficient automation in register configuration code generation in related technologies. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating the register configuration code generation method of this application is provided in Embodiment 1. Figure 2 A schematic diagram of the process for generating the initialization configuration file provided in Embodiment 1 of the register configuration code generation method of this application; Figure 3 A schematic diagram illustrating the process of obtaining a structured configuration dataset provided in Embodiment 1 of the register configuration code generation method of this application; Figure 4 This is a schematic diagram of the module structure of the register configuration code generation device according to an embodiment of this application; Figure 5This is a schematic diagram of the device structure of the hardware operating environment involved in the register configuration code generation method in this application embodiment.

[0020] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0022] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0023] The main solution in this application embodiment is: Obtain standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space; The system address mapping table is parsed to generate an initialization configuration file. Based on the initialization configuration file, the mapping relationship information of each address segment and the target node identifier are extracted to determine the target register to be configured and the corresponding configuration requirements. The configuration requirements are associated with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters; Based on the structured configuration dataset, register configuration code in the target format is generated.

[0024] In this embodiment, the application uses a register configuration code generation device as the execution subject. For ease of description, it will be referred to as "device" in detail below.

[0025] Compared to related technologies that rely on manually entering configuration parameters item by item by referring to the system address mapping table and register specification documents, or simply using the register manual as a single information source for format conversion, this application obtains standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space; parses the system address mapping table to generate an initialization configuration file; based on the initialization configuration file, extracts the mapping relationship information of each address segment and the target node identifier to determine the target register to be configured and the corresponding configuration requirements; associates the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters; and generates register configuration code in the target format based on the structured configuration dataset. Understandably, this application adopts an automated processing paradigm with the system address mapping table as the core driving data source. After obtaining standardized input information containing at least the system address mapping table, the semantic information of each address segment in the mapping table is automatically parsed and the mapping relationship information and target node identifier are extracted. This automatically determines which registers need to be configured and what the corresponding configuration requirements are. Therefore, based on the association operation between the determined configuration requirements and the register specification information, the configuration parameters can be automatically matched and filled, thereby determining a structured configuration dataset containing complete configuration parameters. Finally, the entire process of generating register configuration code from the system address mapping table is automated, solving the technical problem of insufficient automation in register configuration code generation in related technologies.

[0026] Because the generation of register configuration code in related technologies either relies on manual translation by comparing each item with the system address mapping table and register specification documents, or can only be based on the fixed format of the register manual for simple text conversion, neither of which elevates the system address mapping table to the core information source driving the configuration generation process. Therefore, when facing complex chip projects with multiple configuration nodes and multiple mapping tables, developers still need to invest a lot of time in manual sorting, translation and verification. During the configuration process, problems such as missing address segments and incorrect node identification are prone to occur, and the degree of automation is obviously insufficient.

[0027] This application provides a solution that transforms the system address mapping table from a configured target object into a core information source driving configuration generation, making the entire register configuration code generation process revolve around the semantic parsing of the system address mapping table. The system address mapping table itself carries complete planning information for the chip's global address space, including the start and end addresses of each address segment, mapping methods, and the type and identifier of the target node. This information precisely corresponds to the core configuration parameters that need to be filled into the registers of each configuration node. This application automatically parses the aforementioned semantic information in the system address mapping table, automatically identifies the target registers to be configured for each address segment and their configuration requirements, and then automatically completes the association matching and filling of configuration parameters by combining register specification information, generating a structured configuration dataset and finally outputting register configuration code in the target format. This achieves a direct mapping from system architecture design documents to register configuration code. Based on this solution, in complex chip projects containing multi-level mapping relationships or a large number of configuration nodes, developers only need to provide standardized system address mapping tables and other input information to automatically obtain complete register configuration code. The configuration process no longer relies on manual comparison and translation, effectively reducing problems such as address segment omissions and node identifier errors caused by manual operation, and improving the generation efficiency and accuracy of register configuration code.

[0028] Based on this, embodiments of this application provide a register configuration code generation method, referring to... Figure 1 , Figure 1 A flowchart illustrating the first embodiment of the register configuration code generation method for this application.

[0029] In this embodiment, the register configuration code generation method includes steps S10 to S40: Step S10: Obtain standardized input information, wherein the standardized input information includes at least a system address mapping table describing the allocation of the system's global address space; It should be noted that standardized input information refers to a collection of information organized and described according to a preset structured format, including but not limited to YAML, JSON, CSV, or Excel formats. The system address mapping table is structured data describing the global address space allocation scheme of the chip system. Its content includes the start and end addresses of each address segment, the mapping method corresponding to each address segment, the unique identifier of the target node, and the node type of the target node. Global address space allocation refers to the distribution plan of all addressable memory and register spaces within the chip system across various bus nodes.

[0030] Understandably, this step provides a unified and complete data foundation for subsequent automatic parsing and configuration generation by obtaining multi-source standardized input information centered on the system address mapping table, so that the configuration generation process no longer relies on manual extraction and organization of information from scattered documents.

[0031] Step S20: Parse the system address mapping table to generate an initialization configuration file. Based on the initialization configuration file, extract the mapping relationship information of each address segment and the target node identifier to determine the target register to be configured and the corresponding configuration requirements. It should be noted that mapping relationship information refers to the correspondence established between each address segment and the target node in the system address mapping table, including but not limited to the binding relationship between the address range from the start address to the end address and the specific target node, as well as the mapping mode adopted. Target node identifier refers to the identity marker used to uniquely identify a target node in the chip system, including but not limited to node number, node type code, or the node's position index in the bus topology. Configuration requirements refer to the set of configuration parameters that need to be written into the registers corresponding to a specific target node and address segment, including but not limited to address-related configuration parameters, node identifier configuration parameters, and mapping mode configuration parameters.

[0032] Understandably, this step automatically extracts the mapping relationship information and target node identifier contained in the system address mapping table by performing semantic parsing, and then deduces which fields of which registers need to be configured and what values ​​they should be configured to, thus realizing the automatic transformation from architecture design description to configuration action.

[0033] Step S30: Associate the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters; It should be noted that register specification information refers to standardized metadata describing each register within each configuration node, including but not limited to register name, register bit width, register offset address within its configuration node, definition of each register field, reset default value, and access permissions. A structured configuration dataset refers to a collection of data organized according to a preset data model, containing complete register configuration parameters. Each record in this dataset corresponds to the complete configuration information of a register to be configured, covering the configuration node to which the register belongs, the register offset address, the configuration values ​​of each field, and the source of each configuration value.

[0034] Understandably, this step automatically calculates and fills in the configuration parameters by matching and associating the configuration requirements obtained from parsing the system address mapping table with the register bit fields defined in the register specification information, without the need for manual table lookups and calculations, thereby improving the efficiency and accuracy of configuration data generation.

[0035] Step S40: Based on the structured configuration dataset, generate register configuration code in the target format.

[0036] It should be noted that the target format refers to the syntax specifications and file type followed by the final output register configuration code, including but not limited to C language header file format, C++ language header file format, text list format, or structured data file format. Register configuration code is a configuration output file that can be directly used in chip system software development or hardware verification environments, containing the complete register write sequence or structured configuration declaration for each configuration node.

[0037] Understandably, this step converts the configuration parameters in the structured configuration dataset into register configuration code that conforms to the target format requirements by using a template engine or preset code generation rules. This completes the fully automated output from the system address mapping table to the final usable configuration code, allowing the configuration generation results to be directly integrated into the project's software engineering or verification environment.

[0038] This embodiment provides a register configuration code generation method, which adopts an automated processing paradigm with the system address mapping table as the core driving data source. After obtaining standardized input information containing at least the system address mapping table, the semantic information of each address segment in the mapping table is automatically parsed and the mapping relationship information and target node identifier are extracted. This automatically determines which registers need to be configured and what the corresponding configuration requirements are. Therefore, based on the association operation between the determined configuration requirements and the register specification information, the configuration parameters can be automatically matched and filled, thereby determining a structured configuration dataset containing complete configuration parameters. Finally, the entire process from the system address mapping table to the register configuration code is automatically generated, solving the technical problem of insufficient automation in register configuration code generation in related technologies.

[0039] In one feasible implementation, the step of parsing the system address mapping table to generate an initialization configuration file includes: Perform data validity verification on the system address mapping table. The data validity verification includes format verification and logical verification. The logical verification is used to detect semantic conflicts between different address segments in the system address mapping table. When the verification fails, an error log is generated and output, indicating the specific field that failed the verification and the corresponding reason for the failure; After the verification is passed, according to the mapping method corresponding to each address segment in the system address mapping table, the address segments are classified and summarized into different mapping tables to obtain a set of classified mapping tables. According to the preset allocation logic, a globally unique identity and a locally unique identity are assigned to each type of node involved in the classified mapping table set. The categorized mapping table set is integrated with the assigned globally unique identifier and locally unique identifier to generate an initialization configuration file.

[0040] It should be noted that data validity verification refers to the automated check of the format and logical correctness of input data before it enters the subsequent processing flow. Format verification refers to checking whether the input file follows the preset structured format syntax requirements, including but not limited to file encoding format, field integrity, and the validity of numerical types. Logical verification refers to checking the inherent rationality of the values ​​of each field in the input data and the correctness of the relationships between different fields. Semantic conflict refers to anomalies that do not conform to the chip system design specifications, such as address space overlap, address gaps, and configuration contradictions of the same target node under different mapping rules between different address segments in the system address mapping table. Error log refers to the data file or output content used to record all error information found during the verification process. Each error message includes the file location of the error, the specific error field, and the specific reason why the field does not meet the verification rules. The categorized mapping table set refers to the collection of multiple mapping tables formed after classifying each address segment in the system address mapping table into the corresponding type of mapping table according to different mapping methods. Different mapping tables correspond to different bus layers or different address space domains. A globally unique identifier (GUI) is an identity number that uniquely identifies a node within the entire chip system. A locally unique identifier (RUI) is an identity number that uniquely identifies a node within a single chip. The same node may have different RUIs on different chips, but can share the same GUI. The initialization configuration file is a structured data file generated after successful verification, which users can use for final review and adjustment. This file summarizes the categorized address range mappings and the globally and locally unique identifiers assigned to each node in a readable format.

[0041] Understandably, this implementation introduces a pre-emptive validity verification mechanism during the parsing of the system address mapping table. This automatically identifies and reports potential format errors and logical conflicts before data enters the core configuration generation process, preventing erroneous data from being passed downstream and affecting the correctness of the final configuration code. Simultaneously, this implementation categorizes and summarizes the verified address segments according to their mapping methods and automatically assigns globally unique and locally unique identifiers to each type of node, generating a structured initialization configuration file. This initialization configuration file serves as standardized input for subsequent automatic association operations and also allows users to manually review and adjust the classification results and identifier assignments before proceeding to later steps, thus balancing the needs of automated processing efficiency with the requirements of fine-grained manual control.

[0042] For example, refer to Figure 2 In this process, the obtained system address mapping table is first subjected to data validity verification. The verification covers both format verification and logical verification. Logical verification is mainly used to detect semantic conflicts such as address space overlap, address gaps, or contradictory mapping rules between different address segments in the system address mapping table. When the verification fails, an error log is generated and output, indicating the specific fields that failed the verification and the corresponding reasons for the failure, facilitating developers to locate and correct problems in the input data. When the verification passes, each address segment is classified into its corresponding type of mapping table according to the mapping method in the system address mapping table, forming a set of categorized mapping tables. Subsequently, according to the preset allocation logic, globally unique identifiers and locally unique identifiers are assigned to each type of node involved in the categorized mapping table set. The categorized mapping table set is then integrated with the assigned identifiers to finally generate an initialization configuration file. This initialization configuration file serves as a standardized intermediate product for subsequent configuration association operations, allowing users to review and adjust the classification results and identifier allocations before proceeding to later steps.

[0043] In one feasible implementation, the step of generating the initialization configuration file includes: When the step of obtaining standardized input information also obtains project information, and the number of chips defined in the project information is at least two, the number of instantiations of each chip type is extracted from the project information, and the set of nodes to be configured across multiple chips is determined based on the number of instantiations of each chip type. For each node in the set of nodes to be configured, automatically derive the mapping and conversion relationship between the globally unique identifier and the locally unique identifier; The mapping transformation relationship is integrated with the classified mapping table set, the assigned globally unique identity, and the locally unique identity to generate the initialization configuration file.

[0044] It should be noted that project information refers to structured data defining the global configuration parameters of a chip project. This includes, but is not limited to, the storage paths of input / output files, chip type definitions, and the number of instantiations for each chip type. "At least two chips" means that the total number of chip instances defined in the project information is no less than two, indicating that the project is a multi-chip system. The number of instantiations for a chip type refers to the specific number of times the same chip type is instantiated and used in a multi-chip system. The set of nodes to be configured across multiple chips refers to the set of configuration nodes in a multi-chip system whose communication links or address mappings involve two or more chips. The register configuration of these nodes needs to consider both the local perspective within their respective chips and the global perspective across chips. The mapping conversion relationship refers to the correspondence conversion rules between the globally unique identifier of the same node and its locally unique identifier within its specific chip in a multi-chip system. This mapping conversion relationship is used to achieve correct indexing of node identifiers between different chips during cross-chip communication.

[0045] Understandably, this implementation uses the number of chips defined in the project information as a criterion to automatically identify nodes spanning multiple chips in a multi-chip system and automatically derives the mapping relationship between the globally unique identifiers and locally unique identifiers of these nodes. This mapping relationship is a key parameter for link node register configuration. In a multi-chip system, developers originally needed to manually derive and fill in this relationship based on the node allocation scheme of each chip. This implementation incorporates this derivation process into an automated workflow, avoiding potential errors in identifier correspondence caused by manual derivation. Furthermore, the mapping relationship is integrated into the initialization configuration file for unified output, ensuring that the initialization configuration file in a multi-chip system can fully reflect the node identifier mapping relationship across chips. This provides an accurate multi-chip perspective input basis for subsequent register configuration data generation.

[0046] In one feasible implementation, the step of associating the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters includes: Extract the target node type corresponding to the target node identifier, as well as the base address and tail address corresponding to each address segment from the configuration requirements; Based on the target node type, search the register specification information for all registers to be configured that are included in the target node type to obtain a list of registers to be configured; For each register to be configured in the list of registers to be configured, the address-related configuration parameters of the register to be configured are determined based on the base address and the tail address; The address-related configuration parameters are matched with the bit fields defined in the register specification information of the register to be configured to generate the configuration data item of the register to be configured. The configuration data items corresponding to all registers to be configured in the register list are aggregated to obtain the structured configuration dataset.

[0047] It should be noted that the target node type refers to the node classification identifier based on the target node's functional positioning and bus connection relationship in the chip system, including but not limited to requesting node type, owner node type, slave node type, and input / output management node type. The base address and tail address refer to the start and end addresses of a certain address segment in the system address mapping table. The base address defines the starting position of the address segment in the global address space, and the tail address defines the ending position of the address segment in the global address space. Together, the base address and tail address determine the complete address range covered by the address segment. The list of registers to be configured is an ordered set of all registers to be configured corresponding to the target node type. Each entry in this list corresponds to the specification definition of a register that needs to be written with configuration parameters. Address-related configuration parameters refer to the register configuration values ​​directly associated with the base address and tail address of the address segment, including but not limited to the base address encoded value and address range encoded value of the high-order address field to be filled into the register. The configuration data item refers to the complete configuration record generated for a single register to be configured. This record includes the offset address of the register within its own configuration node, the value to be configured for each bit field in the register, and the basis for generating these values.

[0048] Understandably, this implementation breaks down the process of associating configuration requirements with register specification information into a progressively refined process, starting from target node type identification, generating a list of registers to be configured, calculating address-related configuration parameters, and matching register bit fields one by one. This implementation uses the target node type as an index to quickly locate all registers to be configured within the register specification information for that type of node. Then, it automatically calculates the address-related configuration parameters for each register based on the base address and tail address extracted from the system address mapping table. The calculation results are then matched one by one with the predefined bit fields in the register specification information to generate configuration data items for each register. Finally, all configuration data items are aggregated into a structured configuration dataset. This progressively refined association mechanism ensures that the configuration value of each register has a clear generation basis and a traceable calculation source, avoiding configuration deviations caused by address calculation errors or bit field matching mistakes during manual comparison.

[0049] For example, refer to Figure 3In this process, the target node type corresponding to the target node identifier and the base and tail addresses corresponding to each address segment are first extracted from the configuration requirements. Then, based on the target node type, all registers to be configured contained in the register specification information are searched to obtain a list of registers to be configured. For each register to be configured in the list, its address-related configuration parameters, including base address encoding values ​​and address range encoding values, are determined based on the base and tail addresses corresponding to the address segment. These address-related configuration parameters are then matched one by one with the predefined bit fields in the register specification information of the register to be configured to generate the configuration data item corresponding to the register to be configured. After all registers in the list of registers to be configured have completed the above matching process, all generated configuration data items are aggregated to finally obtain a structured configuration dataset. Each record in this structured configuration dataset corresponds to the complete configuration information of a register to be configured, covering the register offset address, the configuration values ​​of each bit field, and the basis for generating the configuration values, which can be directly used as input data for subsequent code generation steps.

[0050] In one feasible implementation, the step of associating the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters includes: Read the initialization configuration file and extract the mapping method, target node identifier, and globally unique identity identifier corresponding to each address segment from the initialization configuration file. By configuring the parser, the mapping method, the target node identifier, and the globally unique identity identifier are used as the association primary key; Based on the associated primary key, locate the register bit field definition in the register specification information that matches the target node identifier; The mapping method and the globally unique identifier are combined with the register bit field definition to generate the structured configuration dataset.

[0051] It should be noted that the initialization configuration file refers to a structured data file generated during the system address mapping table parsing stage. This file summarizes the categorized mapping table set and the assigned globally unique identifiers and locally unique identifiers. This file serves as one of the standardized inputs for subsequent association operations. The mapping method refers to the bus routing mode identifier used by each address segment in the system address mapping table, including but not limited to direct mapping, hash mapping, or region-based mapping. Different mapping methods correspond to different register bit field encoding rules. The configuration parser is a functional module used to read the initialization configuration file and extract structured configuration information. This module parses each field in the initialization configuration file according to a preset data model and combines the extracted mapping method, target node identifier, and globally unique identifier into an association primary key. The association primary key is a composite index key composed of the mapping method, target node identifier, and globally unique identifier fields. It is used to uniquely locate the register bit field definition corresponding to a specific address segment and target node in the register specification information. Register bit field definition refers to the detailed description of each bit field inside each register in the register specification information, including but not limited to the bit field name, the start bit and the end bit of the bit field, the functional meaning of the bit field, and the range of values ​​that the bit field can be written to.

[0052] It is understood that this implementation provides an alternative path for associating configuration requirements with register specification information, independent of the aforementioned register-by-register matching method starting from configuration requirements. This implementation directly utilizes the initialization configuration file generated during the parsing phase as the input source for the association operation. The configuration parser combines the completed mapping method, target node identifier, and globally unique identifier from the initialization configuration file into an association key. This association key is then used to locate and match within the register specification information. Finally, the mapping method and globally unique identifier are fused with the corresponding register bit field definitions to generate a structured configuration dataset. This implementation achieves efficient correspondence between the initialization configuration file and register specification information through the association key mechanism, enabling the node identifier allocation results in the initialization configuration file, which have been reviewed and adjusted by the user, to directly drive the subsequent generation of register configuration data, reducing intermediate conversion steps.

[0053] In one feasible implementation, after the step of generating the structured configuration dataset, the method further includes: Receive custom configuration parameters input through a special configuration intervention interface, wherein the custom configuration parameters include supplementary configuration data or instructions to override parameters already generated in the structured configuration dataset; According to the overwrite instruction, the supplementary configuration data is written into the structured configuration dataset, replacing the original parameters in the structured configuration dataset corresponding to the overwrite instruction, to obtain an updated structured configuration dataset, which is then used as input for subsequent code generation steps.

[0054] It should be noted that the specialized configuration intervention interface refers to a pre-defined functional entry point in the fully automated configuration generation process for receiving external intervention data. This interface supports injecting additional configuration parameters into the configuration generation process through manual editing or importing external files. External file formats include, but are not limited to, text, Excel, or YAML formats. Custom configuration parameters refer to configuration values ​​or instructions manually specified by the user based on specific debugging needs or special application scenarios. Their source is independent of standardized input information such as system address mapping tables and register specification information, and includes, but is not limited to, assigning bit fields to specific registers, overriding identifiers for specific nodes, or modifying the mapping method for specific address ranges. Supplementary configuration data refers to additional configuration content not included in the standardized input information but actually required to be written to registers for specific items. Override instructions are replacement instructions issued by the user for one or more configuration parameters that have been automatically generated in the structured configuration dataset. These instructions explicitly specify the location of the parameter to be replaced in the structured configuration dataset and the new parameter value used for replacement. The updated structured configuration dataset refers to the new structured configuration dataset obtained after writing and replacing the original structured configuration dataset according to the overwrite instruction. This dataset retains all the original configuration parameters that were not modified by the overwrite instruction, and replaces the original parameters specified by the overwrite instruction with supplementary configuration data.

[0055] Understandably, this implementation provides a channel for manual intervention after generating the structured configuration dataset, allowing users to input custom configuration parameters through a specialized configuration intervention interface to supplement or override the automatically generated configuration content. In the fully automated configuration generation process, there may be a few project-specific requirements or debugging scenarios that necessitate manually specifying specific configuration values. This implementation addresses this by replacing the override command with the original structured configuration dataset, enabling manually specified configuration parameters to seamlessly integrate into the automatically generated configuration data system. This maintains the overall automation level of the process while preserving flexible manual intervention capabilities for special scenarios. The updated structured configuration dataset serves as input for subsequent code generation steps, ensuring that the final output register configuration code simultaneously reflects both the automatically generated standardized configuration and the manually supplemented customized configuration.

[0056] Based on the first embodiment of this application, in the second embodiment of this application, the same or similar content as the first embodiment can be referred to the above description, and will not be repeated hereafter.

[0057] This embodiment provides a specific implementation of a register configuration code generation method. The scheme in this embodiment uses the System Address Map (SAM table) as the core driving data source, and through a three-layer architecture of standard input layer, logic processing layer, and code generation layer, achieves fully automatic generation from standardized input information to register configuration code.

[0058] The standard input layer in this embodiment is used to provide standardized input information, specifically including configuration node information, system address mapping table, project information, configuration node register information, and optional specialized configuration intervention interface.

[0059] Configuration node information provides standardized metadata for each configuration node in the chip system, representing the chip's structural information, including the type, quantity, and unique identifier of each configuration node. Configuration node information supports various structured file formats, such as XML, CSV, Excel, YAML, and JSON. An example of YAML-formatted configuration node information is provided, which defines the name and identifier fields of various node types in the chip system, such as request nodes, owner nodes, and dependent nodes, using a tree-like hierarchical structure.

[0060] The system address mapping table provides a standardized system-level address space allocation scheme, clearly defining the mapping relationship of each configuration node in the global address space. It supports file formats such as Excel, CSV, and XML. Taking the Excel format of the system address mapping table as an example, each row corresponds to an address range, and each column defines the start address, end address, mapping method, unique identifier of the target node, and node type of that address range.

[0061] Project information is used to define global parameters at the project level, including input and output file paths, chip types and quantities, etc. It supports the configuration of multi-chip systems and the extension of their connection relationships, and supports file formats such as Excel and YAML.

[0062] Specialized configuration access interfaces are set up to meet specific scenarios or debugging needs. They provide the ability to manually edit or inject additional configuration parameters through specific files, including Excel format, text format, etc.

[0063] The configuration node register information is used to provide detailed specifications for each register within the configuration node, including register name, bit width, offset address, bit field definition, reset default value, and access permissions. It supports file formats such as XML, CSV, Excel, YAML, and JSON.

[0064] The logic processing layer in this embodiment includes a data parser, a configuration parser, a configuration node register parser, and a register configuration structured data generator. The logic processing layer also outputs error logs and parsing result reports, as well as initialization configuration files or configuration files.

[0065] The data parser reads and parses configuration node information, system address mapping tables, and project information, verifying the legality of the data. This verification includes format and logical checks, and outputs error logs and parsing result reports, generating an initialization configuration file. Error logs and parsing result reports are returned during the data verification process, including format or logical errors identified during verification, and the printout of key parsing results. The initialization configuration file or configuration file categorizes and summarizes system address mapping table information into different mapping tables, such as the Request Node System Address Map (RNSAM) and the Home Node System Address Map (HNSAM), etc. It assigns globally unique identifiers and locally unique identifiers to various types of nodes according to preset allocation logic, ultimately generating a standardized structured data file. This structured data file can be in a specific format, such as an Excel file or a JSON file, serving as a reference for subsequent processing. Users can perform final review and adjustment of the allocation results in this initialization configuration file, such as adjusting the mapping method of the home node in the Double Data Rate Synchronous Dynamic Random Access Memory Region (DDR region).

[0066] The configuration parser is used to parse the initialization configuration file or information in the configuration file, integrate the basic information of each node, classify them according to the address segment type in the system address mapping table, integrate the configuration information required by each address segment, such as base address and tail address, target node type, target node identifier, record the globally unique identifier and the locally unique identifier and their mapping relationship, and provide them to the register configuration structured data generator in a structured data format.

[0067] The configuration node register parser is used to parse configuration node register information, extract the specification data of each register, and provide it to the register configuration structured data generator in a structured data format.

[0068] The register configuration structured data generator is used to intelligently associate and fuse system configuration parameters with register specification data according to predefined configuration rules and mapping relationships, generating a final complete and structured register configuration dataset that contains all the information required for the final code.

[0069] The code generation layer in this embodiment includes a code generator, register configuration code, and error logs and register configuration reports. The code generator, based on a template engine, transforms the register configuration dataset into source code in the target language or format, and includes validity checks during the code generation process. The register configuration code is the final automated register configuration output file, supporting file formats such as C language header files, C++ language header files, and text list formats. The error log and register configuration report are returned during the validation phase of the code generation process, including format or logical errors identified during validation, as well as the printed output of key results from the code generation process.

[0070] The following describes the workflow of this embodiment using a specific chip system interconnect scenario. In a chip system based on a mesh network interconnect architecture, there are four node types: requesting nodes, home nodes, slave nodes, and input / output management nodes. This chip system needs to map the target node of a request using a system address mapping table. Therefore, in the register configuration, the contents of the system address mapping table typically need to be configured into the registers corresponding to each node. The configuration content includes the start and end addresses of each address segment, the mapping method corresponding to the address segment, the unique identifier of the target node, the node type, and some other configurations. Due to the large amount of configuration content, manual coding is labor-intensive, and errors are prone to occur when matching node identifiers.

[0071] Using the register configuration code generation method of this embodiment, developers first prepare standardized input information, including a system address mapping table edited in Excel format, configuration node information edited in YAML format, project information edited in Excel or YAML format, and configuration node register information edited in JSON or Excel format. The data parser reads and parses the above input information, performing format and logical checks. In the logical check, the data parser detects semantic conflicts such as address space overlaps between different address segments, address gaps, or configuration contradictions of the same target node under different mapping rules in the system address mapping table. After passing the check, the data parser categorizes and summarizes each address segment in the system address mapping table according to the mapping method into different mapping tables such as the request node system address mapping table and the home node system address mapping table. Based on preset allocation logic, it assigns globally unique identifiers and locally unique identifiers to request node types, globally unique identifiers and locally unique identifiers to home node types, globally unique identifiers and locally unique identifiers to subordinate node types, and so on. Finally, the categorized mapping table set and the assigned identifiers are integrated to generate the initialization configuration file. Users can review this initialization configuration file, for example, to check if the mapping method of the belonging node needs to be adjusted. In this initialization configuration file, developers can also inject additional project-specific configuration parameters through a specialized configuration intervention interface, such as overriding the identifier assignment result of a certain node.

[0072] After reviewing and adjusting the initialization configuration file, the configuration parser reads the configuration file, extracts the mapping method, target node identifier, and globally unique identifier for each address segment, and passes these fields to the register configuration structured data generator. Simultaneously, the configuration node register parser parses the configuration node register information, extracts the offset address, bit field definition, and other specification data for each register, and also passes this data to the register configuration structured data generator. Based on preset configuration rules, the register configuration structured data generator matches the mapping method field with the corresponding pattern encoding bit field in the register bit field definition, matches the globally unique identifier with the target node identifier bit field, and matches the base address and tail address with the high-order bits of the address field, generating complete configuration data items for each corresponding register segment, and finally aggregating them into a structured configuration dataset.

[0073] The code generator reads the structured configuration dataset and, based on a predefined C language header file template, fills in each data item in the configuration dataset into the corresponding placeholder position in the template, generating a C language header file containing configuration code for all request node system address mapping table registers, home node system address mapping table registers, and other node registers. This header file can be directly referenced by the chip system's firmware project or verification environment.

[0074] In a multi-chip system, when the project information defines at least two chips, the data parser extracts the instantiation count of each chip type from the project information, determines the set of nodes to be configured across multiple chips, and automatically derives the mapping relationship between globally unique identifiers and locally unique identifiers for each node in the set. In a mesh network multi-chip interconnect architecture, each chip needs to convert between globally unique identifiers and locally unique identifiers to index specific nodes, and the corresponding conversion relationship needs to be configured in different link node registers. This embodiment incorporates the derivation of this mapping relationship into the automated processing flow of the data parser or configuration parser. The derivation result is output along with the initialization configuration file for use in subsequent register configuration data generation steps.

[0075] As an alternative implementation, the structured file format for the standardized input information described above is not limited to the formats listed in this embodiment, such as Excel, YAML, JSON, CSV, and XML. Other structured or semi-structured file formats with hierarchical data organization capabilities can also be used. Configuration node information and the system address mapping table can be stored together in the same file or separately in multiple independent files, indexed by the file paths defined in the project information. The classification method for each address segment in the system address mapping table is not limited to classification by mapping method; it can also be classified according to bus hierarchy, address space domain, or target node type. The output format of the initialization configuration file is not limited to a specific format such as Excel or JSON; it can also be in YAML or Extensible Markup Language (XML) format.

[0076] As an alternative implementation, the template engine upon which the code generator is based can be replaced with a script-driven generation method. This involves reading the structured configuration dataset line by line using a predefined conversion script and calling the corresponding conversion subroutine based on the register type field to generate code lines. The target output format is not limited to C or C++ header files; it can also be a register configuration module in a hardware description language format, a register model description file required for the verification environment, or other project-specific formats. The input method for the specialized configuration intervention interface is not limited to manual editing or file import; it can also be achieved by pre-defining an override rule file in the project information, which will automatically read and execute override logic during the configuration generation process.

[0077] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the register configuration code generation method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0078] This application also provides a register configuration code generation apparatus, please refer to... Figure 4The register configuration code generation device includes: The acquisition module 10 is used to acquire standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space. The parsing module 20 is used to parse the system address mapping table to generate an initialization configuration file. Based on the initialization configuration file, it extracts the mapping relationship information of each address segment and the target node identifier to determine the target register to be configured and the corresponding configuration requirements. The association module 30 is used to associate the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters. The generation module 40 is used to generate register configuration code in the target format based on the structured configuration dataset.

[0079] And / or, the register configuration code generation apparatus includes: The first verification module is used to perform data validity verification on the system address mapping table. The data validity verification includes format verification and logical verification. The logical verification is used to detect semantic conflicts between different address segments in the system address mapping table. The first log generation module is used to generate and output an error log when the verification fails. The error log indicates the specific field where the verification failed and the corresponding reason for the failure. The first classification module is used to classify and summarize each address segment into different mapping tables according to the mapping method corresponding to each address segment in the system address mapping table after the verification is passed, so as to obtain a set of classified mapping tables. The first allocation module is used to allocate globally unique identifiers and locally unique identifiers to various types of nodes involved in the classified mapping table set according to a preset allocation logic. The first integration module is used to integrate the classified mapping table set with the allocated globally unique identifier and locally unique identifier to generate an initialization configuration file.

[0080] And / or, the register configuration code generation apparatus includes: The first extraction module is used to extract the number of instantiations of each chip type from the project information when the acquisition module 10 has also acquired project information and the number of chips defined in the project information is at least two, and to determine the set of nodes to be configured across multiple chips based on the number of instantiations of each chip type. The first derivation module is used to automatically derive the mapping and conversion relationship between the globally unique identifier and the locally unique identifier for each node in the set of nodes to be configured; The second integration module is used to integrate the mapping transformation relationship with the classified mapping table set, the allocated globally unique identity identifier and locally unique identity identifier to generate the initialization configuration file.

[0081] And / or, the register configuration code generation apparatus includes: The second extraction module is used to extract the target node type corresponding to the target node identifier, as well as the base address and tail address corresponding to each address segment from the configuration requirements. The first lookup module is used to search for all registers to be configured in the register specification information according to the target node type, and obtain a list of registers to be configured. The first determining module is used to determine the address-related configuration parameters of each register to be configured in the list of registers to be configured, based on the base address and the tail address. The first matching module is used to match the address-related configuration parameters with the bit fields defined in the register specification information of the register to be configured, and generate the configuration data item of the register to be configured. The first aggregation module is used to aggregate the configuration data items corresponding to all registers to be configured in the register list to obtain the structured configuration dataset.

[0082] And / or, the register configuration code generation apparatus includes: The first reading module is used to read the initialization configuration file and extract the mapping method, target node identifier, and globally unique identity identifier corresponding to each address segment from the initialization configuration file. The second association module is used to configure the parser to use the mapping method, the target node identifier, and the globally unique identity identifier as the association primary key; The first positioning module is used to locate the register bit field definition that matches the target node identifier in the register specification information based on the associated primary key. The first fusion module is used to fuse the mapping method and the globally unique identifier with the register bit field definition to generate the structured configuration dataset.

[0083] And / or, the register configuration code generation apparatus includes: The first receiving module is configured to receive custom configuration parameters input through a special configuration intervention interface after the step of generating the structured configuration dataset. The custom configuration parameters include supplementary configuration data or instructions to overwrite parameters already generated in the structured configuration dataset. The first writing module is used to write the supplementary configuration data into the structured configuration dataset according to the overwrite instruction, replace the original parameters in the structured configuration dataset corresponding to the overwrite instruction, and obtain an updated structured configuration dataset, so as to use the updated structured configuration dataset as input for subsequent code generation steps.

[0084] The register configuration code generation apparatus provided in this application, employing the register configuration code generation method in the above embodiments, can solve the technical problem of insufficient automation in register configuration code generation in related technologies. Compared with related technologies, the beneficial effects of the register configuration code generation apparatus provided in this application are the same as those of the register configuration code generation method provided in the above embodiments, and other technical features in the register configuration code generation apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0085] This application provides a register configuration code generation device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to execute the register configuration code generation method in Embodiment 1 above.

[0086] The following is for reference. Figure 5 The diagram illustrates a structural schematic of a register configuration code generation device suitable for implementing embodiments of this application. The register configuration code generation device in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, tablets, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital televisions and desktop computers. Figure 5 The register configuration code generation device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0087] like Figure 5As shown, the register configuration code generation device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the register configuration code generation device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the register configuration code generation device to communicate wirelessly or wiredly with other devices to exchange data. While the figure shows register configuration code generation devices with various systems, it should be understood that implementation or having all of the systems shown is not required. More or fewer systems may be implemented alternatively.

[0088] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0089] The register configuration code generation device provided in this application, employing the register configuration code generation method in the above embodiments, can solve the technical problem of insufficient automation in register configuration code generation in related technologies. Compared with related technologies, the beneficial effects of the register configuration code generation device provided in this application are the same as those of the register configuration code generation method provided in the above embodiments, and other technical features in this register configuration code generation device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0090] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0091] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0092] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the register configuration code generation method in the above embodiments.

[0093] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0094] The aforementioned computer-readable storage medium may be included in the register configuration code generation device; or it may exist independently and not be assembled into the register configuration code generation device.

[0095] The aforementioned computer-readable storage medium carries one or more programs that, when executed by the register-configured code generation device, cause the register-configured code generation device to: Obtain standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space; The system address mapping table is parsed to generate an initialization configuration file. Based on the initialization configuration file, the mapping relationship information of each address segment and the target node identifier are extracted to determine the target register to be configured and the corresponding configuration requirements. The configuration requirements are associated with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters; Based on the structured configuration dataset, register configuration code in the target format is generated.

[0096] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0098] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0099] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described register configuration code generation method, thereby solving the technical problem of insufficient automation in register configuration code generation in related technologies. Compared with related technologies, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the register configuration code generation method provided in the above embodiments, and will not be repeated here.

[0100] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the register configuration code generation method described above.

[0101] The computer program product provided in this application can solve the technical problem of insufficient automation in register configuration code generation in related technologies. Compared with related technologies, the beneficial effects of the computer program product provided in this application are the same as those of the register configuration code generation method provided in the above embodiments, and will not be repeated here.

[0102] All acquisition of signals, information, or actions in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization of the relevant device owner.

[0103] The above description is only a part of the embodiments of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the technical concept of this application and using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included in the scope of protection of this application.

Claims

1. A method for generating register configuration code, characterized in that, The method includes: Obtain standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space; The system address mapping table is parsed to generate an initialization configuration file. Based on the initialization configuration file, the mapping relationship information of each address segment and the target node identifier are extracted to determine the target register to be configured and the corresponding configuration requirements. The configuration requirements are associated with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters; Based on the structured configuration dataset, register configuration code in the target format is generated.

2. The method according to claim 1, characterized in that, The step of parsing the system address mapping table to generate the initialization configuration file includes: Perform data validity verification on the system address mapping table. The data validity verification includes format verification and logical verification. The logical verification is used to detect semantic conflicts between different address segments in the system address mapping table. When the verification fails, an error log is generated and output, indicating the specific field that failed the verification and the corresponding reason for the failure; After the verification is passed, according to the mapping method corresponding to each address segment in the system address mapping table, the address segments are classified and summarized into different mapping tables to obtain a set of classified mapping tables. According to the preset allocation logic, a globally unique identity and a locally unique identity are assigned to each type of node involved in the classified mapping table set. The categorized mapping table set is integrated with the assigned globally unique identifier and locally unique identifier to generate an initialization configuration file.

3. The method according to claim 2, characterized in that, The steps for generating the initialization configuration file include: When the step of obtaining standardized input information also obtains project information, and the number of chips defined in the project information is at least two, the number of instantiations of each chip type is extracted from the project information, and the set of nodes to be configured across multiple chips is determined based on the number of instantiations of each chip type. For each node in the set of nodes to be configured, automatically derive the mapping and conversion relationship between the globally unique identifier and the locally unique identifier; The mapping transformation relationship is integrated with the classified mapping table set, the assigned globally unique identity, and the locally unique identity to generate the initialization configuration file.

4. The method according to claim 1, characterized in that, The step of associating the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters includes: Extract the target node type corresponding to the target node identifier, as well as the base address and tail address corresponding to each address segment, from the configuration requirements; Based on the target node type, search the register specification information for all registers to be configured that are included in the target node type to obtain a list of registers to be configured; For each register to be configured in the list of registers to be configured, the address-related configuration parameters of the register to be configured are determined based on the base address and the tail address; The address-related configuration parameters are matched with the bit fields defined in the register specification information of the register to be configured to generate the configuration data item of the register to be configured. The configuration data items corresponding to all registers to be configured in the register list are aggregated to obtain the structured configuration dataset.

5. The method according to claim 1, characterized in that, The step of associating the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters includes: Read the initialization configuration file and extract the mapping method, target node identifier, and globally unique identity identifier corresponding to each address segment from the initialization configuration file. By configuring the parser, the mapping method, the target node identifier, and the globally unique identity identifier are used as the association primary key; Based on the associated primary key, locate the register bit field definition that matches the target node identifier in the register specification information; The mapping method and the globally unique identifier are combined with the register bit field definition to generate the structured configuration dataset.

6. The method according to claim 1, characterized in that, Following the step of generating the structured configuration dataset, the method further includes: Receive custom configuration parameters input through a special configuration intervention interface, wherein the custom configuration parameters include supplementary configuration data or instructions to override parameters already generated in the structured configuration dataset; According to the overwrite instruction, the supplementary configuration data is written into the structured configuration dataset, replacing the original parameters in the structured configuration dataset corresponding to the overwrite instruction, to obtain an updated structured configuration dataset, which is then used as input for subsequent code generation steps.

7. A register configuration code generation apparatus, characterized in that, The device includes: The acquisition module is used to acquire standardized input information, which includes at least a system address mapping table describing the allocation of the system's global address space. The parsing module is used to parse the system address mapping table to generate an initialization configuration file. Based on the initialization configuration file, it extracts the mapping relationship information of each address segment and the target node identifier to determine the target register to be configured and the corresponding configuration requirements. The association module is used to associate the configuration requirements with the corresponding register specification information to generate a structured configuration dataset containing complete configuration parameters. The generation module is used to generate register configuration code in the target format based on the structured configuration dataset.

8. A register configuration code generation device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the register configuration code generation method as described in any one of claims 1 to 6.

9. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the register configuration code generation method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the register configuration code generation method as described in any one of claims 1 to 6.

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