Microinstruction cache apparatus, processor architecture, chip, method and device

Abstract

The application relates to the technical field of processors, and provides a microinstruction cache device, a processor architecture, a chip, a method and equipment, the microinstruction cache device comprises a data cache array used for storing microinstructions; a tag cache array used for storing address tags of the microinstructions; wherein a tag multiplexing mapping relationship is configured between the tag cache array and the data cache array, the tag multiplexing mapping relationship comprises that a plurality of microinstruction entries belonging to the same address continuous block share the same address tag entry; a cache management unit is coupled with the tag cache array and the data cache array, and is configured to perform data operation based on the tag multiplexing mapping relationship. According to the embodiment of the application, the effective capacity of the microinstruction cache can be effectively improved without significantly increasing the chip area and power consumption and without deteriorating the timing convergence.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a microinstruction cache device, processor architecture, chip, method, and apparatus. Background Technology

[0002] In modern high-performance processors, a micro-operation cache is typically used to accelerate the instruction decoding process. This cache stores decoded micro-operations (uOps). When the processor executes an instruction at the same address again, it can directly read the decoding result from the micro-operation cache, thus skipping repeated decoding and improving execution efficiency.

[0003] like Figure 1 As shown, a traditional microinstruction cache consists of two parts: a data cache array and an address tag array. This microinstruction cache employs a one-to-one mapping structure where "one address tag corresponds to one microinstruction entry" (e.g., ...). Figure 1 In this architecture, Tag0 corresponds to Data0, Tag1 corresponds to Data1, and Tag2 corresponds to Data2. Each storage entry requires an independent address tag and is compared in parallel. As the cache capacity or number of paths increases, this structure leads to a significant increase in tag storage area, difficulty in timing convergence, and increased dynamic power consumption. Some improvements have been made to alleviate these problems by compressing micro-operations or optimizing tag comparison methods, but none of them have fundamentally reduced the overhead of tag storage and comparison, nor can they simultaneously meet the requirements of area, timing, and power consumption.

[0004] Therefore, how to effectively increase the effective capacity of the microinstruction cache without significantly increasing chip area and power consumption or deteriorating timing convergence has become an urgent technical problem to be solved. Summary of the Invention

[0005] The purpose of this application is to provide a microinstruction cache device, processor architecture, chip, method, and apparatus to solve or alleviate the above-mentioned technical problems.

[0006] To achieve the above objectives, in one aspect, embodiments of this application provide a microinstruction cache device based on a heterogeneous architecture, comprising: A data cache array is used to store microinstructions; A tag cache array is used to store the address tags of the microinstructions; wherein, a tag reuse mapping relationship is configured between the tag cache array and the data cache array, and the tag reuse mapping relationship includes: multiple microinstruction entries belonging to the same address contiguous block share the same address tag entry; The cache management unit, coupled to the tag cache array and the data cache array, is configured to perform data operations based on the tag reuse mapping relationship.

[0007] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the tag reuse mapping relationship specifically includes: Based on the instruction address continuity of the branch prediction window or cache line, a single physical address tag entry in the tag cache array is mapped to multiple micro-instruction entries in the data cache array, so that the multiple micro-instruction entries share the same physical address tag entry.

[0008] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the tag cache array and the data cache array are divided into multiple groups, and different groups have different tag reuse ratios.

[0009] In the heterogeneous architecture-based microinstruction caching device of this application embodiment, the tag reuse ratio is dynamically determined according to the size of the branch prediction window or the cache line, and the tag reuse ratio is positively correlated with the size of the branch prediction window or the cache line.

[0010] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the data cache array includes multiple fixed-size common entries and at least one shared domain, wherein the shared domain is associated with the multiple common entries; The device is also configured with a data sharing mapping relationship, which includes: When the number of microinstructions in a microinstruction entry is not greater than the capacity of the common entry, the microinstruction entry is mapped to a single common entry; When the number of microinstructions in a microinstruction entry exceeds the capacity of the public entry, the microinstruction entry is mapped to a single public entry and its associated shared domain.

[0011] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the shared domain is divided into multiple shared sub-regions, and each shared sub-region is associated with a set of common entries; When the number of microinstructions in a microinstruction entry is not greater than the capacity of the common entry, the microinstruction entry is mapped to the common entry; when the number of microinstructions in a microinstruction entry is greater than the capacity of the common entry, the microinstruction entry is mapped to the common entry and its associated shared sub-region.

[0012] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the data cache array includes a variety of microinstruction entry formats with different capacities, and different capacity entry formats correspond to different microinstruction storage quantities.

[0013] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the cache management unit is configured as follows: The storage path of the data cache array is divided into multiple logical replacement groups according to the tag reuse grouping, and each logical replacement group corresponds to a tag reuse group; an inter-group replacement strategy is performed between the logical replacement groups to determine the target logical replacement group to be replaced; an intra-group replacement strategy is performed within the target logical replacement group to determine the target storage path to be replaced.

[0014] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the cache management unit is further configured as follows: When the shared domain is full, the microinstruction entry to be replaced in the shared domain is selected based on the popularity information of each microinstruction entry.

[0015] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the cache management unit is further configured as follows: When an address tag is hit within a single clock cycle, multiple microinstruction entries corresponding to that address tag are read in parallel from the data cache array based on the tag multiplexing mapping relationship, and the read multiple microinstruction entries are merged into a microinstruction stream based on program order.

[0016] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the cache management unit is further configured as follows: The offset address of the next instruction is calculated based on the sequence offset of the microinstruction entry at the end of the microinstruction stream, and the current instruction fetch window is released when the completion status bits of each microinstruction entry in the microinstruction stream are valid.

[0017] In the heterogeneous architecture-based microinstruction cache device of this application embodiment, the cache management unit is further configured as follows: When consecutive branch prediction windows cause storage entry slots in the data cache array to become idle, the tag bit width of the tag cache array is redefined or the bit width used for group indexing in the address is adjusted to eliminate the idleness.

[0018] On the other hand, embodiments of this application also provide a processor architecture, including: Instruction decoding unit; Microinstruction queue; and The aforementioned microinstruction cache device is disposed between the instruction decoding unit and the microinstruction queue.

[0019] On the other hand, embodiments of this application also provide a chip, including the processor architecture described above.

[0020] On the other hand, embodiments of this application also provide a microinstruction cache control method based on a heterogeneous architecture, the method comprising: Receive a write request for a microinstruction and store the microinstruction into a data cache array according to the address contiguous block to which the microinstruction belongs; The microinstructions are stored based on a tag reuse mapping relationship, which includes mapping multiple microinstruction entries belonging to the same address contiguous block to the same address tag entry in the tag cache array. In response to the instruction fetch request of the microinstruction, the target address tag is found by searching the tag cache array, and the corresponding microinstruction data is read from the data cache array according to the tag reuse mapping relationship.

[0021] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, reading the corresponding microinstruction data from the data cache array includes reading multiple microinstruction entries associated with the target address tag in parallel within a single clock cycle.

[0022] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the storage of the microinstructions based on the tag reuse mapping relationship specifically includes: Identify multiple microinstructions belonging to the same branch prediction window or the same cache line in the processor pipeline; The multiple microinstructions are respectively stored into multiple microinstruction entries in the data cache array; The multiple microinstruction entries are marked as sharing the same physical address tag entry in the tag cache array.

[0023] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the tag cache array and the data cache array are divided into multiple groups, and different groups have different tag reuse ratios. The method further includes: dynamically determining the label reuse ratio based on the size of the branch prediction window, such that the label reuse ratio is positively correlated with the size of the branch prediction window.

[0024] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the method further includes managing data sharing mapping, which includes: The data cache array is divided into multiple fixed-size common entries and at least one shared domain; When the number of microinstructions in the microinstruction entry to be stored is not greater than the capacity of the public entry, it is stored in the public entry; When the number of microinstructions in a microinstruction entry to be stored exceeds the capacity of the common entry, the microinstruction entry is stored in the common entry, and the overflowing microinstruction data is stored in the shared domain.

[0025] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the shared domain is divided into multiple shared sub-regions, and each shared sub-region is associated with a set of common entries; When storing microinstruction entries into the public entry and its associated shared domain, the specific steps are as follows: the microinstruction entries are stored into the public entry, and the overflowing microinstruction data is stored into the shared sub-region associated with the public entry.

[0026] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the method further includes performing a replacement operation, wherein the replacement operation includes: The storage path of the data cache array is divided into multiple logical replacement groups according to the tag reuse grouping, and each logical replacement group corresponds to a tag reuse group; An inter-group replacement strategy is implemented among the logical replacement groups to determine the target logical replacement group to be replaced. Within the target logical replacement group, an intra-group replacement strategy is implemented to determine the target storage path to be replaced.

[0027] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the method further includes: When the shared domain is full, based on the popularity information of each microinstruction entry, the microinstruction entry to be replaced in the shared domain is selected for replacement.

[0028] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, reading the corresponding microinstruction data from the data cache array specifically includes: When an address tag is hit within a single clock cycle, multiple microinstruction entries corresponding to that address tag are read in parallel from the data cache array; Multiple microinstruction entries read are merged into a microinstruction stream based on program order.

[0029] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the method further includes: The offset address of the next instruction is calculated based on the sequence offset of the microinstruction entry at the end of the microinstruction stream. When the completion status bits of each microinstruction entry in the microinstruction stream are all valid, the current instruction fetch window is released.

[0030] In the microinstruction cache control method based on heterogeneous architecture in this application embodiment, the method further includes: When consecutive branch prediction windows cause storage entry slots in the data cache array to become idle, the tag bit width of the tag cache array is redefined or the bit width used for group indexing in the address is adjusted to eliminate the idleness.

[0031] On the other hand, embodiments of this application also provide a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the computer program, when run by the processor, executes instructions of the above-described method.

[0032] As can be seen from the technical solutions provided in the embodiments of this application above, by establishing a tag reuse mapping relationship, multiple microinstruction entries belonging to the same address contiguous block can share the same address tag entry. This changes the traditional one-to-one mapping structure of "one entry corresponds to one tag" in the microinstruction cache to a many-to-one mapping structure of "multiple entries sharing one tag." This change directly reduces the number of tag entries that need to be stored in the tag cache array, reduces the parallelism of tag comparison during each access, and thus fundamentally solves the problems of excessive tag storage area, complex comparison logic leading to timing convergence difficulties, and high power consumption caused by increasing the microinstruction cache capacity. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 A schematic diagram of a microinstruction cache device in the prior art is shown; Figure 2 A schematic diagram of a microinstruction cache device in some embodiments of this application is shown; Figure 3 This illustration shows a schematic diagram of multiple microinstruction entries sharing the same address label entry in one embodiment of this application; Figure 4 This illustration shows a grouping diagram of different label reuse ratios in one embodiment of this application; Figure 5 A schematic diagram of data sharing mapping in one embodiment of this application is shown; Figure 6 This illustration shows a schematic diagram of group associativity under a single Entry format and a shared domain in a microinstruction cache according to one embodiment of this application; Figure 7 This illustration shows a schematic diagram of grouping multiple Entry formats under a shared domain in a microinstruction cache according to one embodiment of this application; Figure 8 This illustration shows a schematic diagram of the cross-substitution of PLRU and TLRU under isomorphic type in one embodiment of this application; Figure 9 This illustration shows a schematic diagram of the cross-substitution of PLRU and TLRU under heterogeneous type in one embodiment of this application; Figure 10 A schematic diagram of the high-bandwidth parallel instruction fetch timing and data flow is shown in one embodiment of this application; Figure 11 A schematic diagram of a processor architecture (partial) in one embodiment of this application is shown; Figure 12 The flowcharts of microinstruction cache control methods based on heterogeneous architectures in some embodiments of this application are shown; Figure 13 A structural block diagram of a computer device in some embodiments of this application is shown.

[0034] [Explanation of Labels in the Attached Image]

[0035] 100. Instruction Fetch Unit; 200. Decoding unit; 300. Microinstruction cache device; 301. Cache Management Unit; 302. Tag cache array; 303. Data cache array; 400. Microinstruction queue; 500. Execution Unit; 1302. Computer equipment; 1304, Processor; 1306. Memory; 1308. Drive mechanism; 1310. Input / output interface; 1312. Input devices; 1314. Output devices; 1316. Presentation equipment; 1318. Graphical User Interface; 1320. Network interface; 1322. Communication link; 1324. Communication bus. Detailed Implementation

[0036] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0037] To facilitate understanding, some terms involved in this application will be explained before describing the embodiments of this application.

[0038] As used in this application, a microinstruction refers to a micro-operation generated after being converted by the decoding unit (DE) and executable by the processor's internal execution unit. A data cache array is a physical cache array used to store microinstruction data in the microinstruction cache. Each cache unit in the data cache array is called a data entry. A data entry is also the smallest physical storage unit in the microinstruction cache, used to store one or more microinstruction data entries.

[0039] As used in this application, an address tag or label is a tag field in the microinstruction cache used for address matching. When the processor accesses an address, it compares the high-order bits of the address with the tag in the cache to determine if a hit occurs. A tag cache array is a physical cache array in the microinstruction cache used to store address tags, and each cache unit in the tag cache array is called an address tag entry.

[0040] As used in this application, a contiguous block of addresses is a contiguous region in the program address space, such as a branch prediction window (BPW) or a cache line.

[0041] As used in this application, tag reuse mapping refers to the mapping relationship that associates multiple microinstruction entries in a data cache array with the same address tag entry in a tag cache array.

[0042] As used in this application, a common entry is a fixed-size basic storage unit in a data cache array. A shared domain refers to an additional storage area in the data cache array used to store microinstructions that overflow beyond the capacity of a common entry.

[0043] As used in this application, data sharing mapping refers to the rules for mapping logical microinstruction entries to physical storage structures (common entries and shared domains) for handling variable-length sets of microinstructions (or instruction blocks).

[0044] As used in this application, the pseudo-Least Recently Used (PLRU) algorithm is an algorithm that approximates Least Recently Used (LRU) using a binary tree. The tree-based Least Recently Used (TLRU) algorithm, similar to PLRU, is another approximate implementation of LRU.

[0045] As used in this application, the instruction fetch window refers to the set of microinstructions that the instruction fetch unit reads from the microinstruction cache in a single instance.

[0046] In summary, this application aims to break away from the fixed, homogeneous structure between address tag entries and microinstruction entries in traditional microinstruction caches. By introducing a reusable, heterogeneous structure (i.e., multiple microinstruction entries can share a single address tag entry), the fixed physical storage space is transformed into a flexible logical storage space. This improves the effective capacity of the microinstruction cache without significantly increasing hardware area, deteriorating timing convergence, or reducing power consumption. Furthermore, by combining data sharing mapping and hierarchical replacement strategies, it is possible to further improve the effective capacity of the microinstruction cache and support high-bandwidth parallel instruction fetching without significantly increasing hardware area, deteriorating timing convergence, or reducing power consumption.

[0047] This application provides a microinstruction cache device based on a heterogeneous architecture, referenced... Figure 2 As shown, in some embodiments of this application, the microinstruction caching device may include: a cache management unit 301, a tag cache array 302, and a data cache array 303. The cache management unit 301 is coupled to the tag cache array 302 and the data cache array 303, respectively. The data cache array 303 is used to store microinstructions. The tag cache array 302 is used to store the address tags of the microinstructions. A tag multiplexing mapping relationship is configured between the tag cache array 302 and the data cache array 303. The tag multiplexing mapping relationship includes: multiple microinstruction entries belonging to the same address contiguous block share the same address tag entry. The cache management unit 301 is configured to perform data operations based on the tag multiplexing mapping relationship.

[0048] This application's embodiments establish a tag reuse mapping relationship, enabling multiple microinstruction entries belonging to the same contiguous address block to share the same address tag entry. This transforms the traditional one-to-one mapping structure of "one entry to one tag" in microinstruction caches into a many-to-one mapping structure where "multiple entries share one tag." This change directly reduces the number of tag entries that need to be stored in the tag cache array, lowers the parallelism of tag comparisons during each access, and fundamentally solves the problems of excessive tag storage area, complex comparison logic leading to timing convergence difficulties, and high power consumption caused by increasing microinstruction cache capacity.

[0049] In some embodiments of this application, both the tag cache array and the data cache array 303 can be SRAM arrays, for example. Each entry (address tag entry) in the tag cache array 302 can be additionally assigned a "shared count" field and pointers to multiple data entries (or associated via an index mapping table). For example, in a 16-way set-associative microinstruction cache design, each row of the tag cache array stores one address tag, and each row of the data cache array 303 corresponds to one microinstruction entry; a "multiplexed bit field" can be added to the address tag entry to indicate which data entries share this address tag (i.e., indicating which data entries this address tag corresponds to).

[0050] In the tag multiplexing mapping relationship of this application embodiment, when the processor fetches an instruction, the tag of the fetched address is compared with the tag in the tag cache array. If a match is found, multiple corresponding data entries are accessed simultaneously according to the shared data entry index recorded in the tag entry of that address.

[0051] For example, such as Figure 3 In the illustrated embodiment, there is a tag reuse mapping relationship between address tag entry Tag Entry 0 and two data entries (Data Entry 0 and Data Entry 1), meaning that Data Entry 0 and Data Entry 1 share Tag Entry 0. If Tag Entry 0 is hit based on the tag of the fetch address, then according to this tag reuse mapping relationship, Data Entry 0 and Data Entry 1 can be accessed simultaneously. Therefore, with this 2:1 tag reuse ratio, the set-associative architecture, which originally required 16 address tags, only requires 8 address tag entries, thus reducing the storage space required for addresses. Furthermore, in this scenario, the number of comparisons is reduced from 16 to 8, the number of parallel comparators can be halved, and the critical path is shortened, thereby effectively reducing the power consumption of address tag comparisons and improving timing convergence.

[0052] In some embodiments of this application, the cache management unit 301 may be implemented using one or more of the following hardware structures: (1) Finite state machine (FSM): used to control the basic operation process of cache reading, writing, replacement, hit / miss handling, etc.

[0053] (2) Combinational logic circuits + registers: such as address decoders, comparators, priority encoders, multiplexers, etc., used to quickly complete tag comparison, entry selection, and data path switching.

[0054] (3) Programmable Logic Array (PLA): Used to implement flexible configuration of mapping rules (such as tag reuse ratio selection and shared domain allocation).

[0055] (4) Dedicated hardware accelerators: such as built-in TLRU / PLRU tree state update circuits, hot counter arrays, shared domain allocators, etc. These circuits are implemented in a hard-wired manner to ensure high performance and low latency.

[0056] Among them, the control logic integrated with the tag cache array 302 and the data cache array 303: Physically, the cache management unit 301 can be distributed in each row of the tag cache array 302 (such as each row having a state machine), or it can be centralized into a global control module, or a hybrid approach (global control + distributed state).

[0057] In some embodiments of this application, a combination of hardwired finite state machines and distributed control logic can also be used: frequent, time-critical operations (such as tag comparison, hit detection, and parallel read enable generation) are implemented using combinational logic, while more complex operations such as replacement algorithm updates, shared domain management, and training processes are implemented using state machines or microcode. Such a physical structure satisfies both high performance requirements and the necessary flexibility.

[0058] In the embodiments of this application, limiting the tag reuse mapping relationship to multiple microinstruction entries belonging to the same contiguous address block (e.g., the same branch prediction window or the same cache line) sharing the same address tag entry (rather than multiple microinstruction entries of arbitrary address ranges sharing the same address tag entry) is one of the purposes of ensuring that the shared address tags are actually the same in physical address, thereby avoiding the following problems in cache access: (1) False Hit: When the processor accesses an address, its tag matches a shared tag, but the actual hit entry stores a microinstruction at a completely different address. The processor will execute the wrong micro-operation, causing the program to crash.

[0059] (2) True Miss Hidden: The correct entry that should have been hit cannot be indexed because the shared tag and address do not match, resulting in a decrease in cache hit rate.

[0060] (3) Replacement algorithm failure: Due to the chaotic correspondence between tags and data entries, replacement algorithms such as LRU / PLRU cannot accurately reflect the actual usage of entries, resulting in a serious reduction in cache management efficiency.

[0061] (4) Cannot support parallel reading: High-bandwidth parallel instruction fetching depends on the ability to determine that multiple related entries belong to the same consecutive instruction block (i.e., the same BPW or cache line) after a shared tag is hit. If the shared tag corresponds to randomly combined entries, it is not safe to read them simultaneously, and forced reading will output incorrect data.

[0062] Therefore, in some embodiments of this application, the tag reuse mapping relationship may specifically include: mapping a single physical address tag entry in the tag cache array to multiple micro-instruction entries in the data cache array based on the instruction address continuity of the branch prediction window or cache line, so that the multiple micro-instruction entries share the same physical address tag entry.

[0063] In some embodiments of this application, to achieve the mapping of multiple microinstruction entries (Data Entry) sharing the same address tag entry (Tag Entry), the traditional address decoding logic can be adjusted. Specifically, the tag multiplexing mapping relationship is manifested in hardware logic as follows: the offset bit width within the physical address is logically extended. In traditional microinstruction caches, the offset bit is used to locate a specific entry within a cache line; however, in this application, since multiple consecutive Data Entry share a Tag, the offset part of the address decoding logic needs to be increased with additional bits (or logical width) to cover all consecutive Data Entry sharing the Tag. In other words, the shared Tag bit width design is logically similar to extending the offset bit, thereby expanding the address space range associated with a Tag and accommodating multiple consecutive microinstruction entries. This design allows instructions belonging to the same consecutive address block (such as a branch prediction window) to be accurately addressed to the corresponding Data Entry through the extended offset bit, without needing to allocate an independent Tag comparison circuit for each Data Entry.

[0064] In some embodiments of this application, during the training phase (training refers to the process of writing the decoded micro-operations and their address tags into the microinstruction cache, equivalent to cache filling or learning operations), the processor's decoding unit stores multiple micro-operations belonging to the same branch prediction window (e.g., containing 4 instructions) into multiple consecutive entries in the data cache array. Simultaneously, the common address tag of these instructions is calculated, written into an entry in the tag cache array, and the index (e.g., Way ID) of the mapped data entry is recorded in that entry. When the decoding unit outputs a set of micro-operations, multiple instructions belonging to the same BPW or the same Cache Line (which have the same high-order PC (Program Counter) bit) are identified. Configuring multiple Data Entry belonging to the same BPW or the same Cache Line to share the same Tag Entry triggers tag reuse allocation.

[0065] In some embodiments of this application, both the tag cache array and the data cache array can be divided into multiple groups, and different groups can have different tag reuse ratios. The tag reuse ratio can be dynamically determined based on the size of the branch prediction window or cache line; correspondingly, the tag reuse ratio is positively correlated with the size of the branch prediction window or the cache line. For example, taking dynamic determination based on the size of the branch prediction window as an example, when the branch prediction window is large, the tag reuse ratio is relatively large, and when the branch prediction window is small, the tag reuse ratio is relatively small. In this way, different sizes of BPWs or Cache Lines can be flexibly adapted through this heterogeneous reuse ratio, reducing idle slots caused by fixed reuse ratios or reuse mismatches, thereby further improving the overall effective capacity of the microinstruction cache.

[0066] For example, in such Figure 4 The illustrated embodiment demonstrates a heterogeneous grouping method between the tag cache array and the data cache array. The 16 paths of the microinstruction cache are divided as follows: paths 0-3 are 4:1 groups (4 data entries share 1 tag entry), paths 4-7 are 2:1 groups (2 data entries share 1 tag entry), paths 8-11 are 1:1 groups (traditional method), and paths 12-15 are 3:2 groups (3 data entries share 2 tag entries, used for cases with irregular window sizes).

[0067] In some embodiments of this application, when consecutive branch prediction windows cause storage entry slots in the data cache array to become idle (storage entry slot waste), the tag bit width of the tag cache array (i.e., dividing the tag portion) or the bit width used for group indexing in the address (such as adjusting the offset bit width) is redefined to eliminate the problem of idle slot waste caused by BPW boundary misalignment, thereby further improving cache utilization.

[0068] In some embodiments of this application, the data cache array may include multiple fixed-size common entries and at least one shared domain, the shared domain being associated with the multiple common entries. The device is also configured with a data sharing mapping relationship, which includes: when the number of microinstructions in a microinstruction entry is not greater than the capacity of the common entry, the microinstruction entry is mapped to a single common entry (i.e., when the number of microinstructions does not overflow, only a single common entry can be written); when the number of microinstructions in a microinstruction entry is greater than the capacity of the common entry, the microinstruction entry is mapped to a single common entry and its associated shared domain (i.e., when the number of microinstructions overflows, the overflowing microinstructions after being written to a single common entry are stored in the shared domain), i.e., SIZE(Data Entry) + SIZE(Share Entry) = SIZE(Logic Entry).

[0069] For example, in such Figure 5 The illustrated embodiment demonstrates a data sharing mapping example based on a common entry area + shared domain. In this example, the common entry has a capacity of 4 microinstructions, and each sub-area of ​​the shared domain also has a capacity of 4 microinstructions. Logically, a block of instructions containing 6 microinstructions needs to be stored. The first 4 microinstructions of this block are stored in the common entry, and the last 2 microinstructions are stored in the shared sub-area bound to the common entry.

[0070] In some embodiments of this application, fixed physical entries in the data cache array can be split into smaller entries, and shared fields can be added. This allows for the compact storage of short instruction blocks (e.g., containing only 2 instructions), reducing or avoiding the problem of a large amount of unused internal fragmentation and wasted storage space when storing short instructions in traditional fixed-size Entries (e.g., 8 instructions / Entry). In other words, variable-length storage can be achieved through this data sharing mapping, allowing logical entries to cross physical boundaries to eliminate fragmentation and avoid storage space waste caused by excessively large entry sizes. More instruction combinations of different lengths can be stored within the same physical area. Here, a physical entry refers to a physical storage unit in the data cache array, i.e., a Data Entry. A logical entry refers to the storage unit corresponding to a complete microinstruction block from an architectural or software perspective; the size of a logical entry is fixed and does not concern itself with its physical storage method.

[0071] For example, if a logical entry contains 8 microinstructions, in the traditional way, each physical entry would need to store 8 microinstructions (i.e., the capacity of a single public entry is 8 microinstructions). However, as... Figure 6As shown, based on the entry splitting method of this application embodiment, each physical entry can be split into storage of 4 micro-instructions (i.e., the capacity of a single common entry is 4 micro-instructions); if a common entry overflows, the overflow portion is stored in the shared domain (e.g., ...). Figure 6 (Share in the middle). Among them, Figure 6 ENTRY-m-0, ENTRY-m-1, etc., are different BPWs (or different instruction blocks).

[0072] In some embodiments of this application, under the above-described data mapping scenario, the shared domain can be further divided into multiple shared sub-regions, each associated with a set of common entries. Thus, when the number of microinstructions in a microinstruction entry is no greater than the capacity of the common entry, the microinstruction entry is mapped to the common entry; when the number of microinstructions in a microinstruction entry is greater than the capacity of the common entry, the microinstruction entry is mapped to the common entry and its associated shared sub-region. By dividing the shared domain into multiple shared sub-regions and binding each sub-region to a set of common entries, access conflicts between multiple groups can be significantly reduced, parallel read / write operations can be supported, the hardware complexity of global allocation management can be reduced, access efficiency can be improved by utilizing spatial locality, and power consumption is reduced because only relevant sub-regions are activated. Therefore, the performance and energy efficiency of the microinstruction cache are further optimized on the basis of variable-length storage.

[0073] In some embodiments of this application, the shared domain can be an independent SRAM block connected to a common entry via a crossbar; each shared sub-region is configured with a valid bit and an occupancy counter, and an overflow pointer can be added to the common entry to point to the shared sub-region.

[0074] In some embodiments of this application, the data cache array may include various microinstruction entry formats with different capacities (e.g., 4, 6, or 8 entries), with different entry formats corresponding to different microinstruction storage quantities. This allows for more precise matching of BPWs of different sizes, further improving the utilization of the Data domain (i.e., the data cache array).

[0075] For example, such as Figure 7 As shown, if there are six consecutive BPWs, each BPW (such as...) Figure 7 The microinstruction numbers corresponding to ENTRY-m-0, ENTRY-m-1, etc. are 4, 6, 6, 8, and 2 respectively, so the entry format can also be adjusted to 4 ( Figure 7 The ENTRY-m-0 entry format in the middle is 4 entries (capacity), 6 ( Figure 7 The ENTRY-m-1 entry format in the middle is 6 entries (capacity), 6 ( Figure 7 The ENTRY-m-2 entry format has a capacity of 6 entries, 8 ( Figure 7 The ENTRY-m-$ entry format in the code is 8 entries (capacity), 2 ( Figure 7 The ENTRY-mn entries in the database have a capacity of 2. If a public entry overflows, the overflow portion is stored in the shared domain (e.g., ...). Figure 7 Share in the middle).

[0076] In some embodiments of this application, storage rows of different widths can be designed in the data cache array, and the bit width for writing and reading can be controlled by a format selection signal. For example, four capacity entries use a 64-bit width (assuming each microinstruction is 16 bits), and eight capacity entries use a 128-bit width. During allocation, the capacity entry closest to and not less than the actual number of microinstructions can be selected.

[0077] Considering that the data cache array may become full (or overflow), that is, when a new microinstruction entry needs to be written to the data cache array, there may be no free entries available in the data cache array; therefore, it is necessary to design a suitable replacement strategy (replacement algorithm) to evict old microinstruction data and write new microinstruction data.

[0078] Therefore, in some embodiments of this application, the cache management unit can also be configured to: divide the storage way of the data cache array into multiple logical replacement groups according to the tag reuse grouping, each logical replacement group corresponding to a tag reuse group; perform inter-group replacement strategy between the logical replacement groups to determine the target logical replacement group to be replaced (i.e., to be evicted); and perform intra-group replacement strategy within the target logical replacement group to determine the target storage way to be replaced (i.e., to be evicted). Here, in the group-connected structure of the cache array, a storage way refers to an independent storage location within each cache set.

[0079] A logical replacement group refers to multiple storage paths (i.e., a tag reuse group) in a data cache array that share the same address tag entry as a logical replacement unit for making replacement decisions. Each logical replacement group corresponds to a tag reuse group, and its size (i.e., the number of storage paths it contains) is determined by the tag reuse ratio of the group (for example, a 4:1 group contains 4 storage paths).

[0080] Inter-group replacement strategy determines from which tag reuse group (i.e., a set of multiple storage paths sharing the same address tag entry) to select the entry to be evicted. This strategy can use algorithms such as TLRU to make decisions among groups, recording the order in which each group has been most recently accessed, and prioritizing the elimination of the least used group. Based on the inter-group replacement strategy, fairness in replacement between different tag reuse groups can be ensured.

[0081] The intra-group replacement strategy, after selecting a target tag reuse group, determines which specific entry to evict from multiple storage paths within that group. This strategy can utilize algorithms such as PLRU to make decisions within the group, recording the access order of each path and prioritizing the eviction of the least used path. This intra-group replacement strategy ensures efficient replacement between storage paths within the same tag reuse group.

[0082] In some embodiments of this application, for homogeneous tag reuse scenarios (i.e., the tag reuse ratio is the same in each group), since the homogeneous structure is relatively simple, the cache management unit can use the LRU algorithm or a weighted LRU algorithm for replacement to achieve efficient replacement. Of course, for homogeneous tag reuse scenarios, a PLRU / TLRU cross-replacement strategy can also be used as needed (e.g., ...). Figure 8 As shown). For heterogeneous tag reuse scenarios (i.e., different tag reuse ratios in different groups), the cache management unit can use a PLRU / TLRU cross-replacement strategy (e.g. Figure 9 As shown in the figure, this is to ensure the fairness and hit rate of replacement in heterogeneous tag reuse scenarios.

[0083] The PLRU / TLRU crossover replacement strategy is a hierarchical replacement strategy consisting of PLRUs and TLRUs. For example... Figure 8 and Figure 9 As shown: the top layer is a TLRU tree (including nodes BIT-0, BIT-1, BIT-2, etc.), used for inter-group substitution decisions; the bottom layer, within the dashed box, is a PLRU tree (including nodes ①, ②, ③, etc.), used for intra-group substitution decisions. Figure 8 The dashed boxes of equal size represent equally divided logical replacement groups; in Figure 9 The varying sizes of the dashed boxes represent tag reuse groups based on the actual tag reuse ratio (different groups may have different storage paths). For example... Figure 8 or Figure 9 As shown, during the decision-making process, the target group to be replaced (i.e., the target logical replacement group) is selected from the TLRU root node according to the status bit. Then, the target storage path to be replaced is specifically selected from the PLRU tree within the group. This ensures the fairness and efficiency of replacement while adapting to different cache structures.

[0084] Similarly, in the scenario of a common entry area + shared domain, when the common entry overflows and the overflowed microinstructions need to be stored in the shared domain, the shared domain may also be full. Therefore, it is also necessary to design a suitable replacement strategy (replacement algorithm) to eliminate the old microinstruction data in the shared domain and write the new microinstruction data.

[0085] Therefore, in some embodiments of this application, the cache management unit can also be configured to: when the shared domain is full, select microinstruction entries to be replaced in the shared domain based on the popularity information of each microinstruction entry. The popularity information of a microinstruction entry refers to a quantitative indicator used to measure the frequency of access or recent use of each microinstruction entry (Entry), typically recorded by a hardware counter or status bit in the cache management unit. When the shared domain is full and space needs to be freed up, the cache management unit selects entries to be replaced based on the popularity information of each microinstruction entry, prioritizing the elimination of microinstruction data with lower popularity (i.e., fewer accesses or less recent use), thereby prioritizing the retention of hot data and improving the effective hit rate of the shared domain.

[0086] In some embodiments of this application, the cache management unit can also be configured to: when an address tag is hit within a single clock cycle, read multiple microinstruction entries corresponding to the address tag in parallel from the data cache array based on the tag multiplexing mapping relationship, and merge the read multiple microinstruction entries into a microinstruction stream based on program order. This can improve instruction fetch bandwidth.

[0087] In some embodiments of this application, the cache management unit is further configured to: merge multiple read microinstruction entries into a microinstruction stream based on program order, calculate the offset address of the next instruction based on the sequence offset of the microinstruction entry at the end of the microinstruction stream, and release the current instruction fetch window when the completion status bits of each microinstruction entry in the microinstruction stream are valid, so as to facilitate the execution of the next instruction fetch window, thereby helping to reduce the risk of pipeline interruption.

[0088] For example, combining Figure 10As shown, with a 2:1 tag reuse ratio (i.e., two microinstruction entries, Entry0 and Entry1, share one address tag entry, Tag0), the fetch unit, after hitting the Tag0 address tag in the TagArray based on the fetch address, simultaneously sends read enable to two different physical locations in the data buffer array based on the index (e.g., index 0 and 1) of the shared data entries (i.e., Entry0 and Entry1) stored in the address tag entry. In this scenario, the read port of the data buffer array needs to support dual reads (e.g., dual-port SRAM or two single-port interleaved reads). Then, the microinstruction groups (uops0 and uops1) read from the two entries are merged into a continuous stream in sequence (e.g., uops0 first, uops1 second) and sent to the microinstruction queue. Then, the seq-offset (i.e., the instruction length covered by the entry) is extracted from the second entry (uops1) and added to the starting PC of the current fetch window to obtain the PC of the next fetch window, i.e., next PC = PC + seq-offset(Entry1). After all the micro-operations corresponding to the last two entries have been fetched by the subsequent pipeline, their respective completion status bits become valid. When both status bits are valid, the resources occupied by the current fetch window are cleared, allowing the next fetch window to begin, i.e., the window is released.

[0089] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more hardware devices.

[0090] This application also provides a processor architecture. (See reference...) Figure 11 As shown, in some embodiments of this application, the processor architecture includes an instruction fetch unit 100, a decoding unit 200, a microinstruction cache device 300, a microinstruction queue 400, and an execution unit 500. The instruction fetch unit 100 fetches instructions from the instruction cache or memory. The decoding unit 200 decodes the fetched instructions into micro-operations (i.e., micro-instructions). The microinstruction cache device 300 is disposed between the instruction decoding unit 200 and the microinstruction queue 400. The microinstruction cache device 300 stores the decoded micro-operations. Specific implementation of storing decoded micro-operations in the microinstruction cache device 300 can be found in the embodiments of the microinstruction cache device described above, and will not be repeated here. The micro-operation queue 400 temporarily stores the microinstruction stream read from the microinstruction cache device for subsequent consumption by the execution unit 500. The execution unit 500 executes the micro-operations, performing arithmetic, logical, and memory access operations.

[0091] This application also provides a chip that includes the processor architecture described above. In some embodiments of this application, the processor architecture may exist as a separate chip. In other embodiments of this application, the processor architecture may be integrated as an IP core into a larger system-on-a-chip (SoC).

[0092] This application also provides a microinstruction cache control method based on heterogeneous architecture, which can be applied to the aforementioned microinstruction cache device, processor architecture, or chip-side. (See references) Figure 12 As shown, in some embodiments of this application, the method includes: Step 121: Receive the write request of the microinstruction, and store the microinstruction into the data cache array according to the address contiguous block to which the microinstruction belongs.

[0093] Step 122: Store the microinstructions based on the tag reuse mapping relationship, wherein the tag reuse mapping relationship includes: mapping multiple microinstruction entries belonging to the same address contiguous block to the same address tag entry in the tag cache array.

[0094] Step 123: In response to the instruction fetch request of the microinstruction, based on finding the target address tag in the tag cache array, and reading the corresponding microinstruction data from the data cache array according to the tag reuse mapping relationship.

[0095] In some embodiments of the microinstruction cache control method of this application, reading the corresponding microinstruction data from the data cache array includes reading multiple microinstruction entries associated with the target address tag in parallel within a single clock cycle.

[0096] In the microinstruction caching control method of some embodiments of this application, storing the microinstructions based on the tag reuse mapping relationship specifically includes: Identify multiple microinstructions belonging to the same branch prediction window or the same cache line in the processor pipeline; The multiple microinstructions are respectively stored into multiple microinstruction entries in the data cache array; The multiple microinstruction entries are marked as sharing the same physical address tag entry in the tag cache array.

[0097] In the microinstruction cache control method of some embodiments of this application, the tag cache array and the data cache array are divided into multiple groups, and different groups have different tag reuse ratios; The method further includes: dynamically determining the label reuse ratio based on the size of the branch prediction window, such that the label reuse ratio is positively correlated with the size of the branch prediction window.

[0098] In some embodiments of the microinstruction cache control method of this application, the method further includes managing a data sharing map, the managing data sharing map including: The data cache array is divided into multiple fixed-size common entries and at least one shared domain; When the number of microinstructions in the microinstruction entry to be stored is not greater than the capacity of the public entry, it is stored in the public entry; When the number of microinstructions in a microinstruction entry to be stored exceeds the capacity of the common entry, the microinstruction entry is stored in the common entry, and the overflowing microinstruction data is stored in the shared domain.

[0099] In the microinstruction cache control method of some embodiments of this application, the shared domain is divided into multiple shared sub-regions, and each shared sub-region is associated with a set of common entries; When storing microinstruction entries into the public entry and its associated shared domain, the specific steps are as follows: the microinstruction entries are stored into the public entry, and the overflowing microinstruction data is stored into the shared sub-region associated with the public entry.

[0100] In some embodiments of the microinstruction cache control method of this application, the method further includes performing a replacement operation, the replacement operation including: The storage path of the data cache array is divided into multiple logical replacement groups according to the tag reuse grouping, and each logical replacement group corresponds to a tag reuse group; An inter-group replacement strategy is implemented among the logical replacement groups to determine the target logical replacement group to be replaced. Within the target logical replacement group, an intra-group replacement strategy is implemented to determine the target storage path to be replaced.

[0101] In some embodiments of the microinstruction cache control method of this application, the method further includes: When the shared domain is full, based on the popularity information of each microinstruction entry, the microinstruction entry to be replaced in the shared domain is selected for replacement.

[0102] In some embodiments of the microinstruction cache control method of this application, reading the corresponding microinstruction data from the data cache array specifically includes: When an address tag is hit within a single clock cycle, multiple microinstruction entries corresponding to that address tag are read in parallel from the data cache array; Multiple microinstruction entries read are merged into a microinstruction stream based on program order.

[0103] In some embodiments of the microinstruction cache control method of this application, the method further includes: The offset address of the next instruction is calculated based on the sequence offset of the microinstruction entry at the end of the microinstruction stream. When the completion status bits of each microinstruction entry in the microinstruction stream are all valid, the current instruction fetch window is released.

[0104] In some embodiments of the microinstruction cache control method of this application, the method further includes: When consecutive branch prediction windows cause storage entry slots in the data cache array to become idle, the tag bit width of the tag cache array is redefined or the bit width used for group indexing in the address is adjusted to eliminate the idleness.

[0105] Although the process described above includes multiple operations that occur in a specific order, it should be clearly understood that these processes may include more or fewer operations that can be executed sequentially or in parallel (e.g., using parallel processors or a multithreaded environment).

[0106] Embodiments of this application also provide a computer device. For example... Figure 13 As shown, in some embodiments of this application, the computer device 1302 may include one or more processors 1304, such as one or more central processing units (CPUs) or graphics processing units (GPUs), each of which may implement one or more hardware threads. The computer device 1302 may also include any memory 1306 for storing any kind of information such as code, settings, data, etc. In one specific embodiment, a computer program is stored on the memory 1306 and can run on the processor 1304. When the computer program is run by the processor 1304, it can execute the instructions of the microinstruction cache control method based on heterogeneous architecture described in any of the above embodiments. Without limitation, for example, the memory 1306 may include any type of RAM, any type of ROM, flash memory, hard disk, optical disk, etc. More generally, any memory can use any technology to store information. Further, any memory can provide volatile or non-volatile retention of information. Further, any memory may represent a fixed or removable component of the computer device 1302. In one scenario, when processor 1304 executes associated instructions stored in any memory or combination of memories, computer device 1302 can perform any operation of the associated instructions. Computer device 1302 also includes one or more drive mechanisms 1308 for interacting with any memory, such as hard disk drive mechanisms, optical disk drive mechanisms, etc.

[0107] Computer device 1302 may also include an input / output interface 1310 (I / O) for receiving various inputs (via input device 1312) and providing various outputs (via output device 1314). A specific output mechanism may include a presentation device 1316 and an associated graphical user interface 1318 (GUI). In other embodiments, the input / output interface 1310 (I / O), input device 1312, and output device 1314 may be omitted, and the device may function solely as a computer device within a network. Computer device 1302 may also include one or more network interfaces 1320 for exchanging data with other devices via one or more communication links 1322. One or more communication buses 1324 couple the components described above together.

[0108] Communication link 1322 can be implemented in any way, such as via a local area network, a wide area network (e.g., the Internet), a point-to-point connection, or any combination thereof. Communication link 1322 may include any combination of hardwired links, wireless links, routers, gateway functions, name servers, etc., governed by any protocol or combination of protocols.

[0109] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), computer-readable storage media, and computer program products according to some embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processor to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processor, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0110] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processor to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0111] These computer program instructions may also be loaded onto a computer or other programmable data processor, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable device for implementing the process. Figure 1One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0112] In a typical configuration, a computer device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0113] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0114] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by computer equipment. As defined in this application, computer-readable media does not include transient media, such as modulated data signals and carrier waves.

[0115] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0116] The embodiments of this application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. The embodiments of this application can also be practiced in distributed computing environments where tasks are performed by remote processors connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0117] It should also be understood that, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0118] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0119] In the description of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this application, as well as the features of different embodiments or examples.

[0120] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A microinstruction cache device based on a heterogeneous architecture, characterized in that, include: A data cache array is used to store microinstructions; A tag cache array is used to store the address tags of the microinstructions; wherein, a tag reuse mapping relationship is configured between the tag cache array and the data cache array, and the tag reuse mapping relationship includes: multiple microinstruction entries belonging to the same address contiguous block share the same address tag entry; The cache management unit, coupled to the tag cache array and the data cache array, is configured to perform data operations based on the tag reuse mapping relationship.

2. The microinstruction cache device based on heterogeneous architecture according to claim 1, characterized in that, The tag reuse mapping relationship specifically includes: Based on the instruction address continuity of the branch prediction window or cache line, a single physical address tag entry in the tag cache array is mapped to multiple micro-instruction entries in the data cache array, so that the multiple micro-instruction entries share the same physical address tag entry.

3. The microinstruction cache device based on heterogeneous architecture according to claim 1, characterized in that: The tag cache array and the data cache array are divided into multiple groups, and different groups have different tag reuse ratios.

4. The microinstruction cache device based on heterogeneous architecture according to claim 3, characterized in that: The tag reuse ratio is dynamically determined based on the size of the branch prediction window or the cache line, and the tag reuse ratio is positively correlated with the size of the branch prediction window or the cache line.

5. The microinstruction cache device based on heterogeneous architecture according to claim 1, characterized in that: The data cache array includes multiple fixed-size public entries and at least one shared domain, the shared domain being associated with the multiple public entries; The device is also configured with a data sharing mapping relationship, which includes: When the number of microinstructions in a microinstruction entry is not greater than the capacity of the common entry, the microinstruction entry is mapped to a single common entry; When the number of microinstructions in a microinstruction entry exceeds the capacity of the public entry, the microinstruction entry is mapped to a single public entry and its associated shared domain.

6. The microinstruction cache device based on heterogeneous architecture according to claim 5, characterized in that: The shared domain is divided into multiple shared sub-regions, each of which is associated with a set of common entries; When the number of microinstructions in a microinstruction entry is not greater than the capacity of the common entry, the microinstruction entry is mapped to the common entry; when the number of microinstructions in a microinstruction entry is greater than the capacity of the common entry, the microinstruction entry is mapped to the common entry and its associated shared sub-region.

7. The microinstruction cache device based on heterogeneous architecture according to claim 1, characterized in that: The data cache array includes various microinstruction entry formats with different capacities, and different capacity entry formats correspond to different amounts of microinstructions stored.

8. The microinstruction cache device based on heterogeneous architecture according to claim 1, characterized in that, The cache management unit is configured as follows: The storage path of the data cache array is divided into multiple logical replacement groups according to the tag reuse grouping, and each logical replacement group corresponds to a tag reuse group; An inter-group replacement strategy is implemented among the logical replacement groups to determine the target logical replacement group to be replaced. Within the target logical replacement group, an intra-group replacement strategy is implemented to determine the target storage path to be replaced.

9. The microinstruction cache device based on heterogeneous architecture according to claim 5, characterized in that, The cache management unit is also configured to: When the shared domain is full, the microinstruction entry to be replaced in the shared domain is selected based on the popularity information of each microinstruction entry.

10. The microinstruction cache device based on heterogeneous architecture according to claim 1, characterized in that, The cache management unit is also configured to: When an address tag is hit within a single clock cycle, multiple microinstruction entries corresponding to that address tag are read in parallel from the data cache array based on the tag multiplexing mapping relationship, and the read multiple microinstruction entries are merged into a microinstruction stream based on program order.

11. The microinstruction cache device based on heterogeneous architecture according to claim 10, characterized in that, The cache management unit is also configured to: The offset address of the next instruction is calculated based on the sequence offset of the microinstruction entry at the end of the microinstruction stream, and the current instruction fetch window is released when the completion status bits of each microinstruction entry in the microinstruction stream are valid.

12. The microinstruction cache device based on heterogeneous architecture according to claim 2, characterized in that, The cache management unit is also configured to: When consecutive branch prediction windows cause storage entry slots in the data cache array to become idle, the tag bit width of the tag cache array is redefined or the bit width used for group indexing in the address is adjusted to eliminate the idleness.

13. A processor architecture, characterized in that, include: Instruction decoding unit; Microinstruction queue; as well as The microinstruction cache device as described in any one of claims 1 to 12, wherein the microinstruction cache device is disposed between the instruction decoding unit and the microinstruction queue.

14. A chip, characterized in that, Including the processor architecture described in claim 13.

15. A microinstruction cache control method based on heterogeneous architecture, characterized in that, The method includes: Receive a write request for a microinstruction and store the microinstruction into a data cache array according to the address contiguous block to which the microinstruction belongs; The microinstructions are stored based on a tag reuse mapping relationship, which includes mapping multiple microinstruction entries belonging to the same address contiguous block to the same address tag entry in the tag cache array. In response to the instruction fetch request of the microinstruction, the target address tag is found by searching the tag cache array, and the corresponding microinstruction data is read from the data cache array according to the tag reuse mapping relationship.

16. The microinstruction cache control method based on heterogeneous architecture according to claim 15, characterized in that, The step of reading the corresponding microinstruction data from the data cache array includes reading multiple microinstruction entries associated with the target address tag in parallel within a single clock cycle.

17. The microinstruction cache control method based on heterogeneous architecture according to claim 15, characterized in that, The storage of the microinstructions based on the tag reuse mapping relationship specifically includes: Identify multiple microinstructions belonging to the same branch prediction window or the same cache line in the processor pipeline; The multiple microinstructions are respectively stored into multiple microinstruction entries in the data cache array; The multiple microinstruction entries are marked as sharing the same physical address tag entry in the tag cache array.

18. The microinstruction cache control method based on heterogeneous architecture according to claim 15, characterized in that, The tag cache array and the data cache array are divided into multiple groups, and different groups have different tag reuse ratios; The method further includes: dynamically determining the label reuse ratio based on the size of the branch prediction window, such that the label reuse ratio is positively correlated with the size of the branch prediction window.

19. The microinstruction cache control method based on heterogeneous architecture according to claim 15, characterized in that, The method further includes managing a data sharing map, which includes: The data cache array is divided into multiple fixed-size common entries and at least one shared domain; When the number of microinstructions in the microinstruction entry to be stored is not greater than the capacity of the public entry, it is stored in the public entry; When the number of microinstructions in a microinstruction entry to be stored exceeds the capacity of the common entry, the microinstruction entry is stored in the common entry, and the overflowing microinstruction data is stored in the shared domain.

20. The microinstruction cache control method based on heterogeneous architecture according to claim 19, characterized in that, The shared domain is divided into multiple shared sub-regions, each of which is associated with a set of common entries; When storing microinstruction entries into the public entry and its associated shared domain, the specific steps are as follows: the microinstruction entries are stored into the public entry, and the overflowing microinstruction data is stored into the shared sub-region associated with the public entry.

21. The microinstruction cache control method based on heterogeneous architecture according to claim 15, characterized in that, The method further includes performing a replacement operation, the replacement operation comprising: The storage path of the data cache array is divided into multiple logical replacement groups according to the tag reuse grouping, and each logical replacement group corresponds to a tag reuse group; An inter-group replacement strategy is implemented among the logical replacement groups to determine the target logical replacement group to be replaced. Within the target logical replacement group, an intra-group replacement strategy is implemented to determine the target storage path to be replaced.

22. The microinstruction cache control method based on heterogeneous architecture according to claim 19, characterized in that, The method further includes: When the shared domain is full, based on the popularity information of each microinstruction entry, the microinstruction entry to be replaced in the shared domain is selected for replacement.

23. The microinstruction cache control method based on heterogeneous architecture according to claim 15, characterized in that, The step of reading the corresponding microinstruction data from the data cache array specifically includes: When an address tag is hit within a single clock cycle, multiple microinstruction entries corresponding to that address tag are read in parallel from the data cache array; Multiple microinstruction entries read are merged into a microinstruction stream based on program order.

24. The microinstruction cache control method based on heterogeneous architecture according to claim 23, characterized in that, The method further includes: The offset address of the next instruction is calculated based on the sequence offset of the microinstruction entry at the end of the microinstruction stream. Release the current instruction fetch window when all completion status bits of each microinstruction entry in the microinstruction stream are valid.

25. The microinstruction cache control method based on heterogeneous architecture according to claim 17, characterized in that, The method further includes: When consecutive branch prediction windows cause storage entry slots in the data cache array to become idle, the tag bit width of the tag cache array is redefined or the bit width used for group indexing in the address is adjusted to eliminate the idleness.

26. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, When the computer program is run by the processor, it executes the instructions of the method according to any one of claims 15-25.

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