A bidirectional ultra-low capacitance and ultra-low clamp transient voltage suppression device and a preparation method thereof

Abstract

The embodiment of the application provides a bidirectional ultra-low capacitance and ultra-low clamping transient voltage suppression device and a preparation method. When the substrate resistivity is between zero point several ohms and several tens of ohms, a first injection area, a second injection area and a third injection area are formed through multiple ion implantations and epitaxial growth, the leakage problem of the bidirectional SCR structure is solved, and thus a transient voltage suppression device with low clamping voltage, small capacitance and low leakage current can be obtained. When the substrate resistivity is between several ohms and several hundred ohms, a first injection area, a second injection area and a third injection area are formed through multiple ion implantations, the leakage problem of the bidirectional SCR structure is solved, and thus a transient voltage suppression device with low clamping voltage, small capacitance and low leakage current can be obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device and its fabrication method. Background Technology

[0002] As the signal transmission rate of electronic products continues to increase and the manufacturing processes of back-end IC devices become increasingly advanced, the ability of electronic products to withstand ESD (electrostatic discharge) and EOS (electrical overstress) is weakening. Therefore, transient voltage suppressor devices (TVS) are needed to protect the back-end ICs of electronic products. This places higher demands on TVS devices, requiring lower clamping voltage, smaller capacitance, and lower leakage current. Existing TVS products suffer from complex structures, high capacitance, and high clamping, posing significant challenges to the protection of back-end ICs. Although some TVS structures can achieve low capacitance and low clamping voltage, they suffer from high leakage current, unstable breakdown voltage Vbr, and are either unusable or have low yields, hindering mass production. Summary of the Invention

[0003] To solve or alleviate the leakage current problem and the problem of excessive capacitance of TVS with low clamping voltage in the existing technology.

[0004] In a first aspect, embodiments of this application provide a bidirectional ultra-low capacitance ultra-low clamping voltage transient voltage suppression device, comprising: a first input / output terminal, a second input / output terminal, a first PNPN structure, and a second PNPN structure;

[0005] The first input / output terminal is connected to the first end of the first PNPN structure and the second end of the second PNPN structure, and the second input / output terminal is connected to the first end of the second PNPN structure and the second end of the first PNPN structure.

[0006] The first PNPN structure includes a first PN junction, a second PN junction, and a third PN junction; the second PNPN structure includes a fourth PN junction, a fifth PN junction, and a sixth PN junction.

[0007] A first injection region is provided between the first PN junction and the second and third PN junctions. A second injection region is provided between the fifth and sixth PN junctions on the side away from the first injection region. A third injection region is provided between the fourth PN junction on the side away from the first injection region.

[0008] In a preferred embodiment of this application, the first PNPN structure is composed of a fourth implantation region, a substrate, a second well, and a fifth implantation region; the second PNPN structure is composed of a sixth implantation region, a substrate, a first well, and a seventh implantation region; the doping type of the substrate is the same as that of the first, second, and third implantation regions, and the first, second, and third implantation regions are disposed in the substrate;

[0009] The seventh injection region is disposed in the first well, the fourth injection region is disposed in the substrate, and the fourth injection region and the seventh injection region are disposed in contact.

[0010] The fifth implantation region is disposed in the second well region, and the sixth implantation region is disposed in the substrate, with the fifth implantation region and the sixth implantation region being connected to each other;

[0011] The first injection region is spaced between the fourth injection region and the second well, the second injection region is located on the side of the first well away from the first injection region, and the third injection region is located on the side of the sixth injection region away from the first injection region.

[0012] The fourth injection region, the first well, the second well, and the sixth injection region are P-type; the first injection region, the second injection region, the third injection region, the fifth injection region, the seventh injection region, and the substrate are N-type.

[0013] In a preferred embodiment of this application, when the first well, the second well, the fifth injection region, and the seventh injection region are all N-type, and the first injection region, the second injection region, the third injection region, the fourth injection region, the sixth injection region, and the substrate are all P-type, the fourth injection region is disposed in the first well, or both the fourth and seventh injection regions are disposed in the first well; the sixth injection region is disposed in the second well, or both the sixth and fifth injection regions are disposed in the second well.

[0014] In a preferred embodiment of this application, a first intrinsic epitaxial layer and a second intrinsic epitaxial layer are sequentially disposed above the substrate. The doping type of the first intrinsic epitaxial layer and the second intrinsic epitaxial layer is the same as that of the substrate. The doping concentration of the first intrinsic epitaxial layer and the second intrinsic epitaxial layer is less than that of the substrate. The first PNPN structure and the second PNPN structure are disposed in the second intrinsic epitaxial layer.

[0015] The first implantation region, the second implantation region, and the third implantation region each extend through the second intrinsic epitaxial layer and the first intrinsic epitaxial layer into the substrate.

[0016] In a preferred embodiment of this application, the first PNPN structure is composed of a fourth injection region, a second intrinsic epitaxial layer, a second well, and a fifth injection region; the second PNPN structure is composed of a sixth injection region, a second intrinsic epitaxial layer, a first well, and a seventh injection region.

[0017] The seventh injection region is disposed in the first well, the fourth injection region is disposed in the second intrinsic epitaxial layer, and the fourth injection region and the seventh injection region are connected to each other;

[0018] The fifth injection region is disposed in the second well region, and the sixth injection region is disposed in the second intrinsic epitaxial layer. The fifth injection region and the sixth injection region are connected to each other.

[0019] The first injection region is spaced between the fourth injection region and the second well, the second injection region is located on the side of the first well away from the first injection region, and the third injection region is located on the side of the sixth injection region away from the first injection region.

[0020] The fourth injection region, the first well, the second well, and the sixth injection region are P-type; the first injection region, the second injection region, the third injection region, the fifth injection region, the seventh injection region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are N-type.

[0021] In a preferred embodiment of this application, when the first well, the second well, the fifth implantation region, and the seventh implantation region are N-type, and the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the sixth implantation region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are all P-type, the fourth implantation region is disposed in the first well, or both the fourth and seventh implantation regions are disposed in the first well; the sixth implantation region is disposed in the second well, or both the sixth and fifth implantation regions are disposed in the second well.

[0022] In a preferred embodiment of this application, when the first well, the second well, the fifth implantation region, and the seventh implantation region are N-type, and the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the sixth implantation region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are all P-type, and when the fourth implantation region and the seventh implantation region are both disposed in the first well and the sixth implantation region and the fifth implantation region are both disposed in the second well, an eighth implantation region is further disposed in the first well region, and a ninth implantation region is further disposed in the second well region;

[0023] The eighth injection area is located on the side of the fourth injection area away from the seventh injection area, and the eighth injection area is connected to the fourth injection area. The ninth injection area is located on the side of the sixth injection area away from the fifth injection area, and the sixth injection area is connected to the ninth injection area.

[0024] Both the eighth and ninth injection regions are N-type.

[0025] In a preferred embodiment of this application, when the first well, the second well, the fifth implantation region, and the seventh implantation region are N-type, and the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the sixth implantation region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are all P-type, and when the fourth implantation region and the seventh implantation region are both disposed in the first well and the sixth implantation region and the fifth implantation region are both disposed in the second well, an eighth implantation region is further disposed in the first well region, and a ninth implantation region is further disposed in the second well region;

[0026] The eighth injection area is located on the side of the seventh injection area away from the fourth injection area, and the eighth injection area is connected to the seventh injection area. The ninth injection area is located on the side of the fifth injection area away from the sixth injection area, and the fifth injection area is connected to the ninth injection area.

[0027] Both the eighth and ninth injection regions are P-type.

[0028] Secondly, embodiments of this application also provide a method for fabricating the aforementioned bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device, the method comprising:

[0029] By growing a first intrinsic epitaxial layer on a substrate, and then performing a first ion implantation and a second ion implantation sequentially on the first intrinsic epitaxial layer, a first primary implantation region, a second primary implantation region, and a third primary implantation region are formed, wherein the energy of the first ion implantation is greater than the energy of the second ion implantation.

[0030] Continue to grow a second intrinsic epitaxial layer on the first intrinsic epitaxial layer, and then perform a third ion implantation and a fourth ion implantation on the second intrinsic epitaxial layer at the positions corresponding to the first primary implantation region, the second primary implantation region and the third primary implantation region, to finally form the first implantation region, the second implantation region and the third implantation region. The energy of the third ion implantation is greater than the energy of the fourth ion implantation.

[0031] A first PNPN structure and a second PNPN structure are formed in the second intrinsic epitaxial layer.

[0032] The resistivity of the substrate is 0.01-50 ohms.

[0033] Thirdly, embodiments of this application also provide a method for fabricating the aforementioned bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device, the method comprising:

[0034] A fifth and a sixth ion implantation are performed sequentially on the substrate to form a first implantation region, a second implantation region, and a third implantation region; the energy of the fifth ion implantation is greater than the energy of the sixth ion implantation.

[0035] A first PNPN structure and a second PNPN structure are formed on the substrate;

[0036] The resistivity of the substrate is 5-500 ohms.

[0037] Compared with the prior art, the embodiments of this application provide a bidirectional ultra-low capacitance ultra-low clamping voltage transient voltage suppression device and its fabrication method. When the substrate resistivity is between a few tenths of an ohm and tens of ohms, a first implantation region, a second implantation region, and a third implantation region are formed through multiple ion implantations and epitaxial growth, solving the leakage problem of the bidirectional SCR structure (SCR structure is short for silicon controlled rectifier, also known as thyristor), thereby obtaining a transient voltage suppression device with low clamping voltage, small capacitance, and low leakage current; or when the substrate resistivity is between a few ohms and hundreds of ohms, a first implantation region, a second implantation region, and a third implantation region are formed through multiple ion implantations, solving the leakage problem of the bidirectional SCR structure, thereby obtaining a transient voltage suppression device with low clamping voltage, small capacitance, and low leakage current. Attached Figure Description

[0038] Non-limiting and non-exhaustive embodiments of the invention are described by way of example with reference to the following figures, wherein:

[0039] Figure 1 The diagram shows an N-type substrate structure for a bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device in the prior art.

[0040] Figure 2 The diagram shows a P-type substrate structure for a bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device in the prior art.

[0041] Figure 3 This diagram shows the structure of the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device provided in Embodiment 1 of the present invention.

[0042] Figure 4 This diagram shows the structure of the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device provided in Embodiment 2 of the present invention.

[0043] Figure 5 This diagram shows the structure of the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device provided in Embodiment 3 of the present invention.

[0044] Figure 6 This diagram shows the structure of the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device provided in Embodiment 4 of the present invention.

[0045] Figure 7 This diagram shows the structure of the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device provided in Embodiment 5 of the present invention.

[0046] Figure 8 This diagram shows the structure of the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device provided in Embodiment 6 of the present invention.

[0047] Figure 9 The diagram shows the structure of the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device provided in Embodiment 7 of the present invention. Detailed Implementation

[0048] To make the above and other features and advantages of the present invention clearer, the invention will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments given herein are for the purpose of explanation to those skilled in the art and are exemplary only, not restrictive.

[0049] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0051] In this embodiment of the invention, the main difference between N-type doping and P-type doping lies in the type of impurity, the conductive carriers, and the type of semiconductor formed.

[0052] N-type doping is achieved by incorporating pentavalent elements (such as phosphorus or arsenic) into a semiconductor. These elements provide additional electrons, giving the semiconductor good electronic conductivity and a negative charge. In N-type semiconductors, the primary charge carriers are electrons.

[0053] P-type doping is achieved by incorporating trivalent elements (such as boron). These elements create holes in the semiconductor, which carry a positive charge, causing the P-type semiconductor to exhibit electrical conductivity. In P-type semiconductors, the dominant charge carriers are holes.

[0054] like Figure 1 and Figure 2 As shown, existing transient voltage suppression protection devices use a high-energy implantation region 6 for bottom isolation. However, the maximum high-energy implantation energy is limited to below 2800 KeV, so ion implantation cannot be too deep. The minimum ion implantation dose needs to be >5e11, so the ion doping concentration cannot be too low. Therefore, the junction capacitance of the product cannot be made too small. This application solves the problems of excessive capacitance and leakage in existing bidirectional low-capacitance TVS products. The main reason for leakage is that punch-through effect is prone to occur when the substrate concentration is low. When a denser substrate is selected, the concentration on both sides of the PN junction is higher, so the capacitance is larger. Or, with high-energy bottom isolation, since the maximum implantation energy is 2800 keV, the implantation depth is shallower, and the concentration on both sides of the PN junction is also relatively high, so the capacitance is also relatively large.

[0055] Example 1

[0056] like Figure 3 As shown, this application embodiment provides a bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device, including: a first input / output terminal 11, a second input / output terminal 12, a first PNPN structure and a second PNPN structure;

[0057] The first input / output terminal 11 is connected to the first end of the first PNPN structure and the second end of the second PNPN structure, and the second input / output terminal 12 is connected to the first end of the second PNPN structure and the second end of the first PNPN structure.

[0058] The first PNPN structure includes a first PN junction, a second PN junction, and a third PN junction; the second PNPN structure includes a fourth PN junction, a fifth PN junction, and a sixth PN junction.

[0059] A first injection region 1 is provided between the first PN junction and the second and third PN junctions. A second injection region 2 is provided between the fifth and sixth PN junctions on the side away from the first injection region 1. A third injection region 3 is provided between the fourth PN junction on the side away from the first injection region 1.

[0060] The first PNPN structure consists of a fourth injection region 4, a substrate 13, a second well 7, and a fifth injection region 8; the second PNPN structure consists of a sixth injection region 9, a substrate 13, a first well 5, and a seventh injection region 10.

[0061] The seventh injection region 10 is disposed in the first well 5, the fourth injection region 4 is disposed in the substrate 13, and the fourth injection region 4 and the seventh injection region 10 are connected to each other;

[0062] The fifth injection region 8 is disposed in the second well 7 region, and the sixth injection region 9 is disposed in the substrate 13. The fifth injection region 8 and the sixth injection region 9 are connected.

[0063] The first injection region 1 is disposed between the fourth injection region 4 and the second well 7, the second injection region 2 is disposed on the side of the first well 5 away from the first injection region 1, and the third injection region 3 is disposed on the side of the sixth injection region 9 away from the first injection region 1; the first injection region 1, the second injection region 2 and the third injection region 3 extend into the substrate 13.

[0064] The fourth injection region 4, the first well 5, the second well 7 and the sixth injection region 9 are P-type; the first injection region 1, the second injection region 2, the third injection region 3, the fifth injection region 8, the seventh injection region 10 and the substrate 13 are N-type.

[0065] The specific preparation process is as follows: In this embodiment, the first implantation region 1, the second implantation region 2 and the third implantation region 3 are formed by the fifth ion implantation (one high-energy implantation) and the sixth ion implantation (one normal implantation) on the N-type substrate 13 (resistivity 5-500 ohms). Then, the first PNPN structure and the second PNPN structure are formed on the substrate 13, thereby constituting a bidirectional low-capacitance low-clamping voltage TVS.

[0066] Example 2

[0067] like Figure 4 As shown, based on Embodiment 1, a first intrinsic epitaxial layer 14 and a second intrinsic epitaxial layer 15 are sequentially disposed above the substrate 13. The concentrations of the first intrinsic epitaxial layer 14 and the second intrinsic epitaxial layer 15 are less than the concentration of the substrate 13. The first PNPN structure and the second PNPN structure are disposed in the second intrinsic epitaxial layer 15.

[0068] The first intrinsic epitaxial layer 14 and the second intrinsic epitaxial layer 15 have the same doping type as the substrate 13, and the first implantation region 1, the second implantation region 2 and the third implantation region 3 extend through the second intrinsic epitaxial layer 15 and the first intrinsic epitaxial layer 14 into the substrate 13.

[0069] The first PNPN structure consists of a fourth injection region 4, a second intrinsic epitaxial layer 15, a second well 7, and a fifth injection region 8; the second PNPN structure consists of a sixth injection region 9, a second intrinsic epitaxial layer 15, a first well 5, and a seventh injection region 10.

[0070] The seventh injection region 10 is disposed in the first well 5, and the fourth injection region 4 is disposed in the second intrinsic epitaxial layer 15. The fourth injection region 4 and the seventh injection region 10 are connected.

[0071] The fifth injection region 8 is disposed in the second well 7 region, and the sixth injection region 9 is disposed in the second intrinsic epitaxial layer 15. The fifth injection region 8 and the sixth injection region 9 are connected.

[0072] The first injection region is spaced between the fourth injection region 4 and the second well 7, the second injection region is located on the side of the first well 5 away from the first injection region, and the third injection region is located on the side of the sixth injection region 9 away from the first injection region.

[0073] The fourth injection region 4, the first well 5, the second well 7, and the sixth injection region 9 are P-type; the first injection region 1, the second injection region 2, the third injection region 3, the fifth injection region 8, the seventh injection region 10, and the substrate are N-type.

[0074] The specific fabrication process is as follows: A first intrinsic epitaxial layer 14 is grown on an N-type substrate 13 (resistivity 0.01-50 ohms). Then, two high-energy ion implantations are performed on the first intrinsic epitaxial layer 14, with energies of 2000 keV and 500 keV, respectively, forming a first primary implantation region, a second primary implantation region, and a third primary implantation region. A second intrinsic epitaxial layer 15 is then grown on the first intrinsic epitaxial layer 14. Then, two high-energy ion implantations (a third ion implantation and a fourth ion implantation) are performed on the second intrinsic epitaxial layer 15 at positions corresponding to the first, second, and third primary implantation regions, with energies of 2000 keV and 500 keV, respectively (the implantation energy of the third ion implantation is greater than that of the fourth ion implantation). Finally, a first implantation region 1, a second implantation region 2, and a third implantation region 3 are formed. The purpose of performing two epitaxial growths and multiple ion implantations is to reduce the impact of the relatively dense substrate 13 on the product capacitance. Finally, a first PNPN structure and a second PNPN structure are formed on the second intrinsic epitaxial layer 15, thereby constituting a bidirectional low-capacitance low-clamping voltage TVS.

[0075] Example 3

[0076] like Figure 5As shown, based on Embodiment 1, when the first well 5, the second well 7, the fifth injection region 8, and the seventh injection region are all N-type, and the first injection region 1, the second injection region 2, the third injection region 3, the fourth injection region 4, the sixth injection region 9, and the substrate 13 are all P-type, the fourth injection region 4 is disposed in the first well 5, and the sixth injection region 9 is disposed in the second well 7.

[0077] The specific fabrication process is as follows: A first intrinsic epitaxial layer 14 is grown on a P-type substrate 13 (resistivity 0.01-50 ohms). Then, two high-energy ion implantations are performed on the first intrinsic epitaxial layer 14, with energies of 2000 keV and 500 keV, respectively, forming a first primary implantation region, a second primary implantation region, and a third primary implantation region. A second intrinsic epitaxial layer 15 is then grown on the first intrinsic epitaxial layer 14. Then, two high-energy ion implantations (a third ion implantation and a fourth ion implantation) are performed on the second intrinsic epitaxial layer 15 at positions corresponding to the first, second, and third primary implantation regions, with energies of 2000 keV and 500 keV, respectively (the implantation energy of the third ion implantation is greater than that of the fourth ion implantation). Finally, a first implantation region 1, a second implantation region 2, and a third implantation region 3 are formed. The purpose of performing two epitaxial growths and multiple ion implantations is to reduce the impact of the relatively dense substrate 13 on the product capacitance. Finally, a first PNPN structure and a second PNPN structure are formed on the second intrinsic epitaxial layer 15, ultimately forming a bidirectional low-capacitance low-clamp voltage TVS.

[0078] Example 4

[0079] like Figure 6 As shown, the device structure in Example 4 is the same as that in Example 3, but the preparation process is different.

[0080] When the first well 5, the second well 7, the fifth injection region 8, and the seventh injection region are all N-type, and the first injection region 1, the second injection region 2, the third injection region 3, the fourth injection region 4, the sixth injection region 9, and the substrate 13 are all P-type, the fourth injection region 4 is disposed in the first well 5, and the sixth injection region 9 is disposed in the second well 7.

[0081] The specific preparation process is as follows: In this embodiment, a first implantation region 1, a second implantation region 2, and a third implantation region 3 with side isolation are formed by a fifth ion implantation (a high-energy implantation) and a sixth ion implantation (a normal implantation) on a P-type substrate 13 (resistivity 5-500 ohms). Then, a first PNPN structure and a second PNPN structure are formed on the substrate 13, and finally a bidirectional low-capacitance low-clamping voltage TVS is formed.

[0082] Example 5

[0083] like Figure 7 As shown, based on Embodiment 3, when the first well 5, the second well 7, the fifth implantation region 8, and the seventh implantation region are all N-type, and the first implantation region 1, the second implantation region 2, the third implantation region 3, the fourth implantation region 4, the sixth implantation region 9, the first intrinsic epitaxial layer 14, the second intrinsic epitaxial layer 15, and the substrate 13 are all P-type, and the fourth implantation region 4 and the seventh implantation region 10 are both disposed in the first well 5 and the sixth implantation region 9 and the fifth implantation region 8 are both disposed in the second well 7.

[0084] The specific fabrication process is as follows: A first intrinsic epitaxial layer 14 is grown on a P-type substrate 13 (resistivity 0.01-50 ohms). Then, two high-energy ion implantations are performed on the first intrinsic epitaxial layer 14, with energies of 2000 keV and 500 keV respectively, forming a first primary implantation region, a second primary implantation region, and a third primary implantation region. A second intrinsic epitaxial layer 15 is then grown on the first intrinsic epitaxial layer 14. Next, two high-energy ion implantations are performed on the second intrinsic epitaxial layer 15 at positions corresponding to the first, second, and third primary implantation regions, with energies of 2000 keV and 500 keV respectively, ultimately forming a first implantation region 1, a second implantation region 2, and a third implantation region 3. The purpose of performing two epitaxial growths and multiple ion implantations is to reduce the impact of the relatively dense substrate 13 on the product capacitance. Finally, a first PNPN structure and a second PNPN structure are formed on the second intrinsic epitaxial layer 15, ultimately forming a bidirectional low-capacitance, low-clamp voltage TVS.

[0085] Example 6

[0086] like Figure 8 As shown, based on Embodiment 4, when the first well 5, the second well 7, the fifth implantation region 8, and the seventh implantation region are all N-type, and the first implantation region 1, the second implantation region 2, the third implantation region 3, the fourth implantation region 4, the sixth implantation region 9, the first intrinsic epitaxial layer 14, the second intrinsic epitaxial layer 15, and the substrate 13 are all P-type, and when the fourth implantation region 4 and the seventh implantation region 10 are both disposed in the first well 5 and the sixth implantation region 9 and the fifth implantation region 8 are both disposed in the second well 7, the first well 5 is further provided with an eighth implantation region 16, and the second well region 7 is further provided with a ninth implantation region 17;

[0087] The eighth injection area 16 is located on the side of the fourth injection area 4 away from the seventh injection area 10, and the eighth injection area 16 is connected to the fourth injection area 4. The ninth injection area 17 is located on the side of the sixth injection area 9 away from the fifth injection area 8, and the sixth injection area 9 is connected to the ninth injection area 17. Both the eighth injection area 16 and the ninth injection area 17 are N-type.

[0088] The specific preparation process is the same as in Example 5, and will not be repeated here.

[0089] Example 7

[0090] like Figure 9 As shown, based on Embodiment 4, when the first well 5, the second well 7, the fifth implantation region 8, and the seventh implantation region are all N-type, and the first implantation region 1, the second implantation region 2, the third implantation region 3, the fourth implantation region 4, the sixth implantation region 9, the first intrinsic epitaxial layer 14, the second intrinsic epitaxial layer 15, and the substrate 13 are all P-type, and when the fourth implantation region 4 and the seventh implantation region 10 are both disposed in the first well 5 and the sixth implantation region 9 and the fifth implantation region 8 are both disposed in the second well 7, the first well 5 is further provided with an eighth implantation region 16, and the second well region 7 is further provided with a ninth implantation region 17;

[0091] The eighth injection area 16 is located on the side of the seventh injection area 10 away from the fourth injection area 4, and the eighth injection area 16 is connected to the seventh injection area 10. The ninth injection area 17 is located on the side of the fifth injection area 8 away from the sixth injection area 9, and the fifth injection area 8 is connected to the ninth injection area 17. Both the eighth injection area 16 and the ninth injection area 17 are P-shaped.

[0092] The specific preparation process is the same as in Example 5, and will not be repeated here.

[0093] Secondly, Examples 2, 3, 5 to 7 were prepared using the following methods:

[0094] By growing a first intrinsic epitaxial layer 14 on a substrate 13, and then performing a first ion implantation and a second ion implantation sequentially on the first intrinsic epitaxial layer 14, a first primary implantation region, a second primary implantation region, and a third primary implantation region are formed, wherein the energy of the first ion implantation is greater than the energy of the second ion implantation.

[0095] Continue to grow a second intrinsic epitaxial layer 15 on the first intrinsic epitaxial layer 14, and then perform a third ion implantation and a fourth ion implantation on the second intrinsic epitaxial layer 15 at the positions corresponding to the first primary implantation region, the second primary implantation region and the third primary implantation region, to finally form a first implantation region 1, a second implantation region 2 and a third implantation region 3. The energy of the third ion implantation is greater than the energy of the fourth ion implantation.

[0096] A first PNPN structure and a second PNPN structure are formed in the second intrinsic epitaxial layer 15.

[0097] It should be noted that the implantation energy for the first and third ion implantations was 2000 keV, and the implantation energy for the second and fourth ion implantations was 500 keV.

[0098] Thirdly, Examples 1 and 4 were prepared using the following methods:

[0099] The fifth and sixth ion implantations are performed sequentially on the substrate 13 to form the first implantation region 1, the second implantation region 2, and the third implantation region 3. The energy of the fifth ion implantation is greater than that of the sixth ion implantation.

[0100] A first PNPN structure and a second PNPN structure are formed on the substrate 13;

[0101] The resistivity of the substrate 13 is 5-500 ohms.

[0102] It should be noted that the fifth ion implantation was a high-energy ion implantation, while the sixth ion implantation was a conventional ion implantation.

[0103] The technical features of the above implementation schemes can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above implementation schemes are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] Although the invention has been described in conjunction with embodiments, those skilled in the art will understand that the above description and drawings are exemplary and not restrictive, and the invention is not limited to the disclosed embodiments. Various modifications and variations are possible without departing from the spirit of the invention.

Claims

1. A bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device, characterized in that, include: First input / output terminal, second input / output terminal, first PNPN structure and second PNPN structure; The first input / output terminal is connected to the first end of the first PNPN structure and the second end of the second PNPN structure, and the second input / output terminal is connected to the first end of the second PNPN structure and the second end of the first PNPN structure. The first PNPN structure includes a first PN junction, a second PN junction, and a third PN junction; the second PNPN structure includes a fourth PN junction, a fifth PN junction, and a sixth PN junction. A first injection region is provided between the first PN junction and the second and third PN junctions. A second injection region is provided between the fifth and sixth PN junctions on the side away from the first injection region. A third injection region is provided between the fourth PN junction on the side away from the first injection region.

2. The bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device as described in claim 1, characterized in that, The first PNPN structure consists of a fourth implantation region, a substrate, a second well, and a fifth implantation region; the second PNPN structure consists of a sixth implantation region, a substrate, a first well, and a seventh implantation region; the doping type of the substrate is the same as that of the first, second, and third implantation regions, and the first, second, and third implantation regions are disposed in the substrate; The seventh injection region is disposed in the first well, the fourth injection region is disposed in the substrate, and the fourth injection region and the seventh injection region are disposed in contact. The fifth implantation region is disposed in the second well region, and the sixth implantation region is disposed in the substrate, with the fifth implantation region and the sixth implantation region being connected to each other; The first injection region is spaced between the fourth injection region and the second well, the second injection region is located on the side of the first well away from the first injection region, and the third injection region is located on the side of the sixth injection region away from the first injection region. The fourth injection region, the first well, the second well, and the sixth injection region are P-type; the first injection region, the second injection region, the third injection region, the fifth injection region, the seventh injection region, and the substrate are N-type.

3. The bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device as described in claim 2, characterized in that, When the first well, the second well, the fifth injection region, and the seventh injection region are all N-type, and the first injection region, the second injection region, the third injection region, the fourth injection region, the sixth injection region, and the substrate are all P-type, the fourth injection region is disposed in the first well, and the sixth injection region is disposed in the second well.

4. The bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device as described in claim 2, characterized in that, A first intrinsic epitaxial layer and a second intrinsic epitaxial layer are sequentially disposed above the substrate. The doping type of the first intrinsic epitaxial layer and the second intrinsic epitaxial layer is the same as that of the substrate. The doping concentration of the first intrinsic epitaxial layer and the second intrinsic epitaxial layer is less than that of the substrate. The first PNPN structure and the second PNPN structure are disposed in the second intrinsic epitaxial layer. The first implantation region, the second implantation region, and the third implantation region each extend through the second intrinsic epitaxial layer and the first intrinsic epitaxial layer into the substrate.

5. The bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device as described in claim 4, characterized in that, The first PNPN structure consists of a fourth injection region, a second intrinsic epitaxial layer, a second well, and a fifth injection region; the second PNPN structure consists of a sixth injection region, a second intrinsic epitaxial layer, a first well, and a seventh injection region. The seventh injection region is disposed in the first well, the fourth injection region is disposed in the second intrinsic epitaxial layer, and the fourth injection region and the seventh injection region are connected to each other; The fifth injection region is disposed in the second well region, and the sixth injection region is disposed in the second intrinsic epitaxial layer. The fifth injection region and the sixth injection region are connected to each other. The first injection region is spaced between the fourth injection region and the second well, the second injection region is located on the side of the first well away from the first injection region, and the third injection region is located on the side of the sixth injection region away from the first injection region. The fourth injection region, the first well, the second well, and the sixth injection region are P-type; the first injection region, the second injection region, the third injection region, the fifth injection region, the seventh injection region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are N-type.

6. The bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device as described in claim 5, characterized in that, When the first well, the second well, the fifth implantation region, and the seventh implantation region are N-type, and the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the sixth implantation region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are all P-type, the fourth implantation region is disposed in the first well, or both the fourth and seventh implantation regions are disposed in the first well; the sixth implantation region is disposed in the second well, or both the sixth and fifth implantation regions are disposed in the second well.

7. The bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device as described in claim 6, characterized in that, When the first well, the second well, the fifth implantation region, and the seventh implantation region are N-type, and the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the sixth implantation region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are all P-type, and when the fourth implantation region and the seventh implantation region are both disposed in the first well and the sixth implantation region and the fifth implantation region are both disposed in the second well, an eighth implantation region is also disposed in the first well region, and a ninth implantation region is also disposed in the second well region; The eighth injection area is located on the side of the fourth injection area away from the seventh injection area, and the eighth injection area is connected to the fourth injection area. The ninth injection area is located on the side of the sixth injection area away from the fifth injection area, and the sixth injection area is connected to the ninth injection area. Both the eighth and ninth injection regions are N-type.

8. The bidirectional ultra-low capacitance ultra-low clamping transient voltage suppression device as described in claim 6, characterized in that, When the first well, the second well, the fifth implantation region, and the seventh implantation region are N-type, and the first implantation region, the second implantation region, the third implantation region, the fourth implantation region, the sixth implantation region, the first intrinsic epitaxial layer, the second intrinsic epitaxial layer, and the substrate are all P-type, and when the fourth implantation region and the seventh implantation region are both disposed in the first well and the sixth implantation region and the fifth implantation region are both disposed in the second well, an eighth implantation region is also disposed in the first well region, and a ninth implantation region is also disposed in the second well region; The eighth injection area is located on the side of the seventh injection area away from the fourth injection area, and the eighth injection area is connected to the seventh injection area. The ninth injection area is located on the side of the fifth injection area away from the sixth injection area, and the fifth injection area is connected to the ninth injection area. Both the eighth and ninth injection regions are P-type.

9. A method for fabricating the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device as described in claim 1, characterized in that, The method includes: By growing a first intrinsic epitaxial layer on a substrate, and then performing a first ion implantation and a second ion implantation sequentially on the first intrinsic epitaxial layer, a first primary implantation region, a second primary implantation region, and a third primary implantation region are formed, wherein the energy of the first ion implantation is greater than the energy of the second ion implantation. Continue to grow a second intrinsic epitaxial layer on the first intrinsic epitaxial layer, and then perform a third ion implantation and a fourth ion implantation on the second intrinsic epitaxial layer at the positions corresponding to the first primary implantation region, the second primary implantation region and the third primary implantation region, to finally form the first implantation region, the second implantation region and the third implantation region. The energy of the third ion implantation is greater than the energy of the fourth ion implantation. A first PNPN structure and a second PNPN structure are formed in the second intrinsic epitaxial layer, wherein the resistivity of the substrate is 0.01-50 ohms.

10. A method for fabricating the bidirectional ultra-low capacitance ultra-low clamp transient voltage suppression device as described in claim 1, characterized in that, The method includes: A fifth and a sixth ion implantation are performed sequentially on the substrate to form a first implantation region, a second implantation region, and a third implantation region. The energy of the fifth ion implantation is greater than that of the sixth ion implantation. A first PNPN structure and a second PNPN structure are formed on the substrate; The resistivity of the substrate is 5-500 ohms.

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