Pixel charging method, driving circuit and display device

Abstract

This application discloses a pixel charging method, driving circuit, and display device, relating to the field of display technology. The method includes: monitoring the crosstalk state of a display panel; obtaining the current charging cycle timing when a crosstalk region exists; and adjusting the current charging cycle timing to a target charging cycle timing, wherein the target charging cycle timing is to charge the red sub-pixel row, blue sub-pixel row, green sub-pixel row, green sub-pixel row, blue sub-pixel row, and red sub-pixel row sequentially. By arranging the green sub-pixel row in two charging opportunities within one cycle, this application stabilizes the voltage of the green sub-pixels. The stable voltage of the green sub-pixels directly reduces the impact of their brightness variations on the overall image, weakening the crosstalk phenomenon that is transmitted from the common electrode voltage fluctuation to the pixel voltage and ultimately manifests as uneven brightness. This mitigates the crosstalk phenomenon caused by insufficient charging and increased capacitive coupling in the TRD pixel architecture.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to pixel charging methods, driving circuits, and display devices. Background Technology

[0002] In the field of display panel manufacturing, LCD (Liquid Crystal Display) technology is highly mature. It widely adopts pixel architectures such as DRD (Dual-Rate Driving) and TRD (Triple-Rate Driving). By increasing the number of gate lines and reducing the number of source lines, the number of source driver chips required is effectively reduced, thereby achieving cost reduction at the material level.

[0003] However, compared to the standard pixel architecture, the TRD pixel architecture has three times the number of gate lines in the vertical direction, resulting in a significant increase in the resistive and capacitive load for data transmission. Consequently, under the same charging conditions, the TRD pixel architecture is more prone to undercharging. If undercharging occurs, the storage capacitor cannot store enough charge, thus failing to effectively stabilize the pixel voltage. This amplifies the impact of capacitive coupling, increasing fluctuations in the common electrode voltage and leading to more severe crosstalk. Summary of the Invention

[0004] The main purpose of this application is to provide a pixel charging method, driving circuit and display device, which aims to solve the technical problem of significant crosstalk in the current TRD pixel architecture.

[0005] To achieve the above objectives, this application proposes a pixel charging method, the pixel charging method comprising: Monitor the crosstalk status of the display panel, wherein the pixel architecture of the display panel is a three-times-rate-driven pixel architecture; When the crosstalk state is that there is a crosstalk area in the display panel, the current charging cycle timing for charging each row of pixel units in the display panel is obtained, wherein any row of pixel units includes a red sub-pixel row, a green sub-pixel row and a blue sub-pixel row arranged in sequence; The current charging cycle timing is adjusted to the target charging cycle timing, wherein the target charging cycle timing includes a first charging timing and a second charging timing under two alternating charging rounds. For any row of pixel units, the first charging timing is to charge the red sub-pixel row, blue sub-pixel row and green sub-pixel row in the pixel unit in sequence during the first charging round, and the second charging timing is to charge the green sub-pixel row, blue sub-pixel row and red sub-pixel row in the pixel unit in sequence during the second charging round.

[0006] In one embodiment, the step of adjusting the current charging cycle timing to the target charging cycle timing includes: Obtain the preset target charging cycle timing and determine the target control signal based on the target charging cycle timing; The current control signal output to the gate line corresponding to each sub-pixel in each row of pixel units is adjusted to output the target control signal to each gate line. The current control signal is used to control the charging of each sub-pixel according to the current charging cycle timing, and the target control signal is used to control the charging of each sub-pixel according to the target charging cycle timing.

[0007] In one embodiment, the step of adjusting the current control signal output to the gate line corresponding to each sub-pixel in each row of the pixel units to output the target control signal to each gate line includes: The current control signal output to the gate line corresponding to each sub-pixel in each row of pixel units in the crosstalk region is adjusted to output the target control signal to each gate line. The crosstalk region is a pixel region where the first gray level value corresponding to the boundary data line is less than the second gray level value corresponding to the adjacent data line, and the difference between the first gray level value and the second gray level value is greater than a preset threshold.

[0008] In one embodiment, the pixel charging method further includes: Monitor the common voltage fluctuation status of the sample display panel; Monitor the brightness changes of red, green, and blue sub-pixels in the three primary color pixel sample areas of the sample display panel; The target charging cycle sequence is determined based on the common voltage fluctuation and the brightness change.

[0009] In one embodiment, the brightness change status includes a brightness change degree ratio, and the step of determining the target charging cycle sequence based on the common voltage fluctuation status and the brightness change status includes: Based on the common voltage fluctuation condition and the standard charging cycle sequence of the sample display panel, determine the sub-pixel coupling frequency ratio corresponding to the common voltage fluctuation condition within the cycle period corresponding to the standard charging cycle sequence, wherein the sub-pixel coupling frequency ratio represents the ratio between the red sub-pixel coupling frequency, the green sub-pixel coupling frequency and the blue sub-pixel coupling frequency; The target charging cycle timing is determined based on the ratio of sub-pixel coupling times and the ratio of brightness change.

[0010] In one embodiment, the step of monitoring the crosstalk status of the display panel includes: Monitor the serial output voltage of each data line in the display panel; The crosstalk state is determined based on each of the serial output voltages.

[0011] In one embodiment, the step of determining the crosstalk state based on each of the serial output voltages includes: Each of the serial output voltages is mapped to a corresponding grayscale value, and any grayscale value is compared with the grayscale value of the adjacent data line to obtain the comparison result; The crosstalk state is determined based on the comparison results.

[0012] In one embodiment, the step of determining the crosstalk state based on the comparison result includes: If the difference between any grayscale value and the grayscale value of an adjacent data line is less than a preset threshold, the crosstalk state is determined to be that there is no crosstalk area on the display panel. If the difference between any grayscale value and the grayscale value of an adjacent data line is greater than or equal to a preset threshold, the crosstalk state is determined to be that there is a crosstalk area in the display panel.

[0013] Furthermore, to achieve the above objectives, this application also proposes a driving circuit, wherein the driving circuit drives a display panel with a pixel architecture of three times the pixel rate, and the driving circuit includes: A gate driving circuit, wherein the gate driving circuit is distributed in the non-display area of ​​the array substrate of the display panel; Multiple gate lines, each of which is connected to the gate driving circuit and each sub-pixel in a corresponding row of pixel units in the display panel, wherein each row of pixel units includes a red sub-pixel row, a green sub-pixel row and a blue sub-pixel row arranged sequentially; Multiple data lines, any one of which is connected to a corresponding column of sub-pixels in the display panel; A source driver chip, wherein the source driver chip is connected to each column of sub-pixels through each of the data lines, and is used to charge each column of sub-pixels; A control chip, connected to both the gate driving circuit and the source driving chip, is used to monitor the crosstalk state of the display panel. When the crosstalk state indicates the presence of a crosstalk region on the display panel, the control chip acquires the current charging cycle timing for charging each row of pixel units in the display panel. The control chip then adjusts the current charging cycle timing to a target charging cycle timing, wherein the target charging cycle timing includes a first charging sequence and a second charging sequence under two alternating charging cycles. For any row of pixel units, the first charging sequence involves sequentially charging the red sub-pixel row, blue sub-pixel row, and green sub-pixel row in the pixel unit during the first charging cycle, and the second charging sequence involves sequentially charging the green sub-pixel row, blue sub-pixel row, and red sub-pixel row in the pixel unit during the second charging cycle.

[0014] In addition, to achieve the above objectives, this application also proposes a display device, which includes a display panel and a driving circuit as described above, wherein the display panel is electrically connected to the driving circuit. The display device further includes: a memory, a processor, and a pixel charging program stored in the memory and executable on the processor, wherein the pixel charging program, when executed by the processor, implements the steps of the pixel charging method as described above.

[0015] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the pixel charging method described above.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: This application monitors the crosstalk state of the display panel and, upon determining the presence of a crosstalk area, adjusts the current charging cycle sequence of each row of pixel units within the panel to a specific target charging cycle sequence. Specifically, in two alternating charging cycles, the red, blue, and green sub-pixel rows of each row of pixel units are charged sequentially in the first charging cycle, and then sequentially in the second charging cycle. This fundamentally changes the charging order of the sub-pixels. Considering the dominant role of green sub-pixels in human visual brightness perception, by arranging the green sub-pixel rows in two charging opportunities within one cycle, the red and green sub-pixel rows are coupled once, and the blue sub-pixel rows are coupled twice throughout the entire charging cycle. However, the impact of blue sub-pixels on human visual brightness perception is relatively small, while the stable voltage of green sub-pixels significantly reduces the impact of brightness changes on the overall image. Therefore, the impact of common electrode voltage fluctuations on the sub-pixels is much lower than in a conventional charging cycle sequence. Therefore, this technical solution optimizes the charge management of sub-pixels with high visual impact by adjusting the charging timing, directly reducing the crosstalk phenomenon that is transmitted from the common electrode voltage fluctuation to the pixel voltage and ultimately manifests as uneven brightness. This significantly weakens the crosstalk phenomenon caused by insufficient charging and increased capacitive coupling in the TRD pixel architecture. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a display panel provided in an embodiment of the pixel charging method of this application; Figure 2 A schematic diagram of the pixel circuit of a display panel provided in an embodiment of the pixel charging method of this application; Figure 3 A schematic diagram of a crosstalk scenario provided for an embodiment of the pixel charging method of this application; Figure 4 A schematic diagram illustrating the crosstalk principle provided in an embodiment of the pixel charging method of this application; Figure 5A schematic diagram of the charging timing and voltage coupling of a conventional pixel charging method provided in the embodiment of the pixel charging method of this application; Figure 6 This is a schematic flowchart of a pixel charging method embodiment 1 of this application; Figure 7 This is a schematic flowchart of Embodiment 2 of the pixel charging method of this application; Figure 8 A schematic diagram of the improved charging timing and voltage coupling of the pixel charging method provided in Embodiment 2 of this application; Figure 9 This is a schematic flowchart of the pixel charging method embodiment three of this application; Figure 10 This is a simplified flowchart illustrating the pixel charging method provided in Embodiment 3 of this application.

[0020] Explanation of icon numbers:

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0023] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution of this application embodiment is: monitoring the crosstalk state of the display panel, wherein the pixel architecture of the display panel is a three-times-rate-driven pixel architecture; when the crosstalk state is that there is a crosstalk area in the display panel, obtaining the current charging cycle timing for charging each row of pixel units in the display panel, wherein any row of pixel units includes a red sub-pixel row, a green sub-pixel row, and a blue sub-pixel row arranged sequentially; adjusting the current charging cycle timing to a target charging cycle timing, wherein the target charging cycle timing includes a first charging timing and a second charging timing under two alternating charging cycles, wherein for any row of pixel units, the first charging timing is to charge the red sub-pixel row, the blue sub-pixel row, and the green sub-pixel row in the pixel unit sequentially in the first charging cycle, and the second charging timing is to charge the green sub-pixel row, the blue sub-pixel row, and the red sub-pixel row in the pixel unit sequentially in the second charging cycle.

[0025] Reference Figure 1 , Figure 1In a display panel with a TRD pixel architecture, the vertical lines connecting each column of R, G, and B sub-pixels are data lines, and the horizontal lines connecting each R, G, and B sub-pixels are gate lines. The array substrate of this display panel integrates a GDL (Gate Driver Line). Each gate line of this GDL circuit controls a corresponding row of sub-pixels. Because the TRD pixel architecture has three times the number of vertical gate lines compared to a standard pixel architecture, the resistive and capacitive load on data transmission is significantly increased. Therefore, under the same charging conditions, the TRD pixel architecture is more prone to undercharging. If undercharging occurs, the storage capacitor cannot store enough charge, thus failing to effectively stabilize the pixel voltage. This amplifies the capacitive coupling effect, increasing fluctuations in the common electrode voltage and resulting in more severe crosstalk.

[0026] Reference Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of a sub-pixel. Capacitive coupling refers to the phenomenon where the voltages between the pixel electrode (Pixel ITO), data line, gate line, and common electrode (Common ITO) influence each other due to the presence of parasitic capacitance Cgs. When the TFT (Thin Film Transistor) is turned off, due to the charge conservation effect, some of the charge in the storage capacitor Cs and the liquid crystal capacitor Clc is transferred to Cgs, causing pixel voltage fluctuations. At this time, the pixel voltage couples to the common electrode voltage, causing it to fluctuate and generating horizontal crosstalk. Simultaneously, there is also a parasitic capacitance Cpd between the pixel ITO and the data line, which is also a major cause of vertical crosstalk. Furthermore, in the diagram, Scanline represents the scan line, and G, D, and S represent the gate, drain, and source of the TFT, respectively.

[0027] Reference Figure 3 , Figure 3 In the image, R, G, and B represent red, green, and blue subpixels, respectively. For example, if there is a white block in the middle of a solid color background with a grayscale value of 127, the grayscale value of the white block is 255. At this time, the source driving voltage of the white block is higher than the source driving voltage of the surrounding area with a grayscale value of 127. When the pixels in the white block area are charged, the common electrode voltage of the area with a grayscale value of 127 around the white block will be coupled and fluctuate. At this time, the area around the white block will appear brighter or darker.

[0028] Reference Figure 4 ,Will Figure 3The display screen is modeled like a bucket, dividing the screen into three equal parts. The middle bucket corresponds to the white area, and the two outer buckets correspond to the grayscale value 127 areas. The water in each bucket represents the common electrode voltage. Since the common electrode voltage is the voltage shared by the entire panel, the water in the three buckets is connected. When the source driver chip charges the pixels in the middle area, it applies a source driver voltage corresponding to grayscale value 255, which is higher than the source driver voltage of the other grayscale value 127 areas. Corresponding to the bucket model, as the water level in the middle bucket increases, and because the bottom of the buckets is connected, the water level in the two outer buckets also rises. This fluctuation in the common electrode voltage causes the areas on either side of the white area to appear either too bright or too dark.

[0029] Furthermore, changes in the source drive voltage will cause fluctuations in the common electrode voltage. Due to the special nature of the TRD architecture, a single data line outputs the source drive voltages for all RGB sub-pixels. Therefore, when the source drive voltage is output, the gate lines are turned on row by row, and the source drive voltages of the RGB sub-pixels are sequentially fed in. When the data for the next row of sub-pixels is sent, the TFTs corresponding to the sub-pixels in the previous row are turned off. At this time, when the sub-pixels in the next row are charging, they will be coupled to the common electrode voltage. The sub-pixels in the previous row will be affected by the fluctuations in the common electrode voltage. (See reference...) Figure 5 . Figure 5 In G3n-2, the solid line represents the red sub-pixel row, the dashed line represents the green sub-pixel row, and the dotted-dash line represents the blue sub-pixel row, where n is an integer ≥ 1. When using a conventional charging sequence with RGB-RGB as one cycle, shortly after the red sub-pixel in row G3n-2 finishes charging and the TFT is turned off, the green sub-pixel in row G3n-1 begins charging. At this instant, the common electrode voltage VCOM is pulled high. At this time, the voltage difference between VCOM and the Pixel ITO of the red sub-pixel in the previous row decreases. Since the charge in the storage capacitor and liquid crystal capacitor in the red sub-pixel is stored before VCOM is coupled, the storage capacitor and liquid crystal capacitor release the charge at this time. After stabilization, the pulled-high VCOM will recover, but at this time the amount of charge in the red sub-pixel is reduced. Macroscopically speaking, some of the charging power is consumed, thus affecting the brightness. Corresponding to the waveform, at the instant the green sub-pixel starts charging, the red sub-pixel releases the charge and couples VCOM downward. The coupling situation of the subsequent green and blue sub-pixels can be inferred by analogy. The coupling situation basically matches the charging sequence. In one charging sequence cycle, the red and green sub-pixels are coupled twice, and the blue sub-pixel is coupled once. In white light, the proportions of the three primary colors are R:G:B=2:7:1. For RGB sub-pixels, under the same voltage fluctuation, the brightness change ratio is also R:G:B=2:7:1. Therefore, the visual impact caused by the coupling of green sub-pixels is the greatest. At this time, we need to adjust the charging sequence to reduce the number of times green sub-pixels are coupled.

[0030] This application provides a solution that monitors the crosstalk state of the display panel and, upon determining the presence of a crosstalk area, adjusts the current charging cycle sequence of each pixel unit within the panel to a specific target charging cycle sequence. This involves sequentially charging the red sub-pixel row, blue sub-pixel row, green sub-pixel row, green sub-pixel row, blue sub-pixel row, and red sub-pixel row, thereby fundamentally changing the charging order of the sub-pixels. Specifically considering the dominant role of green sub-pixels in human visual brightness perception, by arranging the green sub-pixel row within two charging opportunities in one cycle, even if some charge is lost due to fluctuations in the common electrode voltage after the first charging, the subsequent second charging can effectively replenish the charge, thus significantly stabilizing the voltage of the green sub-pixels. The stable voltage of the green sub-pixels directly and significantly reduces the impact of brightness variations on the overall image. Therefore, this technical solution optimizes the charge management of sub-pixels with high visual impact by adjusting the charging timing, directly reducing the crosstalk phenomenon that is transmitted from the common electrode voltage fluctuation to the pixel voltage and ultimately manifests as uneven brightness. This significantly weakens the crosstalk phenomenon caused by insufficient charging and increased capacitive coupling in the TRD pixel architecture.

[0031] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or a display device capable of performing the above functions. The following description uses a display device as an example to illustrate this embodiment and the subsequent embodiments.

[0032] Based on this, embodiments of this application provide a pixel charging method, referring to... Figure 6 , Figure 6 This is a schematic flowchart of the first embodiment of the pixel charging method of this application.

[0033] In this embodiment, the pixel charging method includes steps S10 to S30: Step S10: Monitor the crosstalk status of the display panel, wherein the pixel architecture of the display panel is a three-times-rate-driven pixel architecture. It's important to note that crosstalk refers to the presence of visual interference in the display panel due to capacitive coupling. Specifically, in the TRD pixel architecture, the increased number of vertical gate lines leads to a greater resistive-capacitive load on data transmission, making the storage capacitor prone to insufficient charging. When the storage capacitor is undercharged, it cannot store enough charge to stabilize the sub-pixel voltage, exacerbating the capacitive coupling effect and causing fluctuations in the common electrode voltage. These fluctuations couple to adjacent pixel electrodes through parasitic capacitance, resulting in uneven brightness patches or edge distortion in the image—the crosstalk phenomenon. Crosstalk is determined by monitoring the display panel's image, such as detecting areas with significant grayscale differences, like small windows or document boundaries in a solid-color background. These areas are more prone to crosstalk due to voltage abrupt changes. The crosstalk state can be, but is not limited to, divided into areas with and without crosstalk, which triggers subsequent charging timing adjustments.

[0034] Step S20: When the crosstalk state is that there is a crosstalk area in the display panel, obtain the current charging cycle timing for charging each row of pixel units in the display panel, wherein any row of pixel units includes a red sub-pixel row, a green sub-pixel row and a blue sub-pixel row set in sequence. It's important to note that a pixel unit refers to a basic display unit in a display panel, composed of red, green, and blue subpixels arranged in a specific order. In the TRD pixel architecture, each row of pixel units includes a row of red subpixels, a row of green subpixels, and a row of blue subpixels arranged sequentially. This means that vertically, the three colors of subpixels are located in three independent rows, each controlled by a dedicated gate line. This regional structure is a core feature of the TRD architecture, reducing the cost of the source driver chip by increasing the number of gate lines and decreasing the number of source lines. Each pixel unit works together to mix and produce the color of a complete pixel, with the red subpixel responsible for the red component, the green subpixel responsible for the green component, and the blue subpixel responsible for the blue component. The combination of the brightness of these three components achieves full-color display.

[0035] The current charging cycle timing is the timing pattern used by the display panel in its current operating state to apply data voltages to the sub-pixel rows in each row of pixel units in a fixed order. In the standard TRD architecture, the current charging cycle timing is typically to charge the red sub-pixel row, green sub-pixel row, blue sub-pixel row, red sub-pixel row, green sub-pixel row, and blue sub-pixel row in sequence, i.e., RGB cycle repetition. This cycle timing determines the order in which gate lines are turned on and data voltages are written, directly affecting the charging process of sub-pixels and the fluctuation characteristics of the common electrode voltage. Obtaining the current charging cycle timing is necessary to compare and switch with the optimized target charging cycle timing after identifying crosstalk regions, thereby specifically improving crosstalk.

[0036] In this context, the red subpixel row refers to an entire row of subpixels in the display panel specifically used to display the red component. Within each row of pixel units in the TRD pixel architecture, the red subpixel row is the first subpixel row, and each red subpixel within it is controlled by an independent gate line. During charging, this row of subpixels receives the data voltage corresponding to the red grayscale from the source drive circuit. The adequacy and stability of its charging directly affect the accuracy of the red brightness in the displayed image. Since red accounts for a relatively small proportion of overall brightness (approximately 20% of white light), its voltage fluctuations have a relatively small impact on visual perception. Therefore, its charging timing can be adjusted to a specific position within the target charging cycle to reduce the number of times it is coupled by common electrode voltage fluctuations, thereby helping to reduce the visual impact of crosstalk.

[0037] A green subpixel row refers to an entire row of subpixels in a display panel specifically designed to display the green component. Within each row of pixel units in the TRD pixel architecture, the green subpixel row is the second subpixel row, and each green subpixel is controlled by an independent gate line. This row of subpixels receives the data voltage corresponding to the green grayscale during charging. Since green accounts for the highest proportion of perceived brightness in human vision (approximately 70% of white light), its voltage fluctuations are most sensitive to overall screen brightness. Therefore, the charging stability of the green subpixel row is crucial for improving crosstalk. The target charging cycle timing compensates for potential charge loss due to common electrode voltage fluctuations by charging twice consecutively within its charging cycle, significantly reducing brightness unevenness caused by crosstalk.

[0038] The blue subpixel row refers to an entire row of subpixels in a display panel specifically used to display the blue component. Within each row of pixel units in the TRD pixel architecture, the blue subpixel row is the third subpixel row, and each blue subpixel is controlled by an independent gate line. This row of subpixels receives the data voltage corresponding to the blue grayscale level during charging. Since blue accounts for a relatively low proportion of overall brightness (approximately 10% of white light), its voltage fluctuations have a relatively small impact on visual perception. During the target charging cycle, the charging order of the blue subpixel row is rearranged so that it charges after the red subpixel row and before the green subpixel row, to balance the coupling effect between subpixels of different colors and prioritize the stability of the green subpixel row.

[0039] Step S30: Adjust the current charging cycle timing to the target charging cycle timing. The target charging cycle timing includes a first charging timing and a second charging timing under two alternating charging rounds. For any row of pixel units, the first charging timing is to charge the red sub-pixel row, blue sub-pixel row and green sub-pixel row in the pixel unit in sequence during the first charging round. The second charging timing is to charge the green sub-pixel row, blue sub-pixel row and red sub-pixel row in the pixel unit in sequence during the second charging round.

[0040] It should be noted that the target charging cycle timing is a specific charging sequence used to replace the current charging cycle timing to mitigate crosstalk. Specifically, this timing involves charging the red, blue, green, and red sub-pixel rows in each row of pixel units sequentially within two adjacent charging cycles, i.e., the RBG-GBR sequence. This design is based on in-depth analysis of the common electrode voltage fluctuation pattern and sub-pixel brightness ratio: within two adjacent charging cycles, i.e., within one charging cycle, the green sub-pixel row is given two charging opportunities. Even if some charge is lost due to voltage coupling after the first charging, it can be replenished in time during the second charging, thus stabilizing the green brightness. At the same time, the charging order of the red and blue sub-pixel rows is adjusted so that the overall coupling frequency is tilted towards colors with lower visual impact. The target charging cycle timing is only activated when a crosstalk region is detected, and is achieved by changing the turn-on order of the gate lines, thereby effectively suppressing crosstalk caused by insufficient charging and capacitive coupling under the TRD architecture.

[0041] Understandably, in the TRD pixel architecture, the increased number of vertical gate lines leads to a significant increase in the resistive and capacitive load of data transmission. Under the same charging conditions, it is easier to experience undercharging. Undercharging weakens the ability of the storage capacitor to stabilize the pixel voltage, thereby exacerbating the capacitive coupling effect and causing fluctuations in the common electrode voltage. Ultimately, this results in obvious crosstalk on the display screen. In particular, because the green sub-pixels have a high brightness ratio, their voltage fluctuations have the most significant impact on the visual experience. Therefore, this embodiment first monitors the crosstalk state of the display panel, and when a crosstalk area is determined to exist, obtains the current charging cycle sequence, and then adjusts it to a specific target charging cycle sequence. That is, in the first charging cycle of two alternating charging rounds, the red sub-pixel rows, blue sub-pixel rows, and green sub-pixel rows in each row of pixel units are charged sequentially, and in the second charging round, the green sub-pixel rows, blue sub-pixel rows, and red sub-pixel rows in each row of pixel units are charged sequentially. This avoids the problem of green sub-pixels being susceptible to charge loss due to voltage fluctuations of the common electrode under the traditional fixed timing, which leads to uneven screen brightness. By rearranging the charging order, two charging opportunities are provided for the green sub-pixel rows within one cycle, effectively compensating for the charge loss that may be caused by voltage coupling, and significantly stabilizing the voltage of the green sub-pixels. At the same time, the coupling effect is distributed more to the blue and red sub-pixels with lower visual sensitivity, thereby suppressing the transmission of common electrode voltage fluctuations to pixel voltage as a whole, reducing the brightness difference of crosstalk in the displayed image, and improving the visual uniformity of the TRD pixel architecture display panel.

[0042] For example, firstly, a detection unit integrated in the display panel driving circuit performs real-time scanning and analysis of the display screen. This detection unit identifies whether there are areas with clear boundaries between light and dark areas in the screen, such as document window edges or color block boundaries, based on image processing algorithms, and directly outputs a binary judgment signal, i.e., crosstalk status, regarding whether there are crosstalk areas on the display panel. Next, the timing controller receives this judgment signal. When the signal indicates the presence of a crosstalk area, the timing controller reads the pre-stored current charging cycle timing for charging each row of pixel units in the display panel from its internal register. Subsequently, the timing controller directly calls another set of preset driving waveform sequences stored internally. This waveform sequence defines the target charging cycle timing, i.e., controlling the GDL circuit to sequentially activate the corresponding red sub-pixel rows, blue sub-pixel rows, and green sub-pixel rows in each row of pixel units in the first charging cycle of the two alternating charging cycles, and sequentially activate the gate lines corresponding to the green sub-pixel rows, blue sub-pixel rows, and red sub-pixel rows in each row of pixel units in the second charging cycle, thereby completing the overall switching of the charging timing.

[0043] This embodiment provides a pixel charging method. By monitoring the crosstalk state of the display panel, and when a crosstalk area is determined to exist, the current charging cycle sequence of each row of pixel units in the panel is adjusted to a specific target charging cycle sequence. That is, in two alternating charging cycles, the red sub-pixel row, blue sub-pixel row, and green sub-pixel row of each row of pixel units are charged sequentially in the first charging cycle, and the green sub-pixel row, blue sub-pixel row, and red sub-pixel row of each row of pixel units are charged sequentially in the second charging cycle. This fundamentally changes the charging order of the sub-pixels. In particular, considering the dominant characteristic of green sub-pixels in human visual brightness perception, by arranging the green sub-pixel row in two charging opportunities within one cycle, the red and green sub-pixel rows are coupled once and the blue sub-pixel row is coupled twice in the entire charging cycle. However, the impact of the blue sub-pixel row on human visual brightness perception is relatively small, while the voltage stability of the green sub-pixels directly and significantly reduces the impact of its brightness changes on the overall image. At this time, the impact of common electrode voltage fluctuations on sub-pixels is much lower than that of conventional charging cycle sequences. Therefore, this technical solution optimizes the charge management of sub-pixels with high visual impact by adjusting the charging timing, directly reducing the crosstalk phenomenon that is transmitted from the common electrode voltage fluctuation to the pixel voltage and ultimately manifests as uneven brightness. This significantly weakens the crosstalk phenomenon caused by insufficient charging and increased capacitive coupling in the TRD pixel architecture.

[0044] In one feasible implementation, step S30 may include steps S31-S32: Step S31: Obtain the preset target charging cycle timing and determine the target control signal based on the target charging cycle timing; It should be noted that the target control signal refers to a set of drive electrical signals used to control the on / off state of each gate line in the display panel, based on a predefined or real-time generated RBG-GBR sequence that charges the red, blue, green, and red sub-pixel rows sequentially. This sequence follows a target charging cycle, i.e., charging the red, blue, green, and red sub-pixel rows in that order. Specifically, this signal can be, but is not limited to, a series of pulse waveforms with specific timing, pulse width, and voltage levels. Its output order corresponds to the target charging cycle sequence, ensuring that in the presence of crosstalk, the gate driver can sequentially open the gate lines corresponding to the sub-pixel rows of the appropriate color, thereby achieving precise adjustment of the pixel charging sequence. The target control signal is typically generated by a timing controller according to preset timing rules and achieved by adjusting the output logic of its internal waveform generator.

[0045] Step S32: The current control signal output to the gate line corresponding to each sub-pixel in each row of pixel units is adjusted to output a target control signal to each gate line. The current control signal is used to control the charging of each sub-pixel according to the current charging cycle timing, and the target control signal is used to control the charging of each sub-pixel according to the target charging cycle timing.

[0046] It should be noted that the current control signal refers to the driving electrical signal generated and output by the display panel before adjusting the charging timing, based on the current charging cycle sequence, such as the conventional RGB sequence of charging the red sub-pixel row, green sub-pixel row, and blue sub-pixel row sequentially. This signal is used to control the switching state of each gate line. This signal also exists in the form of a pulse waveform, and its timing logic is consistent with the current charging cycle sequence, controlling the gate lines to turn on row by row in the default order to achieve normal charging of the sub-pixels. The current control signal is usually generated by the timing controller according to default settings or basic driving parameters, and is the baseline control signal for maintaining the normal operation of the display panel.

[0047] It is understandable that if there is a deviation in the adjustment process of the charging cycle timing, it may lead to disordered gate line opening sequence, causing display abnormalities or even aggravating crosstalk. To this end, this embodiment further obtains a preset target charging cycle timing and determines the corresponding target control signal based on this timing. Then, the current control signal output to the gate line corresponding to each sub-pixel in each row of pixel units is adjusted to output the target control signal to each gate line, thereby clarifying the timing adjustment as a specific electrical signal control operation. This scheme avoids problems such as signal asynchrony and gate drive disorder caused by ambiguous timing switching logic or inaccurate execution. By directly presetting and replacing the control signal, it ensures that the gate lines are turned on strictly according to the target charging cycle timing, realizing precise and hardware-based execution of charging timing adjustment. This effectively reduces crosstalk while ensuring the reliability and control consistency of the display panel driving process.

[0048] For example, after determining that there is a crosstalk area in the display panel, the timing controller directly calls the target charging cycle timing code corresponding to the RGB-GBR sequence from multiple pre-stored inherent timing modes. This code acts as an index, triggering the waveform generation unit within the timing controller to output a series of target control signals with specific timing, voltage, and pulse width, i.e., a set of pulse sequences corresponding to the turn-on order of each gate line. Simultaneously, the timing controller maintains the output of the original current control signal, synchronized with the current charging cycle timing (such as the RGB-RGB sequence), to the GDL circuit. When adjustment is required, the controller uses an internal multiplexer to switch the signals output to all relevant GDL circuits from the current control signal to the target control signal at a preset synchronization point, thereby completing the global adjustment of the charging order of all pixel units in one go, without needing to perform signal calculation and matching row by row or region by region.

[0049] In the specific implementation process, step S32 may also include step A32: Step A32: Adjust the current control signal output to the gate line corresponding to each sub-pixel in each row of pixel units in the crosstalk region to output the target control signal to each gate line. The crosstalk region is a pixel region where the first gray level value corresponding to the boundary data line is less than the second gray level value corresponding to the adjacent data line, and the difference between the first gray level value and the second gray level value is greater than a preset threshold.

[0050] For example, the serial output voltage of each data line of the display panel is first sampled and quantized into a digital voltage value by a high-speed analog-to-digital converter. This digital voltage value is then input into a lookup table that stores a voltage-grayscale correspondence. This lookup table is built based on the panel's gamma curve characteristics, thus accurately mapping the real-time voltage signal of each data line to the corresponding grayscale value. Next, at the end of each row scan cycle, the logic processing unit subtracts the grayscale value of each column (i.e., the first grayscale value) from the grayscale values ​​of its left and right adjacent columns (i.e., the second grayscale values) to obtain a series of continuous grayscale differences. These differences are sent to the state judgment unit. When the state judgment unit detects that the first grayscale value of any column is less than the second grayscale value of its adjacent data line, and the grayscale difference between the first and second grayscale values ​​is greater than a preset threshold, it designates the column and its left or right pixel area on the display panel as a crosstalk region (if the first grayscale value of the column is less than the second grayscale value of its left adjacent data line, the crosstalk region is the column and its right pixel area; if the first grayscale value of the column is less than the second grayscale value of its right adjacent data line, the crosstalk region is the column and its left pixel area). The timing controller then directly calls the target charging cycle timing code corresponding to the RGB-GBR sequence from multiple internally stored inherent timing patterns. This code acts as an index, triggering the waveform generation unit within the timing controller to output a series of target control signals with specific timing, voltage, and pulse width—that is, a set of pulse sequences corresponding to the turn-on sequence of each gate line. Simultaneously, the timing controller maintains the output of the original current control signal, synchronized with the current charging cycle timing (e.g., RGB-RGB sequence), to the GDL circuit. When adjustments are needed, the controller uses an internal multiplexer to switch the signal output to the relevant GDL circuit in the crosstalk region from the current control signal to the target control signal at a preset synchronization time. This allows the controller to adjust the charging sequence of a specific pixel unit in one go, without having to perform signal calculation and matching row by row or region by region.

[0051] In specific implementation, the pixel charging method may also include steps S01 to S02: Step S01: Obtain the minimum brightness change that the human eye can perceive in the display panel, and the gamma curve of the green sub-pixel in the display panel. The gamma curve is used to characterize the mapping relationship between the grayscale value and the brightness value of the green sub-pixel. It should be noted that the minimum brightness change refers to the smallest critical value of brightness difference in a displayed image that the human eye can subjectively perceive, i.e., the brightness difference threshold perceived by human vision. This can be derived from the concept of minimum perceptible difference in visual physiology. Given observation conditions and background brightness, this value corresponds to a fixed range of brightness change. In this embodiment, this minimum brightness change serves as the starting input for the preset threshold determination process, elevating crosstalk detection from the traditional electrical or empirical threshold level to a perceptual level aligned with the actual visual experience of the human eye.

[0052] The gamma curve of a green subpixel refers to the non-linear mapping relationship between the input grayscale value of a green subpixel in a display panel and its corresponding output brightness value. It can be expressed as a power function, depending on the liquid crystal response characteristics and driving configuration of the panel. In this embodiment, this gamma curve is specifically selected instead of the average gamma curve of the entire panel or the gamma curves of the red and blue subpixels because the brightness variation of the green subpixel has the most significant visual impact on crosstalk. Reverse mapping based on this curve allows a preset threshold to directly reflect the photoelectric conversion characteristics of the green channel.

[0053] Step S02: Convert the minimum brightness change into grayscale change based on the gamma curve, and use the grayscale change as a preset threshold.

[0054] It should be noted that the grayscale change refers to the absolute value of the difference between the grayscale values ​​carried by any adjacent data lines in the display panel, which directly originates from the comparison result of grayscale values ​​obtained after mapping the serial output voltage. In this embodiment, the grayscale change specifically refers to the critical grayscale difference value corresponding to the minimum brightness change obtained after inverse conversion of the green sub-pixel gamma curve, and is set as a preset threshold for determining the crosstalk state, thereby establishing a quantitative correlation between human eye perception sensitivity and panel driving electrical signals.

[0055] Understandably, since the green subpixel has the highest brightness, crosstalk is naturally most affected by the green subpixel. Therefore, mapping the minimum brightness change in visual perception using the gamma curve of the green subpixel will result in a smaller grayscale threshold than using the average gamma curve or the gamma curve of the red / blue subpixel, thus ensuring that crosstalk detection can more sensitively capture the green brightness fluctuations that have the greatest impact on the human eye.

[0056] For example, before the display panel leaves the factory, the minimum perceptible difference in brightness displayed on the panel under typical viewing conditions is obtained through testing. This minimum perceptible difference is used as the minimum brightness change and stored in the panel's driver control chip. Simultaneously, during panel manufacturing, a color analyzer is used to measure the actual output brightness of the green sub-pixels at each grayscale input. Based on the measurement data, a gamma curve for the green sub-pixels is fitted. This gamma curve is stored in the non-volatile memory of the driver control chip in the form of a lookup table. Each row of the lookup table records a grayscale value and its corresponding brightness value. When the display panel is working normally, when a preset threshold needs to be determined, the timing controller reads the minimum brightness change and the gamma curve lookup table of the green sub-pixels from the memory. Then, using a mid-grayscale value (e.g., grayscale 127) as a reference point, the derivative of the brightness with respect to the grayscale at that reference point is calculated. The minimum brightness change is then divided by this derivative value to obtain the critical grayscale change at that reference point. Finally, this critical grayscale change is written as the preset threshold into a register for subsequent crosstalk region determination.

[0057] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in Embodiment 1 above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 7 The pixel charging method also includes steps S100~S300: Step S100: Monitor the common voltage fluctuation of the sample display panel; It should be noted that common voltage fluctuation refers to the unstable changes in the common electrode voltage VCOM caused by capacitive coupling, obtained through actual measurement or circuit simulation of the sample display panel under specific charging conditions. Specifically, this can manifest as, but is not limited to, signal transitions on the gate and data lines coupling to the common electrode via parasitic capacitance when the sample display panel operates according to the standard charging cycle sequence. This causes periodic or non-periodic voltage fluctuations in the common electrode voltage during the charging process. Monitoring this condition can involve, but is not limited to, using a voltage probe or built-in sensor to capture the voltage waveform on the common electrode and analyzing its fluctuation amplitude, frequency, instantaneous offset, and timing correlation with sub-pixel charging actions, thereby quantitatively assessing the strength of capacitive coupling and its potential impact on display stability.

[0058] Step S200: Monitor the brightness changes of the red, green, and blue sub-pixels in the three primary color pixel sample areas of the sample display panel; It should be noted that brightness variation refers to the abnormal changes in the brightness of the red, green, and blue sub-pixels within the sample area of ​​the three primary color pixels in the display panel, observed through optical measurement or visual evaluation methods under the influence of common voltage fluctuations. Specifically, when the common electrode voltage fluctuates, it changes the actual voltage of the pixel electrode through the storage capacitor and liquid crystal capacitor, causing the light transmittance of the sub-pixel to deviate from the expected value, thus manifesting as increased or decreased brightness. Monitoring this condition can be done, but is not limited to, under a controlled display screen such as a grayscale test image, by using a luminance meter or color analyzer to measure the brightness output of each color sub-pixel area separately and recording its change or trend relative to a stable reference value. This reflects the different sensitivities of different color sub-pixels to voltage fluctuations and their contribution to the overall crosstalk visual performance.

[0059] Step S300: Determine the target charging cycle sequence based on the common voltage fluctuation and brightness change.

[0060] Understandably, this implementation first monitors the common voltage fluctuation of the sample display panel, i.e., the change in the common electrode voltage due to capacitive coupling, and simultaneously monitors the brightness changes of the red, green, and blue sub-pixels in the three primary color pixel sample areas of the panel, i.e., the brightness shift of each color sub-pixel under voltage fluctuations. Then, based on a comprehensive analysis of these two physical conditions, the target charging cycle timing is determined. This avoids the problem of incomplete crosstalk improvement or poor adaptability caused by relying on experience or general preset timing. By combining actual electrical fluctuation and optical response data to customize the timing, the optimized design of the target charging cycle timing is achieved, thereby ensuring that the timing adjustment more accurately matches the panel characteristics and improving the effectiveness and robustness of crosstalk suppression.

[0061] For example, firstly, the sample display panel is connected to the driving test system and displayed a preset static test image, such as a white window pattern against a mid-grayscale background, according to the standard charging cycle sequence (e.g., RGB-RGB sequence). Simultaneously, a voltage probe with high input impedance is used to directly contact the common electrode pads of the panel, and the waveform data of the common electrode voltage changing over time is acquired and recorded in real time, thereby quantifying its fluctuation amplitude and timing to obtain the common voltage fluctuation status. Then, under the same driving conditions, a calibrated imaging luminance meter or microspectroradiometer is used to simultaneously measure the brightness values ​​of the red, green, and blue sub-pixels under the test image, targeting selected three-primary-color pixel sample areas on the sample panel, and recording the brightness change curves of each color sub-pixel during the charging cycle to obtain the brightness change status. Finally, the collected voltage waveform data and brightness change curves are input into the data processing unit. Through correlation analysis, such as finding the time sequence correspondence between voltage fluctuation peaks and brightness change points, the impact of different charging sequences on common voltage fluctuations and brightness stability of each color sub-pixel is evaluated. Thus, the charging sequence that minimizes the brightness fluctuation of the green sub-pixel is directly selected as the target charging cycle sequence, such as the RBG-GBR sequence, to complete the deterministic design of the timing.

[0062] In one feasible implementation, the brightness change status includes the brightness change degree ratio, and step S300 may include steps S301~S302: Step S301: Based on the common voltage fluctuation status and the standard charging cycle sequence of the sample display panel, determine the sub-pixel coupling frequency ratio corresponding to the common voltage fluctuation status within the cycle corresponding to the standard charging cycle sequence, wherein the sub-pixel coupling frequency ratio represents the ratio between the red sub-pixel coupling frequency, the green sub-pixel coupling frequency and the blue sub-pixel coupling frequency. It should be noted that the standard charging cycle timing refers to the conventional charging timing mode used as a comparison benchmark, without the optimization and adjustment of this invention. It is typically the factory default driving sequence of the sample display panel or the driving sequence commonly used in the industry. Specifically, in the TRD pixel architecture, this timing is generally defined as sequentially charging the red sub-pixel row, green sub-pixel row, and blue sub-pixel row in each row of pixel units, i.e., the RGB-RGB sequence, and repeating cyclically. The standard charging cycle timing is the basic reference for analyzing the coupling effect of common voltage fluctuations. Its corresponding gate line turn-on sequence is fixed and used as the basis for calculating the timing relationship between common voltage fluctuations and sub-pixel charging actions when determining the sub-pixel coupling ratio.

[0063] The subpixel coupling frequency ratio refers to the proportion among different color subpixels of the number of significant fluctuations in the common electrode voltage caused by charging actions within a complete charging cycle corresponding to a standard charging cycle sequence. Specifically, by analyzing the correspondence between the common voltage fluctuation and the charging time of each subpixel under the standard timing sequence, the number of common voltage fluctuations caused by charging actions for each of the red, green, and blue subpixels can be statistically determined. For example, in a conventional RGB timing sequence, there might be a situation where red and green subpixels are coupled twice each, and blue subpixels are coupled once, then the subpixel coupling frequency ratio is R:G:B = 2:2:1. This ratio directly reflects the frequency difference of voltage interference faced by different color subpixels under standard driving, and is an important intermediate variable for scientifically deriving the target charging cycle sequence by combining it with the brightness change ratio.

[0064] Step S302: Determine the target charging cycle timing based on the ratio of sub-pixel coupling times and the ratio of brightness change degree.

[0065] It should be noted that the brightness variation ratio refers to the relative proportion of the brightness changes of the red, green, and blue sub-pixels in a sample display panel under the same common electrode voltage fluctuation conditions, obtained through experimental measurement or theoretical analysis. This ratio reflects the differences in the sensitivity of different color sub-pixels to voltage fluctuations in human vision and display characteristics. For example, based on the brightness contribution ratio of each color in white light (e.g., R:G:B=2:7:1) and electro-optical response characteristics, the green sub-pixel, due to its highest brightness proportion, often experiences the most significant brightness change caused by the same voltage fluctuation. Therefore, the brightness variation ratio is usually highest for the green sub-pixel, followed by red, and lowest for blue. This ratio is a key parameter for quantitatively assessing the visual impact of crosstalk and is used to prioritize stabilizing the color component with the greatest impact on overall brightness when adjusting the charging sequence.

[0066] Understandably, the determination of the target charging cycle timing may rely on overall trend judgment or trial-and-error adjustments, lacking quantitative and normalized decision-making basis, resulting in low timing optimization efficiency and potentially suboptimal results. Therefore, this implementation first quantitatively analyzes the coupling frequency of the common voltage fluctuation to red, green, and blue sub-pixels within one cycle based on the common voltage fluctuation situation and the standard charging cycle timing, determining the sub-pixel coupling frequency ratio. Then, this ratio, representing the frequency of electrical interference, is combined with the ratio of brightness change, representing differences in optical sensitivity. Through correlation analysis between the two, for example, seeking a timing sequence that corresponds to a low coupling frequency for highly visually sensitive colors, the target charging cycle timing is determined. This approach effectively avoids the subjectivity, inefficiency, and unstable optimization results that may result from relying solely on experimental data for rough judgment or on engineers' experience to select timing sequences. By introducing two key quantitative parameters, the coupling frequency ratio and the brightness change ratio, and performing synergistic optimization, the objective, model-based, and optimized determination of the target charging cycle timing sequence is achieved. This fundamentally ensures that the designed timing sequence can most effectively guide voltage coupling interference to the color channel with the least visual impact, maximizing the crosstalk suppression effect and predictability.

[0067] For example, firstly, a standard charging cycle sequence, i.e., RGB-RGB order, is applied to the sample display panel, driving it to display a high-contrast test image, while simultaneously acquiring the voltage waveform on the common electrode. By performing time-domain analysis on this waveform, the voltage fluctuation peaks caused by each sub-pixel charging action are accurately identified. Based on the correspondence between the peak occurrence time and the charging time of each color sub-pixel in the standard sequence, the number of times the red, green, and blue sub-pixels respectively cause or experience common voltage fluctuations within a complete cycle is statistically calculated. This allows for the calculation of the sub-pixel coupling ratio, for example, R:G:B=2:2:1, which can be referenced... Figure 5 . Figure 5In G3n-2, the solid line represents the red sub-pixel row, the dashed line represents the green sub-pixel row, and the dotted-dash line represents the blue sub-pixel row, where n is an integer ≥ 1. Shortly after the red subpixel in row G3n-2 finishes charging and the TFT is turned off, the green subpixel in row G3n-1 begins charging. At this instant, VCOM is pulled high, and the voltage difference between VCOM and the Pixel ITO of the red subpixel in the previous row decreases. Since the charge in the storage capacitor and liquid crystal capacitor in the red subpixel was stored before VCOM was coupled, the storage capacitor and liquid crystal capacitor release the charge at this time. After stabilization, the pulled-high VCOM will recover, but the amount of charge in the red subpixel is reduced. Macroscopically speaking, some of the charging power is consumed, which affects the brightness. In the waveform, this corresponds to the instant the green subpixel starts charging. The red subpixel releases the charge and couples VCOM downward. The coupling situation of the subsequent green and blue subpixels can be inferred by analogy. The coupling situation basically matches the charging sequence. In one charging cycle, the five couplings are in the following order: red subpixel, green subpixel, blue subpixel, red subpixel, and green subpixel. That is, the red and green subpixels are coupled twice, and the blue subpixel is coupled once.

[0068] Meanwhile, under the same test conditions, optical measurement equipment was used to record the instantaneous brightness changes of the red, green, and blue sub-pixel regions during common voltage fluctuations, and the ratio of their brightness changes was calculated, for example, based on visual weights R:G:B = 2:7:1. Subsequently, the ratio of sub-pixel coupling times and the ratio of brightness changes were input into an optimization algorithm. The core objective of this algorithm is to find a new charging sequence that makes the ratio of coupling times as negatively correlated with the ratio of brightness changes as possible. That is, to minimize the coupling times of the visually sensitive green sub-pixels, while allocating more coupling times to the visually less sensitive blue or red sub-pixels. Through iterative calculation or searching a pre-defined mapping table, the target charging cycle sequence that meets this optimization objective is finally determined, such as the RBG-GBR sequence, which can be referenced. Figure 8 , Figure 8 In G3n-2, the solid line represents the red sub-pixel row, the dashed line represents the green sub-pixel row, and the dotted-dash line represents the blue sub-pixel row, where n is an integer ≥ 1. In one charging timing cycle, the VCOM is coupled four times in the following order: red sub-pixel, blue sub-pixel, green sub-pixel, and blue sub-pixel again. That is, only the blue sub-pixel is coupled twice, while the red and green sub-pixels are coupled once each.

[0069] Based on the first and / or second embodiments of this application, in the third embodiment of this application, the content that is the same as or similar to that in embodiments one and two above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 9 Step S10 in the pixel charging method may also include steps S11 to S12: Step S11: Monitor the serial output voltage of each data line in the display panel; It should be noted that the serial output voltage is a series of analog voltage signals output sequentially through each data line by the source drive circuit of the display panel. Specifically, in the TRD pixel architecture, each data line applies its required data voltage, corresponding to the displayed grayscale, to the corresponding red, green, and blue sub-pixels in that column at different times in a serial manner. These voltage signals that appear sequentially on the data lines according to a specific charging sequence constitute the serial output voltage. Monitoring this voltage essentially captures the real-time electrical signal changes on the data lines. Its waveform and amplitude directly reflect the grayscale information being written to each sub-pixel, which is the basis for subsequently determining crosstalk areas by analyzing the voltage (or converted grayscale) differences between adjacent data lines.

[0070] Step S12: Determine the crosstalk status based on each serial output voltage.

[0071] It is understandable that if the crosstalk monitoring method is unclear or unreliable, it may lead to inaccurate crosstalk region identification, response delay, or false triggering, thereby affecting the effectiveness and stability of the entire timing adjustment scheme. Therefore, this embodiment directly monitors the serial output voltage of each data line in the display panel, i.e., the data voltage signals sequentially output by the source drive circuit to each sub-pixel, and determines the crosstalk state based on the changes in these voltage signals, thus anchoring the state monitoring to the actual electrical output of the drive circuit. This scheme effectively avoids problems such as environmental interference, high computational complexity, or poor real-time performance that may be introduced by relying on external optical sensors, image processing algorithms, or other indirect means. By utilizing the inherent data line voltage signals of the display panel for real-time analysis, it achieves accurate, low-latency, and high-reliability crosstalk state monitoring, thereby ensuring that subsequent charging timing adjustments are accurately triggered only when real electrical anomalies occur, improving the response accuracy and robustness of the entire crosstalk improvement system.

[0072] For example, each data line of the display panel is connected to a high-speed voltage sampling circuit. This circuit samples the serial output voltage transmitted on the data line in real time at a rate higher than the data line signal update frequency, and converts the continuous analog voltage signal into a corresponding digital voltage sequence. Subsequently, a dedicated logic processing unit receives the digital voltage sequence corresponding to all data lines and calculates the absolute difference of voltage amplitude between adjacent data lines at any given time in real time. When the system detects that the absolute voltage difference between specific adjacent data lines continuously exceeds a preset voltage difference threshold within multiple consecutive scan cycles, it determines that there is a risk of crosstalk due to voltage fluctuations in that area, and thus marks the crosstalk status of the display panel as a crosstalk-affected area.

[0073] In this embodiment, the serial output voltage of each data line in the display panel is directly monitored, and the crosstalk state is determined based on the changes in these voltage signals. This avoids the problems of ambient light interference, computational complexity, response delay, and high false judgment rate that may be introduced by indirect monitoring methods such as optical sensors or image recognition. It achieves real-time, accurate, and direct electrical-level detection of crosstalk state, thereby ensuring that the subsequent charging timing adjustment mechanism is only triggered when there is indeed an abnormal electrical signal (i.e., a voltage change indicates that there may be a screen boundary). This improves the reliability, response speed, and judgment accuracy of the entire crosstalk improvement system.

[0074] In one feasible implementation, step S12 may include steps S121-S122: Step S121: Map each serial output voltage to a corresponding grayscale value, and compare any grayscale value with the grayscale value of the adjacent data line to obtain the comparison result; Step S122: Determine the crosstalk status based on the comparison results.

[0075] It is understandable that, although directly comparing the voltage signals of the serial output voltages can reflect electrical changes, the voltage values ​​themselves do not correspond perfectly linearly with the final displayed visual grayscale, and may be affected by factors such as noise, attenuation, or driving nonlinearity. If the judgment is based solely on the original voltage difference, it may lead to inconsistent crosstalk identification standards, increased false positive rates, or limited adaptability. To address this, this embodiment further maps each serial output voltage to a corresponding grayscale value that better conforms to human visual perception and display standards. Then, it directly compares any grayscale value with the grayscale value of the adjacent data line to obtain the difference result, and determines the crosstalk state accordingly, thereby transforming the state criterion from the underlying electrical signal to the upper-level display semantics. This solution effectively avoids the problems of difficulty in setting judgment thresholds, poor environmental adaptability, and disconnection from actual visual crosstalk that may be caused by the physical fluctuations or non-intuitive nature of voltage signals themselves. By using grayscale values, a standardized measure that is directly related to the content of the image, for difference analysis, it realizes the intuitiveness, normalization, and high robustness of crosstalk state judgment, thereby ensuring that the crosstalk detection results more accurately correspond to the actual visual boundary area and improving the pertinence of subsequent timing adjustments and the effectiveness of display optimization.

[0076] For example, the serial output voltage of each data line on the display panel is first sampled and quantized into a digital voltage value by a high-speed analog-to-digital converter. This digital voltage value is then input into a lookup table pre-stored with a voltage-grayscale correspondence. This lookup table is built based on the panel's gamma curve characteristics, thus accurately mapping the real-time voltage signal of each data line to its corresponding grayscale value. Next, at the end of each row scan cycle, the logic processing unit subtracts the grayscale value of each column from the grayscale values ​​of its left and right adjacent columns, obtaining a series of continuous grayscale differences. These differences are sent to a status judgment unit, which analyzes the distribution pattern of the differences, such as the occurrence of high differences in multiple consecutive columns, to determine whether there are potential crosstalk boundary regions in the image caused by sudden grayscale changes, and outputs the crosstalk status judgment result accordingly.

[0077] In specific implementation, step S122 may include step A122 or step B122: Step A122: If the difference between any grayscale value and the grayscale value of the adjacent data line is less than a preset threshold, the crosstalk state is determined to be that there is no crosstalk area on the display panel. Step B122: If the difference between any grayscale value and the grayscale value of an adjacent data line is greater than or equal to a preset threshold, the crosstalk state is determined to be that there is a crosstalk area on the display panel.

[0078] Understandably, if only the grayscale difference is calculated without clearly defining what level of difference can be considered crosstalk, i.e., without a clear quantification threshold, the judgment result may be too sensitive (misjudging slight grayscale transitions as crosstalk) or too insensitive (missing actual crosstalk), thus making the entire timing adjustment system unstable or malfunctioning. Therefore, this implementation sets a preset grayscale difference threshold and explicitly compares the grayscale difference with this threshold: when the difference is less than the threshold, the display panel is determined to have no crosstalk area; when the difference is greater than or equal to the threshold, a crosstalk area is determined to exist. This provides a clear and unified quantification standard for determining crosstalk status. This solution avoids system malfunctions, reduced reliability, or poor consistency caused by ambiguous judgment boundaries. By introducing an objective threshold, it achieves the digitization, standardization, and stabilization of crosstalk status determination, ensuring that the subsequent charging timing adjustment mechanism is only triggered when truly necessary (i.e., the grayscale transition reaches a visually perceptible level). This improves the system's anti-interference capability while also optimizing the efficiency of system resource utilization.

[0079] For example, a configurable threshold register is preset inside the logic processing unit, where a preset threshold (e.g., a grayscale difference of 80) is stored as an objective standard for determining crosstalk. After the unit completes real-time comparison of the grayscale values ​​of adjacent data lines and obtains a series of absolute values ​​of grayscale differences, these absolute values ​​are input one by one into a digital comparator and compared with the preset threshold read from the threshold register. The comparator outputs a binary logic signal: if the input value is less than the preset threshold, it outputs logic "0", determining that there is no crosstalk in the corresponding area; if the input value is greater than or equal to the preset threshold, it outputs logic "1", determining that there is crosstalk in the corresponding area. Finally, a state decision circuit performs spatial domain aggregation analysis on the decision outputs of all columns. For example, when multiple consecutive columns output logic "1", the crosstalk state of the display panel is globally determined to be either "crosstalk area present" or "crosstalk area absent", and the corresponding subsequent processing flow is triggered.

[0080] For example, to help understand the implementation flow of the pixel charging method obtained by combining Embodiment 1 and Embodiment 2 above, please refer to... Figure 10 , Figure 10 A simplified flowchart of a pixel charging method is provided, specifically: First, the serial output voltage of each data line on the display panel is monitored in real time. Then, these voltage signals are mapped to intuitive grayscale values ​​based on the panel characteristics, and the difference in grayscale values ​​between adjacent data lines is calculated. Simultaneously, the solution also monitors the fluctuation of the common electrode voltage and the brightness changes of red, green, and blue sub-pixels on a sample display panel in advance or in parallel, providing a basis for timing design. Next, it is determined whether the absolute value of the calculated grayscale difference reaches a preset threshold: if it does not, it is determined that there is no obvious crosstalk area in the current image, and the process ends; if it reaches or exceeds the threshold, it is determined that a crosstalk area exists. In the case of a crosstalk area, the currently used charging cycle timing is obtained, such as the conventional RGB-RGB sequence, and then combined with the target charging cycle timing determined by sample analysis, such as the RBG-GBR sequence, to complete targeted adjustments to the charging timing. This reduces the impact of crosstalk on the visual experience by changing the charging order of sub-pixel rows.

[0081] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the pixel charging method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0082] This application also provides a driving circuit, which drives a display panel with a pixel architecture of three times the pixel rate. The driving circuit includes: Gate driving circuit, the gate driving circuit is distributed in the non-display area of ​​the array substrate of the display panel; Multiple gate lines, each gate line being connected to the gate driving circuit and each sub-pixel in a corresponding row of pixel units in the display panel, wherein each row of pixel units includes a red sub-pixel row, a green sub-pixel row, and a blue sub-pixel row arranged sequentially; Multiple data lines, each of which is connected to a corresponding column of sub-pixels in the display panel; The source driver chip is connected to each column of sub-pixels through each data line and is used to charge each column of sub-pixels. A control chip, connected to both the gate drive circuit and the source drive chip, is used to monitor the crosstalk state of the display panel. When the crosstalk state indicates the presence of a crosstalk region on the display panel, the control chip acquires the current charging cycle timing for charging each row of pixel units in the display panel. The control chip then adjusts the current charging cycle timing to a target charging cycle timing. The target charging cycle timing includes a first charging timing and a second charging timing under two alternating charging cycles. For any row of pixel units, the first charging timing is to charge the red sub-pixel row, blue sub-pixel row, and green sub-pixel row in the pixel unit sequentially under the first charging cycle. The second charging timing is to charge the green sub-pixel row, blue sub-pixel row, and red sub-pixel row in the pixel unit sequentially under the second charging cycle.

[0083] It should be noted that the gate driving circuit refers to the circuit integrated into the non-display area of ​​the display panel array substrate, used to replace the traditional independent gate driving chip. This GDL circuit consists of multiple cascaded shift register units and level shifting devices, implemented directly through metal traces and TFTs on the array substrate, without the need for additional independent gate driving chips. Structurally, the GDL circuit connects to the TFT gates of each sub-pixel in the corresponding row pixel unit through each gate line, receiving gate clock signals, start pulses, output enable signals, and / or control signals from the control chip, and accordingly generating high-level gate turn-on voltages to sequentially turn on the sub-pixels row by row to receive data voltages. Compared to traditional solutions, the GDL circuit not only reduces material costs and bonding process complexity, but also allows for flexible adjustment of the gate line turn-on sequence according to different gate clock sequences issued by the control chip, providing a hardware foundation for achieving the target charging cycle timing of this embodiment under the TRD pixel architecture.

[0084] The control chip in the driving circuit provided in this application is used to execute the pixel charging method in the above embodiments, which can solve the technical problem of significant crosstalk in the current TRD pixel architecture. Compared with the prior art, the beneficial effects of the driving circuit provided in this application are the same as those of the pixel charging method provided in the above embodiments, and other technical features in the driving circuit are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0085] This application provides a display device, which includes a display panel and a driving circuit as described in the above embodiments, wherein the display panel is electrically connected to the driving circuit. The display device further includes: a memory, a processor, and a pixel charging program stored in the memory and executable on the processor, wherein the pixel charging program, when executed by the processor, implements the steps of the pixel charging method as described in any one of claims 1 to 8.

[0086] The display device provided in this application, employing the pixel charging method in the above embodiments, can solve the technical problem of significant crosstalk in the current TRD pixel architecture. Compared with the prior art, the beneficial effects of the display device provided in this application are the same as those of the pixel charging method provided in the above embodiments, and other technical features in this display device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0087] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0089] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the pixel charging method in the above embodiments.

[0090] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0091] The aforementioned computer-readable storage medium may be included in the display device; or it may exist independently and not assembled into the display device.

[0092] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by the display device, the display device causes the display device to: monitor the crosstalk state of the display panel, wherein the pixel architecture of the display panel is a three-times-rate-driven pixel architecture; when the crosstalk state is that there is a crosstalk area on the display panel, acquire the current charging cycle timing for charging each row of pixel units in the display panel, wherein any row of pixel units includes a red sub-pixel row, a green sub-pixel row, and a blue sub-pixel row arranged sequentially; adjust the current charging cycle timing to a target charging cycle timing, wherein the target charging cycle timing includes a first charging timing and a second charging timing under two alternating charging cycles, wherein for any row of pixel units, the first charging timing is to charge the red sub-pixel row, blue sub-pixel row, and green sub-pixel row in the pixel unit sequentially in the first charging cycle, and the second charging timing is to charge the green sub-pixel row, blue sub-pixel row, and red sub-pixel row in the pixel unit sequentially in the second charging cycle.

[0093] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0094] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0095] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0096] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described pixel charging method, which can solve the technical problem of significant crosstalk in the current TRD pixel architecture. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the pixel charging method provided in the above embodiments, and will not be repeated here.

[0097] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A pixel charging method characterized by, The pixel charging method includes: Monitor the crosstalk status of the display panel, wherein the pixel architecture of the display panel is a three-times-rate-driven pixel architecture; When the crosstalk state is that there is a crosstalk area in the display panel, the current charging cycle timing for charging each row of pixel units in the display panel is obtained, wherein any row of pixel units includes a red sub-pixel row, a green sub-pixel row and a blue sub-pixel row arranged in sequence; The current charging cycle timing is adjusted to the target charging cycle timing, wherein the target charging cycle timing includes a first charging timing and a second charging timing under two alternating charging rounds. For any row of pixel units, the first charging timing is to charge the red sub-pixel row, blue sub-pixel row and green sub-pixel row in the pixel unit in sequence during the first charging round, and the second charging timing is to charge the green sub-pixel row, blue sub-pixel row and red sub-pixel row in the pixel unit in sequence during the second charging round.

2. The pixel charging method according to claim 1, wherein The step of adjusting the current charging cycle timing to the target charging cycle timing includes: Obtain the preset target charging cycle timing and determine the target control signal based on the target charging cycle timing; The current control signal output to the gate line corresponding to each sub-pixel in each row of pixel units is adjusted to output the target control signal to each gate line. The current control signal is used to control the charging of each sub-pixel according to the current charging cycle timing, and the target control signal is used to control the charging of each sub-pixel according to the target charging cycle timing.

3. The pixel charging method as described in claim 2, characterized in that, The step of adjusting the current control signal output to the gate line corresponding to each sub-pixel in each row of the pixel unit to output the target control signal to each gate line includes: The current control signal output to the gate line corresponding to each sub-pixel in each row of pixel units in the crosstalk region is adjusted to output the target control signal to each gate line. The crosstalk region is a pixel region where the first gray level value corresponding to the boundary data line is less than the second gray level value corresponding to the adjacent data line, and the difference between the first gray level value and the second gray level value is greater than a preset threshold.

4. The pixel charging method as described in claim 1, characterized in that, The pixel charging method further includes: Monitor the common voltage fluctuation status of the sample display panel; Monitor the brightness changes of red, green, and blue sub-pixels in the three primary color pixel sample areas of the sample display panel; The target charging cycle sequence is determined based on the common voltage fluctuation and the brightness change.

5. The pixel charging method as described in claim 4, characterized in that, The brightness change status includes a brightness change degree ratio, and the step of determining the target charging cycle sequence based on the common voltage fluctuation status and the brightness change status includes: Based on the common voltage fluctuation condition and the standard charging cycle sequence of the sample display panel, determine the sub-pixel coupling frequency ratio corresponding to the common voltage fluctuation condition within the cycle period corresponding to the standard charging cycle sequence, wherein the sub-pixel coupling frequency ratio represents the ratio between the red sub-pixel coupling frequency, the green sub-pixel coupling frequency and the blue sub-pixel coupling frequency; The target charging cycle timing is determined based on the ratio of sub-pixel coupling times and the ratio of brightness change.

6. The pixel charging method as described in claim 1, characterized in that, The steps for monitoring the crosstalk status of the display panel include: Monitor the serial output voltage of each data line in the display panel; The crosstalk state is determined based on each of the serial output voltages.

7. The pixel charging method as described in claim 6, characterized in that, The step of determining the crosstalk state based on each of the serial output voltages includes: Each of the serial output voltages is mapped to a corresponding grayscale value, and any grayscale value is compared with the grayscale value of the adjacent data line to obtain the comparison result; The crosstalk state is determined based on the comparison results.

8. The pixel charging method as described in claim 7, characterized in that, The step of determining the crosstalk state based on the comparison result includes: If the difference between any grayscale value and the grayscale value of an adjacent data line is less than a preset threshold, the crosstalk state is determined to be that there is no crosstalk area on the display panel. If the difference between any grayscale value and the grayscale value of an adjacent data line is greater than or equal to a preset threshold, the crosstalk state is determined to be that there is a crosstalk area in the display panel.

9. A driving circuit, characterized in that, The driving circuit is used to drive a display panel with a pixel architecture that is a 3x speed-up pixel architecture. The driving circuit includes: A gate driving circuit, wherein the gate driving circuit is distributed in the non-display area of ​​the array substrate of the display panel; Multiple gate lines, each of which is connected to the gate driving circuit and each sub-pixel in a corresponding row of pixel units in the display panel, wherein each row of pixel units includes a red sub-pixel row, a green sub-pixel row and a blue sub-pixel row arranged sequentially; Multiple data lines, any one of which is connected to a corresponding column of sub-pixels in the display panel; A source driver chip, wherein the source driver chip is connected to each column of sub-pixels through each of the data lines, and is used to charge each column of sub-pixels; A control chip, connected to both the gate driving circuit and the source driving chip, is used to monitor the crosstalk state of the display panel. When the crosstalk state indicates the presence of a crosstalk region on the display panel, the control chip acquires the current charging cycle timing for charging each row of pixel units in the display panel. The control chip then adjusts the current charging cycle timing to a target charging cycle timing, wherein the target charging cycle timing includes a first charging sequence and a second charging sequence under two alternating charging cycles. For any row of pixel units, the first charging sequence involves sequentially charging the red sub-pixel row, blue sub-pixel row, and green sub-pixel row in the pixel unit during the first charging cycle, and the second charging sequence involves sequentially charging the green sub-pixel row, blue sub-pixel row, and red sub-pixel row in the pixel unit during the second charging cycle.

10. A display device, characterized in that, The display device includes a display panel and a driving circuit as described in claim 9, wherein the display panel is electrically connected to the driving circuit. The display device further includes: a memory, a processor, and a pixel charging program stored in the memory and executable on the processor, wherein the pixel charging program, when executed by the processor, implements the steps of the pixel charging method as described in any one of claims 1 to 8.

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