Techniques for increasing dram capacity using generic dram dies

Abstract

Various embodiments include a memory device that can be configured to have either a wide data bus interface or a narrow data bus interface. A wide data bus interface is suitable for low-cost applications such as smartphones and laptops. A narrow data bus interface is suitable for applications requiring high storage density, such as data servers in data centers. The width of the wide data bus is twice the width of the narrow data bus. In a narrow data bus configuration, the memory device transmits twice the number of data words in a single burst transfer compared to a wide data bus configuration. Therefore, regardless of the configuration, the number of bits transmitted in a single burst transfer is the same, thereby simplifying the control logic of the memory device. The memory device can further be adapted to various packaging options to facilitate high-density storage designs.

Description

[0001] Cross-reference to related applications This application claims priority to U.S. co-pending patent application No. 19 / 306,821, filed August 21, 2025, entitled “TECHNIQUESFOR INCREASING CAPACITY OF DRAM USING A COMMON DRAM DIE,” which claims priority to U.S. provisional patent application No. 63 / 699,693, filed September 26, 2024, entitled “TECHNIQUES FOR INCREASING CAPACITY OF DRAM USING A COMMON DRAM DIE.” The subject matter of the relevant applications is incorporated herein by reference. Technical Field

[0002] Various embodiments generally relate to computer memory devices, and more specifically, to techniques for increasing DRAM capacity using general-purpose DRAM dies. Background Technology

[0003] Computer systems typically include, among other things, one or more processing units, such as a central processing unit (CPU) and / or a graphics processing unit (GPU), and one or more memory systems. One type of memory system is called system memory, which is accessible to both one or more CPUs and one or more GPUs. Another type of memory system is graphics memory, which is typically accessible to only one or more GPUs. These memory systems include multiple memory devices. An exemplary memory device used in system memory and / or graphics memory is synchronous dynamic random access memory (SDRAM, or more simply DRAM).

[0004] DRAM devices can be configured in various ways depending on the application. For example, a DRAM device can be configured to have a wider data bus width, such as 16 data bits, 12 data bits, or 8 data bits. With a wider data bus width, a given total data bus width can be achieved with fewer memory devices. For example, a total data bus width of 48 bits using the aforementioned memory devices can be achieved with 3, 4, or 6 memory devices, respectively. By keeping the total number of memory devices small, DRAM devices with wider data bus widths are suitable for applications where cost is critical, such as smartphones, tablets, laptops, and / or similar applications.

[0005] Alternatively, DRAM devices can be configured with a narrower data bus width, for example, half the width of the aforementioned DRAM devices. Such memory devices can have data bus widths of 8 data bits, 6 data bits, or 4 data bits, respectively. To achieve a total data bus width of 48 bits using these memory devices with narrower data bus widths, 6, 8, or 12 memory devices would be required, respectively. Therefore, these memory devices are less suitable for applications where low cost is critical. However, for applications requiring high memory density, such as storage servers for data centers, media servers for video streaming, and / or similar applications, using DRAM devices with narrower data bus widths is advantageous. DRAM devices for such applications are typically packaged in multi-die packages, such that a single package includes multiple DRAM dies.

[0006] In addition to having different data bus widths, DRAM devices configured for different applications can also have different channel interfaces, different data access modes, different timing requirements, and / or the like. Therefore, conventional DRAM devices have different internal dies, each with different control logic for managing the operation of the DRAM device. One drawback of this approach of using different dies for different DRAM devices is the increased manufacturing complexity due to the need to design and manufacture many different types of DRAM device dies for different applications. Furthermore, the complexity of inventory management increases with the number of different dies used for different DRAM devices. For example, if a manufacturer manufactures an excess of one type of DRAM memory die while having an insufficient quantity of another type, the manufacturer may have an excess of laptop memory devices in stock if demand for laptop applications decreases. Conversely, if demand for data server applications increases, the manufacturer may have an insufficient inventory of data server memory devices.

[0007] One possible solution to this problem is to manufacture DRAM devices capable of adapting to all the aforementioned applications. Such DRAM devices would need to include a superset of the internal control logic found in various conventional DRAM devices, allowing them to accommodate different data prefetch sizes, channel interfaces, data access modes, and / or similar configurations from multiple conventional DRAM devices. For example, a conventional DRAM device with a 12-bit data bus width can prefetch 256 data bits from the DRAM memory core at a time, while a conventional DRAM device with a 6-bit data bus width can prefetch 128 data bits at a time. DRAM devices replacing these two conventional DRAM devices would need control logic capable of prefetching either 256 or 128 data bits at a time, depending on the DRAM device configuration. However, such control logic can be extremely complex, increasing the complexity, die area, and cost of DRAM devices deployed in applications that do not require such complex control logic. Furthermore, such complex control logic may not meet the constraints of different industry standards for DRAM devices. Therefore, DRAM devices designed in this way may not be compatible with one or more industry standard interfaces, and thus may not be compatible for certain applications.

[0008] As explained above, there is a need in the art for more efficient technologies to manufacture DRAM devices for various applications. Summary of the Invention

[0009] Various embodiments of this disclosure illustrate a memory device. The memory device includes a first memory die. The first memory die includes a first memory core, a first prefetch buffer coupled to the first memory core and configured to store data for at least a portion of the first memory core, and a first data bus interface coupled to the first prefetch buffer and configured to have one of a first bit width or a second bit width. When configured to have the first bit width, the first data bus interface transmits data between the first prefetch buffer and an external device in the form of data transmission bursts having a first burst length. When configured to have the second bit width, the first data bus interface transmits data between the first prefetch buffer and the external device in the form of data transmission bursts having a second burst length different from the first burst length.

[0010] Other embodiments include, but are not limited to: systems that implement one or more aspects of the disclosed technology, one or more computer-readable media including instructions for performing one or more aspects of the disclosed technology, and methods for performing one or more aspects of the disclosed technology.

[0011] Compared to existing technologies, at least one technical advantage of the disclosed technology is that, using the disclosed technology, a general-purpose die can be configured to have either a wide data bus width or a narrow data bus width, where the narrow data bus width is half the width of the wide data bus width. Furthermore, by doubling the data burst length when the data bus width is halved, the same internal prefetch size can be maintained. In contrast, conventional methods maintain the same burst length when the data bus width is halved, resulting in a 50% reduction in channel efficiency. Furthermore, the packaging of this general-purpose die can include additional read data strobe signals, write clocks, and data bus pin assignment options, making the resulting package easier to vertically stack and enabling even higher memory densities at the system level. Using these technologies, a single general-purpose DRAM die can be configured and packaged to accommodate different data bus widths for different applications without significantly increasing channel logic complexity or die surface area. These advantages represent one or more technical improvements over existing methods. Attached Figure Description

[0012] To gain a detailed understanding of the features described in the various embodiments above, a more specific description of the inventive concept briefly outlined above can be obtained by referring to the various embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of the inventive concept and should not be considered as limiting the scope in any way, and other equally effective embodiments exist.

[0013] Figure 1 It is a block diagram of a computer system configured to implement one or more aspects of various embodiments; Figure 2A-2B Block diagrams illustrating different configurations of a DRAM device, according to various embodiments, are shown. The DRAM device is included in... Figure 1 The system memory and / or parallel processing memory of the computer system; Figure 3 According to various embodiments, the use of Figure 2A System configuration of DRAM devices; Figure 4 According to various embodiments, the use of Figure 2B System configuration of DRAM devices; Figure 5 According to various embodiments, it is shown how DRAM dies can be vertically stacked in a multi-die DRAM package; Figure 6 According to various embodiments, a format for data transmission in a DRAM device with a burst length of 48 bits is shown; Figure 7Timing diagrams optimized for the command bus of DRAM devices supporting 48-bit burst lengths are shown according to various embodiments. Figure 8 Timing diagrams for chip select training of a DRAM device with a 6-bit data bus width are shown according to various embodiments; and Figure 9 The following is a timing diagram illustrating command bus training for a DRAM device with a 6-bit data bus width, according to various embodiments. Detailed Implementation

[0014] In the following description, numerous specific details are set forth to provide a more thorough understanding of the various embodiments. However, it will be apparent to those skilled in the art that the inventive concept can be practiced without one or more of these specific details.

[0015] System Overview Figure 1 This is a block diagram of a computer system 100 configured to implement one or more aspects of various embodiments. As shown, the computer system 100 includes, but is not limited to, a central processing unit (CPU) 102 and system memory 104, which are coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. The memory bridge 105 is coupled to the system memory 104 via a system memory controller 130. The memory bridge 105 is further coupled to an I / O (input / output) bridge 107 via a communication path 106, and the I / O bridge 107 is coupled to a switch 116. The parallel processing subsystem 112 is coupled to a parallel processing memory 134 via a parallel processing subsystem (PPS) memory controller 132.

[0016] In operation, I / O bridge 107 is configured to receive user input from input device 108, such as a keyboard or mouse, and forward that input to CPU 102 for processing via communication path 106 and memory bridge 105. Switch 116 is configured to provide connectivity between I / O bridge 107 and other components of computer system 100, such as network adapter 118 and various add-on cards 120 and 121.

[0017] As also shown in the figure, I / O bridge 107 is coupled to system disk 114, which can be configured to store content, applications, and data used by CPU 102 and parallel processing subsystem 112. Generally, system disk 114 provides non-volatile storage for applications and data and may include fixed or removable hard disk drives, flash memory devices, and CD-ROMs (CD-ROMs), DVD-ROMs (Digital Multifunction Optical Disc ROMs), Blu-ray, HD-DVD (High Definition DVD), or other magnetic, optical, or solid-state storage devices. Finally, although not explicitly shown, other components, such as universal serial buses or other port connections, optical disc drives, digital multifunction optical disc drives, film recording devices, etc., may also be connected to I / O bridge 107.

[0018] In various embodiments, memory bridge 105 may be a northbridge chip, and I / O bridge 107 may be a southbridge chip. Furthermore, communication paths 106 and 113, as well as other communication paths within computer system 100, may be implemented using any technically suitable protocol, including but not limited to AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0019] In some embodiments, the parallel processing subsystem 112 includes a graphics subsystem that provides pixels to a display device 110, which may be any conventional cathode ray tube, liquid crystal display, light-emitting diode display, and / or similar device. In such embodiments, the parallel processing subsystem 112 incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry. Such circuitry may be combined across one or more parallel processing units (PPUs) contained within the parallel processing subsystem 112. In some embodiments, each PPU includes a graphics processing unit (GPU) that may be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data supplied by the CPU 102 and / or system memory 104. Each PPU may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or memory devices, or in any other technically feasible manner.

[0020] In some embodiments, the parallel processing subsystem 112 incorporates circuitry optimized for general and / or computational processing. Similarly, such circuitry may be combined across one or more PPUs contained within the parallel processing subsystem 112, which are configured to perform such general and / or computational operations. In yet another embodiment, one or more PPUs contained within the parallel processing subsystem 112 may be configured to perform graphics processing, general processing, and computational processing operations. The system memory 104 includes at least one device driver 103 configured to manage the processing operations of one or more PPUs within the parallel processing subsystem 112.

[0021] In various embodiments, the parallel processing subsystem 112 can be coupled with... Figure 1 One or more other components can be integrated to form a single system. For example, the parallel processing subsystem 112 can be integrated with the CPU 102 and other interconnect circuitry on a single chip to form a system-on-a-chip (SoC).

[0022] In operation, CPU 102 is the main processor of computer system 100, controlling and coordinating the operation of other system components. Specifically, CPU 102 issues commands to control the operation of the PPU within parallel processing subsystem 112. In some embodiments, CPU 102 writes the command stream for the PPU within parallel processing subsystem 112 into a data structure (…). Figure 1 (Not explicitly shown), the data structure may reside in system memory 104, PP memory 134, or another storage location accessible to both CPU 102 and PPU. A pointer to the data structure is written to the push buffer to initiate processing of the command stream within the data structure. The PPU reads the command stream from the push buffer and then executes the commands asynchronously relative to the operation of CPU 102. In embodiments that generate multiple push buffers, the application can control the scheduling of different push buffers by specifying an execution priority for each push buffer through device driver 103.

[0023] Each PPU includes an I / O (input / output) unit that communicates with the rest of the computer system 100 via communication path 113 and memory bridge 105. The I / O unit generates packets (or other signals) for transmission on communication path 113 and also receives all incoming packets (or other signals) from communication path 113, directing the incoming packets to appropriate components of the PPU. The connection between the PPU and the rest of the computer system 100 can vary. In some embodiments, the parallel processing subsystem 112, including at least one PPU, is implemented as an add-in card that can be inserted into an expansion slot of the computer system 100. In other embodiments, the PPU may be integrated on a single chip using a bus bridge (e.g., memory bridge 105 or I / O bridge 107). Similarly, in other embodiments, some or all of the components of the PPU may be included together with the CPU 102 in a single integrated circuit or system-on-a-chip (SoC).

[0024] The CPU 102 and the PPU within the parallel processing subsystem 112 access the system memory via the system memory controller 130. The system memory controller 130 signals memory devices included in the system memory 104 to initiate memory devices, send commands to memory devices, write data to memory devices, read data from memory devices, and / or perform similar operations. An exemplary memory device used in the system memory 104 is Double Data Rate SDRAM (DDR SDRAM, or more simply DDR). DDR memory devices perform memory write and read operations at twice the data rate of the previous generation of Single Data Rate (SDR) memory devices.

[0025] Furthermore, the PPU and / or other components within the parallel processing subsystem 112 access the PP memory 134 via the parallel processing subsystem (PPS) memory controller 132. The PPS memory controller 132 signals memory devices included in the PP memory 134 to initiate memory devices, send commands to memory devices, write data to memory devices, read data from memory devices, and / or perform similar operations. An exemplary memory device used in the PP memory 134 is Synchronous Graphics Random Access Memory (SGRAM), a specialized form of SDRAM used for computer graphics applications. A particular type of SGRAM is Graphics Double Data Rate SGRAM (GDDR SDRAM, or more simply GDDR). Compared to DDR memory devices, GDDR memory devices are configured with a wider data bus to transfer more data bits in each memory write and read operation. By employing double data rate technology and a wider data bus, GDDR memory devices enable the high data transfer rates typically required by PPUs.

[0026] It should be understood that the system illustrated herein is illustrative and is subject to variation and modification. The connection topology, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112, can be modified as needed. For example, in some embodiments, system memory 104 may be directly connected to CPU 102 instead of via memory bridge 105, and other devices will communicate with system memory 104 via memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystems 112 may be connected to I / O bridge 107 or directly to CPU 102 instead of via memory bridge 105. In still other embodiments, I / O bridge 107 and memory bridge 105 may be integrated into a single chip rather than existing as one or more discrete devices. Finally, in some embodiments, Figure 1 One or more of the components shown may be absent. For example, switch 116 can be omitted, and network adapter 118 and add-on cards 120, 121 can be directly connected to I / O bridge 107.

[0027] It should be understood that the core architecture described herein is illustrative and subject to change and modification. Among other things, within the scope of the disclosed embodiments, Figure 1 The computer system 100 may include any number of CPUs 102, parallel processing subsystems 112, or memory systems, such as system memory 104 and parallel processing memory 134. Furthermore, as used herein, references to shared memory may include any technically feasible type of memory, including but not limited to local memory shared by one or more PPUs within a parallel processing subsystem 112, memory shared among multiple parallel processing subsystems 112, cache memory, parallel processing memory 134, and / or system memory 104. It should also be noted that, as used herein, references to cache memory may include any technically feasible type of memory, including but not limited to L1 cache, L1.5 cache, and L2 cache. In view of the foregoing, those skilled in the art will understand that... Figure 1 The architecture described herein does not limit the scope of the various embodiments of this disclosure.

[0028] Increase DRAM capacity using general-purpose DRAM dies Various embodiments include an improved DRAM device with a general-purpose memory die that can be configured to have different data bus widths for different applications. The memory device can be configured to have a wide data bus width and a specified data burst length. Alternatively, the memory device can be configured to have a narrow data bus width half the wide data bus width and a data burst length twice the specified data burst length. By doubling the burst length when the data bus width is halved, both configurations of the memory device can maintain the same internal prefetch size. In some examples, the prefetch size of the memory device can be 288 bits. With this prefetch size, the memory device can be configured to have a 12-bit data bus width and a 24-bit burst length, or to have a 6-bit data bus width and a 48-bit burst length. Maintaining the same internal prefetch size for both configurations simplifies the channel control logic for the memory die.

[0029] Furthermore, a general-purpose die can be packaged in different configurations. For example, a package for a general-purpose memory die includes multiple read data strobe and write clock pins, allowing the read data strobe inputs and write clock inputs of the memory die to be routed to different pins of the memory device package. Similarly, a general-purpose memory die may include an internal data bus that allows, for example, all 12 bits to be routed to pins of the memory device package, or only 6 bits out of the 12 bits to pins of the memory device package. In this latter configuration, the memory die includes a mode through which the six most significant data pins or the six least significant data pins of the 12-bit data bus can be selected to route to pins of the memory device package.

[0030] These packaging options allow more memory devices to be placed on a single memory rank, effectively doubling memory capacity without increasing the surface area of ​​the memory device package. Therefore, higher memory capacity can be achieved without increasing the package surface area, providing additional memory capacity for applications requiring large amounts of memory, such as data servers in data centers.

[0031] Figure 2A-2B Block diagrams illustrating different configurations of DRAM devices 210 and 260, according to various embodiments, are shown. These DRAM devices 210 and 260 are included in... Figure 1 The system memory 104 and / or parallel processing memory 134 of the computer system 100. For example... Figure 2AAs shown, the first configuration of DRAM device 210 includes, but is not limited to, two sub-channels, namely sub-channel 0 220(0) and sub-channel 1 220(1). DRAM device 210 further includes, but is not limited to, a 12-bit data bus (X12 DQ bus) 230 and a command (CA) bus 240.

[0032] During operation, data is stored in and retrieved from the memory core (not shown) of DRAM device 210. DRAM device 210 receives commands via CA bus 240, such as commands to perform read operations, write operations, prefetch operations, and / or similar operations.

[0033] DRAM device 210, in response to receiving a write operation via CA bus 240, stores data in the memory core. DRAM device 210, in response to receiving a read operation via CA bus 240, retrieves data from the memory core. To reduce the number of individual write and read operations routed to the memory core, DRAM device 210 accesses data in the memory core via prefetch operations. More specifically, DRAM device 210 can retrieve several data words from the memory core via prefetch operations and store these data words in an internal prefetch buffer. Similarly, DRAM device 210 can store several data words from the internal prefetch buffer into the memory core. In some embodiments, the prefetch buffer stores 288 bits, including 256 data bits and 32 parameter bits. DRAM device 210 transfers data between the prefetch buffer and an external device in bursts, where a burst is a series of consecutive data transfers, and the width of each data transfer is the width of the data bus, i.e., 12 bits. The consecutive data transfers are performed within consecutive clock cycles, and each data transfer in a burst includes a data field referred to as a peck. Therefore, in order to transmit 288 bits between the prefetch buffer and the external device, the DRAM device 210 performs a burst of 24 beats, with 12 bits per beat.

[0034] In summary, subchannel 0 220(0) and subchannel 1 220(1) provide a 12-bit interface for the data in the prefetch buffer via the X12 DQ bus 230. For example... Figure 2AAs shown, subchannel 0 220(0) and subchannel 1 220(1) can provide a 12-bit interface via a single 12-bit channel through the X12 DQ bus 230. For example, DRAM device 210 can be configured with two subchannels, subchannel 0 220(0) and subchannel 1 220(1), which are configured as a single 12-bit channel with a burst length of 24 beats. Successive data access operations, such as read or write operations, can be routed to the same subchannel. Alternatively or additionally, successive data access operations can alternate between subchannel 0 220(0) and subchannel 1 220(1). Alternatively or additionally, subchannel 0 220(0) and subchannel 1 220(1) can each be routed via a separate subchannel ( Figure 2A (Not shown in the image) provides a 12-bit interface.

[0035] During a read operation, DRAM device 210 transmits 288 bits of the prefetch buffer in data packets via X12 DQ bus 230. DRAM device 210 transmits these data packets in 24-buzz bursts, with each burst containing a 12-bit data field. Similarly, during a write operation, DRAM device 210 stores received data in 288 bits of the prefetch buffer in data packets via X12 DQ bus 230. DRAM device 210 receives these data packets in 24-buzz bursts, with each burst containing a 12-bit data field.

[0036] In addition, DRAM device 210 may include other signals (not shown) to facilitate various operations of DRAM device 210. In this regard, DRAM device 210 may include one or more chip select (CS) signals that are switched to enable or disable the DRAM device. DRAM device 210 may include one or more write clock (WCK) signals that synchronize data transmitted to DRAM device 210. DRAM device 210 may further include one or more read clock (RCK) signals that synchronize data retrieved from DRAM device 210. DRAM device 210 may further include one or more data strobe (DS) signals that are switched when data presented on X12 DQ bus 230 is valid, such as data to be stored in DRAM device 210 during a write operation, data to be retrieved from DRAM device 210 during a read operation, and / or similar data.

[0037] Configuring the DRAM device 210 with a 12-bit data bus, such as the X12 DQ bus 230, is advantageous for applications where a wider data bus width is suitable. A wider data bus width may be appropriate where low cost is critical, such as in smartphones, tablets, laptops, and / or similar applications.

[0038] like Figure 2B As shown, the second configuration of DRAM device 260 includes, but is not limited to, two sub-channels, namely sub-channel 0 270(0) and sub-channel 1 270(1). DRAM device 260 further includes, but is not limited to, a 6-bit data bus (X6 DQ bus) 280 and a command (CA) bus 290.

[0039] During operation, data is stored in and retrieved from the memory core (not shown) of the DRAM device 260. The DRAM device 260 receives commands via the CA bus 290, such as commands to perform read operations, write operations, prefetch operations, and / or similar operations.

[0040] DRAM device 260, in response to receiving a write operation via CA bus 290, stores data in the memory core. DRAM device 260, in response to receiving a read operation via CA bus 290, retrieves data from the memory core. To reduce the number of individual write and read operations routed to the memory core, DRAM device 260 accesses data in the memory core via prefetch operations. More specifically, DRAM device 260 can retrieve several data words from the memory core via prefetch operations and store these data words in an internal prefetch buffer. Similarly, DRAM device 260 can store several data words from the internal prefetch buffer into the memory core. In some embodiments, the prefetch buffer stores 288 bits, including 256 data bits and 32 parameter bits. DRAM device 260 transfers data between the prefetch buffer and an external device in bursts, where a burst is a series of consecutive data transfers, and the width of each data transfer is the width of the data bus, i.e., 6 bits. The consecutive data transfers are performed within consecutive clock cycles, and each data transfer in a burst includes a data field called a peck. Therefore, in order to transmit 288 bits between the prefetch buffer and the external device, the DRAM device 210 performs a burst with a burst length of 48 beats, with 6 bits per beat.

[0041] In summary, subchannel 0 270(0) and subchannel 1 270(1) provide a 6-bit interface for the data in the prefetch buffer via the X6 DQ bus 280. For example... Figure 2BAs shown, subchannel 0 270(0) and subchannel 1 270(1) can provide a 6-bit interface via a single 6-bit channel through the X6 DQ bus 280. For example, DRAM device 260 can be configured with two subchannels, subchannel 0 270(0) and subchannel 1 270(1), which are configured as a single 6-bit channel with a burst length of 48 bits. Successive data access operations, such as read or write operations, can be directed to the same subchannel. Alternatively or additionally, successive data access operations can alternate between subchannel 0 270(0) and subchannel 1 270(1). Alternatively or additionally, subchannel 0 270(0) and subchannel 1 270(1) can each be accessed via a separate subchannel ( Figure 2B (Not shown in the image) provides a 6-bit interface.

[0042] During a read operation, DRAM device 260 transmits 288 bits of the prefetch buffer in data packets via X6 DQ bus 280. DRAM device 260 transmits these data packets in 48-buzz bursts, with each burst containing a 6-bit data field. Similarly, during a write operation, DRAM device 260 stores received data in 288 bits of the prefetch buffer in data packets via X6 DQ bus 280. DRAM device 260 receives these data packets in 48-buzz bursts, with each burst containing a 6-bit data field.

[0043] In addition, DRAM device 260 may include other signals (not shown) to facilitate various operations of DRAM device 260. In this regard, DRAM device 260 may include one or more chip select (CS) signals that are switched to enable or disable the DRAM device. DRAM device 260 may include one or more write clock (WCK) signals that synchronize data transmitted to DRAM device 260. DRAM device 260 may further include one or more read clock (RCK) signals that synchronize data retrieved from DRAM device 260. DRAM device 260 may further include one or more data strobe (DS) signals that are switched when data presented on X6 DQ bus 280 is valid, such as data to be stored in DRAM device 260 during a write operation, data to be retrieved from DRAM device 260 during a read operation, and / or similar data.

[0044] Configuring the DRAM device 260 with a 6-bit data bus, such as the X6 DQ bus 280, is advantageous for applications where a narrower data bus width is suitable. A narrower data bus width may be appropriate where high memory density is critical, such as for data storage servers in data centers, media servers for video streaming, and / or similar applications.

[0045] Using a single general-purpose die, the DRAM device can be configured as a DRAM device 210 with a 12-bit interface and a 24-bit burst length, or as a DRAM device 260 with a 6-bit interface and a 48-bit burst length. This configuration can be selected during packaging via hardware mechanisms, such as through one or more configuration fuses, wires, signal traces, and / or other hardwired components on the surface of the DRAM device's memory die. Additionally or alternatively, the configuration can be selected at runtime via software mechanisms, such as through one or more programmable register bits included in the DRAM device's memory die. Figure 2A As shown, DRAM device 210 can be packaged as a single memory die in a single-die DRAM package. Additionally or alternatively, multiple DRAM devices 210 can be packaged together as multiple dies in a multi-die DRAM package. Similarly, as... Figure 2B As shown, DRAM device 260 can be packaged as a single memory die in a single-die DRAM package. Alternatively or additionally, multiple DRAM devices 260 can be packaged together as multiple dies in a multi-die DRAM package. Whether it is DRAM device 210 or DRAM device 260, the number of memory dies in the multi-die DRAM package can be 1 memory die, 2 memory dies, 4 memory dies, 8 memory dies, 16 memory dies, and / or a similar number of memory dies. These memory dies can be arranged horizontally and / or stacked vertically within the multi-die DRAM package.

[0046] Figure 3 According to various embodiments, the use of Figure 2A The system configuration of the DRAM device 210. For example... Figure 3 As shown, the system configuration includes, but is not limited to, a multi-die DRAM package 300, which further includes DRAM device 310 and DRAM device 360. Each of DRAM device 310 and DRAM device 360 ​​is configured to... Figure 2A The same memory die as the DRAM device 210.

[0047] DRAM device 310 includes, but is not limited to, two sub-channels, namely sub-channel 0 320(0) and sub-channel 1 320(1). DRAM device 310 further includes, but is not limited to, a 12-bit data bus (X12 DQ bus) 330 and a command (CA) bus 340. The functions of sub-channel 0 320(0), sub-channel 1 320(1), X12 DQ bus 330 and CA bus 340 are substantially combined as follows Figure 2A As stated above.

[0048] DRAM device 360 ​​includes, but is not limited to, two sub-channels, namely sub-channel 0 370(0) and sub-channel 1 370(1). DRAM device 360 ​​further includes, but is not limited to, a 12-bit data bus (X12 DQ bus) 380 and a command (CA) bus 390. The functions of sub-channel 0 370(0), sub-channel 1 370(1), X12 DQ bus 380, and CA bus 390 are essentially the same as combined Figure 2A As stated above.

[0049] In summary, DRAM devices 310 and 360 can provide 24-bit interfaces via X12 DQ buses 330 and 380 respectively, with a burst length of 24 cycles. Successive data access operations, such as read or write operations, can be routed to the same subchannel. Alternatively or additionally, successive data access operations can alternate between subchannel 0 and subchannel 1 of DRAM devices 310 and 360 respectively.

[0050] Figure 4 According to various embodiments, the use of Figure 2B The system configuration of the DRAM device 260. For example... Figure 4 As shown, the system configuration includes, but is not limited to, a multi-die DRAM package 400, which further includes DRAM device 410 and DRAM device 460. Each of DRAM device 410 and DRAM device 460 is configured to... Figure 2B The DRAM device 260 has the same memory die.

[0051] DRAM device 410 includes, but is not limited to, two sub-channels, namely sub-channel 0 420(0) and sub-channel 1 420(1). DRAM device 410 further includes, but is not limited to, a 6-bit data bus (X6 DQ bus) 430 and a command (CA) bus 440. The functions of sub-channel 0 420(0), sub-channel 1 420(1), X6 DQ bus 430 and CA bus 440 are substantially combined as follows Figure 2B As stated above.

[0052] DRAM device 460 includes, but is not limited to, two sub-channels, namely sub-channel 0 470(0) and sub-channel 1 470(1). DRAM device 460 further includes, but is not limited to, a 6-bit data bus (X6 DQ bus) 480 and a command (CA) bus 490. The functions of sub-channel 0 470(0), sub-channel 1 470(1), X6 DQ bus 480, and CA bus 490 are essentially the same as combined. Figure 2B As stated above.

[0053] In summary, DRAM devices 410 and 460 can provide 12-bit interfaces via X6 DQ buses 430 and 480 respectively, with a burst length of 48 cycles. Successive data access operations, such as read or write operations, can be routed to the same subchannel. Alternatively or additionally, successive data access operations can alternate between subchannel 0 and subchannel 1 of DRAM devices 410 and 460 respectively.

[0054] Figure 5 According to various embodiments, how DRAM dies are vertically stacked in a multi-die DRAM package 500 is illustrated. As shown, the multi-die DRAM package 500 includes, but is not limited to, four DRAM dies 540(0), 540(1), 540(2), and 540(3). Additionally or alternatively, the multi-die DRAM package 500 may include any number of DRAM dies 540, including 1 DRAM die 540, 2 DRAM dies 540, 4 DRAM dies 540, 8 DRAM dies 540, 16 DRAM dies, and / or a similar number of DRAM dies 540. Each of the DRAM dies 540(0), 540(1), 540(2), and 540(3) is configured to... Figure 2B The DRAM device 260 is the same. Therefore, DRAM dies 540(0), 540(1), 540(2) and 540(3) are configured to support a 6-bit data bus width.

[0055] Each of the memory dies 540(0), 540(1), 540(2), and 540(3) is a general-purpose die that can be configured in a specific manner. For example, as shown, memory dies 540(0), 540(1), 540(2), and 540(3) are configured to support a 6-bit data bus width. In other configurations, memory dies 540(0), 540(1), 540(2), and 540(3) can be configured to support a 12-bit data bus width. Furthermore, each of the memory dies 540(0), 540(1), 540(2), and 540(3) can be configured to support six LSBs of the 12-bit data bus of the DRAM package 500, or six MSBs of the 12-bit data bus of the DRAM package 500.

[0056] The DRAM dies 540 included in the DRAM package 500 can be configured in one or more rank in any technically feasible combination. Furthermore, the DRAM dies 540 included in the DRAM package 500 can be configured as one or more channels in any technically feasible combination. As used herein, a rank refers to a group of DRAM dies sharing an address bus, data bus, chip select signal, and / or the like. As used herein, a channel refers to a connection between a memory controller and one or more rank. The memory controller (not shown) is responsible for storing and retrieving data from the DRAM device, configuring the DRAM device, performing various timing and maintenance functions and / or similar operations on the DRAM device. Typically, the DRAM device 540 can be organized into one or more rank, and any one or more rank can communicate with the memory controller via a single channel or via multiple channels.

[0057] As shown in the figure, the DRAM package 500 includes two ranks. The first rank, called rank 0, includes DRAM dies 540(0) and 540(2). DRAM die 540(0) stores the data corresponding to the six least significant data bits (LSBs), DQ0-5, for the 12-bit data bus of the DRAM package 500. DRAM die 540(2) stores the data corresponding to the six most significant data bits (MSBs), DQ6-11, for the 12-bit data bus of the DRAM package 500. Similarly, the second rank, called rank 1, includes DRAM dies 540(1) and 540(3). DRAM die 540(1) stores the data corresponding to the six LSBs, DQ0-5, for the 12-bit data bus of the DRAM package 500. DRAM die 540(3) stores the data corresponding to the six MSBs, DQ6-11, for the 12-bit data bus of the DRAM package 500.

[0058] The DQ0-5 bus 510 is the data bus interface for the 6 LSBs of the 12-bit data bus of the DRAM package 500. Therefore, the DQ0-5 bus 510 is connected to DRAM die 540(0) and DRAM die 540(1), where DRAM die 540(0) stores data for rank 0 corresponding to the 6 LSBs, and DRAM die 540(1) stores data for rank 1 corresponding to the 6 LSBs. Similarly, the RDQS_LWCK_L 520 is the control bus interface for the 6 LSBs of the 12-bit data bus of the DRAM package 500. This control bus includes read data strobe (RDQS_L) for the 6 LSBs, write clock signal (WCK_L) for the 6 LSBs, and / or similar signals. Therefore, the RDQS_LWCK_L 520 is connected to DRAM die 540(0) and DRAM die 540(1) to route control signals associated with the six LSBs of rank 0 and rank 1, respectively.

[0059] The DQ6-11 bus 515 is the data bus interface for 6 MSBs of the 12-bit data bus of the DRAM package 500. Therefore, the DQ6-11 bus 515 is connected to DRAM dies 540(2) and DRAM dies 540(3), where DRAM die 540(2) stores data corresponding to 6 MSBs for rank 0, and DRAM die 540(3) stores data corresponding to 6 MSBs for rank 1. Similarly, the RDQS_UWCK_U 525 is the control bus interface for 6 MSBs of the 12-bit data bus of the DRAM package 500. This control bus includes a read data strobe (RDQS_U) for 6 MSBs, a write clock signal (WCK_U) for 6 MSBs, and / or similar signals. Therefore, the RDQS_UWCK_U 525 is connected to DRAM dies 540(2) and DRAM dies 540(3) to route control signals associated with the six MSBs of rank 0 and rank 1, respectively.

[0060] DRAM package 500 may have individual chip select (CS) signals (not shown), with each of the two ranks receiving an individual CS signal. The first CS signal provides chip select for rank 0 and is therefore connected to DRAM die 540(0) and DRAM die 540(2). The second CS signal provides chip select for rank 1 and is therefore connected to DRAM die 540(1) and DRAM die 540(3). By configuring DRAM dies 540(0) and DRAM die 540(1) to route data and control signals to the corresponding 6 LSBs, and configuring DRAM dies 540(2) and DRAM die 540(3) to route data and control signals to the corresponding 6 MSBs, the four DRAM dies 540(0), 540(1), 540(2), and 540(3) may be mounted vertically to each other and may be connected to each other via vertically oriented wires. Furthermore, the four DRAM dies 540(0), 540(1), 540(2), and 540(3) can receive commands from the Common Command (CA) bus 530. Therefore, the CA bus 530 is connected to all four DRAM dies 540(0), 540(1), 540(2), and 540(3).

[0061] Figure 6 According to various embodiments, a format 600 for data transmission in a DRAM device having a 48-bit burst length is illustrated. The DRAM device can be any DRAM device configured with a 6-bit data bus width, such as... Figure 2B DRAM device 260, Figure 4 DRAM devices 410 and 460, Figure 5The DRAM dies are 540(0), 540(1), 540(2), and 540(3) and / or similar devices. As described herein, a conventional DRAM device with a 12-bit data bus width can transmit 288 bits in a single burst, with a burst length of 24 beats and 12 bits per beat. To transmit the same amount of data on a 6-bit data bus, the DRAM device described herein can transmit 288 bits in a single burst, with a burst length of 48 beats and 6 bits per beat. The DRAM device can use any technically feasible format to perform this 288-bit transmission.

[0062] A format of this type 600 that transmits 288 bits on a 6-bit data bus (DQ5...DQ0) 610. Figure 6 As shown in the diagram. This format 600 shows which bits are included in each 620-bit burst. The 288 bits of this burst include, but are not limited to, 256 data bits (labeled D0 to D255) and 32 parameter bits.

[0063] although Figure 6 The shown step 620 consists of three groups of 16 steps each, but these three groups are adjacent. Therefore, the 48 steps 620 of format 600 can be transmitted within 48 consecutive clock cycles. The first step 620 is marked "0" and includes data bits D17, D16, D9, D8, D1, and D0, which are transmitted on DQ5, DQ4, DQ3, DQ2, DQ1, and DQ0, respectively. The second step 620 is marked "1" and includes data bits D19, D18, D11, D10, D3, and D2, which are transmitted on DQ5, DQ4, DQ3, DQ2, DQ1, and DQ0, respectively, and so on.

[0064] The 32 parameter bits may include 16 metadata bits (labeled M0 to M15) and / or 16 link protection bits (labeled LP0 to LP15). In any given burst, the 16 metadata bits and / or 16 link protection bits may be present or absent in any combination. For example, in a given burst, both the 16 metadata bits and 16 link protection bits may be present. Alternatively, in a given burst, the 16 metadata bits may be present, while the 16 link protection bits may be absent. Alternatively, in a given burst, the 16 metadata bits may be absent, while the 16 link protection bits may be present. Alternatively, in a given burst, neither the 16 metadata bits nor the 16 link protection bits may be absent. If present, the 16 metadata bits may be transmitted on DQ5 and DQ4 of data bus 610 during cycles 8 to 11 and cycles 32 to 35. If present, the 16 link protection bits can be transmitted on DQ5 and DQ4 of data bus 610 during cycles 20 to 23 and 44 to 47. When absent, the bits reserved for the 16 metadata bits and / or 16 link protection bits can be fixed at a low voltage, representing a logic "0" level.

[0065] Figure 7 According to various embodiments, timing diagrams optimized for the command bus of a DRAM device supporting a 48-bit burst length are shown. As shown in timing diagram 700, the DRAM device can be configured to support quadruple data rate (QDR) data transmission. With QDR, four data bits can be transmitted per clock cycle. Therefore, the corresponding 48-bit burst of data can be transmitted via data bus 715(0) over 12 clock cycles. Conventionally, commands can be sent to the DRAM device via CA bus 710(0) using double data rate (DDR) data transmission. With DDR, two data bits can be transmitted per clock cycle, one bit on the rising edge of the clock signal and one bit on the falling edge of the clock cycle. As a result, the DRAM device can receive an activation (ACT) command during clock cycles 1-4, a read or write command (RD / WR) during clock cycles 5-6, and a precharge (PRE) command for the next DRAM access during clock cycles 7-8. This approach may result in underutilization of the CA bus 710(0) because the CA bus 710(0) is idle during clock cycles 9-12 while the burst is still transmitting data via the data bus 715(0).

[0066] To improve utilization, timing diagram 720 again shows the 48-bit data corresponding to the burst being transmitted via data bus 735(0) over 12 clock cycles. However, commands are sent to the DRAM device via CA bus 730(0) using single data rate (SDR) data transmission. With SDR, one data bit can be transmitted per clock cycle. Therefore, the time for each command transmission is doubled compared to timing diagram 700. Thus, the DRAM device can receive activation (ACT) commands during clock cycles 1-8, read or write commands (RD / WR) during clock cycles 9-12, and precharge (PRE) commands for the next DRAM access during clock cycles 13-16. This approach allows for better utilization of CA bus 730(0) because CA bus 730(0) is no longer idle while the burst is transmitting data via data bus 735(0).

[0067] Timing diagrams 700 and 720 illustrate data transfer using an open-page strategy. With an open-page strategy, DRAM pages remain open or active after an access, allowing for faster access to the same memory page for the next access when needed. However, with an open-page strategy, a precharge cycle may be required before the next access to the DRAM memory. Timing diagram 740 illustrates the transfer of 48 data packets corresponding to a burst over 12 clock cycles via data bus 755(0). Commands are transmitted to the DRAM device using single data rate (SDR) data transfer and a closed-page strategy via CA bus 750(0). With a closed-page strategy, DRAM pages are closed or become inactive after each access. The DRAM device can receive an activation (ACT) command during clock cycles 1-8 and a read or write command (RD / WR) with an automatic precharge (AP) combination during clock cycles 9-12. With a closed-page strategy, no separate precharge command is required. Therefore, when using the page-closing strategy, the number of clock cycles occupied by the transmission of burst data via the data bus 755(0) is the same as the number of clock cycles occupied by the transmission of commands via the CA bus 750(0).

[0068] Figure 8This diagram illustrates timing diagram 800 for chip select training of a DRAM device with a 6-bit data bus width, according to various embodiments. The chip select (CS) signal enables or disables the DRAM device from performing data transfer functions. Typically, the chip select signal is active low, meaning a low voltage on the chip select signal enables the DRAM device to perform data transfer, while a high voltage on the chip select signal disables the DRAM device from performing data transfer. The DRAM device receives the chip select signal from a memory controller, which transfers data to and receives data from the DRAM device. The memory controller can perform chip select training operations on the DRAM device to fine-tune the timing of the chip select signal between the memory controller and the DRAM device. By performing chip select training, the memory controller can reduce data transfer time, thereby improving the memory performance of the DRAM device.

[0069] During chip select training, the memory controller transmits data and control signals to the DRAM device via the data bus interface. When the DRAM device is configured with a 12-bit data bus width, the memory controller can use all 12 bits of the data bus to transmit data and control signals to the DRAM device. When the DRAM device is configured with a 6-bit data bus width, the memory controller uses only 6 bits of the data bus to transmit the same data and control signals to the DRAM device. Therefore, the memory controller uses a smaller number of bits in the data bus interface to transmit data to the DRAM device. Furthermore, the memory controller can combine multiple functions into a single control signal.

[0070] During the chip select training operation, the memory controller sends an 8-bit digital representation of a reference voltage (Vref) to the DRAM device. This reference voltage is used by the DRAM device to distinguish between low voltages representing logic "0" and high voltages representing logic "1". The memory controller can use different reference voltage values ​​to test the chip select signal to determine which reference voltage value, relative to other candidate reference voltages, produces the highest signal integrity, the most accurate sampling, and the largest timing margin.

[0071] To initiate chip select training, the memory controller sends a specific sequence of commands to the DRAM device, indicating that the chip select training operation should begin. The memory controller then sends a rising edge 820 on the DQ[5] 802 data bit to begin the chip select training operation. Because the 8-bit digital representation of the reference voltage has more bits than the 6-bit data bus width, the memory controller cannot send the digital representation of the reference voltage in a single step. Instead, the memory controller sends the digital representation in two steps via four data bits, namely the DQ[3:0] 806 data bits. The memory controller presents four bits of the digital representation on the DQ[3:0] 806 data bits and sends a first rising edge 840 on the DQ[4] 804 data bit. The DRAM device uses the rising edge 840 on the DQ[4] 804 data bit to sample the four bits of the digital representation on the DQ[3:0] 806 data bits. The memory controller presents the remaining 4 bits of the digital representation on the 806 data bits of DQ[3:0] and transmits a second rising edge 842 on the 804 data bits of DQ[4]. The DRAM device samples the remaining 4 bits of the digital representation on the 806 data bits of DQ[3:0] using the rising edge 842 on the 804 data bits of DQ[4]. After receiving two 4-bit portions of the digital representation, the DRAM device updates the reference voltage used for the chip select signal. The memory controller transmits a third rising edge 844 on the 804 data bits of DQ[4] to trigger the DRAM device to transmit the comparison result to the memory controller and reset the internal chip select counter.

[0072] The memory controller may repeatedly transmit additional digital representations of other candidate reference voltages and receive comparison results until the memory controller determines which reference voltage provides the best chip select result. After completing the chip select training operation, the memory controller transmits a falling edge (not shown) on the DQ[5] 802 data bit to terminate the chip select training operation.

[0073] Figure 9 This document illustrates a timing diagram 900 for command bus training of a DRAM device with a 6-bit data bus width, according to various embodiments. The command (CA) bus receives commands for the DRAM device from the memory controller. These commands can instruct the DRAM device to perform write and read operations, prefetch operations, chip select training operations, command bus training operations, and / or similar operations directed to the memory core. The memory controller can perform command bus training operations on the DRAM device to fine-tune the timing of the data pins of the command bus between the memory controller and the DRAM device. By performing command bus training, the memory controller can reduce data transfer time, thereby improving the memory performance of the DRAM device.

[0074] During command bus training operations, the memory controller transmits data and control signals to the DRAM device via the data bus interface. When the DRAM device is configured with a 12-bit data bus width, the memory controller can use all 12 bits of the data bus to transmit data and control signals to the DRAM device. When the DRAM device is configured with a 6-bit data bus width, the memory controller uses only 6 bits of the data bus to transmit the same data and control signals to the DRAM device. Therefore, the memory controller uses a smaller number of bits in the data bus interface to transmit data to the DRAM device. Furthermore, the memory controller can combine multiple functions into a single control signal.

[0075] During command bus training, the memory controller transmits an 8-bit digital representation of a reference voltage (Vref) to the DRAM device. This reference voltage is used by the DRAM device to distinguish between low voltages representing logic "0" and high voltages representing logic "1". The memory controller can use different reference voltage values ​​to test individual bits of the command bus to determine which reference voltage value, relative to other candidate reference voltages, produces the highest signal integrity, the most accurate sampling, and the largest timing margin.

[0076] To initiate command bus training, the memory controller sends a specific command sequence to the DRAM device, indicating that the command bus training operation should begin. The memory controller then sends a rising edge 920 on the DQ[5] 902 data bit to begin the command bus training operation. Since the 8-bit digital representation of the reference voltage has more bits than the 6-bit data bus width, the memory controller cannot send the digital representation of the reference voltage in a single step. Instead, the memory controller sends the digital representation in two steps via four data bits, namely the DQ[3:0] 906 data bits. The memory controller presents four bits of the digital representation on the DQ[3:0] 906 data bits and sends a first rising edge 940 on the DQ[4] 904 data bit. The DRAM device samples the four bits of the digital representation on the DQ[3:0] 906 data bits using the rising edge 940 on the DQ[4] 904 data bit. The memory controller presents the remaining 4 bits of the digital representation on the DQ[3:0] 906 data bits and transmits a second rising edge 942 on the DQ[4] 904 data bits. The DRAM device samples the remaining 4 bits of the digital representation on the DQ[3:0] 906 data bits using the rising edge 942 on the DQ[4] 904 data bits. After receiving two 4-bit portions of the digital representation, the DRAM device updates the reference voltage used for the command bus. The memory controller transmits a third rising edge 944 on the DQ[4] 904 data bits to trigger the DRAM device to transmit the comparison result to the memory controller and reset the internal linear feedback shift register (LFSR). This LFSR performs a data scrambling operation to increase the reliability of data and command transmission between the memory controller and the DRAM device.

[0077] The memory controller may repeat the steps of transmitting additional digital representations of other candidate reference voltages and receiving comparison results until the memory controller determines which reference voltage provides the best command bus result. After completing the command bus training operation, the memory controller transmits a falling edge (not shown) on the DQ[5] 902 data bit to terminate the command bus training operation.

[0078] In summary, various embodiments include an improved DRAM device having a general-purpose memory die that can be configured to have different data bus widths for different applications. The memory device can be configured to have a wide data bus width and a specified data burst length. Alternatively, the memory device can be configured to have a narrow data bus width half the wide data bus width and a data burst length twice the specified data burst length. By doubling the burst length when the data bus width is halved, both configurations of the memory device can maintain the same internal prefetch size. In some examples, the prefetch size of the memory device can be 288 bits. With this prefetch size, the memory device can be configured to have a 12-bit data bus width and a 24-bit burst length, or to have a 6-bit data bus width and a 48-bit burst length. Maintaining the same internal prefetch size for both configurations simplifies the channel control logic for the memory die.

[0079] Furthermore, a general-purpose die can be packaged in different configurations. For example, a package for a general-purpose memory die includes multiple read data strobe and write clock pins, allowing the read data strobe inputs and write clock inputs of the memory die to be routed to different pins of the memory device package. Similarly, a general-purpose memory die may include an internal data bus that allows, for example, all 12 bits to be routed to pins of the memory device package, or only 6 bits out of the 12 bits to pins of the memory device package. In the latter configuration, the memory die includes a mode in which the six most significant data pins or the six least significant data pins of the 12-bit data bus can be selected to be routed to pins of the memory device package.

[0080] These packaging options allow more memory devices to be placed on a single rank, effectively doubling memory capacity without increasing the surface area of ​​the memory device package. Therefore, higher memory capacity can be achieved without increasing the package surface area, providing additional memory capacity for applications requiring large amounts of memory, such as data servers in data centers.

[0081] Compared to existing technologies, at least one technical advantage of the disclosed technology is that, using the disclosed technology, a general-purpose die can be configured to have either a wide data bus width or a narrow data bus width, where the narrow data bus width is half the width of the wide data bus width. Furthermore, by doubling the data burst length when the data bus width is halved, the same internal prefetch size can be maintained. In contrast, conventional methods maintain the same burst length when the data bus width is halved, resulting in a 50% reduction in channel efficiency. Furthermore, the packaging for such a general-purpose die can include additional read strobe signals, write clocks, and data bus pin assignment options, making the resulting package easier to vertically stack and enabling even higher memory densities at the system level. Using these technologies, a single general-purpose DRAM die can be configured and packaged to accommodate different data bus widths for different applications without significantly increasing channel logic complexity or die surface area. These advantages represent one or more technical improvements over existing methods.

[0082] Any element of any claim and / or any combination of any element described in this application, in any manner, falls within the scope of this disclosure and protection.

[0083] The various embodiments described are for illustrative purposes only and are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

[0084] Aspects of this embodiment may be embodied as a system, method, or computer program product. Therefore, aspects of this disclosure may take the form of a completely hardware embodiment, a completely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, which may generally be referred to herein as a “module” or a “system.” Furthermore, aspects of this disclosure may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code.

[0085] Any combination of one or more computer-readable media may be used. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media will include the following: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable optical disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the context of this document, a computer-readable storage medium may be any tangible medium that may contain or store programs for use by or in connection with an instruction execution system, apparatus, or device.

[0086] The aspects of this disclosure have been described above with reference to flowchart examples and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart examples and / or block diagrams, and combinations of blocks in the flowchart examples and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, can perform the functions / actions specified in the flowchart and / or block diagram blocks. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, an application-specific processor, or a field-programmable gate array (FPGA).

[0087] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in a flowchart or block diagram may represent a module, segment, or portion of code, comprising one or more executable instructions for implementing one or more specified logical functions. It should also be noted that in some alternative implementations, the functions indicated in the boxes may differ from the order indicated in the figures. For example, two boxes shown consecutively may actually execute substantially simultaneously, or these boxes may sometimes execute in reverse order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart examples, and combinations of boxes in the block diagram and / or flowchart examples, may be implemented by a dedicated hardware-based system or a combination of dedicated hardware and computer instructions that perform the specified functions or actions.

[0088] Although the foregoing describes embodiments of this disclosure, other and further embodiments of this disclosure may be devised without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A memory device, comprising: The first memory die includes: First memory core; A first prefetch buffer, the first prefetch buffer being coupled to the first memory core and configured to store data for at least a portion of the first memory core; and A first data bus interface, coupled to the first prefetch buffer, is configurable to have either a first bit width or a second bit width. in: When configured to have the first bit width, the first data bus interface transmits data between the first prefetch buffer and the external device in a data transmission burst with a first burst length; and When configured to have the second bit width, the first data bus interface transmits data between the first prefetch buffer and the external device in a data transmission burst with a second burst length that is different from the first burst length.

2. The memory device according to claim 1, wherein, The first bit width is 12 bits, and the second bit width is 6 bits.

3. The memory device according to claim 1, wherein, The first burst length is 24, and the second burst length is 48.

4. The memory device according to claim 1, wherein: The memory device further includes a second memory die that is substantially similar to the first memory die, the second memory die including a second data bus interface that can be configured to have the first bit width or the second bit width; The first data bus interface is connected to the first set of connections on the first memory die; The second data bus interface is connected to the second set of connections on the second memory die; and The physical location of the first group connected on the first memory die is different from the physical location of the second group connected on the second memory die.

5. The memory device according to claim 4, wherein, The first die and the second die are stacked vertically in the physical package of the memory device.

6. The memory device according to claim 4, wherein, The first memory die includes a first memory block of the memory device, and the second memory die includes a second memory block of the memory device.

7. The memory device according to claim 4, wherein, The first memory die and the second memory die comprise a first memory block of the memory device.

8. The memory device according to claim 1, wherein, Whether the first data bus interface is configured to have the first bit width or the second bit width is based on the hard-wired components included in the memory die.

9. The memory device according to claim 1, wherein, Whether the first data bus interface is configured to have the first bit width or the second bit width is based on the value stored in one or more bits of a programmable register included in the memory die.

10. The memory device according to claim 1, wherein, When the memory device is in training mode: The memory controller transmits a first portion of the digital representation of the voltage reference via a portion of the first data bus interface at the first moment; and The memory controller transmits a second portion of the digital representation of the voltage reference via a portion of the first data bus interface at a second time.

11. A system comprising: Memory controller; as well as A memory device coupled to the memory controller, wherein the memory device includes: The first memory die includes: Memory core, A prefetch buffer, coupled to the memory core and configured to store at least a portion of the data for the memory core, and A data bus interface, which can be configured to have either a first bit width or a second bit width. in: When configured to have the first bit width, the data bus interface transmits data between the prefetch buffer and the memory controller in data transmission bursts with a first burst length, and When configured to have the second bit width, the data bus interface transmits data between the prefetch buffer and the memory controller in a data transmission burst with a second burst length that is different from the first burst length.

12. The system according to claim 11, wherein, The first bit width is 12 bits, and the second bit width is 6 bits.

13. The system according to claim 11, wherein, The first burst length is 24, and the second burst length is 48.

14. The system according to claim 11, wherein: The memory device further includes a second memory die substantially similar to the first memory die, the second memory die including a second data bus interface configurable to have either the first bit width or the second bit width. The first data bus interface is connected to the first set of connections on the first memory die. The second data bus interface is connected to the second set of connections on the second memory die, and The physical location of the first group connected on the first memory die is different from the physical location of the second group connected on the second memory die.

15. The system according to claim 14, wherein, The first die and the second die are stacked vertically in the physical package of the memory device.

16. The system according to claim 14, wherein, The first memory die includes a first memory block of the memory device, and the second memory die includes a second memory block of the memory device.

17. The system according to claim 14, wherein, The first memory die and the second memory die comprise a first memory block of the memory device.

18. The system according to claim 11, wherein, Whether the first data bus interface is configured to have the first bit width or the second bit width is based on the hard-wired components included in the first memory die.

19. The system according to claim 11, wherein, Whether the first data bus interface is configured to have the first bit width or the second bit width is based on the value in one or more bits of a programmable register included in the first memory die.

20. The system according to claim 11, wherein, When the memory device is in training mode: The memory controller transmits a first portion of the digital representation of the voltage reference via a portion of the first data bus interface at the first moment; and The memory controller transmits a second portion of the digital representation of the voltage reference via a portion of the first data bus interface at a second time.

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