Asymmetric laminated PCB press-bonding cooling temperature control method and device for embedded power module

Abstract

The application relates to a non-symmetrical laminated PCB pressing and cooling temperature control method and device for embedded power modules, and belongs to the technical field of chip pressing and temperature control, and comprises the following steps: obtaining complete structure information of a current non-symmetrical laminated PCB, and establishing a three-dimensional geometric model of the current non-symmetrical laminated PCB based on the complete structure information; determining the mechanical and thermophysical performance parameters of the temperature change of the material of each layer of the non-symmetrical laminated PCB in a preset material parameter database according to the complete structure information; inputting the three-dimensional geometric model as a solution domain and the mechanical and thermophysical performance parameters into a pre-established finite element thermal-mechanical coupling transient model for transient solution to obtain an internal stress vector field; and determining a cooling temperature control strategy based on the internal stress vector field. The application solves the stress evolution law in the cooling process and matches the exclusive temperature control strategy, overcomes the defects that stress release is not complete and the board surface is easy to rebound and warp in the traditional scheme, and effectively reduces residual stress.

Description

Technical Field

[0001] This invention relates to the field of chip lamination temperature control technology, and in particular to a method and apparatus for cooling and controlling the temperature of asymmetric stacked PCBs with embedded power modules. Background Technology

[0002] Power embedded packaging refers to directly embedding power chips, such as silicon-based, silicon carbide, or gallium nitride semiconductor chips, into the dielectric layer inside a PCB. The PCB's layered structure enables electrical interconnection and heat dissipation management of the chips, improving the integration of power electronic systems and showing broad application prospects in electric vehicles and new energy power generation. The PCB layered structure of embedded power modules differs fundamentally from conventional PCBs. Conventional multilayer PCBs typically employ symmetrical or near-symmetrical layer designs, while embedded power modules, due to the concentration of power chips, copper blocks, ceramic substrates, and other components in specific layers, exhibit significant material and structural asymmetry in the thickness direction. The PCB lamination process typically includes three stages: heating, curing, and cooling. In the high-temperature lamination stage, the resin in the prepreg softens, flows, and fills the gaps between layers, subsequently undergoing gradual cross-linking and curing in the isothermal curing stage. Upon entering the cooling stage, the resin transitions from a fluid state to a solid state, and the materials in each layer begin to shrink from high temperature to room temperature. Due to differences in the coefficients of thermal expansion of different materials, the amount of shrinkage varies among layers during the cooling process.

[0003] In conventional symmetrical stacked PCBs, the shrinkage on the top and bottom sides is basically balanced, and the internal stress caused by shrinkage in the two layers can cancel each other out. However, in asymmetrical stacked PCBs with embedded power modules, due to the significant difference in the coefficient of thermal expansion between copper and the surrounding resin substrate, the copper layer will exert a strong restraint on the shrinkage of the surrounding cured resin during the cooling process, resulting in a large shear stress at the interface between the two. Since the copper layer and the embedded components are deviated from the neutral plane of the stack in the thickness direction, this restraint effect is difficult to be symmetrically canceled on the top and bottom sides of the board thickness, thereby further inducing unbalanced bending moments along the board surface. Meanwhile, when the temperature drops below the glass transition temperature of the resin, the resin matrix modulus increases sharply, and its viscous flowability is essentially lost. The non-uniform internal stress generated earlier cannot be effectively released through resin creep or molecular chain segment movement, but is permanently frozen within the board as residual stress. The direct macroscopic manifestation of this residual stress is board warping. Severe warping not only increases the difficulty of subsequent drilling alignment and deteriorates the heat dissipation interface contact of power chips, but may also weaken the connection reliability of the copper pillar and pad interface in the long term, and may even further amplify the inherent CTE mismatch stress between the chip and the substrate, causing chip cracking or interface delamination. To address the warping problem of the aforementioned asymmetric PCB stack-up structure during lamination, existing technologies have proposed solutions from multiple perspectives. One type of solution focuses on the design and adjustment of the laminated structure. For example, by pairing two asymmetric multilayer boards and stacking them together, or by using release buffer materials and prepregs, the multilayer boards are first made into a symmetrical structure before lamination. Another type of solution focuses on the material treatment before lamination. For example, the waste area of ​​the prepreg on the asymmetric side is drilled to cut off its lever arm to reduce stress.

[0004] However, the above-mentioned existing technical solutions still have the following drawbacks in practical applications:

[0005] Taking a typical manufacturing scenario of embedding silicon carbide power modules in electric vehicle motor controllers as an example, this module embeds a thick copper block and a ceramic substrate in a specific layer near the heat dissipation surface. The metal ratio of the upper and lower stacked layers differs significantly, resulting in strong asymmetry. When using a lamination scheme to form a symmetrical structure by pairing and stacking, an additional sacrificial plate that is mirror-symmetrical to the plate to be laminated must be prepared. After lamination, it is then peeled off through a release interface. This process not only multiplies the consumption of materials such as prepreg and copper foil, but also the peeling force can easily break the established internal stress balance, causing the already flattened plate surface to warp irregularly again. For heavy copper power modules with copper blocks exceeding a certain thickness, this rebound effect is particularly prominent. If a solution is adopted to drill holes in the waste area of ​​the asymmetric prepreg to cut the lever arm, its effective implementation depends on reserving sufficient non-circuit area around the substrate. However, in order to reduce parasitic inductance and improve heat dissipation efficiency, the copper foil, heat dissipation vias, and buried copper blocks around the chip almost cover the entire board surface. The actual usable width of the edge waste area is often less than 2mm. Drilling dense holes in such a narrow area is not only prone to damaging the internal copper layer or causing edge cracking, but the drilled holes are also unable to fully release the high-density shrinkage stress around the large-size buried copper area. Therefore, in asymmetric embedded power modules with severely limited stacked structure space and extremely high metal filling rate, the above solutions are either limited by cost and board removal stress, or constrained by the area of ​​processable waste area. Ultimately, they are all unable to effectively control the unbalanced shrinkage stress caused by the mismatch of the material's thermal expansion coefficient during the pressing and cooling stage, making it still difficult to maintain the consistency and controllability of board warpage under mass production conditions. Summary of the Invention

[0006] Therefore, it is necessary to provide a method and apparatus for cooling and controlling the temperature of embedded power modules by laminating and cooling PCBs to address the aforementioned technical problems.

[0007] This invention provides a method for cooling and temperature control during the lamination of an asymmetric multilayer PCB for embedded power modules, the method comprising:

[0008] Obtain the complete structural information of the current asymmetric stacked PCB, and establish a three-dimensional geometric model of the current asymmetric stacked PCB based on the complete structural information;

[0009] Based on the complete structural information, the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB are determined in the preset material parameter database as a function of temperature.

[0010] Using the three-dimensional geometric model as the solution domain, the mechanical and thermophysical performance parameters are input into a pre-established finite element thermo-mechanical coupled transient model for transient solution to obtain the internal stress vector field. The finite element thermo-mechanical coupled transient model is used to calculate the temperature distribution at each moment during the cooling process and the thermal strain and stress response caused by the difference in the thermal expansion coefficients of each layer of material in the solution domain provided by the three-dimensional geometric model, combined with the mechanical and thermophysical performance parameters of each material partition. Finally, the internal stress vector field characterizing the magnitude, direction and spatial distribution of the internal stress of the stack is output.

[0011] The cooling temperature control strategy is determined based on the internal stress vector field, which is a spatiotemporally coupled three-dimensional vector time series dataset used to characterize the stress evolution of the PCB asymmetric stacked structure under the pressing and cooling process.

[0012] In one embodiment, before the step of using the three-dimensional geometric model as the solution domain, inputting the mechanical and thermophysical performance parameters into a pre-established finite element thermo-mechanical coupled transient model for transient solution to obtain the internal stress vector field, the method further includes:

[0013] Based on the material parameter database, a finite element thermo-mechanical coupled transient model is established for the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB as a function of temperature.

[0014] The finite element thermo-mechanical coupled transient model uses transient temperature-displacement coupling to solve the problem. It combines the viscoelastic constitutive properties of the semi-cured resin with the asymmetric compression cooling boundary conditions to reproduce the dynamic evolution of internal stress in the PCB as it cools from the high curing temperature to room temperature.

[0015] In one embodiment, the establishment of the finite element thermo-mechanical coupled transient model includes:

[0016] Establish a general parametric geometric template for asymmetric stacked PCBs;

[0017] The general parametric geometric template is meshed to generate a finite element mesh model;

[0018] Based on the mechanical and thermophysical property parameters of each layer of the constituent materials in the material parameter database, temperature-dependent material properties are defined for the material partitions of copper foil, ceramic substrate, prepreg resin, chip and embedded copper block on the finite element mesh model.

[0019] Apply heat transfer boundary conditions for upper and lower hot plates and normal pressing pressure boundary conditions to the finite element mesh model.

[0020] Set the transient thermo-mechanical coupling solution type, define the initial cooling temperature, the termination temperature and the cooling duration, and specify the output variable as the internal stress vector field to complete the construction of the finite element thermo-mechanical coupling transient model.

[0021] In one embodiment, the temperature-dependent material properties defined for the material partitions of copper foil, ceramic substrate, prepreg resin, chip, and embedded copper block on the finite element mesh model based on the mechanical and thermophysical property parameters of each layer of constituent materials in the material parameter database include:

[0022] For the material partitions of copper foil, ceramic substrate, chip and embedded copper block, the mechanical and thermophysical property parameters of the corresponding materials are retrieved from the material parameter database, and the elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity and density change with temperature are assigned to all elements in the partition on the finite element mesh model.

[0023] For the material partitioning of the prepreg resin, the basic mechanical and thermophysical property parameters of the prepreg resin are first retrieved from the material parameter database. On the finite element mesh model, all elements in the partition are assigned sequential values ​​of elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity, and density as a function of temperature. Then, the viscoelastic relaxation spectrum parameters of the glass transition temperature region are retrieved from the material parameter database and implanted into the corresponding partition. The implantation of the viscoelastic relaxation spectrum parameters is used to describe the nonlinear evolution of the modulus of the prepreg resin with temperature and the stress relaxation behavior in the glass transition temperature region.

[0024] In one embodiment, the material partitioning of the prepreg resin is characterized by a generalized Maxwell viscoelastic constitutive model to represent its temperature-dependent viscoelastic properties. The generalized Maxwell viscoelastic constitutive model is constructed by multiple sets of Maxwell units in parallel. The stress relaxation modulus of the resin is discretized by Prony series to characterize the viscoelastic evolution of the resin at different cooling stages.

[0025] The expression for the Prony series is:

[0026] ;

[0027] in, The shear relaxation modulus of the resin changes dynamically over time and is used to characterize the instantaneous viscoelastic stiffness of the resin. The equilibrium modulus after the resin is fully relaxed represents the elastic matrix properties after the resin is fully relaxed. The relaxation modulus weights of the i-th Maxwell element group; is the characteristic relaxation time of the i-th Maxwell unit; n is the number of Maxwell unit fitting groups; The time required for real-time calculation of the compression cooling process.

[0028] In one embodiment, the generalized Maxwell viscoelastic constitutive model, combined with the WLF time-temperature superposition principle, achieves a coupling relationship between temperature and relaxation characteristics. The time-temperature shift factor at different temperatures is calculated using the WLF equation, mapping the resin stress relaxation curve under varying temperature conditions to the master curve at the glass transition reference temperature. The WLF equation expression is as follows:

[0029] ;

[0030] in, It is the time-temperature shift factor; The glass transition temperature of the prepreg resin; The current real-time absolute temperature of the finite element element; , These are dimensionless fitting constants inherent to the resin material, calibrated by dynamic mechanical tests, and are used to characterize the sensitivity coefficient of temperature shift to relaxation rate and the temperature correction interval coefficient of the glass transition temperature range, respectively.

[0031] In one embodiment, the complete structural information includes stack-up structure information, embedded component information, and copper foil pattern information; the step of establishing a three-dimensional geometric model of the current asymmetric stack-up PCB based on the complete structural information includes:

[0032] Obtain the stack-up structure information of the current asymmetric stack-up PCB, and establish the two-dimensional planar contours of each dielectric layer and conductive layer based on the stack-up structure information.

[0033] All the two-dimensional planar contours are stacked along the thickness direction in the actual stacking order to obtain the geometric model of the stacked main body;

[0034] Obtain the embedded component information of the current asymmetric stacked PCB, and embed the three-dimensional solid geometry of the power chip, embedded copper block and ceramic substrate in the corresponding layer according to the embedded component information in the stacked main body geometric model to obtain the stacked main body geometric model with embedded components.

[0035] Define the contact interface relationship between each embedded element and the surrounding medium layer. The contact interface relationship refers to the mechanical connection relationship between the outer surface of each embedded element and the inner surface of the embedded cavity formed by the geometric model of the stacked main body during the embedding process. It is used to describe the displacement and stress transfer behavior at the interface of heterogeneous materials.

[0036] The copper foil pattern information of the current asymmetric stacked PCB is obtained, and according to the copper foil pattern information, the copper foil distribution characteristics are assigned to each conductive layer in the geometric model of the stacked main body with embedded components, so as to complete the establishment of the three-dimensional geometric model of the current asymmetric stacked PCB.

[0037] The present invention also provides a PCB lamination cooling temperature control device for implementing the asymmetric laminated PCB lamination cooling temperature control method for embedded power modules as described in any of the above claims, the device comprising:

[0038] The 3D geometric modeling module is used to obtain the complete structural information of the current asymmetric stacked PCB and establish a 3D geometric model of the current asymmetric stacked PCB based on the complete structural information.

[0039] The material parameter matching module is used to determine the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB as a function of temperature based on the complete structural information in a preset material parameter database.

[0040] The thermo-mechanical coupling simulation solution module is used to take the three-dimensional geometric model as the solution domain, input the mechanical and thermophysical performance parameters into the pre-established finite element thermo-mechanical coupling transient model for transient solution, and obtain the internal stress vector field;

[0041] A cooling temperature control strategy generation module is used to determine a cooling temperature control strategy based on the internal stress vector field.

[0042] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the asymmetric stacked PCB lamination cooling temperature control method for embedded power modules as described above.

[0043] The present invention also provides a computer storage medium storing a computer program, which, when executed by a processor, implements the asymmetric stacked PCB lamination cooling temperature control method for embedded power modules as described above.

[0044] The above-mentioned asymmetric multilayer PCB lamination cooling and temperature control method, device, electronic equipment, and storage medium for embedded power modules have the following advantages compared to existing technologies:

[0045] (1) This invention first accurately collects the complete structural information of asymmetric stacked PCBs and constructs a high-precision three-dimensional geometric model to fully reproduce irregular embedded structures such as embedded copper blocks, ceramic substrates, and power chips, as well as asymmetric stacked layouts; then, it matches the mechanical and thermophysical performance parameters of each layer material as the temperature dynamically changes, accurately restoring the thermal expansion coefficient mismatch characteristics of heterogeneous materials; relying on a self-developed thermo-mechanical coupled transient finite element model, it solves the dynamic response of temperature, strain, and stress during the cooling process in a full time sequence, outputting a high-precision spatiotemporal coupled internal stress vector field, accurately locating the residual stress concentration area and evolution law; finally, it formulates a dedicated cooling temperature control strategy based on the stress evolution characteristics. This application overcomes the defects of traditional paired stacking schemes, such as high material costs, stress rebound warping during disassembly, and insufficient stress release in the waste area drilling, which easily damages the board material. It can effectively control the unbalanced shrinkage bending moment and residual stress during the cooling process of asymmetric stacked PCBs, improving the consistency and yield of product production.

[0046] (2) This invention is based on the generalized Maxwell viscoelastic constitutive model combined with the WLF time-temperature superposition principle. By fitting the resin stress relaxation modulus through the Prony series, it accurately characterizes the nonlinear modulus change and stress relaxation behavior of the prepreg resin in the glass transition temperature range, and simultaneously achieves accurate mapping of the resin relaxation characteristics under variable temperature conditions. Compared with the traditional constant parameter simulation method, it can realistically reproduce the entire process of stress freezing and release from high temperature curing to room temperature cooling, solving the problems of conventional simulation being unable to adapt to the temperature-dependent viscoelasticity of resin and large deviations in stress calculation, and providing accurate data support for the formulation of temperature control strategies. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0048] Figure 1 This is a schematic flowchart of the asymmetric stacked PCB lamination cooling and temperature control method for embedded power modules provided by the present invention.

[0049] Figure 2 This is a schematic diagram of the architecture design of the finite element thermo-mechanical coupling transient model of the asymmetric stacked PCB lamination cooling temperature control method for embedded power modules in a specific embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of the internal stress vector field of the high-temperature, high-elasticity resin-embedded copper interface unit in the asymmetric laminated PCB lamination cooling temperature control method for embedded power modules provided in a specific embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of the internal stress vector field of the glass transition critical state interface unit in the asymmetric multilayer PCB lamination cooling temperature control method for embedded power modules in a specific embodiment of the present invention.

[0052] Figure 5 This is a schematic diagram of the internal stress vector field of the singular unit at the corner of the low-temperature glassy chip in the asymmetric laminated PCB lamination cooling temperature control method for embedded power modules provided in a specific embodiment of the present invention.

[0053] Figure 6 This is a schematic diagram of the PCB lamination cooling temperature control device provided by the present invention.

[0054] Figure 7 This is a diagram of the internal structure of the electronic device provided by the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] The following is combined Figures 1 to 7 The present invention describes a method and apparatus for cooling and controlling the temperature of embedded power module by laminating asymmetric stacked PCB.

[0057] like Figure 1 As shown, in one embodiment, a method for cooling and temperature control of asymmetric multilayer PCB lamination for embedded power modules includes the following steps:

[0058] Step S100: Obtain the complete structural information of the current asymmetric stacked PCB, and establish a three-dimensional geometric model of the current asymmetric stacked PCB based on the complete structural information.

[0059] In this embodiment, the complete structural information in step S100 includes stacked structure information, embedded component information, and copper foil pattern information; the three-dimensional geometric model is used to fully characterize the thickness and stacking order of each dielectric layer and conductive layer of the current asymmetric stacked PCB, the spatial position and geometric shape of each embedded component, and the copper foil distribution characteristics of each conductive layer.

[0060] In some embodiments, step S100 specifically includes the following sub-steps:

[0061] S110: Obtain the stack-up structure information of the current asymmetric stack-up PCB, and establish the two-dimensional planar contours of each dielectric layer and conductive layer based on the stack-up structure information.

[0062] S120: Stack all two-dimensional planar contours along the thickness direction according to the actual stacking order to obtain the geometric model of the stacked main body.

[0063] S130: Obtain the embedded component information of the current asymmetric stacked PCB, and embed the three-dimensional solid geometry of the power chip, embedded copper block and ceramic substrate in the corresponding layer according to the embedded component information in the stacked main body geometric model to obtain the stacked main body geometric model with embedded components.

[0064] S140 defines the contact interface relationship between each embedded element and the surrounding dielectric layer.

[0065] S150: Obtain the copper foil pattern information of the current asymmetric stacked PCB, and in the geometric model of the stacked main body with embedded components, assign copper foil distribution characteristics to each conductive layer according to the copper foil pattern information to complete the establishment of the three-dimensional geometric model of the current asymmetric stacked PCB.

[0066] The following is a detailed explanation of the sub-steps S110-S150 of S100 above:

[0067] S110: Obtain the stack-up structure information of the current asymmetric stack-up PCB, and establish the two-dimensional planar contours of each dielectric layer and conductive layer based on the stack-up structure information.

[0068] In S110 above, the stack-up structure information refers to a set of data including the arrangement order of the dielectric and conductive layers in the thickness direction, the thickness of each layer, and the material type. This data can be extracted from the design documents or process specifications of the current asymmetric stack-up PCB. Specifically, the stack-up structure information includes:

[0069] The lamination sequence information is used to define the arrangement sequence of each dielectric layer and conductive layer in the thickness direction. For example, from top to bottom, the order is top copper foil, first prepreg, second copper foil, second prepreg, ..., bottom copper foil, so as to determine the Z-axis positioning reference of each layer in subsequent stacking operations.

[0070] The thickness information for each layer includes the nominal copper thickness and tolerance range for each conductive layer, as well as the prepreg model used for each dielectric layer and the nominal thickness after curing. For dielectric layers with multiple prepreg sheets stacked together, the thickness information for each layer also includes the number of stacked sheets and the total thickness.

[0071] The material category information for each layer is used to identify the type of prepreg resin system used in each dielectric layer, as well as the type of copper foil used in each conductive layer.

[0072] The outer contour dimension information of the plate is used to define the boundary range of each layer in the XY plane, and serves as the dimensional reference for S110 to establish the two-dimensional planar contour of each layer.

[0073] Based on the above stacked structure information, the specific method for S110 to establish the two-dimensional planar contours of each dielectric layer and conductive layer is as follows: taking the PCB board surface as the XY plane, the two-dimensional planar contours of each layer are created one by one in the order from the top layer to the bottom layer; among them, the two-dimensional planar contour of the conductive layer is defined by the outer contour size of the board surface; the two-dimensional planar contour of the dielectric layer is also defined by the outer contour size of the board surface, and its thickness information is temporarily stored for subsequent stacking operations.

[0074] S120: Stack all two-dimensional planar contours along the thickness direction according to the actual stacking order to obtain the geometric model of the stacked main body.

[0075] In the above-mentioned S120, the stacked main geometric model refers to a three-dimensional layered structure formed by sequentially stretching or stacking along the thickness direction (Z-axis) based on the two-dimensional planar outlines of each dielectric layer and conductive layer established in S110.

[0076] In some embodiments, S120 specifically includes the following steps:

[0077] Step 1.2.1: Using the outer contour dimensions of the plate surface determined in S110 as the boundary reference of the XY plane, and establishing a three-dimensional coordinate system with the thickness direction as the Z axis.

[0078] In this embodiment, the bottom surface of the first layer of two-dimensional planar contour is set as the zero point of the Z-axis, serving as the reference datum surface for the entire stacked main geometric model.

[0079] Step 1.2.2: According to the arrangement sequence defined by the lamination sequence information obtained in S110, starting from the bottom layer, stretch each two-dimensional planar contour along the positive Z-axis to its corresponding thickness value to generate the three-dimensional solid or sheet of each layer.

[0080] The specific operation is as follows: For the conductive layer, the stretching height is the nominal value of the copper thickness of the conductive layer; for the dielectric layer, the stretching height is the nominal value of the thickness of the prepreg used in the dielectric layer after curing. If the dielectric layer is composed of multiple prepregs, the stretching height is the total thickness of the stack. After each layer is stretched, the upper surface of the layer is used as the bottom surface of the next layer, and the next layer is stretched, thereby ensuring that there are no gaps or penetrations between adjacent layers in the thickness direction, and that the interfaces are geometrically coplanar.

[0081] Step 1.2.3: After all the two-dimensional planar contours of all layers have been stretched in the Z direction and stacked in sequence as described above, a complete three-dimensional layered structure is obtained as the geometric model of the stacked main body.

[0082] The geometric model of the stacked main body in this embodiment fully preserves the thickness dimension, spatial sequence and interlayer interface relationship of each conductive layer and dielectric layer. It serves as the geometric host model for the embedded element in S130 and is also the geometric basis for assigning material properties and applying boundary conditions in the subsequent step S240.

[0083] S130: Obtain the embedded component information of the current asymmetric stacked PCB, and embed the three-dimensional solid geometry of the power chip, embedded copper block and ceramic substrate in the corresponding layer according to the embedded component information in the stacked main body geometric model to obtain the stacked main body geometric model with embedded components.

[0084] In S130 above, the embedded component information includes the following:

[0085] The component category identifier is used to distinguish whether the embedded component is a power chip, a copper block, or a ceramic substrate, so as to determine the material property classification of each component in the subsequent finite element analysis.

[0086] The component geometry includes the length, width, and thickness of the power chip, the length, width, and thickness of the embedded copper block and its shape characteristics, as well as the length, width, and thickness of the ceramic substrate. The shape characteristics of the embedded copper block further include chamfer dimensions, step height and position, and side etching texture, to ensure that the geometry of the embedded copper block closely approximates the actual physical interface.

[0087] The component embedding layer is used to specify the Z-axis height range of each component in the overall geometric model of the stack. Specifically, it is expressed as the starting and ending conductive layer numbers occupied by the component, or the embedding depth range of the component in the dielectric layer.

[0088] The component's position on the board surface includes the coordinates of the center point of each component in the XY plane and the rotation angle, which is used to determine the two-dimensional positioning and orientation of the component on the board surface.

[0089] In some embodiments, based on the above-mentioned embedded component information, the specific execution process of embedding each component in the stacked main body geometric model in S130 is as follows:

[0090] Step 1.3.1: Determine the Z-axis height range occupied by the component based on the embedded layer position, so as to locate the corresponding dielectric layer or conductive layer range in the geometric model of the stacked body, and determine the placement position and orientation of the component in the XY plane based on the component's position in the board surface, at the corresponding Z-axis height, using the component's center point coordinates and rotation angle.

[0091] Step 1.3.2: Based on the component category identifier and component geometry, create a three-dimensional solid geometry that matches the actual dimensions of each component.

[0092] The power chip and ceramic substrate are modeled as cuboid solids, while the embedded copper block is modeled as a solid containing external features such as chamfers and steps.

[0093] Step 1.3.3: In the stacked main body geometric model, the volume occupied by each component is removed in the corresponding medium layer through Boolean difference operation or geometric cutting to form an embedded cavity that matches the shape of the component, and the three-dimensional solid geometry of each component is placed in the corresponding embedded cavity; after all the embedded components are embedded in the above manner, the resulting geometric model is used as the stacked main body geometric model with embedded components.

[0094] S140 defines the contact interface relationship between each embedded element and the surrounding dielectric layer.

[0095] In S140 above, the contact interface relationship refers to the mechanical connection between the outer surface of each embedded component and the inner surface of the embedded cavity formed in S130. This connection is used to describe the displacement and stress transfer behavior at the interface of heterogeneous materials in subsequent finite element analysis. These interfaces are key connection areas formed by the bonding of the prepreg resin with the chip, embedded copper block, and ceramic substrate after high-temperature pressing and curing. They are also the main load-bearing areas for shear stress generated during the cooling stage due to the difference in thermal expansion coefficients. Therefore, it is necessary to clearly define their contact constraint conditions during the geometric modeling stage to ensure the accuracy of stress simulation.

[0096] In some embodiments, S140 specifically includes the following sub-steps:

[0097] Step 1.4.1: Traverse all embedded elements in the geometric model of the stacked main body with embedded elements. For each embedded element, extract all the outer surfaces of its three-dimensional solid geometry and find the inner surface of the embedded cavity that is geometrically coincident with or adjacent to the outer surface in the surrounding medium layer. Identify each pair of corresponding surfaces as a contact surface combination.

[0098] Step 1.4.2: Establish contact pairs for each contact surface combination.

[0099] The outer surface of the embedded element is designated as the master surface, and the inner surface of the embedded cavity of the dielectric layer is designated as the slave surface, so as to clarify the reference direction for contact search and constraint application.

[0100] Step 1.4.3: Set contact attributes uniformly for all contact pairs.

[0101] In this embodiment, the normal contact behavior is set as a binding constraint to simulate the tight adhesion between the prepreg resin and the surface of the embedded component after high-temperature curing, ensuring continuous displacement and no relative separation at the interface. The tangential contact behavior is set as no slippage to accurately transmit the shear stress caused by the mismatch in the thermal expansion coefficients of copper and resin. In this embodiment, the bonding interface between all embedded components and the surrounding dielectric layer is assumed to be ideal, and initial delamination defects are not considered.

[0102] Once the contact interface relationships of all embedded elements are defined as described above, the heterogeneous material interfaces in the geometric model of the stacked main body with embedded elements will have clear mechanical transmission paths. This provides a geometric basis for automatically generating contact elements in these interface regions during mesh generation in the subsequent step S220, and also lays the foundation for accurately simulating the generation and transmission of interface stress after applying the boundary conditions of the upper and lower hot plates in S250.

[0103] S150: Obtain the copper foil pattern information of the current asymmetric stacked PCB, and in the geometric model of the stacked main body with embedded components, assign copper foil distribution characteristics to each conductive layer according to the copper foil pattern information to complete the establishment of the three-dimensional geometric model of the current asymmetric stacked PCB.

[0104] In S150 above, copper foil graphic information refers to a set of data describing the spatial distribution of copper foil-covered and copper-free areas on each conductive layer, which can be extracted from the line layer of the current asymmetric stacked PCB's Gerber file, ODB++ file, or PCB design source file.

[0105] Specifically, the copper foil graphic information includes the following:

[0106] The copper boundary contour data for each conductive layer is used to define the planar boundary between copper-containing and copper-free areas on each conductive layer. This copper boundary contour data consists of closed polylines or curves, precisely depicting the geometric boundaries of traces, pads, large copper areas, and the regions containing heat dissipation via arrays.

[0107] The residual copper percentage parameter of each conductive layer is used to characterize the percentage of copper foil coverage area on each conductive layer relative to the total area of ​​that layer, serving as a macroscopic quantitative indicator of the degree of asymmetry in copper foil distribution. For asymmetric embedded power modules with extremely high metal filling rates, the residual copper percentage parameter directly reflects the degree of difference in metal proportion between the upper and lower conductive layers, and is an important reference for predicting the asymmetric shrinkage trend during the cooling stage.

[0108] Copper thickness markings are used to distinguish the copper thickness specifications of different areas on each conductive layer, such as the thickness difference between the base copper thickness and the thickness of locally thickened copper areas, so that the actual metal volume of each area can be accurately reflected when copper distribution characteristics are subsequently assigned.

[0109] In some embodiments, based on the above copper foil pattern information, the specific execution process of S150 assigning copper foil distribution characteristics to each conductive layer is as follows:

[0110] Step 1.5.1: In the geometric model of the stacked main body with embedded components, according to the lamination sequence information obtained in S110, the Z-axis height positions of each conductive layer are traversed sequentially.

[0111] Step 1.5.2: For each conductive layer, based on the copper boundary contour data of the layer, project and cut out the boundary line between the copper-containing area and the copper-free area on the three-dimensional solid or sheet of the layer. The copper-containing area is retained as the copper material partition of the conductive layer, and the copper-free area is marked as the dielectric filling area.

[0112] Step 1.5.3: For conductive layers with varying copper thicknesses, the areas with thicker copper plating are separately divided and assigned corresponding thickness values ​​based on the copper thickness markings.

[0113] After all conductive layers have been assigned copper distribution characteristics in the manner described above, the resulting three-dimensional geometric model not only fully characterizes the thickness and stacking order of each dielectric and conductive layer, the spatial position and geometric shape of each embedded component, but also accurately expresses the actual copper distribution state on each conductive layer. This allows it to accurately reflect the difference in metal ratio between upper and lower layers caused by the asymmetric copper distribution in the current asymmetric stacked PCB, providing geometric input consistent with the actual structure for the accurate calculation of the internal stress vector field caused by the mismatch between the thermal expansion coefficients of copper and resin in the finite element thermo-mechanical coupling transient model in step S300.

[0114] Step S200: Based on the complete structural information, determine the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB as a function of temperature in the preset material parameter database.

[0115] In step S200 above, the material parameter database is a pre-established collection of data that stores the performance parameters of commonly used materials in PCB manufacturing. The database is indexed according to the category identifier of each material. Each record contains a sequence of mechanical and thermophysical performance parameters of the material arranged by temperature nodes in the entire temperature range from room temperature to the pressing and curing temperature, thereby accurately describing the characteristics of material properties changing with temperature.

[0116] In some embodiments, step S200 mainly determines the mechanical and thermophysical performance parameters through a material category identifier index matching method. It should be noted that, in this embodiment, for copper foil, ceramic substrate, power chip, and embedded copper block materials, the corresponding mechanical and thermophysical performance parameters include elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity, and the sequence of density changes with temperature. However, for semi-cured resins, it is also necessary to obtain the glass transition temperature and viscoelastic relaxation spectrum parameters of the glass transition temperature range. The glass transition temperature refers to the median or starting temperature of the temperature range in which the semi-cured resin transitions from a highly elastic state to a glassy state; it is the critical temperature range where the resin modulus changes drastically and the coefficient of thermal expansion inflects. The viscoelastic relaxation spectrum parameters of the glass transition temperature range refer to a set of parameters describing the stress relaxation time and temperature dependence of the semi-cured resin within the glass transition temperature range, including the relaxation modulus-time curve, the time-temperature superposition shift factor, and the dynamic mechanical analysis curves of storage modulus and loss modulus as a function of temperature and frequency.

[0117] Step S300: Using the three-dimensional geometric model as the solution domain, the mechanical and thermophysical performance parameters are input into the pre-established finite element thermo-mechanical coupled transient model for transient solution to obtain the internal stress vector field.

[0118] In this embodiment, the finite element thermo-mechanical coupled transient model is a pre-established numerical simulation model used to simulate the coupled evolution of temperature field and stress field during the entire process of cooling down an asymmetric multilayer PCB from curing temperature to room temperature. Specifically, the finite element thermo-mechanical coupled transient model is used to calculate the temperature distribution at each moment during the cooling process and the thermal strain and stress response caused by the difference in thermal expansion coefficients of each layer of material in the solution domain provided by the three-dimensional geometric model, combined with the mechanical and thermophysical performance parameters of each material partition. Finally, it outputs the internal stress vector field that characterizes the magnitude, direction and spatial distribution of stress inside the multilayer.

[0119] In some embodiments, the sub-steps for establishing the finite element thermo-mechanical coupling transient model before step S300 include the following:

[0120] Step S10: Establish a general parametric geometric template for asymmetric stacked PCBs.

[0121] Step S20: Mesh the general parametric geometric template to generate a finite element mesh model.

[0122] Step S30: Based on the mechanical and thermophysical property parameters of each layer of constituent materials in the material parameter database, temperature-dependent material properties are defined for the material partitions of copper foil, ceramic substrate, prepreg resin, chip and embedded copper block on the finite element mesh model.

[0123] Step S40: Apply heat transfer boundary conditions for the upper and lower hot plates and normal pressing pressure boundary conditions to the finite element mesh model.

[0124] Step S50: Set the transient thermo-mechanical coupling solution type, define the initial cooling temperature, the termination temperature and the cooling duration, and specify the output variable as the internal stress vector field to complete the construction of the finite element thermo-mechanical coupling transient model.

[0125] The following section elaborates on sub-steps S10-S50, which involve establishing the finite element thermo-mechanical coupling transient model prior to step S300:

[0126] Step S10: Establish a general parametric geometric template for asymmetric stacked PCBs.

[0127] In step S10 above, the general parametric geometry template is a pre-built parametric framework for quickly generating 3D geometric models of asymmetric stacked PCBs. This template is not specific to any particular PCB, but rather abstracts and aggregates the common structural features of asymmetric stacked PCBs, defining structural elements such as the number of layers, layer thickness, geometric dimensions of embedded components, and their embedding positions as editable parameter variables. When dealing with a specific model of asymmetric stacked PCB, simply assign the corresponding values ​​from the current PCB's stacked structure information, embedded component information, and copper foil graphic information obtained in S100 to the respective parameter variables. This will drive the template to automatically generate a 3D geometric model consistent with the PCB structure, thereby avoiding manual modeling from scratch for each simulation and significantly improving model building efficiency and consistency.

[0128] Step S20: Mesh the general parametric geometric template to generate a finite element mesh model.

[0129] In step S20 above, mesh generation refers to the process of discretizing the three-dimensional geometric model generated by the general parametric geometric template established in S10 into a finite number of elements and nodes. Its purpose is to transform the continuous geometric solution domain into a discrete computational domain that can be used by the finite element solver for numerical calculation. The finite element mesh model is the data set consisting of all elements, nodes and their topological relationships after mesh generation. It is the direct object of operation in subsequent steps S30 (assigning material properties), S40 (applying loads and boundary conditions), and S50 (performing transient solutions).

[0130] In some embodiments, step S20 specifically includes the following steps:

[0131] S21. Select the mesh cell type based on the geometric characteristics of each material partition in the general parametric geometry template.

[0132] For the dielectric and conductive layers in the stacked body, since their thickness dimension is much smaller than their in-plane dimension, hexahedral or quadrilateral shell elements are preferred for structured meshing to reduce the number of elements and improve computational efficiency. For embedded components such as power chips, copper blocks, and ceramic substrates, since their location is a critical stress concentration area, tetrahedral elements are used for unstructured meshing to better adapt to the shape characteristics of the components and the irregular geometric boundaries of the embedded cavities.

[0133] S22, apply a preset mesh encryption rule to the interface region of metal-resin heterogeneous materials.

[0134] The preset mesh refinement rules stipulate that at the interfaces between the copper foil and the prepreg resin, the contact interfaces between the outer surface of the embedded copper block and the inner surface of the embedded cavity, and the contact interfaces between the chip and the ceramic substrate and the surrounding dielectric layer, the mesh cell size is reduced to one-third to one-fifth of the cell size of the surrounding substrate area. A gentle transition gradient is set from the refined area to the unrefined area to ensure sufficient resolution and accuracy in the shear stress calculation at the interface. The extent of the refined area is automatically determined based on the difference in elastic modulus and thermal expansion coefficient between the materials on both sides of the interface. The greater the difference, the greater the depth of the refined area extending into the substrate.

[0135] S23 performs regular mesh generation in non-interface areas.

[0136] Conventional mesh generation refers to discretizing the interiors of dielectric layers, conductive layers, and embedded components far from heterogeneous material interfaces using larger cell sizes. This controls the overall number of cells in the model and balances computational accuracy with solution efficiency. The cell size in conventional regions is automatically adapted based on the overall PCB thickness and in-plane dimensions, typically 1 to 2 times the thickness dimension.

[0137] The discretized data set obtained through S21-S23 above, consisting of all elements, nodes, and topological relationships, is the finite element mesh model. This model completely preserves the geometric boundaries of each dielectric layer, conductive layer, and embedded element in the original three-dimensional geometric model.

[0138] Step S30: Based on the mechanical and thermophysical property parameters of each layer of constituent materials in the material parameter database, temperature-dependent material properties are defined for the material partitions of copper foil, ceramic substrate, prepreg resin, chip and embedded copper block on the finite element mesh model.

[0139] The temperature-dependent material properties include the sequence of elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity, and density changes with temperature across the entire temperature range from room temperature to curing temperature for each material partition. These properties are used in transient thermo-mechanical coupling solutions to provide accurate constitutive parameters for each element in the finite element mesh model corresponding to its current temperature, thereby calculating the thermal strain increment and stress response at each moment during the cooling process. It is important to note that for the material partitions of the prepreg resin, in addition to the above parameters, the temperature-dependent material properties also include the glass transition temperature and the viscoelastic relaxation spectrum parameters of the glass transition temperature region. This describes the nonlinear evolution of the prepreg resin's modulus with temperature and its stress relaxation behavior within the glass transition temperature region, ensuring that the finite element model can accurately capture the peak value and evolution characteristics of the interfacial shear stress during the critical transition stage from viscoelastic to elastic resin.

[0140] In some embodiments, the step of defining temperature-dependent material properties for the material partitions of copper foil, ceramic substrate, prepreg resin, chip, and embedded copper block on the finite element mesh model based on mechanical and thermophysical performance parameters in step S30 is as follows:

[0141] S31, for the material partitions of copper foil, ceramic substrate, chip and embedded copper block, the mechanical and thermophysical property parameters of the corresponding materials are retrieved from the material parameter database, and the elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity and density change with temperature are assigned to all elements in the partition on the finite element mesh model.

[0142] It should be noted that, because the prepreg resin undergoes a glass transition during cooling, its modulus changes drastically by several orders of magnitude within the glass transition temperature range, accompanied by a significant stress relaxation effect. Step S30 also includes:

[0143] S32, for the material partition of the prepreg resin, firstly retrieve the basic mechanical and thermophysical property parameters of the prepreg resin from the material parameter database, and assign a sequence of values ​​for elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity and density as a function of temperature to all elements in the partition on the finite element mesh model; then retrieve the viscoelastic relaxation spectrum parameters of the glass transition temperature region from the material parameter database, and implant the viscoelastic relaxation spectrum parameters into the corresponding partition.

[0144] Among them, the incorporation of viscoelastic relaxation spectrum parameters is used to fully describe the nonlinear evolution of the modulus of the prepreg resin with temperature and its stress relaxation behavior in the glass transition temperature range.

[0145] Specifically, implantation refers to the process of writing viscoelastic relaxation spectrum parameters in Prony series form into the material constitutive subroutine of the prepreg resin material partition in the finite element unit of that partition. This switches the material constitutive relationship of that partition from a single linear elastic model to a generalized Maxwell viscoelastic model. The viscoelastic constitutive model in Prony series form consists of multiple Maxwell elements connected in parallel. The relaxation time and weighting coefficients of each element are obtained by nonlinear fitting of the relaxation modulus-time curve in the viscoelastic relaxation spectrum parameters. A time-temperature superposition shift factor is used to map the relaxation behavior at different temperatures to the master curve at the reference temperature. The dynamic mechanical analysis curves of storage modulus and loss modulus as a function of temperature and frequency are used to verify the accuracy of the Prony series fitting. After implantation, in each time step of the finite element solution, the elements of the prepreg resin partition call the corresponding relaxation modulus and shift factor according to their current temperature to calculate the stress increment and stress relaxation amount for that time step, thereby accurately simulating the transient evolution of interfacial shear stress during the transition of the resin from viscoelastic to elastic during cooling.

[0146] Specifically, the expression for the Prony series is:

[0147] ;

[0148] in, The shear relaxation modulus of the resin changes dynamically over time and is used to characterize the instantaneous viscoelastic stiffness of the resin. The equilibrium modulus of the resin after complete relaxation corresponds to the residual stiffness of the resin under long-term steady state, and characterizes the elastic matrix properties of the resin after complete relaxation. is the relaxation modulus weight of the i-th Maxwell element, and is the non-negative fitting coefficient used to allocate the proportion of stress relaxation contribution under different time scales; is the characteristic relaxation time of the i-th Maxwell unit, with the dimension of time, used to correspond to the stress decay rate of the resin in different stages of high temperature and high elasticity, glass transition temperature, and low temperature glass state. n is the number of Maxwell unit fitting groups. By connecting multiple groups of units in parallel, the full temperature range and full time range relaxation scale of the resin from instantaneous rapid relaxation to long-term slow relaxation are covered, accurately matching the viscoelastic evolution characteristics of the resin in the cooling process of asymmetric stacked PCB. The time required for real-time calculation of the compression cooling process.

[0149] The generalized Maxwell viscoelastic constitutive model, combined with the WLF time-temperature superposition principle, achieves a coupling relationship between temperature and relaxation characteristics. The time-temperature shift factor at different temperatures is calculated using the WLF equation, mapping the resin stress relaxation curve under varying temperature conditions to the master curve at the glass transition reference temperature. The expression for the WLF equation is:

[0150] ;

[0151] in, is the time-temperature shift factor, a dimensionless coefficient used to convert the stress relaxation time of resin at any temperature to the equivalent relaxation time corresponding to the reference temperature, thereby achieving a unified mapping of relaxation characteristics at different temperatures. The glass transition temperature of the prepreg resin is expressed in °C. It is the critical temperature at which the resin transitions from a highly elastic state to a glassy state, and serves as the reference temperature for viscoelasticity calculations in this invention. This represents the current real-time absolute temperature of the finite element, in °C, corresponding to the element temperature at each iteration step during the cooling transient process. , These are dimensionless fitting constants inherent to the resin material, calibrated by dynamic mechanical tests, and are used to characterize the sensitivity coefficient of temperature shift to relaxation rate and the temperature correction interval coefficient of the glass transition temperature region, respectively. By using the time-temperature shift factor to correct the resin relaxation time under different cooling times and different temperature field distributions in real time, the accurate iterative calculation and continuous evolution fitting of the resin viscoelastic behavior under asymmetric cooling and transient temperature conditions are achieved.

[0152] Step S40: Apply heat transfer boundary conditions for the upper and lower hot plates and normal pressing pressure boundary conditions to the finite element mesh model.

[0153] In step S40 above, the upper and lower hot plate heat transfer boundary conditions refer to the temperature boundary constraints that simulate the heat conduction applied by the upper and lower hot plates of the laminator to the PCB board surface, and the normal pressing pressure boundary conditions refer to the mechanical boundary constraints that simulate the normal pressing force applied by the laminator to the PCB through the upper and lower hot plates. Together, they constitute the external load input of the finite element thermo-mechanical coupled transient model, which is a necessary condition for driving the model to transiently cool down from the curing high temperature to room temperature and calculating the thermal strain and stress response throughout the cooling process. In this embodiment, the upper and lower hot plate heat transfer boundary conditions take the first type of thermal boundary conditions as an example. The initial temperature, i.e., the curing temperature, is set to 180°C. During the cooling stage, the temperature of the upper hot plate decreases from 180°C to 25°C room temperature at a rate of 2.5°C / min, and the temperature of the lower hot plate decreases from 180°C to 25°C room temperature at a rate of 2.0°C / min. The maximum transient temperature difference between the upper and lower hot plates is maintained at 5°C. The normal pressing pressure boundary conditions take the application of a uniformly distributed normal pressure of 2.5MPa on the upper surface of the top layer and a Z-direction fixed displacement constraint on the lower surface of the bottom layer as an example.

[0154] Step S50: Set the transient thermo-mechanical coupling solution type, define the initial cooling temperature, the termination temperature and the cooling duration, and specify the output variable as the internal stress vector field to complete the construction of the finite element thermo-mechanical coupling transient model.

[0155] In step S50 above, the transient thermo-mechanical coupling solution type refers to the calculation strategy of synchronously coupling the transient heat transfer analysis of the temperature field with the structural mechanical response analysis. This strategy needs to take into account the continuous change of the temperature field with time during the cooling process. The thermal expansion coefficient, elastic modulus and viscoelastic behavior of each material are strongly correlated with temperature. Therefore, it is necessary to solve the transient temperature distribution first at each time step, and then use the temperature increment as a thermal strain load to synchronously substitute into the mechanical equilibrium equation to solve the stress increment. Only in this way can the internal stress accumulation process caused by the non-uniform evolution of the temperature field and the change of material properties with temperature be accurately captured throughout the cooling process.

[0156] In some embodiments, step S50 specifically includes the following steps:

[0157] S51, set the solution type to transient thermo-mechanical coupling analysis.

[0158] In this method, a temperature-displacement coupled solver is enabled in the finite element solver. It is specified that in each time step, the heat conduction equation is solved first to update the nodal temperature field, and then the nodal temperature change is converted into thermal strain increment, which is substituted into the mechanical constitutive equation to solve the displacement field and stress field of that time step, so as to achieve bidirectional synchronous iteration of the temperature field and stress field.

[0159] S52 defines the initial temperature for cooling.

[0160] The initial cooling temperature is set to the curing temperature reached by the current asymmetric laminated PCB in the lamination process, that is, the constant temperature platform temperature at which the prepreg resin completes cross-linking and curing; in this embodiment, the initial cooling temperature is 180°C.

[0161] S53 defines the cooling termination temperature.

[0162] The cooling termination temperature is set to the target room temperature at the end of the cooling process. In this embodiment, the cooling termination temperature is 25°C.

[0163] S54 defines the cooling duration.

[0164] The cooling time was calculated based on the standard cooling rate and temperature span specified in the current lamination process specifications for asymmetric multilayer PCBs. In this embodiment, the total cooling time was 62 minutes, corresponding to an average cooling rate of 2.5℃ / min.

[0165] S55 specifies the output variable.

[0166] The solver specifies that at each time step, the outputs are the global nodal temperature, global nodal displacement, and stress tensor at the integration points of all elements. The internal stress vector field is then assembled from the stress tensors of each element through a volume-weighted average. The internal stress vector field contains the magnitude, direction, and spatial coordinates of the principal stresses of each element, and is used to comprehensively characterize the magnitude, direction, and spatial distribution of the internal stresses of the stack throughout the cooling process.

[0167] It is important to note that the finite element thermo-mechanical coupled transient model in this embodiment is used to overcome the limitations of the simplification assumptions in traditional steady-state thermal stress analysis. Specifically, it cannot fully reflect the dynamic accumulation process of internal stress under complex conditions such as asymmetric copper distribution, heterogeneous embedding interfaces, resin viscoelastic relaxation, and asymmetric temperature control between the upper and lower plates. Traditional steady-state thermal stress analysis often employs linear elastic material assumptions, uniform temperature boundaries, and static final-state solutions, only outputting room-temperature final-state stress results. It completely ignores the dynamic temperature evolution, temperature dependence of material properties, and interface stress relaxation behavior throughout the pressing and cooling process, leading to significant deviations between simulation results and actual PCB pressing residual stress and board warpage.

[0168] To address the aforementioned technical deficiencies, this embodiment constructs a full-process transient coupling simulation framework to fully reproduce the bidirectional coupling evolution of the temperature field and stress field during the entire process of asymmetric stacked PCB cooling from high curing temperature to room temperature. It accurately quantifies the distribution of the internal stress vector field and warping trend under the combined effects of asymmetric structure and asymmetric temperature control, providing quantitative numerical basis for optimizing the pressing and cooling temperature control strategy.

[0169] In terms of specific model design, the finite element thermo-mechanical coupled transient model in this embodiment combines multi-scale mesh generation, generalized Maxwell viscoelastic constitutive model, asymmetric temperature boundary and adaptive step size transient solution strategy. It can simultaneously capture local stress concentration and global warping trend from the details of the stacked structure and the characteristics of embedded components. It achieves synchronous thermo-mechanical iteration throughout the cooling process through the temperature-displacement direct coupling mechanism, and applies the viscoelastic relaxation effect to restore the stress decay behavior during the glass transition stage of the resin. This effectively makes up for the description deviation of the transient stress evolution process in traditional linear elastic steady-state analysis, and greatly improves the realism and accuracy of thermal stress simulation of complex asymmetric stacked PCBs.

[0170] To achieve high-precision and reproducible simulation modeling, this model adopts a parametric-driven modeling approach to complete the geometric model construction. Through multiple types of structured parameters, it accurately represents the complex multi-level structural features of the PCB, avoiding the problems of low efficiency, poor consistency, and large errors in traditional manual modeling. In some embodiments, the modeling of the finite element thermo-mechanical coupling transient model mainly adopts three types of editable parameter variables to drive the modeling: stack-up structure parameters, embedded component parameters, and copper foil pattern parameters, which are used to fully characterize the multi-level structural features of asymmetric stack-up PCBs. The stack-up structure parameters are used to define the thickness, material type, and stacking sequence of each dielectric layer and conductive layer, and to restore the basic geometric framework of the layered structure, such as the thickness tolerance of each layer and the number of prepreg sheets stacked. The embedded component parameters are used to accurately locate the three-dimensional dimensions and spatial positions of the power chip, embedded copper block, and ceramic substrate, and to characterize the heterogeneous interface features of the embedded structure, such as the chamfers and steps of the embedded copper block. The copper foil pattern parameters are used to distinguish the copper-containing and copper-free areas of each conductive layer, and to quantify the asymmetric thermal expansion effect caused by the difference in residual copper ratio between upper and lower layers, such as the distribution characteristics of locally thick copper-plated areas and heat dissipation via arrays. Finally, the three-dimensional solid is constructed through Boolean operations and region cutting. At the same time, all heterogeneous material contact surfaces are automatically identified and independent surface sets are generated, providing geometric indexes for subsequent contact constraints and mesh refinement. In this way, this embodiment can avoid the errors and inefficiencies of repeated manual modeling in a single simulation and ensure the consistency between geometric input and actual PCB structure.

[0171] Based on the accurate geometric model, to balance global solution efficiency with stress solution accuracy in key regions, this model is equipped with a differentiated multi-scale meshing strategy, which adapts the corresponding element type and meshing rules to the stress gradient characteristics of different structural regions. In some embodiments, the multi-scale meshing strategy adopted by the finite element thermo-mechanical coupled transient model is as follows:

[0172] In terms of element selection, the dielectric and conductive layers of the stacked main body adopt linear reduced integral hexahedral thermal-mechanical coupling elements (C3D8RT), which are suitable for the structured partitioning of layered structures and can effectively suppress the shear lock-in effect in the thickness direction, making them suitable for transient heat transfer and large deformation coupled calculations. For embedded components such as power chips, embedded copper blocks, and ceramic substrates, as well as their surrounding embedded areas, quadratic tetrahedral thermal-mechanical coupling elements (C3D10MT) are adopted, which are suitable for complex geometric boundaries such as chamfers and steps, ensuring the mesh fit and stress calculation accuracy of curved areas.

[0173] At the mesh refinement level, for stress concentration areas such as the copper-resin interlayer interface and the bonding interface between embedded components and resin, a gradient refinement rule is implemented: the thickness of the first layer unit at the interface is 1 / 4 of the thickness of the unit in the substrate area, and three transition units are set along the normal direction to achieve a smooth dimensional transition. The extension width of the refinement area into the substrate is twice the characteristic dimension of the interface. The refinement intensity is automatically adapted according to the difference in elastic modulus and thermal expansion coefficient between the materials on both sides of the interface. The greater the difference, the smaller the refinement scale, ensuring the calculation resolution of interface shear stress and peel stress and avoiding numerical distortion.

[0174] At the global quality control level, the in-plane reference element size is set to 0.8mm, and each layer in the thickness direction is divided into at least 2 elements; in stress singular areas such as the chamfer of the buried copper block and the edge of the chip, the element size is refined to 0.2mm; the Jacobian determinant of all elements is controlled above 0.6, and the element warpage is less than 0.15 to ensure the stability and convergence of the numerical solution.

[0175] After completing geometric modeling and mesh discretization, to accurately reproduce the dynamic evolution of material mechanical and thermophysical properties throughout the cooling process and to conform to the real material property changes, this model constructs a temperature-dependent constitutive material module. Temperature-related constitutive relationships and thermophysical parameters are assigned to different material zones. All parameters are interpolated and updated in real time with the solution temperature to accurately simulate the influence of material property evolution on the stress field throughout the cooling process. This embodiment adopts a zone-differentiated constitutive design to address the differentiated physical properties of metallic / ceramic materials and semi-cured resins:

[0176] For metal and ceramic materials such as copper foil, embedded copper blocks, ceramic substrates, and power chips, a linear elastic constitutive model is adopted. The material performance parameters are discretely taken at 5℃ temperature intervals, and the current temperature of the unit is matched by linear interpolation during the solution process. Taking copper foil as an example: at 25℃, the elastic modulus is 110GPa, Poisson's ratio is 0.34, the coefficient of thermal expansion is 17ppm / ℃, the thermal conductivity is 401W / (m·K), and the specific heat capacity is 385J / (kg·K); at 180℃, the elastic modulus is 95GPa, the coefficient of thermal expansion is 19ppm / ℃, and the thermal conductivity is 393W / (m·K). This reflects the influence of metal modulus softening and thermal expansion characteristics changes on the overall stress at high temperatures.

[0177] For prepreg resin materials, a generalized Maxwell viscoelastic model (Prony series form) combined with the time-temperature superposition principle is adopted to accurately describe the modulus abrupt change and stress relaxation behavior of the resin within the glass transition temperature range. This is the core design that distinguishes this model from traditional linear elastic stress analysis. Specific parameters are set as follows: glass transition temperature Tg is set to 125℃, the Prony series includes 6 sets of parallel Maxwell elements, and the relaxation time covers… The interval corresponds to a relaxation modulus weight decreasing from 0.7 to 0.05; the time-temperature shift factor is calculated using the WLF equation ( , (Reference temperature is Tg). Based on the simple thermorheological material assumption, the relaxation behavior at different temperatures is mapped to the master curve of the reference temperature, which greatly reduces the workload of calibrating temperature-related parameters.

[0178] This constitutive model incorporates a material subroutine into the finite element unit. At each time step, based on the current temperature at the element integration point, it calls the corresponding relaxation modulus and shift factor to simultaneously calculate the thermal strain increment and stress relaxation. In the highly elastic state above Tg, the resin stress relaxation effect is significant, and the interfacial shear stress gradually decreases over time. In the glassy state below Tg, the resin approaches linear elasticity, the stress relaxation effect is negligible, and internal stress enters a rapid accumulation phase. This allows for accurate capture of the stress evolution inflection point in the glass transition temperature range, avoiding the overestimation of stress in the high-temperature stage by traditional linear elastic models.

[0179] In addition, to better reflect the characteristics of the actual pressing process and restore the true source of residual stress, the model introduces an equivalent correction for curing shrinkage: taking the end of curing and heat preservation at 180℃ as the zero stress point, the volume shrinkage caused by resin curing and cross-linking is equivalent to the additional thermal expansion coefficient. The equivalent shrinkage coefficient in the X / Y direction is 3ppm / ℃, and in the Z direction it is 30ppm / ℃, thus restoring the contribution of curing shrinkage to residual stress.

[0180] After completing the material constitutive definition, in order to fully replicate the actual working conditions of the laminator pressing and cooling and ensure that the simulation boundary is highly consistent with the production conditions, this model builds a multiphysics boundary loading module to provide accurate thermal and mechanical boundary driving for transient solutions. This is the key input for reproducing the actual pressing conditions and ensuring the simulation's authenticity.

[0181] Specifically, the heat transfer boundary conditions in this embodiment adopt the first type of asymmetric temperature boundary (Dirichlet boundary) on the upper and lower plates, respectively corresponding to the temperature history of the upper and lower hot plates of the laminator: the temperature of the upper hot plate drops from 180°C to 25°C room temperature at a rate of 2.5°C / min, and the temperature of the lower hot plate drops from 180°C to 25°C room temperature at a rate of 2.0°C / min. The maximum transient temperature difference between the upper and lower hot plates is maintained at 5°C to simulate the process scenario of asymmetric temperature control; natural convection boundaries are set on the side of the PCB and the inner wall of the through hole, with a convection heat transfer coefficient h=5W / (m²·K), and the ambient temperature is set to 25°C to simulate the side heat dissipation effect.

[0182] Regarding the mechanical boundary conditions, a fully fixed displacement constraint (Ux=Uy=Uz=0) is applied to the bottom surface of the PCB to limit the overall rigid body displacement; a uniformly distributed normal pressure of 2.5MPa is applied to the top surface to simulate the pressing load of the laminator, ensuring close contact between the interfaces of each layer throughout the cooling process, while allowing in-plane deformation and warping caused by thermal expansion and contraction. The initial state is set to zero stress, corresponding to the physical state after curing and heat preservation are completed and the resin is fully cross-linked and flowed, at which point the internal stress is completely released.

[0183] Regarding interface contact constraints, all embedded components are bonded to the surrounding resin with a tie constraint, ensuring continuous normal displacement and no tangential slippage. This simulates the tight bond between the prepreg and the component surface after high-temperature curing, ensuring continuous stress transmission at the interface and avoiding non-physical results such as false stress abrupt changes or interface separation.

[0184] With the geometric model, mesh, material constitutive model, and boundary conditions all configured, this model adopts a high-precision transient coupling solution strategy to achieve dynamic coupling solution of temperature and stress fields and accurately capture the entire process of transient stress evolution. Through a two-way synchronous iteration mechanism and adaptive step size control, the solution accuracy and computational efficiency are balanced.

[0185] Specifically, the coupled solution logic is as follows: in each time step, the transient heat conduction equation is solved first to update the temperature of all nodes in the field; then the temperature increment is converted into thermal strain load, substituted into the mechanical equilibrium equation, and combined with the material constitutive parameters at the current temperature to solve the nodal displacement field and element stress field; the element stress state and material properties are updated synchronously as the initial conditions for the next time step, thereby realizing the bidirectional synchronous iteration of the temperature field and stress field.

[0186] The adaptive time step control strategy is as follows: the initial time step is set to 0.1 min, the minimum step to 0.01 min, and the maximum step to 1 min; in the glass transition temperature range (110℃~140℃), the time step is automatically refined to 0.05 min to accurately capture the stress inflection point corresponding to the constitutive abrupt change in the material; in the high-temperature and low-temperature ranges where the cooling is gradual, the step size is automatically increased. The convergence criterion is set as follows: thermal analysis temperature residual ≤ ℃, mechanical analysis displacement residual ≤ Force residual ≤ This ensures the numerical stability and physical rationality of each solution step.

[0187] At the output level, result frames are output at 1-minute intervals. Output variables include the temperature of all nodes, nodal displacement, stress tensor of element integration points (von Mises stress, maximum principal stress, interface shear stress), and interface contact stress. Finally, by using the volume-weighted average of element stress tensors, an internal stress vector field covering the entire cooling process is assembled, which includes the stress magnitude, direction, and evolution over time at each spatial location.

[0188] In summary, referring to Figure 2 The architecture design in the finite element thermo-mechanical coupling transient model of this embodiment is referenced as follows in actual operation: Input layer: -[Number of layers, thickness of each layer, material type, board size]# Basic layer structure parameters of asymmetric stacked PCB; -[Component type, length, width and height dimensions, center coordinates, shape characteristics]# Power chip, embedded copper block, ceramic substrate embedding parameters; -[Outline of each copper layer, residual copper ratio, local thick copper area]#Asymmetric copper foil distribution parameters of conductive layer; -[Full-temperature thermo / mechanical parameters, Prony spectrum of resin viscoelasticity, WLF time-temperature parameters]#Constraint data set of materials with temperature; -[180℃ curing temperature, 2.5℃ / min upper plate cooling, 2.0℃ / min lower plate cooling, 2.5MPa compressive stress, 25℃ room temperature]# Process boundary parameters.

[0189] Geometry and Mesh Building Module: 1. Parametric geometry generation layer: -Laminated and stretched layer by layer to replicate the actual laminated assembly structure; - Boolean embedding operation of embedded components to match the shape of the physical object and generate the embedded cavity; - The copper foil outline of the conductive layer is cut to distinguish between the copper area and the dielectric filling area; - Automatic identification of heterogeneous material interfaces generates a standardized set of contact surfaces.

[0190] 2. Multi-scale mesh segmentation: -Layered main body: C3D8RT hexahedral thermo-mechanical coupled structured unit; - Embedded component area: C3D10MT tetrahedral secondary thermo-mechanical coupling unstructured unit; -Heterogeneous interface encryption: The interface unit size is 1 / 4 of the base size, and it is configured with 3 layers of transition units; - Mesh quality constraints: Jacobian determinant ≥ 0.6, element warpage ≤ 0.15.

[0191] Material and boundary definition module: 3. Temperature-dependent constitutive assignment layer: -Metal / Ceramic materials: linear elastic constitutive model, linear interpolation update at 5℃ temperature intervals; - Semi-cured resin: Generalized Maxwell viscoelastic constitutive model (Prony series + WLF time-temperature superposition); - Curing shrinkage correction: Equivalent additional thermal expansion coefficient compensates for resin volume shrinkage.

[0192] 4. Multi-field boundary loading layer: - Thermal boundary: Asymmetric Dirichlet temperature boundary of upper and lower plates + 5W / (m²·K) natural convection boundary of the side; -Mechanical boundary: bottom surface fully fixed displacement constraint + top surface 2.5MPa uniformly distributed normal pressing pressure; - Interface constraints: Heterogeneous bonding interface Tie binding constraint, normal continuous and tangential no slip.

[0193] Coupled solution and output module: 5. Transient thermo-mechanical coupling solution layer: -Solution mechanism: Temperature-displacement direct coupling, single-step heat conduction priority, and mechanical iteration synchronous update; - Adaptive time step: 0.01~1min for the normal segment, and the glass transition temperature range (110~140℃) is refined to 0.05min; - Convergence criterion: Temperature residual ≤ ℃, displacement residual ≤ Force residual ≤ .

[0194] 6. Post-processing output layer: -Time-series sampling: Outputs full-field temperature, displacement, and element stress tensor every 1 minute, covering the entire cycle from 0 to 62 minutes; - Stress assembly: Volume weighted averaging generates an internal stress vector field containing magnitude, direction, and spatial coordinates; - Reliability verification: Strain energy and thermal energy conservation verification, and removal of abnormal value frames.

[0195] Output layer: -[Total number of global elements, 6-dimensional stress components, 62-frame time steps]#0~62min full cooling process internal stress vector field dataset.

[0196] In step S300 above, the asymmetric multilayer PCB three-dimensional geometric model obtained in S100 is used as the numerical solution domain. A finite element thermo-mechanical coupled transient model with pre-completed mesh generation, constitutive definition, and boundary configuration is imported. Simultaneously, the mechanical and thermophysical property parameters of each component material as a function of temperature obtained in S200 are input to carry out thermo-mechanical bidirectional coupled transient numerical solution. Finally, a spatiotemporal coupled internal stress vector field covering the complete cooling process is output. The final internal stress vector field is a spatiotemporally coupled three-dimensional vector time-series dataset, and its data dimension format is [total number of global elements, 6 dimensions]. Taking stress components and 62 time steps as an example, in the spatial dimension, it covers all finite element units of the entire PCB, including all areas such as laminated dielectrics, copper foils, embedded chips / copper blocks, and heterogeneous interfaces; in the physical dimension, it outputs a complete 6-dimensional stress tensor (3 normal stresses + 3 shear stresses), which can synthesize von Mises equivalent stress, maximum principal stress, and interface shear / peel stress; in the temporal dimension, it includes the complete cooling process from 0 to 62 minutes, with one frame of time data every 1 minute, continuously covering the entire evolution stage from high-temperature curing state to glass transition temperature zone to room temperature steady state. Among them, the magnitude of stress is used to accurately quantify the stress concentration degree in different regions; the spatial direction of stress is used to characterize the stress direction corresponding to interlayer tension, interface shear, and board warping; the temporal evolution law of stress is used to reconstruct the entire process of stress accumulation, decay, and abrupt change caused by resin relaxation, asymmetric temperature control, and structural mismatch.

[0197] An example of an internal stress vector field is as follows:

[0198] Assuming the total number of effective elements in the global domain is N=86240 after the simulation, and the total number of time sampling steps is 62 frames (0~62min), the final output of the internal stress vector field will be a three-dimensional temporal tensor with dimensions [86240, 6, 62]. Specifically, any finite element i and any time t can output a complete three-dimensional stress vector.

[0199] The stress vector of element i at minute t = ;

[0200] In the formula: , , It is a triaxial orthogonal normal stress (tension / compression vector). , , For triaxial shear stress (slip vector), each set of 6-dimensional data not only contains the magnitude of the stress, but also has its own spatial force direction attribute, forming a stress vector in a strictly physical sense.

[0201] The following combination Figures 3-5 Let's take the original output of a model as an example:

[0202] (1) High-temperature, high-elasticity state (t=10min, T=152℃) resin-embedded copper interface unit: Stress vector: [0.24MPa, 0.18MPa, 0.85MPa, 0.11MPa, 0.23MPa, 0.09MPa]; The corresponding physical characteristics are: significant elastic relaxation of the resin, low normal stress level, slight accumulation of shear stress, no obvious stress concentration, and the vector direction is distributed along the tangential direction of the interface.

[0203] (2) Interface unit of glass transition critical state (t=28min, T=125℃, near Tg): Stress vector: [1.42MPa, 1.33MPa, 3.96MPa, 0.42MPa, 0.68MPa, 0.31MPa]; Physical manifestations: The resin modulus increases sharply, relaxation failure occurs, normal compressive stress accumulates rapidly, and shear stress increases significantly. This is the stage with the fastest stress growth in the entire process, and the vector changes from tangential slip to normal extrusion.

[0204] (3) Low-temperature glassy state (t=62min, room temperature steady state) chip corner singular units: Stress vector: [4.52MPa, 4.16MPa, 8.93MPa, 1.22MPa, 1.86MPa, 0.97MPa]; Physical characteristics: The resin is fully vitrified and has no relaxation effect. The stiffness mismatch of the embedded heterogeneous structure causes significant stress concentration, with the stress vector pointing to the outer corner of the chip, corresponding to local warping deformation of the board surface.

[0205] From a spatial field morphology perspective, this temporal vector field can be equivalent to a three-dimensional stress vector cloud map that evolves continuously over time: each grid node is equipped with a three-dimensional stress arrow, the arrow length representing the stress amplitude and the arrow direction representing the principal stress direction. The arrows across the entire field dynamically evolve with the cooling time, visually demonstrating the complete physical process of early interface slip, mid-term glass transition stress abrupt change, late-term local stress concentration, and global warping. Compared to traditional steady-state simulations that only output single-point scalar stress values, the spatiotemporal vector field output by this model can completely characterize the entire mechanism of stress generation, relaxation, accumulation, and shaping of PCB asymmetric stacked structures under asymmetric temperature control processes.

[0206] Step S400: Determine the cooling temperature control strategy based on the internal stress vector field.

[0207] In step S400 above, the cooling temperature control strategy is a differentiated and time-sequential pressing and cooling control scheme that matches the structural characteristics, material temperature change characteristics, and stress evolution laws of asymmetric stacked PCBs. The core is to solve the defects of the process caused by the inability of traditional uniform cooling and fixed cooling rate temperature control methods to adapt to asymmetric stacked structures, such as excessive residual stress, board warping and deformation, delamination of embedded component interfaces, and circuit cracking. By specifically controlling the cooling rate of the upper and lower hot plates, the holding time of the temperature zone, the temperature difference threshold, and the pressure coordination parameters, the dynamic release and precise control of internal stress throughout the cooling process is achieved, ultimately reducing the residual stress and warping of the finished PCB, and effectively ensuring the structural integrity and electrical reliability of the embedded power module.

[0208] In some embodiments, step S400 specifically includes the following steps:

[0209] S410, perform temporal feature extraction and spatial feature analysis on the internal stress vector field, and select key stress feature parameters.

[0210] In the above S410, the temporal characteristics are the dynamic changes of the internal stress vector field with cooling time and temperature range, and the spatial characteristics are the differences in the distribution of the internal stress vector field in the PCB stack thickness direction, the XY plane of the board surface, and the heterogeneous embedding interface region.

[0211] In some embodiments, S410 specifically includes the following sub-steps:

[0212] Step 4.1.1: Analyze the time-series evolution data of the internal stress vector field frame by frame to extract the temperature-stress time-series correlation features.

[0213] Specifically, by traversing the stress vector data of each frame of the entire cooling time series and combining it with the global temperature field data at the corresponding time, three cooling stages were defined: high-temperature elastic state, glass transition temperature region, and low-temperature glass state. Stress evolution characteristics were extracted for each stage: in the high-temperature elastic state (temperature > 140℃), the resin stress relaxation rate and the cumulative rate of increase of interfacial shear stress were extracted; in the glass transition temperature region (110℃~140℃, covering the critical range of resin Tg=125℃), the peak value of stress abrupt change, the extreme value of stress rate increase, and the temperature and time nodes corresponding to the modulus abrupt change were extracted; in the low-temperature glass state (temperature < 110℃), the residual stress settling rate and stress stability threshold parameters were extracted. Simultaneously, the temporal and temperature correspondences of the occurrence of stress extreme values ​​throughout the entire process were recorded, clearly identifying the glass transition temperature region as the core sensitive region for internal stress accumulation and abrupt changes.

[0214] Step 4.1.2: Perform global analysis on the spatial distribution data of the internal stress vector field to extract the asymmetric stress distribution characteristics.

[0215] Specifically, based on the 6-dimensional stress vector data of the global unit, the stress amplitude and stress direction differences of the top, bottom, and intermediate dielectric layers of the PCB are compared to extract the interlayer stress difference parameters caused by the asymmetric copper foil distribution between the upper and lower layers; the heterogeneous embedding interfaces of power chips, embedded copper blocks, ceramic substrates and resin are identified, and the concentrated area coordinates and extreme value parameters of interface shear stress and peel stress are extracted; the distribution law of principal stress direction in different areas of the board surface is statistically analyzed, the correspondence between the stress vector direction and the board surface warping deformation trend is matched, and the stress spatial mismatch characteristics caused by the asymmetric stacked structure are determined.

[0216] Step 4.1.3: Integrate temporal and spatial features to obtain a set of key stress feature parameters.

[0217] The set of key stress characteristic parameters includes: peak stress in the glass transition temperature zone, maximum interlayer stress difference, extreme value of concentrated stress at heterogeneous interfaces, critical temperature for stress abrupt change, effective duration of stress relaxation, residual stress shaping threshold, and degree of asymmetric distribution of stress on the plate surface.

[0218] It should be noted that the aforementioned key stress characteristic parameters can also be rapidly calibrated and verified using digital image-related DIC full-field strain testing technology, moiré warp optical detection technology, and conventional finite element steady-state thermal stress simulation technology.

[0219] S420, based on the stress key characteristic parameters, match the preset temperature control parameter mapping rules to generate an initial differentiated cooling temperature control parameter set.

[0220] In S420 above, the preset temperature control parameter mapping rules are a pre-established process association rule library adapted to the asymmetric stacked PCB structure and material properties. This library can perform one-to-one matching of process parameters for the extracted key stress feature parameters. This step is mainly based on the various key stress feature parameters obtained from the analysis, combined with the stress relaxation law of the resin glass transition temperature zone, the interlayer shrinkage mismatch characteristics caused by the asymmetric distribution of upper and lower copper foils, and the stress concentration characteristics of the embedded heterogeneous interface. It adaptively matches the corresponding cooling rate, glass transition temperature zone slow release time, dynamic temperature difference threshold of upper and lower hot plates, and collaborative pressing process parameters, and quickly integrates and generates a set of initial differentiated cooling temperature control parameters adapted to the current asymmetric stacked PCB structure.

[0221] Specifically, the determination of the initial differentiated cooling temperature control parameter set in this embodiment includes, but is not limited to: determining the cooling rate and constant temperature slow release time of the resin sensitive temperature zone based on the stress mutation critical temperature and the stress peak value of the glass transition temperature zone; determining the differentiated cooling ratio of the upper and lower hot plates based on the maximum stress difference between layers and the asymmetric distribution of stress on the plate surface; determining the dynamic temperature difference threshold of the upper and lower hot plates throughout the cooling process based on the extreme value of concentrated stress at the heterogeneous interface; and determining the full-process collaborative pressing pressure parameters based on the effective stress relaxation time and the residual stress shaping threshold.

[0222] It is important to note that the aforementioned temperature control parameter mapping rules were pre-constructed through extensive simulation calibration and process experiment fitting. Specifically, the construction method involved using multiple batches of asymmetric multilayer PCB samples with different residual copper ratios and embedding layouts. The aforementioned finite element thermo-mechanical coupling transient model was used to iterate through the stress evolution results corresponding to different cooling rates, temperature zone slow-release durations, inter-board temperature differences, and lamination pressures. The one-to-one correspondence between various key stress characteristic parameters and optimal cooling process parameters was statistically analyzed. Combined with the boundary constraints of the PCB lamination and curing process and the viscoelastic temperature change mechanism of the resin, standardized parameter mapping relationships were fitted and solidified into a rule base. This mapping rule, after simulation iteration verification and actual process validation, can achieve accurate and rapid matching of stress characteristic parameters to cooling process parameters, eliminating the need for repeated trial and error debugging for each PCB, thus possessing both universality and specificity.

[0223] S430, perform simulation iteration verification and parameter optimization on the initial differentiated cooling temperature control parameter group to determine the optimal cooling temperature control strategy.

[0224] In the S430 mentioned above, the initial differentiated cooling temperature control parameter set is a basic process parameter obtained by direct matching of stress characteristics. It has problems such as multi-parameter coupling influence and insufficient local parameter adaptability. It is necessary to use the finite element thermo-mechanical coupling transient model for iterative simulation. Relying only on the internal stress vector field data output by the model, the internal stress relief effect and stress concentration improvement effect under different parameter combinations are checked. Redundant parameters are eliminated and the parameter matching relationship is optimized to obtain the optimal temperature control strategy that takes into account both stress control accuracy and production efficiency.

[0225] In some embodiments, S430 specifically includes the following sub-steps:

[0226] Step 4.3.1: Input the initial differentiated cooling temperature control parameter set into the finite element thermo-mechanical coupling transient model, carry out secondary transient simulation, and obtain the optimized internal stress vector field.

[0227] Specifically, using the cooling rate, holding time, temperature difference threshold, and pressing pressure corresponding to the initial temperature control parameter set as new boundary conditions, the thermo-mechanical coupling evolution of the entire cooling process is reproduced, and the global stress vector data and plate displacement deformation data are resolved to quantify and optimize the residual stress amplitude, interface shear stress level, and interlayer stress difference.

[0228] Step 4.3.2: Construct a multi-objective optimization evaluation system and verify the adaptability of temperature control parameters.

[0229] The multi-objective optimization evaluation system includes three core evaluation indicators: residual stress compliance rate, heterogeneous interface stress relief rate, and interlayer stress uniformity, coupled with cooling time efficiency. The residual stress compliance rate is used to assess whether the residual stress across all cells is below the process threshold; the heterogeneous interface stress relief rate is used to assess the stress optimization effect at the interfaces between the chip, embedded copper block, ceramic substrate, and resin; the interlayer stress uniformity is used to assess the improvement effect of asymmetric cooling on the stress mismatch of the laminate; and the cooling time is used to assess process production efficiency.

[0230] Step 4.3.3: Iteratively optimize the temperature control parameters based on the verification results and lock in the optimal parameter combination.

[0231] If the optimized residual stress, interface concentrated stress, and interlayer stress difference still exceed the preset process threshold, the insulation time of the sensitive temperature zone, the difference in cooling rate between the upper and lower plates, and the dynamic temperature difference threshold parameters are adjusted in reverse. The simulation and verification are repeated until all stress indicators meet the process requirements. If all stress indicators are optimal and the cooling time is controllable, the iteration is stopped and the current temperature control parameter combination is locked as the optimal process parameters.

[0232] S440, based on the optimal combination of process parameters, solidifies a lamination cooling temperature control strategy adapted to current asymmetric stacked PCBs.

[0233] In the aforementioned S440, the final solidified cooling temperature control strategy is a time-sequential, differentiated, and adaptive complete process solution that strictly matches the current asymmetric stacked PCB stack structure, asymmetric copper foil distribution, embedded component layout, and material temperature change characteristics. Compared with the traditional uniform temperature control solution, it can effectively reduce stress concentration, stress abrupt changes, and warping deformation problems during the cooling process of asymmetric structures.

[0234] The PCB lamination cooling temperature control device provided by the present invention is described below. The PCB lamination cooling temperature control device described below can be referred to in correspondence with the asymmetric laminated PCB lamination cooling temperature control method for embedded power modules described above.

[0235] like Figure 6As shown, in one embodiment, a PCB lamination cooling temperature control device includes a three-dimensional geometric modeling module, a material parameter matching module, a thermo-mechanical coupling simulation solution module, and a cooling temperature control strategy generation module.

[0236] The 3D geometric modeling module is used to obtain the complete structural information of the current asymmetric stacked PCB and to establish a 3D geometric model of the current asymmetric stacked PCB based on the complete structural information.

[0237] The material parameter matching module is used to determine the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB as a function of temperature based on the complete structural information in a preset material parameter database.

[0238] The thermo-mechanical coupling simulation solution module is used to take the three-dimensional geometric model as the solution domain, input the mechanical and thermophysical performance parameters into the pre-established finite element thermo-mechanical coupling transient model for transient solution, and obtain the internal stress vector field.

[0239] The cooling temperature control strategy generation module is used to determine the cooling temperature control strategy based on the internal stress vector field.

[0240] Figure 7 This example illustrates a schematic diagram of the physical structure of an electronic device, which can be a smart terminal. Its internal structure diagram can be as follows: Figure 7 As shown, this electronic device includes a processor, internal memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements the aforementioned asymmetric multilayer PCB lamination cooling temperature control method for embedded power modules.

[0241] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the electronic device to which the present invention is applied. A specific electronic device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0242] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for cooling and temperature control during the lamination of an asymmetric multilayer PCB for embedded power modules, characterized in that, The method includes: Obtain the complete structural information of the current asymmetric stacked PCB, and establish a three-dimensional geometric model of the current asymmetric stacked PCB based on the complete structural information; Based on the complete structural information, the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB are determined in the preset material parameter database as a function of temperature. Using the three-dimensional geometric model as the solution domain, the mechanical and thermophysical performance parameters are input into a pre-established finite element thermo-mechanical coupled transient model for transient solution to obtain the internal stress vector field. The finite element thermo-mechanical coupled transient model is used to calculate the temperature distribution at each moment during the cooling process and the thermal strain and stress response caused by the difference in the thermal expansion coefficients of each layer of material in the solution domain provided by the three-dimensional geometric model, combined with the mechanical and thermophysical performance parameters of each material partition. Finally, the internal stress vector field characterizing the magnitude, direction and spatial distribution of the internal stress of the stack is output. The cooling temperature control strategy is determined based on the internal stress vector field, which is a spatiotemporally coupled three-dimensional vector time series dataset used to characterize the stress evolution of the PCB asymmetric stacked structure under the pressing and cooling process. Before the step of using the three-dimensional geometric model as the solution domain, inputting the mechanical and thermophysical performance parameters into a pre-established finite element thermo-mechanical coupled transient model for transient solution to obtain the internal stress vector field, the method further includes: Based on the material parameter database, a finite element thermo-mechanical coupled transient model is established for the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB as a function of temperature. The finite element thermo-mechanical coupled transient model uses transient temperature-displacement coupling to solve the problem. It combines the viscoelastic constitutive properties of the semi-cured resin with the asymmetric compression cooling boundary conditions to reproduce the dynamic evolution of internal stress in the PCB from high curing temperature to room temperature. The complete structural information includes stack-up structure information, embedded component information, and copper foil pattern information; the establishment of a three-dimensional geometric model of the current asymmetric stack-up PCB based on the complete structural information includes: Obtain the stack-up structure information of the current asymmetric stack-up PCB, and establish the two-dimensional planar contours of each dielectric layer and conductive layer based on the stack-up structure information. All the two-dimensional planar contours are stacked along the thickness direction in the actual stacking order to obtain the geometric model of the stacked main body; Obtain the embedded component information of the current asymmetric stacked PCB, and embed the three-dimensional solid geometry of the power chip, embedded copper block and ceramic substrate in the corresponding layer according to the embedded component information in the stacked main body geometric model to obtain the stacked main body geometric model with embedded components. Define the contact interface relationship between each embedded element and the surrounding medium layer. The contact interface relationship refers to the mechanical connection relationship between the outer surface of each embedded element and the inner surface of the embedded cavity formed by the geometric model of the stacked main body during the embedding process. It is used to describe the displacement and stress transfer behavior at the interface of heterogeneous materials. The copper foil pattern information of the current asymmetric stacked PCB is obtained, and according to the copper foil pattern information, the copper foil distribution characteristics are assigned to each conductive layer in the geometric model of the stacked main body with embedded components, so as to complete the establishment of the three-dimensional geometric model of the current asymmetric stacked PCB. The cooling temperature control strategy determined based on the internal stress vector field includes: Temporal and spatial features of the internal stress vector field are extracted and analyzed to obtain key stress feature parameters. Based on the aforementioned key stress characteristic parameters, a preset temperature control parameter mapping rule is matched to generate an initial differentiated cooling temperature control parameter set. The initial differentiated cooling temperature control parameter set is simulated and iteratively verified and optimized to determine the optimal cooling temperature control strategy, which includes the optimal parameter combination. Based on the optimal parameter combination, a lamination cooling temperature control strategy adapted to the current asymmetric stacked PCB is solidified.

2. The asymmetric laminated PCB lamination cooling and temperature control method for embedded power modules according to claim 1, characterized in that, The establishment of the finite element thermo-mechanical coupled transient model includes: Establish a general parametric geometric template for asymmetric stacked PCBs; The general parametric geometric template is meshed to generate a finite element mesh model; Based on the mechanical and thermophysical property parameters of each layer of the constituent materials in the material parameter database, temperature-dependent material properties are defined for the material partitions of copper foil, ceramic substrate, prepreg resin, chip and embedded copper block on the finite element mesh model. Apply heat transfer boundary conditions for upper and lower hot plates and normal pressing pressure boundary conditions to the finite element mesh model. Set the transient thermo-mechanical coupling solution type, define the initial cooling temperature, the termination temperature and the cooling duration, and specify the output variable as the internal stress vector field to complete the construction of the finite element thermo-mechanical coupling transient model.

3. The asymmetric laminated PCB lamination cooling and temperature control method for embedded power modules according to claim 2, characterized in that, Based on the mechanical and thermophysical property parameters of each layer of constituent materials in the material parameter database, the temperature-dependent material properties are defined for the material partitions of copper foil, ceramic substrate, prepreg resin, chip, and embedded copper block on the finite element mesh model, including: For the material partitions of copper foil, ceramic substrate, chip and embedded copper block, the mechanical and thermophysical property parameters of the corresponding materials are retrieved from the material parameter database, and the elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity and density change with temperature are assigned to all elements in the partition on the finite element mesh model. For the material partitioning of the prepreg resin, the basic mechanical and thermophysical property parameters of the prepreg resin are first retrieved from the material parameter database. On the finite element mesh model, all elements in the partition are assigned sequential values ​​of elastic modulus, Poisson's ratio, coefficient of thermal expansion, thermal conductivity, specific heat capacity, and density as a function of temperature. Then, the viscoelastic relaxation spectrum parameters of the glass transition temperature region are retrieved from the material parameter database and implanted into the corresponding partition. The implantation of the viscoelastic relaxation spectrum parameters is used to describe the nonlinear evolution of the modulus of the prepreg resin with temperature and the stress relaxation behavior in the glass transition temperature region.

4. The asymmetric laminated PCB lamination cooling and temperature control method for embedded power modules according to claim 3, characterized in that, The material partitioning of the prepreg resin is characterized by the temperature-dependent viscoelastic properties using the generalized Maxwell viscoelastic constitutive model. The generalized Maxwell viscoelastic constitutive model is constructed by multiple sets of Maxwell units in parallel. The stress relaxation modulus of the resin is discretized by Prony series to characterize the viscoelastic evolution of the resin at different cooling stages. The expression for the Prony series is: ； in, The shear relaxation modulus of the resin changes dynamically over time and is used to characterize the instantaneous viscoelastic stiffness of the resin. The equilibrium modulus after the resin is fully relaxed represents the elastic matrix properties after the resin is fully relaxed. Let be the relaxation modulus weight of the i-th Maxwell element; is the characteristic relaxation time of the i-th Maxwell unit; n is the number of Maxwell unit fitting groups; The time required for real-time calculation of the compression cooling process.

5. The asymmetric laminated PCB lamination cooling and temperature control method for embedded power modules according to claim 4, characterized in that, The generalized Maxwell viscoelastic constitutive model, combined with the WLF time-temperature superposition principle, achieves a coupling relationship between temperature and relaxation characteristics. The time-temperature shift factor at different temperatures is calculated using the WLF equation, mapping the resin stress relaxation curve under varying temperature conditions to the master curve at the glass transition reference temperature. The expression for the WLF equation is: ； in, It is the time-temperature shift factor; The glass transition temperature of the prepreg resin; The current real-time absolute temperature of the finite element element; , These are dimensionless fitting constants inherent to the resin material, calibrated by dynamic mechanical tests, and are used to characterize the sensitivity coefficient of temperature shift to relaxation rate and the temperature correction interval coefficient of the glass transition temperature range, respectively.

6. A PCB lamination cooling and temperature control device, characterized in that, The apparatus for implementing the asymmetric laminated PCB lamination cooling and temperature control method for embedded power modules according to any one of claims 1 to 5, the apparatus comprising: The 3D geometric modeling module is used to obtain the complete structural information of the current asymmetric stacked PCB and establish a 3D geometric model of the current asymmetric stacked PCB based on the complete structural information. The material parameter matching module is used to determine the mechanical and thermophysical property parameters of each layer of the asymmetric multilayer PCB as a function of temperature based on the complete structural information in a preset material parameter database. The thermo-mechanical coupling simulation solution module is used to take the three-dimensional geometric model as the solution domain, input the mechanical and thermophysical performance parameters into the pre-established finite element thermo-mechanical coupling transient model for transient solution, and obtain the internal stress vector field; A cooling temperature control strategy generation module is used to determine a cooling temperature control strategy based on the internal stress vector field.

7. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the asymmetric stacked PCB lamination cooling temperature control method for embedded power modules as described in any one of claims 1 to 5.

8. A computer storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the asymmetric stacked PCB lamination cooling temperature control method for embedded power modules as described in any one of claims 1 to 5.

Images